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1 | d0f7453d | Huacai Chen | /*
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2 | d0f7453d | Huacai Chen | * bonito north bridge support
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3 | d0f7453d | Huacai Chen | *
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4 | d0f7453d | Huacai Chen | * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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5 | d0f7453d | Huacai Chen | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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6 | d0f7453d | Huacai Chen | *
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7 | d0f7453d | Huacai Chen | * This code is licensed under the GNU GPL v2.
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8 | 6b620ca3 | Paolo Bonzini | *
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9 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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10 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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11 | d0f7453d | Huacai Chen | */
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12 | d0f7453d | Huacai Chen | |
13 | d0f7453d | Huacai Chen | /*
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14 | d0f7453d | Huacai Chen | * fulong 2e mini pc has a bonito north bridge.
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15 | d0f7453d | Huacai Chen | */
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16 | d0f7453d | Huacai Chen | |
17 | d0f7453d | Huacai Chen | /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
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18 | d0f7453d | Huacai Chen | *
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19 | d0f7453d | Huacai Chen | * devfn pci_slot<<3 + funno
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20 | d0f7453d | Huacai Chen | * one pci bus can have 32 devices and each device can have 8 functions.
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21 | d0f7453d | Huacai Chen | *
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22 | d0f7453d | Huacai Chen | * In bonito north bridge, pci slot = IDSEL bit - 12.
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23 | d0f7453d | Huacai Chen | * For example, PCI_IDSEL_VIA686B = 17,
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24 | d0f7453d | Huacai Chen | * pci slot = 17-12=5
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25 | d0f7453d | Huacai Chen | *
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26 | d0f7453d | Huacai Chen | * so
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27 | d0f7453d | Huacai Chen | * VT686B_FUN0's devfn = (5<<3)+0
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28 | d0f7453d | Huacai Chen | * VT686B_FUN1's devfn = (5<<3)+1
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29 | d0f7453d | Huacai Chen | *
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30 | d0f7453d | Huacai Chen | * qemu also uses pci address for north bridge to access pci config register.
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31 | d0f7453d | Huacai Chen | * bus_no [23:16]
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32 | d0f7453d | Huacai Chen | * dev_no [15:11]
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33 | d0f7453d | Huacai Chen | * fun_no [10:8]
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34 | d0f7453d | Huacai Chen | * reg_no [7:2]
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35 | d0f7453d | Huacai Chen | *
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36 | d0f7453d | Huacai Chen | * so function bonito_sbridge_pciaddr for the translation from
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37 | d0f7453d | Huacai Chen | * north bridge address to pci address.
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38 | d0f7453d | Huacai Chen | */
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39 | d0f7453d | Huacai Chen | |
40 | d0f7453d | Huacai Chen | #include <assert.h> |
41 | d0f7453d | Huacai Chen | |
42 | d0f7453d | Huacai Chen | #include "hw.h" |
43 | d0f7453d | Huacai Chen | #include "pci.h" |
44 | d0f7453d | Huacai Chen | #include "pc.h" |
45 | d0f7453d | Huacai Chen | #include "mips.h" |
46 | d0f7453d | Huacai Chen | #include "pci_host.h" |
47 | d0f7453d | Huacai Chen | #include "sysemu.h" |
48 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
49 | d0f7453d | Huacai Chen | |
50 | d0f7453d | Huacai Chen | //#define DEBUG_BONITO
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51 | d0f7453d | Huacai Chen | |
52 | d0f7453d | Huacai Chen | #ifdef DEBUG_BONITO
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53 | d0f7453d | Huacai Chen | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
54 | d0f7453d | Huacai Chen | #else
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55 | d0f7453d | Huacai Chen | #define DPRINTF(fmt, ...)
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56 | d0f7453d | Huacai Chen | #endif
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57 | d0f7453d | Huacai Chen | |
58 | d0f7453d | Huacai Chen | /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
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59 | d0f7453d | Huacai Chen | #define BONITO_BOOT_BASE 0x1fc00000 |
60 | d0f7453d | Huacai Chen | #define BONITO_BOOT_SIZE 0x00100000 |
61 | d0f7453d | Huacai Chen | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) |
62 | d0f7453d | Huacai Chen | #define BONITO_FLASH_BASE 0x1c000000 |
63 | d0f7453d | Huacai Chen | #define BONITO_FLASH_SIZE 0x03000000 |
64 | d0f7453d | Huacai Chen | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) |
65 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_BASE 0x1f800000 |
66 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_SIZE 0x00400000 |
67 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) |
68 | d0f7453d | Huacai Chen | #define BONITO_REG_BASE 0x1fe00000 |
69 | d0f7453d | Huacai Chen | #define BONITO_REG_SIZE 0x00040000 |
70 | d0f7453d | Huacai Chen | #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) |
71 | d0f7453d | Huacai Chen | #define BONITO_DEV_BASE 0x1ff00000 |
72 | d0f7453d | Huacai Chen | #define BONITO_DEV_SIZE 0x00100000 |
73 | d0f7453d | Huacai Chen | #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) |
74 | d0f7453d | Huacai Chen | #define BONITO_PCILO_BASE 0x10000000 |
75 | d0f7453d | Huacai Chen | #define BONITO_PCILO_BASE_VA 0xb0000000 |
76 | d0f7453d | Huacai Chen | #define BONITO_PCILO_SIZE 0x0c000000 |
77 | d0f7453d | Huacai Chen | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) |
78 | d0f7453d | Huacai Chen | #define BONITO_PCILO0_BASE 0x10000000 |
79 | d0f7453d | Huacai Chen | #define BONITO_PCILO1_BASE 0x14000000 |
80 | d0f7453d | Huacai Chen | #define BONITO_PCILO2_BASE 0x18000000 |
81 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_BASE 0x20000000 |
82 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_SIZE 0x20000000 |
83 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) |
84 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_BASE 0x1fd00000 |
85 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_BASE_VA 0xbfd00000 |
86 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_SIZE 0x00010000 |
87 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) |
88 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_BASE 0x1fe80000 |
89 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_SIZE 0x00080000 |
90 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) |
91 | d0f7453d | Huacai Chen | |
92 | d0f7453d | Huacai Chen | |
93 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIGBASE 0x00 |
94 | d0f7453d | Huacai Chen | #define BONITO_REGBASE 0x100 |
95 | d0f7453d | Huacai Chen | |
96 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
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97 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIG_SIZE (0x100) |
98 | d0f7453d | Huacai Chen | |
99 | d0f7453d | Huacai Chen | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
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100 | d0f7453d | Huacai Chen | #define BONITO_INTERNAL_REG_SIZE (0x70) |
101 | d0f7453d | Huacai Chen | |
102 | d0f7453d | Huacai Chen | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
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103 | d0f7453d | Huacai Chen | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
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104 | d0f7453d | Huacai Chen | |
105 | d0f7453d | Huacai Chen | |
106 | d0f7453d | Huacai Chen | |
107 | d0f7453d | Huacai Chen | /* 1. Bonito h/w Configuration */
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108 | d0f7453d | Huacai Chen | /* Power on register */
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109 | d0f7453d | Huacai Chen | |
110 | d0f7453d | Huacai Chen | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ |
111 | d0f7453d | Huacai Chen | #define BONITO_BONGENCFG_OFFSET 0x4 |
112 | d0f7453d | Huacai Chen | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ |
113 | d0f7453d | Huacai Chen | |
114 | d0f7453d | Huacai Chen | /* 2. IO & IDE configuration */
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115 | d0f7453d | Huacai Chen | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ |
116 | d0f7453d | Huacai Chen | |
117 | d0f7453d | Huacai Chen | /* 3. IO & IDE configuration */
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118 | d0f7453d | Huacai Chen | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ |
119 | d0f7453d | Huacai Chen | |
120 | d0f7453d | Huacai Chen | /* 4. PCI address map control */
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121 | d0f7453d | Huacai Chen | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ |
122 | d0f7453d | Huacai Chen | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ |
123 | d0f7453d | Huacai Chen | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ |
124 | d0f7453d | Huacai Chen | |
125 | d0f7453d | Huacai Chen | /* 5. ICU & GPIO regs */
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126 | d0f7453d | Huacai Chen | /* GPIO Regs - r/w */
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127 | d0f7453d | Huacai Chen | #define BONITO_GPIODATA_OFFSET 0x1c |
128 | d0f7453d | Huacai Chen | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ |
129 | d0f7453d | Huacai Chen | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ |
130 | d0f7453d | Huacai Chen | |
131 | d0f7453d | Huacai Chen | /* ICU Configuration Regs - r/w */
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132 | d0f7453d | Huacai Chen | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ |
133 | d0f7453d | Huacai Chen | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ |
134 | d0f7453d | Huacai Chen | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ |
135 | d0f7453d | Huacai Chen | |
136 | d0f7453d | Huacai Chen | /* ICU Enable Regs - IntEn & IntISR are r/o. */
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137 | d0f7453d | Huacai Chen | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ |
138 | d0f7453d | Huacai Chen | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ |
139 | d0f7453d | Huacai Chen | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ |
140 | d0f7453d | Huacai Chen | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ |
141 | d0f7453d | Huacai Chen | |
142 | d0f7453d | Huacai Chen | /* PCI mail boxes */
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143 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL0_OFFSET 0x40 |
144 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL1_OFFSET 0x44 |
145 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL2_OFFSET 0x48 |
146 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL3_OFFSET 0x4c |
147 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ |
148 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ |
149 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ |
150 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ |
151 | d0f7453d | Huacai Chen | |
152 | d0f7453d | Huacai Chen | /* 6. PCI cache */
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153 | d0f7453d | Huacai Chen | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ |
154 | d0f7453d | Huacai Chen | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ |
155 | d0f7453d | Huacai Chen | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ |
156 | d0f7453d | Huacai Chen | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ |
157 | d0f7453d | Huacai Chen | |
158 | d0f7453d | Huacai Chen | /* 7. other*/
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159 | d0f7453d | Huacai Chen | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ |
160 | d0f7453d | Huacai Chen | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ |
161 | d0f7453d | Huacai Chen | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ |
162 | d0f7453d | Huacai Chen | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ |
163 | d0f7453d | Huacai Chen | |
164 | d0f7453d | Huacai Chen | #define BONITO_REGS (0x70 >> 2) |
165 | d0f7453d | Huacai Chen | |
166 | d0f7453d | Huacai Chen | /* PCI config for south bridge. type 0 */
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167 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ |
168 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_IDSEL_OFFSET 11 |
169 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ |
170 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_FUN_OFFSET 8 |
171 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_REG_MASK 0xFC |
172 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_REG_OFFSET 0 |
173 | d0f7453d | Huacai Chen | |
174 | d0f7453d | Huacai Chen | |
175 | d0f7453d | Huacai Chen | /* idsel BIT = pci slot number +12 */
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176 | d0f7453d | Huacai Chen | #define PCI_SLOT_BASE 12 |
177 | d0f7453d | Huacai Chen | #define PCI_IDSEL_VIA686B_BIT (17) |
178 | d0f7453d | Huacai Chen | #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) |
179 | d0f7453d | Huacai Chen | |
180 | d0f7453d | Huacai Chen | #define PCI_ADDR(busno,devno,funno,regno) \
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181 | d0f7453d | Huacai Chen | ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) |
182 | d0f7453d | Huacai Chen | |
183 | c5589ee9 | Andreas Färber | #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" |
184 | c5589ee9 | Andreas Färber | |
185 | c5589ee9 | Andreas Färber | typedef struct BonitoState BonitoState; |
186 | d0f7453d | Huacai Chen | |
187 | d0f7453d | Huacai Chen | typedef struct PCIBonitoState |
188 | d0f7453d | Huacai Chen | { |
189 | d0f7453d | Huacai Chen | PCIDevice dev; |
190 | c5589ee9 | Andreas Färber | |
191 | d0f7453d | Huacai Chen | BonitoState *pcihost; |
192 | d0f7453d | Huacai Chen | uint32_t regs[BONITO_REGS]; |
193 | d0f7453d | Huacai Chen | |
194 | d0f7453d | Huacai Chen | struct bonldma {
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195 | d0f7453d | Huacai Chen | uint32_t ldmactrl; |
196 | d0f7453d | Huacai Chen | uint32_t ldmastat; |
197 | d0f7453d | Huacai Chen | uint32_t ldmaaddr; |
198 | d0f7453d | Huacai Chen | uint32_t ldmago; |
199 | d0f7453d | Huacai Chen | } bonldma; |
200 | d0f7453d | Huacai Chen | |
201 | d0f7453d | Huacai Chen | /* Based at 1fe00300, bonito Copier */
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202 | d0f7453d | Huacai Chen | struct boncop {
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203 | d0f7453d | Huacai Chen | uint32_t copctrl; |
204 | d0f7453d | Huacai Chen | uint32_t copstat; |
205 | d0f7453d | Huacai Chen | uint32_t coppaddr; |
206 | d0f7453d | Huacai Chen | uint32_t copgo; |
207 | d0f7453d | Huacai Chen | } boncop; |
208 | d0f7453d | Huacai Chen | |
209 | d0f7453d | Huacai Chen | /* Bonito registers */
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210 | 89200979 | Benoît Canet | MemoryRegion iomem; |
211 | def344a6 | Benoît Canet | MemoryRegion iomem_ldma; |
212 | 9a542a48 | Benoît Canet | MemoryRegion iomem_cop; |
213 | d0f7453d | Huacai Chen | |
214 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciio_start; |
215 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciio_length; |
216 | d0f7453d | Huacai Chen | int bonito_pciio_handle;
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217 | d0f7453d | Huacai Chen | |
218 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_localio_start; |
219 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_localio_length; |
220 | d0f7453d | Huacai Chen | int bonito_localio_handle;
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221 | d0f7453d | Huacai Chen | |
222 | d0f7453d | Huacai Chen | } PCIBonitoState; |
223 | d0f7453d | Huacai Chen | |
224 | c5589ee9 | Andreas Färber | #define BONITO_PCI_HOST_BRIDGE(obj) \
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225 | c5589ee9 | Andreas Färber | OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) |
226 | c5589ee9 | Andreas Färber | |
227 | c5589ee9 | Andreas Färber | struct BonitoState {
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228 | c5589ee9 | Andreas Färber | PCIHostState parent_obj; |
229 | c5589ee9 | Andreas Färber | |
230 | c5589ee9 | Andreas Färber | qemu_irq *pic; |
231 | c5589ee9 | Andreas Färber | |
232 | c5589ee9 | Andreas Färber | PCIBonitoState *pci_dev; |
233 | c5589ee9 | Andreas Färber | }; |
234 | d0f7453d | Huacai Chen | |
235 | 89200979 | Benoît Canet | static void bonito_writel(void *opaque, target_phys_addr_t addr, |
236 | 89200979 | Benoît Canet | uint64_t val, unsigned size)
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237 | d0f7453d | Huacai Chen | { |
238 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
239 | d0f7453d | Huacai Chen | uint32_t saddr; |
240 | d0f7453d | Huacai Chen | int reset = 0; |
241 | d0f7453d | Huacai Chen | |
242 | d0f7453d | Huacai Chen | saddr = (addr - BONITO_REGBASE) >> 2;
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243 | d0f7453d | Huacai Chen | |
244 | b2bedb21 | Stefan Weil | DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); |
245 | d0f7453d | Huacai Chen | switch (saddr) {
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246 | d0f7453d | Huacai Chen | case BONITO_BONPONCFG:
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247 | d0f7453d | Huacai Chen | case BONITO_IODEVCFG:
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248 | d0f7453d | Huacai Chen | case BONITO_SDCFG:
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249 | d0f7453d | Huacai Chen | case BONITO_PCIMAP:
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250 | d0f7453d | Huacai Chen | case BONITO_PCIMEMBASECFG:
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251 | d0f7453d | Huacai Chen | case BONITO_PCIMAP_CFG:
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252 | d0f7453d | Huacai Chen | case BONITO_GPIODATA:
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253 | d0f7453d | Huacai Chen | case BONITO_GPIOIE:
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254 | d0f7453d | Huacai Chen | case BONITO_INTEDGE:
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255 | d0f7453d | Huacai Chen | case BONITO_INTSTEER:
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256 | d0f7453d | Huacai Chen | case BONITO_INTPOL:
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257 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL0:
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258 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL1:
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259 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL2:
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260 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL3:
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261 | d0f7453d | Huacai Chen | case BONITO_PCICACHECTRL:
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262 | d0f7453d | Huacai Chen | case BONITO_PCICACHETAG:
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263 | d0f7453d | Huacai Chen | case BONITO_PCIBADADDR:
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264 | d0f7453d | Huacai Chen | case BONITO_PCIMSTAT:
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265 | d0f7453d | Huacai Chen | case BONITO_TIMECFG:
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266 | d0f7453d | Huacai Chen | case BONITO_CPUCFG:
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267 | d0f7453d | Huacai Chen | case BONITO_DQCFG:
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268 | d0f7453d | Huacai Chen | case BONITO_MEMSIZE:
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269 | d0f7453d | Huacai Chen | s->regs[saddr] = val; |
270 | d0f7453d | Huacai Chen | break;
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271 | d0f7453d | Huacai Chen | case BONITO_BONGENCFG:
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272 | d0f7453d | Huacai Chen | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { |
273 | d0f7453d | Huacai Chen | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ |
274 | d0f7453d | Huacai Chen | } |
275 | d0f7453d | Huacai Chen | s->regs[saddr] = val; |
276 | d0f7453d | Huacai Chen | if (reset) {
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277 | d0f7453d | Huacai Chen | qemu_system_reset_request(); |
278 | d0f7453d | Huacai Chen | } |
279 | d0f7453d | Huacai Chen | break;
|
280 | d0f7453d | Huacai Chen | case BONITO_INTENSET:
|
281 | d0f7453d | Huacai Chen | s->regs[BONITO_INTENSET] = val; |
282 | d0f7453d | Huacai Chen | s->regs[BONITO_INTEN] |= val; |
283 | d0f7453d | Huacai Chen | break;
|
284 | d0f7453d | Huacai Chen | case BONITO_INTENCLR:
|
285 | d0f7453d | Huacai Chen | s->regs[BONITO_INTENCLR] = val; |
286 | d0f7453d | Huacai Chen | s->regs[BONITO_INTEN] &= ~val; |
287 | d0f7453d | Huacai Chen | break;
|
288 | d0f7453d | Huacai Chen | case BONITO_INTEN:
|
289 | d0f7453d | Huacai Chen | case BONITO_INTISR:
|
290 | b2bedb21 | Stefan Weil | DPRINTF("write to readonly bonito register %x\n", saddr);
|
291 | d0f7453d | Huacai Chen | break;
|
292 | d0f7453d | Huacai Chen | default:
|
293 | b2bedb21 | Stefan Weil | DPRINTF("write to unknown bonito register %x\n", saddr);
|
294 | d0f7453d | Huacai Chen | break;
|
295 | d0f7453d | Huacai Chen | } |
296 | d0f7453d | Huacai Chen | } |
297 | d0f7453d | Huacai Chen | |
298 | 89200979 | Benoît Canet | static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr, |
299 | 89200979 | Benoît Canet | unsigned size)
|
300 | d0f7453d | Huacai Chen | { |
301 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
302 | d0f7453d | Huacai Chen | uint32_t saddr; |
303 | d0f7453d | Huacai Chen | |
304 | d0f7453d | Huacai Chen | saddr = (addr - BONITO_REGBASE) >> 2;
|
305 | d0f7453d | Huacai Chen | |
306 | b2bedb21 | Stefan Weil | DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); |
307 | d0f7453d | Huacai Chen | switch (saddr) {
|
308 | d0f7453d | Huacai Chen | case BONITO_INTISR:
|
309 | d0f7453d | Huacai Chen | return s->regs[saddr];
|
310 | d0f7453d | Huacai Chen | default:
|
311 | d0f7453d | Huacai Chen | return s->regs[saddr];
|
312 | d0f7453d | Huacai Chen | } |
313 | d0f7453d | Huacai Chen | } |
314 | d0f7453d | Huacai Chen | |
315 | 89200979 | Benoît Canet | static const MemoryRegionOps bonito_ops = { |
316 | 89200979 | Benoît Canet | .read = bonito_readl, |
317 | 89200979 | Benoît Canet | .write = bonito_writel, |
318 | 89200979 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
319 | 89200979 | Benoît Canet | .valid = { |
320 | 89200979 | Benoît Canet | .min_access_size = 4,
|
321 | 89200979 | Benoît Canet | .max_access_size = 4,
|
322 | 89200979 | Benoît Canet | }, |
323 | d0f7453d | Huacai Chen | }; |
324 | d0f7453d | Huacai Chen | |
325 | d0f7453d | Huacai Chen | static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, |
326 | 183e1d40 | Benoît Canet | uint64_t val, unsigned size)
|
327 | d0f7453d | Huacai Chen | { |
328 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
329 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
330 | d0f7453d | Huacai Chen | |
331 | b2bedb21 | Stefan Weil | DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
332 | c5589ee9 | Andreas Färber | d->config_write(d, addr, val, 4);
|
333 | d0f7453d | Huacai Chen | } |
334 | d0f7453d | Huacai Chen | |
335 | 183e1d40 | Benoît Canet | static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr, |
336 | 183e1d40 | Benoît Canet | unsigned size)
|
337 | d0f7453d | Huacai Chen | { |
338 | d0f7453d | Huacai Chen | |
339 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
340 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
341 | d0f7453d | Huacai Chen | |
342 | d0f7453d | Huacai Chen | DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); |
343 | c5589ee9 | Andreas Färber | return d->config_read(d, addr, 4); |
344 | d0f7453d | Huacai Chen | } |
345 | d0f7453d | Huacai Chen | |
346 | d0f7453d | Huacai Chen | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
|
347 | d0f7453d | Huacai Chen | |
348 | 183e1d40 | Benoît Canet | static const MemoryRegionOps bonito_pciconf_ops = { |
349 | 183e1d40 | Benoît Canet | .read = bonito_pciconf_readl, |
350 | 183e1d40 | Benoît Canet | .write = bonito_pciconf_writel, |
351 | 183e1d40 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
352 | 183e1d40 | Benoît Canet | .valid = { |
353 | 183e1d40 | Benoît Canet | .min_access_size = 4,
|
354 | 183e1d40 | Benoît Canet | .max_access_size = 4,
|
355 | 183e1d40 | Benoît Canet | }, |
356 | d0f7453d | Huacai Chen | }; |
357 | d0f7453d | Huacai Chen | |
358 | def344a6 | Benoît Canet | static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr, |
359 | def344a6 | Benoît Canet | unsigned size)
|
360 | d0f7453d | Huacai Chen | { |
361 | d0f7453d | Huacai Chen | uint32_t val; |
362 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
363 | d0f7453d | Huacai Chen | |
364 | d0f7453d | Huacai Chen | val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
|
365 | d0f7453d | Huacai Chen | |
366 | d0f7453d | Huacai Chen | return val;
|
367 | d0f7453d | Huacai Chen | } |
368 | d0f7453d | Huacai Chen | |
369 | d0f7453d | Huacai Chen | static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr, |
370 | def344a6 | Benoît Canet | uint64_t val, unsigned size)
|
371 | d0f7453d | Huacai Chen | { |
372 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
373 | d0f7453d | Huacai Chen | |
374 | d0f7453d | Huacai Chen | ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; |
375 | d0f7453d | Huacai Chen | } |
376 | d0f7453d | Huacai Chen | |
377 | def344a6 | Benoît Canet | static const MemoryRegionOps bonito_ldma_ops = { |
378 | def344a6 | Benoît Canet | .read = bonito_ldma_readl, |
379 | def344a6 | Benoît Canet | .write = bonito_ldma_writel, |
380 | def344a6 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
381 | def344a6 | Benoît Canet | .valid = { |
382 | def344a6 | Benoît Canet | .min_access_size = 4,
|
383 | def344a6 | Benoît Canet | .max_access_size = 4,
|
384 | def344a6 | Benoît Canet | }, |
385 | d0f7453d | Huacai Chen | }; |
386 | d0f7453d | Huacai Chen | |
387 | 9a542a48 | Benoît Canet | static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr, |
388 | 9a542a48 | Benoît Canet | unsigned size)
|
389 | d0f7453d | Huacai Chen | { |
390 | d0f7453d | Huacai Chen | uint32_t val; |
391 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
392 | d0f7453d | Huacai Chen | |
393 | d0f7453d | Huacai Chen | val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
|
394 | d0f7453d | Huacai Chen | |
395 | d0f7453d | Huacai Chen | return val;
|
396 | d0f7453d | Huacai Chen | } |
397 | d0f7453d | Huacai Chen | |
398 | d0f7453d | Huacai Chen | static void bonito_cop_writel(void *opaque, target_phys_addr_t addr, |
399 | 9a542a48 | Benoît Canet | uint64_t val, unsigned size)
|
400 | d0f7453d | Huacai Chen | { |
401 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
402 | d0f7453d | Huacai Chen | |
403 | d0f7453d | Huacai Chen | ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; |
404 | d0f7453d | Huacai Chen | } |
405 | d0f7453d | Huacai Chen | |
406 | 9a542a48 | Benoît Canet | static const MemoryRegionOps bonito_cop_ops = { |
407 | 9a542a48 | Benoît Canet | .read = bonito_cop_readl, |
408 | 9a542a48 | Benoît Canet | .write = bonito_cop_writel, |
409 | 9a542a48 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
410 | 9a542a48 | Benoît Canet | .valid = { |
411 | 9a542a48 | Benoît Canet | .min_access_size = 4,
|
412 | 9a542a48 | Benoît Canet | .max_access_size = 4,
|
413 | 9a542a48 | Benoît Canet | }, |
414 | d0f7453d | Huacai Chen | }; |
415 | d0f7453d | Huacai Chen | |
416 | d0f7453d | Huacai Chen | static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) |
417 | d0f7453d | Huacai Chen | { |
418 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
419 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
420 | d0f7453d | Huacai Chen | uint32_t cfgaddr; |
421 | d0f7453d | Huacai Chen | uint32_t idsel; |
422 | d0f7453d | Huacai Chen | uint32_t devno; |
423 | d0f7453d | Huacai Chen | uint32_t funno; |
424 | d0f7453d | Huacai Chen | uint32_t regno; |
425 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
426 | d0f7453d | Huacai Chen | |
427 | d0f7453d | Huacai Chen | /* support type0 pci config */
|
428 | d0f7453d | Huacai Chen | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { |
429 | d0f7453d | Huacai Chen | return 0xffffffff; |
430 | d0f7453d | Huacai Chen | } |
431 | d0f7453d | Huacai Chen | |
432 | d0f7453d | Huacai Chen | cfgaddr = addr & 0xffff;
|
433 | d0f7453d | Huacai Chen | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; |
434 | d0f7453d | Huacai Chen | |
435 | d0f7453d | Huacai Chen | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; |
436 | d0f7453d | Huacai Chen | devno = ffs(idsel) - 1;
|
437 | d0f7453d | Huacai Chen | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; |
438 | d0f7453d | Huacai Chen | regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; |
439 | d0f7453d | Huacai Chen | |
440 | d0f7453d | Huacai Chen | if (idsel == 0) { |
441 | c5589ee9 | Andreas Färber | fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx
|
442 | d0f7453d | Huacai Chen | ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
|
443 | d0f7453d | Huacai Chen | exit(1);
|
444 | d0f7453d | Huacai Chen | } |
445 | c5589ee9 | Andreas Färber | pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); |
446 | b2bedb21 | Stefan Weil | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
|
447 | c5589ee9 | Andreas Färber | cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); |
448 | d0f7453d | Huacai Chen | |
449 | d0f7453d | Huacai Chen | return pciaddr;
|
450 | d0f7453d | Huacai Chen | } |
451 | d0f7453d | Huacai Chen | |
452 | d0f7453d | Huacai Chen | static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr, |
453 | d0f7453d | Huacai Chen | uint32_t val) |
454 | d0f7453d | Huacai Chen | { |
455 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
456 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
457 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
458 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
459 | d0f7453d | Huacai Chen | uint16_t status; |
460 | d0f7453d | Huacai Chen | |
461 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); |
462 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
463 | d0f7453d | Huacai Chen | |
464 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
465 | d0f7453d | Huacai Chen | return;
|
466 | d0f7453d | Huacai Chen | } |
467 | d0f7453d | Huacai Chen | |
468 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
469 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
470 | c5589ee9 | Andreas Färber | pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1); |
471 | d0f7453d | Huacai Chen | |
472 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
473 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
474 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
475 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
476 | d0f7453d | Huacai Chen | } |
477 | d0f7453d | Huacai Chen | |
478 | d0f7453d | Huacai Chen | static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr, |
479 | d0f7453d | Huacai Chen | uint32_t val) |
480 | d0f7453d | Huacai Chen | { |
481 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
482 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
483 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
484 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
485 | d0f7453d | Huacai Chen | uint16_t status; |
486 | d0f7453d | Huacai Chen | |
487 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); |
488 | c5589ee9 | Andreas Färber | assert((addr & 0x1) == 0); |
489 | d0f7453d | Huacai Chen | |
490 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
491 | d0f7453d | Huacai Chen | |
492 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
493 | d0f7453d | Huacai Chen | return;
|
494 | d0f7453d | Huacai Chen | } |
495 | d0f7453d | Huacai Chen | |
496 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
497 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
498 | c5589ee9 | Andreas Färber | pci_data_write(phb->bus, phb->config_reg, val, 2);
|
499 | d0f7453d | Huacai Chen | |
500 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
501 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
502 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
503 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
504 | d0f7453d | Huacai Chen | } |
505 | d0f7453d | Huacai Chen | |
506 | d0f7453d | Huacai Chen | static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, |
507 | d0f7453d | Huacai Chen | uint32_t val) |
508 | d0f7453d | Huacai Chen | { |
509 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
510 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
511 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
512 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
513 | d0f7453d | Huacai Chen | uint16_t status; |
514 | d0f7453d | Huacai Chen | |
515 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
516 | c5589ee9 | Andreas Färber | assert((addr & 0x3) == 0); |
517 | d0f7453d | Huacai Chen | |
518 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
519 | d0f7453d | Huacai Chen | |
520 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
521 | d0f7453d | Huacai Chen | return;
|
522 | d0f7453d | Huacai Chen | } |
523 | d0f7453d | Huacai Chen | |
524 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
525 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
526 | c5589ee9 | Andreas Färber | pci_data_write(phb->bus, phb->config_reg, val, 4);
|
527 | d0f7453d | Huacai Chen | |
528 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
529 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
530 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
531 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
532 | d0f7453d | Huacai Chen | } |
533 | d0f7453d | Huacai Chen | |
534 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr) |
535 | d0f7453d | Huacai Chen | { |
536 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
537 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
538 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
539 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
540 | d0f7453d | Huacai Chen | uint16_t status; |
541 | d0f7453d | Huacai Chen | |
542 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); |
543 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
544 | d0f7453d | Huacai Chen | |
545 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
546 | d0f7453d | Huacai Chen | return 0xff; |
547 | d0f7453d | Huacai Chen | } |
548 | d0f7453d | Huacai Chen | |
549 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
550 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
551 | d0f7453d | Huacai Chen | |
552 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
553 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
554 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
555 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
556 | d0f7453d | Huacai Chen | |
557 | c5589ee9 | Andreas Färber | return pci_data_read(phb->bus, phb->config_reg, 1); |
558 | d0f7453d | Huacai Chen | } |
559 | d0f7453d | Huacai Chen | |
560 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr) |
561 | d0f7453d | Huacai Chen | { |
562 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
563 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
564 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
565 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
566 | d0f7453d | Huacai Chen | uint16_t status; |
567 | d0f7453d | Huacai Chen | |
568 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); |
569 | c5589ee9 | Andreas Färber | assert((addr & 0x1) == 0); |
570 | d0f7453d | Huacai Chen | |
571 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
572 | d0f7453d | Huacai Chen | |
573 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
574 | d0f7453d | Huacai Chen | return 0xffff; |
575 | d0f7453d | Huacai Chen | } |
576 | d0f7453d | Huacai Chen | |
577 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
578 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
579 | d0f7453d | Huacai Chen | |
580 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
581 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
582 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
583 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
584 | d0f7453d | Huacai Chen | |
585 | c5589ee9 | Andreas Färber | return pci_data_read(phb->bus, phb->config_reg, 2); |
586 | d0f7453d | Huacai Chen | } |
587 | d0f7453d | Huacai Chen | |
588 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) |
589 | d0f7453d | Huacai Chen | { |
590 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
591 | c5589ee9 | Andreas Färber | PCIDevice *d = PCI_DEVICE(s); |
592 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(s->pcihost)); |
593 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
594 | d0f7453d | Huacai Chen | uint16_t status; |
595 | d0f7453d | Huacai Chen | |
596 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); |
597 | c5589ee9 | Andreas Färber | assert((addr & 0x3) == 0); |
598 | d0f7453d | Huacai Chen | |
599 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
600 | d0f7453d | Huacai Chen | |
601 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
602 | d0f7453d | Huacai Chen | return 0xffffffff; |
603 | d0f7453d | Huacai Chen | } |
604 | d0f7453d | Huacai Chen | |
605 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
606 | c5589ee9 | Andreas Färber | phb->config_reg = (pciaddr) | (1u << 31); |
607 | d0f7453d | Huacai Chen | |
608 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
609 | c5589ee9 | Andreas Färber | status = pci_get_word(d->config + PCI_STATUS); |
610 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
611 | c5589ee9 | Andreas Färber | pci_set_word(d->config + PCI_STATUS, status); |
612 | d0f7453d | Huacai Chen | |
613 | c5589ee9 | Andreas Färber | return pci_data_read(phb->bus, phb->config_reg, 4); |
614 | d0f7453d | Huacai Chen | } |
615 | d0f7453d | Huacai Chen | |
616 | d0f7453d | Huacai Chen | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
|
617 | 845cbeb8 | Benoît Canet | static const MemoryRegionOps bonito_spciconf_ops = { |
618 | 845cbeb8 | Benoît Canet | .old_mmio = { |
619 | 845cbeb8 | Benoît Canet | .read = { |
620 | 845cbeb8 | Benoît Canet | bonito_spciconf_readb, |
621 | 845cbeb8 | Benoît Canet | bonito_spciconf_readw, |
622 | 845cbeb8 | Benoît Canet | bonito_spciconf_readl, |
623 | 845cbeb8 | Benoît Canet | }, |
624 | 845cbeb8 | Benoît Canet | .write = { |
625 | 845cbeb8 | Benoît Canet | bonito_spciconf_writeb, |
626 | 845cbeb8 | Benoît Canet | bonito_spciconf_writew, |
627 | 845cbeb8 | Benoît Canet | bonito_spciconf_writel, |
628 | 845cbeb8 | Benoît Canet | }, |
629 | 845cbeb8 | Benoît Canet | }, |
630 | 845cbeb8 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
631 | d0f7453d | Huacai Chen | }; |
632 | d0f7453d | Huacai Chen | |
633 | d0f7453d | Huacai Chen | #define BONITO_IRQ_BASE 32 |
634 | d0f7453d | Huacai Chen | |
635 | d0f7453d | Huacai Chen | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) |
636 | d0f7453d | Huacai Chen | { |
637 | c5589ee9 | Andreas Färber | BonitoState *s = opaque; |
638 | c5589ee9 | Andreas Färber | qemu_irq *pic = s->pic; |
639 | c5589ee9 | Andreas Färber | PCIBonitoState *bonito_state = s->pci_dev; |
640 | d0f7453d | Huacai Chen | int internal_irq = irq_num - BONITO_IRQ_BASE;
|
641 | d0f7453d | Huacai Chen | |
642 | c5589ee9 | Andreas Färber | if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { |
643 | d0f7453d | Huacai Chen | qemu_irq_pulse(*pic); |
644 | d0f7453d | Huacai Chen | } else { /* level triggered */ |
645 | c5589ee9 | Andreas Färber | if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { |
646 | d0f7453d | Huacai Chen | qemu_irq_raise(*pic); |
647 | d0f7453d | Huacai Chen | } else {
|
648 | d0f7453d | Huacai Chen | qemu_irq_lower(*pic); |
649 | d0f7453d | Huacai Chen | } |
650 | d0f7453d | Huacai Chen | } |
651 | d0f7453d | Huacai Chen | } |
652 | d0f7453d | Huacai Chen | |
653 | d0f7453d | Huacai Chen | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
|
654 | d0f7453d | Huacai Chen | static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) |
655 | d0f7453d | Huacai Chen | { |
656 | d0f7453d | Huacai Chen | int slot;
|
657 | d0f7453d | Huacai Chen | |
658 | d0f7453d | Huacai Chen | slot = (pci_dev->devfn >> 3);
|
659 | d0f7453d | Huacai Chen | |
660 | d0f7453d | Huacai Chen | switch (slot) {
|
661 | d0f7453d | Huacai Chen | case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ |
662 | d0f7453d | Huacai Chen | return irq_num % 4 + BONITO_IRQ_BASE; |
663 | d0f7453d | Huacai Chen | case 6: /* FULONG2E_ATI_SLOT, VGA */ |
664 | d0f7453d | Huacai Chen | return 4 + BONITO_IRQ_BASE; |
665 | d0f7453d | Huacai Chen | case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ |
666 | d0f7453d | Huacai Chen | return 5 + BONITO_IRQ_BASE; |
667 | d0f7453d | Huacai Chen | case 8 ... 12: /* PCI slot 1 to 4 */ |
668 | d0f7453d | Huacai Chen | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; |
669 | d0f7453d | Huacai Chen | default: /* Unknown device, don't do any translation */ |
670 | d0f7453d | Huacai Chen | return irq_num;
|
671 | d0f7453d | Huacai Chen | } |
672 | d0f7453d | Huacai Chen | } |
673 | d0f7453d | Huacai Chen | |
674 | d0f7453d | Huacai Chen | static void bonito_reset(void *opaque) |
675 | d0f7453d | Huacai Chen | { |
676 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
677 | d0f7453d | Huacai Chen | |
678 | d0f7453d | Huacai Chen | /* set the default value of north bridge registers */
|
679 | d0f7453d | Huacai Chen | |
680 | d0f7453d | Huacai Chen | s->regs[BONITO_BONPONCFG] = 0xc40;
|
681 | d0f7453d | Huacai Chen | s->regs[BONITO_BONGENCFG] = 0x1384;
|
682 | d0f7453d | Huacai Chen | s->regs[BONITO_IODEVCFG] = 0x2bff8010;
|
683 | d0f7453d | Huacai Chen | s->regs[BONITO_SDCFG] = 0x255e0091;
|
684 | d0f7453d | Huacai Chen | |
685 | d0f7453d | Huacai Chen | s->regs[BONITO_GPIODATA] = 0x1ff;
|
686 | d0f7453d | Huacai Chen | s->regs[BONITO_GPIOIE] = 0x1ff;
|
687 | d0f7453d | Huacai Chen | s->regs[BONITO_DQCFG] = 0x8;
|
688 | d0f7453d | Huacai Chen | s->regs[BONITO_MEMSIZE] = 0x10000000;
|
689 | d0f7453d | Huacai Chen | s->regs[BONITO_PCIMAP] = 0x6140;
|
690 | d0f7453d | Huacai Chen | } |
691 | d0f7453d | Huacai Chen | |
692 | d0f7453d | Huacai Chen | static const VMStateDescription vmstate_bonito = { |
693 | d0f7453d | Huacai Chen | .name = "Bonito",
|
694 | d0f7453d | Huacai Chen | .version_id = 1,
|
695 | d0f7453d | Huacai Chen | .minimum_version_id = 1,
|
696 | d0f7453d | Huacai Chen | .minimum_version_id_old = 1,
|
697 | d0f7453d | Huacai Chen | .fields = (VMStateField []) { |
698 | d0f7453d | Huacai Chen | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), |
699 | d0f7453d | Huacai Chen | VMSTATE_END_OF_LIST() |
700 | d0f7453d | Huacai Chen | } |
701 | d0f7453d | Huacai Chen | }; |
702 | d0f7453d | Huacai Chen | |
703 | d0f7453d | Huacai Chen | static int bonito_pcihost_initfn(SysBusDevice *dev) |
704 | d0f7453d | Huacai Chen | { |
705 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, dev); |
706 | c5589ee9 | Andreas Färber | |
707 | c5589ee9 | Andreas Färber | phb->bus = pci_register_bus(DEVICE(dev), "pci",
|
708 | c5589ee9 | Andreas Färber | pci_bonito_set_irq, pci_bonito_map_irq, dev, |
709 | c5589ee9 | Andreas Färber | get_system_memory(), get_system_io(), |
710 | c5589ee9 | Andreas Färber | 0x28, 32); |
711 | c5589ee9 | Andreas Färber | |
712 | d0f7453d | Huacai Chen | return 0; |
713 | d0f7453d | Huacai Chen | } |
714 | d0f7453d | Huacai Chen | |
715 | d0f7453d | Huacai Chen | static int bonito_initfn(PCIDevice *dev) |
716 | d0f7453d | Huacai Chen | { |
717 | d0f7453d | Huacai Chen | PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); |
718 | c5589ee9 | Andreas Färber | SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); |
719 | c5589ee9 | Andreas Färber | PCIHostState *phb = FROM_SYSBUS(PCIHostState, sysbus); |
720 | d0f7453d | Huacai Chen | |
721 | d0f7453d | Huacai Chen | /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
|
722 | d0f7453d | Huacai Chen | pci_config_set_prog_interface(dev->config, 0x00);
|
723 | d0f7453d | Huacai Chen | |
724 | d0f7453d | Huacai Chen | /* set the north bridge register mapping */
|
725 | 89200979 | Benoît Canet | memory_region_init_io(&s->iomem, &bonito_ops, s, |
726 | 89200979 | Benoît Canet | "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
|
727 | 750ecd44 | Avi Kivity | sysbus_init_mmio(sysbus, &s->iomem); |
728 | 89200979 | Benoît Canet | sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
|
729 | d0f7453d | Huacai Chen | |
730 | d0f7453d | Huacai Chen | /* set the north bridge pci configure mapping */
|
731 | c5589ee9 | Andreas Färber | memory_region_init_io(&phb->conf_mem, &bonito_pciconf_ops, s, |
732 | 183e1d40 | Benoît Canet | "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
|
733 | c5589ee9 | Andreas Färber | sysbus_init_mmio(sysbus, &phb->conf_mem); |
734 | 183e1d40 | Benoît Canet | sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
|
735 | d0f7453d | Huacai Chen | |
736 | d0f7453d | Huacai Chen | /* set the south bridge pci configure mapping */
|
737 | c5589ee9 | Andreas Färber | memory_region_init_io(&phb->data_mem, &bonito_spciconf_ops, s, |
738 | 845cbeb8 | Benoît Canet | "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
|
739 | c5589ee9 | Andreas Färber | sysbus_init_mmio(sysbus, &phb->data_mem); |
740 | 845cbeb8 | Benoît Canet | sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
|
741 | d0f7453d | Huacai Chen | |
742 | def344a6 | Benoît Canet | memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s, |
743 | def344a6 | Benoît Canet | "ldma", 0x100); |
744 | 750ecd44 | Avi Kivity | sysbus_init_mmio(sysbus, &s->iomem_ldma); |
745 | def344a6 | Benoît Canet | sysbus_mmio_map(sysbus, 3, 0xbfe00200); |
746 | d0f7453d | Huacai Chen | |
747 | 9a542a48 | Benoît Canet | memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s, |
748 | 9a542a48 | Benoît Canet | "cop", 0x100); |
749 | 750ecd44 | Avi Kivity | sysbus_init_mmio(sysbus, &s->iomem_cop); |
750 | 9a542a48 | Benoît Canet | sysbus_mmio_map(sysbus, 4, 0xbfe00300); |
751 | d0f7453d | Huacai Chen | |
752 | d0f7453d | Huacai Chen | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
|
753 | d0f7453d | Huacai Chen | s->bonito_pciio_start = BONITO_PCIIO_BASE; |
754 | d0f7453d | Huacai Chen | s->bonito_pciio_length = BONITO_PCIIO_SIZE; |
755 | d0f7453d | Huacai Chen | isa_mem_base = s->bonito_pciio_start; |
756 | 968d683c | Alexander Graf | isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); |
757 | d0f7453d | Huacai Chen | |
758 | d0f7453d | Huacai Chen | /* add pci local io mapping */
|
759 | d0f7453d | Huacai Chen | s->bonito_localio_start = BONITO_DEV_BASE; |
760 | d0f7453d | Huacai Chen | s->bonito_localio_length = BONITO_DEV_SIZE; |
761 | 968d683c | Alexander Graf | isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); |
762 | d0f7453d | Huacai Chen | |
763 | d0f7453d | Huacai Chen | /* set the default value of north bridge pci config */
|
764 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_COMMAND, 0x0000);
|
765 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_STATUS, 0x0000);
|
766 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
|
767 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
|
768 | d0f7453d | Huacai Chen | |
769 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
|
770 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
|
771 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
|
772 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
|
773 | d0f7453d | Huacai Chen | |
774 | d0f7453d | Huacai Chen | qemu_register_reset(bonito_reset, s); |
775 | d0f7453d | Huacai Chen | |
776 | d0f7453d | Huacai Chen | return 0; |
777 | d0f7453d | Huacai Chen | } |
778 | d0f7453d | Huacai Chen | |
779 | d0f7453d | Huacai Chen | PCIBus *bonito_init(qemu_irq *pic) |
780 | d0f7453d | Huacai Chen | { |
781 | d0f7453d | Huacai Chen | DeviceState *dev; |
782 | d0f7453d | Huacai Chen | BonitoState *pcihost; |
783 | c5589ee9 | Andreas Färber | PCIHostState *phb; |
784 | d0f7453d | Huacai Chen | PCIBonitoState *s; |
785 | d0f7453d | Huacai Chen | PCIDevice *d; |
786 | d0f7453d | Huacai Chen | |
787 | c5589ee9 | Andreas Färber | dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE);
|
788 | c5589ee9 | Andreas Färber | phb = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
789 | c5589ee9 | Andreas Färber | pcihost = BONITO_PCI_HOST_BRIDGE(dev); |
790 | c5589ee9 | Andreas Färber | pcihost->pic = pic; |
791 | d0f7453d | Huacai Chen | qdev_init_nofail(dev); |
792 | d0f7453d | Huacai Chen | |
793 | 89200979 | Benoît Canet | /* set the pcihost pointer before bonito_initfn is called */
|
794 | c5589ee9 | Andreas Färber | d = pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito"); |
795 | d0f7453d | Huacai Chen | s = DO_UPCAST(PCIBonitoState, dev, d); |
796 | d0f7453d | Huacai Chen | s->pcihost = pcihost; |
797 | c5589ee9 | Andreas Färber | pcihost->pci_dev = s; |
798 | c5589ee9 | Andreas Färber | qdev_init_nofail(DEVICE(d)); |
799 | d0f7453d | Huacai Chen | |
800 | c5589ee9 | Andreas Färber | return phb->bus;
|
801 | d0f7453d | Huacai Chen | } |
802 | d0f7453d | Huacai Chen | |
803 | 40021f08 | Anthony Liguori | static void bonito_class_init(ObjectClass *klass, void *data) |
804 | 40021f08 | Anthony Liguori | { |
805 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
806 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
807 | 40021f08 | Anthony Liguori | |
808 | 40021f08 | Anthony Liguori | k->init = bonito_initfn; |
809 | 40021f08 | Anthony Liguori | k->vendor_id = 0xdf53;
|
810 | 40021f08 | Anthony Liguori | k->device_id = 0x00d5;
|
811 | 40021f08 | Anthony Liguori | k->revision = 0x01;
|
812 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_BRIDGE_HOST; |
813 | 39bffca2 | Anthony Liguori | dc->desc = "Host bridge";
|
814 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
815 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_bonito; |
816 | 40021f08 | Anthony Liguori | } |
817 | 40021f08 | Anthony Liguori | |
818 | 4240abff | Andreas Färber | static const TypeInfo bonito_info = { |
819 | 39bffca2 | Anthony Liguori | .name = "Bonito",
|
820 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
821 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIBonitoState),
|
822 | 39bffca2 | Anthony Liguori | .class_init = bonito_class_init, |
823 | d0f7453d | Huacai Chen | }; |
824 | d0f7453d | Huacai Chen | |
825 | 999e12bb | Anthony Liguori | static void bonito_pcihost_class_init(ObjectClass *klass, void *data) |
826 | 999e12bb | Anthony Liguori | { |
827 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
828 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
829 | 999e12bb | Anthony Liguori | |
830 | 999e12bb | Anthony Liguori | k->init = bonito_pcihost_initfn; |
831 | 39bffca2 | Anthony Liguori | dc->no_user = 1;
|
832 | 999e12bb | Anthony Liguori | } |
833 | 999e12bb | Anthony Liguori | |
834 | 4240abff | Andreas Färber | static const TypeInfo bonito_pcihost_info = { |
835 | c5589ee9 | Andreas Färber | .name = TYPE_BONITO_PCI_HOST_BRIDGE, |
836 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
837 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(BonitoState),
|
838 | 39bffca2 | Anthony Liguori | .class_init = bonito_pcihost_class_init, |
839 | d0f7453d | Huacai Chen | }; |
840 | d0f7453d | Huacai Chen | |
841 | 83f7d43a | Andreas Färber | static void bonito_register_types(void) |
842 | d0f7453d | Huacai Chen | { |
843 | 39bffca2 | Anthony Liguori | type_register_static(&bonito_pcihost_info); |
844 | 39bffca2 | Anthony Liguori | type_register_static(&bonito_info); |
845 | d0f7453d | Huacai Chen | } |
846 | 83f7d43a | Andreas Färber | |
847 | 83f7d43a | Andreas Färber | type_init(bonito_register_types) |