root / hw / grlib.h @ 03a6b667
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/*
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* QEMU GRLIB Components
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef _GRLIB_H_
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#define _GRLIB_H_
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#include "qdev.h" |
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#include "sysbus.h" |
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/* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
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* http://www.gaisler.com/products/grlib/grip.pdf
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*/
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/* IRQMP */
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typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in); |
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void grlib_irqmp_set_irq(void *opaque, int irq, int level); |
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void grlib_irqmp_ack(DeviceState *dev, int intno); |
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static inline |
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DeviceState *grlib_irqmp_create(target_phys_addr_t base, |
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CPUSPARCState *env, |
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qemu_irq **cpu_irqs, |
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uint32_t nr_irqs, |
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set_pil_in_fn set_pil_in) |
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{ |
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DeviceState *dev; |
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assert(cpu_irqs != NULL);
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dev = qdev_create(NULL, "grlib,irqmp"); |
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qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
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qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
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if (qdev_init(dev)) {
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return NULL; |
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} |
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env->irq_manager = dev; |
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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*cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, |
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dev, |
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nr_irqs); |
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return dev;
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} |
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/* GPTimer */
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static inline |
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DeviceState *grlib_gptimer_create(target_phys_addr_t base, |
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uint32_t nr_timers, |
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uint32_t freq, |
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qemu_irq *cpu_irqs, |
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int base_irq)
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{ |
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DeviceState *dev; |
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int i;
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dev = qdev_create(NULL, "grlib,gptimer"); |
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qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
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qdev_prop_set_uint32(dev, "frequency", freq);
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qdev_prop_set_uint32(dev, "irq-line", base_irq);
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if (qdev_init(dev)) {
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return NULL; |
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} |
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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for (i = 0; i < nr_timers; i++) { |
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sysbus_connect_irq(sysbus_from_qdev(dev), i, cpu_irqs[base_irq + i]); |
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} |
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return dev;
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} |
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/* APB UART */
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static inline |
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DeviceState *grlib_apbuart_create(target_phys_addr_t base, |
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CharDriverState *serial, |
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qemu_irq irq) |
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{ |
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DeviceState *dev; |
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dev = qdev_create(NULL, "grlib,apbuart"); |
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qdev_prop_set_chr(dev, "chrdev", serial);
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if (qdev_init(dev)) {
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return NULL; |
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} |
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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} |
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#endif /* ! _GRLIB_H_ */ |