root / hw / gt64xxx.c @ 03a6b667
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/*
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* QEMU GT64120 PCI host
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*
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* Copyright (c) 2006,2007 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "mips.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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#include "pc.h" |
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#include "exec-memory.h" |
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|
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//#define DEBUG
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#ifdef DEBUG
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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|
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#define GT_REGS (0x1000 >> 2) |
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|
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/* CPU Configuration */
|
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#define GT_CPU (0x000 >> 2) |
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#define GT_MULTI (0x120 >> 2) |
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|
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/* CPU Address Decode */
|
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#define GT_SCS10LD (0x008 >> 2) |
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#define GT_SCS10HD (0x010 >> 2) |
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#define GT_SCS32LD (0x018 >> 2) |
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#define GT_SCS32HD (0x020 >> 2) |
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#define GT_CS20LD (0x028 >> 2) |
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#define GT_CS20HD (0x030 >> 2) |
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#define GT_CS3BOOTLD (0x038 >> 2) |
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#define GT_CS3BOOTHD (0x040 >> 2) |
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#define GT_PCI0IOLD (0x048 >> 2) |
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#define GT_PCI0IOHD (0x050 >> 2) |
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#define GT_PCI0M0LD (0x058 >> 2) |
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#define GT_PCI0M0HD (0x060 >> 2) |
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#define GT_PCI0M1LD (0x080 >> 2) |
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#define GT_PCI0M1HD (0x088 >> 2) |
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#define GT_PCI1IOLD (0x090 >> 2) |
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#define GT_PCI1IOHD (0x098 >> 2) |
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#define GT_PCI1M0LD (0x0a0 >> 2) |
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#define GT_PCI1M0HD (0x0a8 >> 2) |
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#define GT_PCI1M1LD (0x0b0 >> 2) |
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#define GT_PCI1M1HD (0x0b8 >> 2) |
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#define GT_ISD (0x068 >> 2) |
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|
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#define GT_SCS10AR (0x0d0 >> 2) |
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#define GT_SCS32AR (0x0d8 >> 2) |
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#define GT_CS20R (0x0e0 >> 2) |
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#define GT_CS3BOOTR (0x0e8 >> 2) |
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|
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#define GT_PCI0IOREMAP (0x0f0 >> 2) |
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#define GT_PCI0M0REMAP (0x0f8 >> 2) |
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#define GT_PCI0M1REMAP (0x100 >> 2) |
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#define GT_PCI1IOREMAP (0x108 >> 2) |
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#define GT_PCI1M0REMAP (0x110 >> 2) |
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#define GT_PCI1M1REMAP (0x118 >> 2) |
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|
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/* CPU Error Report */
|
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#define GT_CPUERR_ADDRLO (0x070 >> 2) |
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#define GT_CPUERR_ADDRHI (0x078 >> 2) |
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#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
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|
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/* CPU Sync Barrier */
|
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#define GT_PCI0SYNC (0x0c0 >> 2) |
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#define GT_PCI1SYNC (0x0c8 >> 2) |
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|
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/* SDRAM and Device Address Decode */
|
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#define GT_SCS0LD (0x400 >> 2) |
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#define GT_SCS0HD (0x404 >> 2) |
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#define GT_SCS1LD (0x408 >> 2) |
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#define GT_SCS1HD (0x40c >> 2) |
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#define GT_SCS2LD (0x410 >> 2) |
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#define GT_SCS2HD (0x414 >> 2) |
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#define GT_SCS3LD (0x418 >> 2) |
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#define GT_SCS3HD (0x41c >> 2) |
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#define GT_CS0LD (0x420 >> 2) |
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#define GT_CS0HD (0x424 >> 2) |
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#define GT_CS1LD (0x428 >> 2) |
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#define GT_CS1HD (0x42c >> 2) |
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#define GT_CS2LD (0x430 >> 2) |
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#define GT_CS2HD (0x434 >> 2) |
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#define GT_CS3LD (0x438 >> 2) |
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#define GT_CS3HD (0x43c >> 2) |
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#define GT_BOOTLD (0x440 >> 2) |
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#define GT_BOOTHD (0x444 >> 2) |
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#define GT_ADERR (0x470 >> 2) |
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|
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/* SDRAM Configuration */
|
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#define GT_SDRAM_CFG (0x448 >> 2) |
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#define GT_SDRAM_OPMODE (0x474 >> 2) |
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#define GT_SDRAM_BM (0x478 >> 2) |
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#define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
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|
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/* SDRAM Parameters */
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#define GT_SDRAM_B0 (0x44c >> 2) |
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#define GT_SDRAM_B1 (0x450 >> 2) |
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#define GT_SDRAM_B2 (0x454 >> 2) |
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#define GT_SDRAM_B3 (0x458 >> 2) |
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|
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/* Device Parameters */
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#define GT_DEV_B0 (0x45c >> 2) |
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#define GT_DEV_B1 (0x460 >> 2) |
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#define GT_DEV_B2 (0x464 >> 2) |
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#define GT_DEV_B3 (0x468 >> 2) |
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#define GT_DEV_BOOT (0x46c >> 2) |
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|
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/* ECC */
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#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
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#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
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#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
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|
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/* DMA Record */
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#define GT_DMA0_CNT (0x800 >> 2) |
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#define GT_DMA1_CNT (0x804 >> 2) |
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#define GT_DMA2_CNT (0x808 >> 2) |
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#define GT_DMA3_CNT (0x80c >> 2) |
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#define GT_DMA0_SA (0x810 >> 2) |
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#define GT_DMA1_SA (0x814 >> 2) |
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#define GT_DMA2_SA (0x818 >> 2) |
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#define GT_DMA3_SA (0x81c >> 2) |
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#define GT_DMA0_DA (0x820 >> 2) |
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#define GT_DMA1_DA (0x824 >> 2) |
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#define GT_DMA2_DA (0x828 >> 2) |
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#define GT_DMA3_DA (0x82c >> 2) |
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#define GT_DMA0_NEXT (0x830 >> 2) |
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#define GT_DMA1_NEXT (0x834 >> 2) |
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#define GT_DMA2_NEXT (0x838 >> 2) |
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#define GT_DMA3_NEXT (0x83c >> 2) |
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#define GT_DMA0_CUR (0x870 >> 2) |
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#define GT_DMA1_CUR (0x874 >> 2) |
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#define GT_DMA2_CUR (0x878 >> 2) |
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#define GT_DMA3_CUR (0x87c >> 2) |
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|
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/* DMA Channel Control */
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#define GT_DMA0_CTRL (0x840 >> 2) |
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#define GT_DMA1_CTRL (0x844 >> 2) |
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#define GT_DMA2_CTRL (0x848 >> 2) |
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#define GT_DMA3_CTRL (0x84c >> 2) |
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|
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/* DMA Arbiter */
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#define GT_DMA_ARB (0x860 >> 2) |
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|
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/* Timer/Counter */
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#define GT_TC0 (0x850 >> 2) |
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#define GT_TC1 (0x854 >> 2) |
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#define GT_TC2 (0x858 >> 2) |
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#define GT_TC3 (0x85c >> 2) |
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#define GT_TC_CONTROL (0x864 >> 2) |
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|
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/* PCI Internal */
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#define GT_PCI0_CMD (0xc00 >> 2) |
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#define GT_PCI0_TOR (0xc04 >> 2) |
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#define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
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#define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
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#define GT_PCI0_BS_CS20 (0xc10 >> 2) |
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#define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
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#define GT_PCI1_IACK (0xc30 >> 2) |
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#define GT_PCI0_IACK (0xc34 >> 2) |
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#define GT_PCI0_BARE (0xc3c >> 2) |
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#define GT_PCI0_PREFMBR (0xc40 >> 2) |
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#define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
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#define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
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#define GT_PCI0_CS20_BAR (0xc50 >> 2) |
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#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
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#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
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#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
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#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
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#define GT_PCI1_CMD (0xc80 >> 2) |
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#define GT_PCI1_TOR (0xc84 >> 2) |
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#define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
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#define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
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#define GT_PCI1_BS_CS20 (0xc90 >> 2) |
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#define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
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#define GT_PCI1_BARE (0xcbc >> 2) |
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#define GT_PCI1_PREFMBR (0xcc0 >> 2) |
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#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
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#define GT_PCI1_SCS32_BAR (0xccc >> 2) |
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#define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
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#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
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#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
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#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
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#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
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#define GT_PCI1_CFGADDR (0xcf0 >> 2) |
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#define GT_PCI1_CFGDATA (0xcf4 >> 2) |
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#define GT_PCI0_CFGADDR (0xcf8 >> 2) |
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#define GT_PCI0_CFGDATA (0xcfc >> 2) |
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|
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/* Interrupts */
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#define GT_INTRCAUSE (0xc18 >> 2) |
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#define GT_INTRMASK (0xc1c >> 2) |
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#define GT_PCI0_ICMASK (0xc24 >> 2) |
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#define GT_PCI0_SERR0MASK (0xc28 >> 2) |
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#define GT_CPU_INTSEL (0xc70 >> 2) |
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#define GT_PCI0_INTSEL (0xc74 >> 2) |
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#define GT_HINTRCAUSE (0xc98 >> 2) |
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#define GT_HINTRMASK (0xc9c >> 2) |
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#define GT_PCI0_HICMASK (0xca4 >> 2) |
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#define GT_PCI1_SERR1MASK (0xca8 >> 2) |
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|
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#define PCI_MAPPING_ENTRY(regname) \
|
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target_phys_addr_t regname ##_start; \ |
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target_phys_addr_t regname ##_length; \ |
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MemoryRegion regname ##_mem |
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|
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#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" |
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|
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#define GT64120_PCI_HOST_BRIDGE(obj) \
|
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OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE) |
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|
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typedef struct GT64120State { |
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PCIHostState pci; |
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|
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uint32_t regs[GT_REGS]; |
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PCI_MAPPING_ENTRY(PCI0IO); |
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PCI_MAPPING_ENTRY(ISD); |
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} GT64120State; |
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|
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/* Adjust range to avoid touching space which isn't mappable via PCI */
|
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/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
|
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0x1fc00000 - 0x1fd00000 */
|
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static void check_reserved_space (target_phys_addr_t *start, |
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target_phys_addr_t *length) |
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{
|
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target_phys_addr_t begin = *start; |
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target_phys_addr_t end = *start + *length; |
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|
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if (end >= 0x1e000000LL && end < 0x1f100000LL) |
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end = 0x1e000000LL;
|
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if (begin >= 0x1e000000LL && begin < 0x1f100000LL) |
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begin = 0x1f100000LL;
|
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if (end >= 0x1fc00000LL && end < 0x1fd00000LL) |
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end = 0x1fc00000LL;
|
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if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) |
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begin = 0x1fd00000LL;
|
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/* XXX: This is broken when a reserved range splits the requested range */
|
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if (end >= 0x1f100000LL && begin < 0x1e000000LL) |
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end = 0x1e000000LL;
|
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if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) |
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end = 0x1fc00000LL;
|
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|
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*start = begin; |
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*length = end - begin; |
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} |
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|
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static void gt64120_isd_mapping(GT64120State *s) |
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{
|
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target_phys_addr_t start = s->regs[GT_ISD] << 21;
|
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target_phys_addr_t length = 0x1000;
|
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|
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if (s->ISD_length) {
|
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memory_region_del_subregion(get_system_memory(), &s->ISD_mem); |
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} |
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check_reserved_space(&start, &length); |
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length = 0x1000;
|
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/* Map new address */
|
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DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx |
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" -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n", |
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s->ISD_length, s->ISD_start, length, start); |
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s->ISD_start = start; |
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s->ISD_length = length; |
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memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); |
| 289 |
} |
| 290 |
|
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static void gt64120_pci_mapping(GT64120State *s) |
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{
|
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/* Update IO mapping */
|
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if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
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{
|
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/* Unmap old IO address */
|
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if (s->PCI0IO_length)
|
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{
|
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memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); |
| 300 |
memory_region_destroy(&s->PCI0IO_mem); |
| 301 |
} |
| 302 |
/* Map new IO address */
|
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s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
|
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s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
| 305 |
isa_mem_base = s->PCI0IO_start; |
| 306 |
if (s->PCI0IO_length) {
|
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isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length); |
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memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, |
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&s->PCI0IO_mem); |
| 310 |
} |
| 311 |
} |
| 312 |
} |
| 313 |
|
| 314 |
static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
| 315 |
uint64_t val, unsigned size)
|
| 316 |
{
|
| 317 |
GT64120State *s = opaque; |
| 318 |
uint32_t saddr; |
| 319 |
|
| 320 |
if (!(s->regs[GT_CPU] & 0x00001000)) |
| 321 |
val = bswap32(val); |
| 322 |
|
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saddr = (addr & 0xfff) >> 2; |
| 324 |
switch (saddr) {
|
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|
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/* CPU Configuration */
|
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case GT_CPU:
|
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s->regs[GT_CPU] = val; |
| 329 |
break;
|
| 330 |
case GT_MULTI:
|
| 331 |
/* Read-only register as only one GT64xxx is present on the CPU bus */
|
| 332 |
break;
|
| 333 |
|
| 334 |
/* CPU Address Decode */
|
| 335 |
case GT_PCI0IOLD:
|
| 336 |
s->regs[GT_PCI0IOLD] = val & 0x00007fff;
|
| 337 |
s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
| 339 |
break;
|
| 340 |
case GT_PCI0M0LD:
|
| 341 |
s->regs[GT_PCI0M0LD] = val & 0x00007fff;
|
| 342 |
s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
|
| 343 |
break;
|
| 344 |
case GT_PCI0M1LD:
|
| 345 |
s->regs[GT_PCI0M1LD] = val & 0x00007fff;
|
| 346 |
s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
|
| 347 |
break;
|
| 348 |
case GT_PCI1IOLD:
|
| 349 |
s->regs[GT_PCI1IOLD] = val & 0x00007fff;
|
| 350 |
s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
|
| 351 |
break;
|
| 352 |
case GT_PCI1M0LD:
|
| 353 |
s->regs[GT_PCI1M0LD] = val & 0x00007fff;
|
| 354 |
s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
|
| 355 |
break;
|
| 356 |
case GT_PCI1M1LD:
|
| 357 |
s->regs[GT_PCI1M1LD] = val & 0x00007fff;
|
| 358 |
s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
|
| 359 |
break;
|
| 360 |
case GT_PCI0IOHD:
|
| 361 |
s->regs[saddr] = val & 0x0000007f;
|
| 362 |
gt64120_pci_mapping(s); |
| 363 |
break;
|
| 364 |
case GT_PCI0M0HD:
|
| 365 |
case GT_PCI0M1HD:
|
| 366 |
case GT_PCI1IOHD:
|
| 367 |
case GT_PCI1M0HD:
|
| 368 |
case GT_PCI1M1HD:
|
| 369 |
s->regs[saddr] = val & 0x0000007f;
|
| 370 |
break;
|
| 371 |
case GT_ISD:
|
| 372 |
s->regs[saddr] = val & 0x00007fff;
|
| 373 |
gt64120_isd_mapping(s); |
| 374 |
break;
|
| 375 |
|
| 376 |
case GT_PCI0IOREMAP:
|
| 377 |
case GT_PCI0M0REMAP:
|
| 378 |
case GT_PCI0M1REMAP:
|
| 379 |
case GT_PCI1IOREMAP:
|
| 380 |
case GT_PCI1M0REMAP:
|
| 381 |
case GT_PCI1M1REMAP:
|
| 382 |
s->regs[saddr] = val & 0x000007ff;
|
| 383 |
break;
|
| 384 |
|
| 385 |
/* CPU Error Report */
|
| 386 |
case GT_CPUERR_ADDRLO:
|
| 387 |
case GT_CPUERR_ADDRHI:
|
| 388 |
case GT_CPUERR_DATALO:
|
| 389 |
case GT_CPUERR_DATAHI:
|
| 390 |
case GT_CPUERR_PARITY:
|
| 391 |
/* Read-only registers, do nothing */
|
| 392 |
break;
|
| 393 |
|
| 394 |
/* CPU Sync Barrier */
|
| 395 |
case GT_PCI0SYNC:
|
| 396 |
case GT_PCI1SYNC:
|
| 397 |
/* Read-only registers, do nothing */
|
| 398 |
break;
|
| 399 |
|
| 400 |
/* SDRAM and Device Address Decode */
|
| 401 |
case GT_SCS0LD:
|
| 402 |
case GT_SCS0HD:
|
| 403 |
case GT_SCS1LD:
|
| 404 |
case GT_SCS1HD:
|
| 405 |
case GT_SCS2LD:
|
| 406 |
case GT_SCS2HD:
|
| 407 |
case GT_SCS3LD:
|
| 408 |
case GT_SCS3HD:
|
| 409 |
case GT_CS0LD:
|
| 410 |
case GT_CS0HD:
|
| 411 |
case GT_CS1LD:
|
| 412 |
case GT_CS1HD:
|
| 413 |
case GT_CS2LD:
|
| 414 |
case GT_CS2HD:
|
| 415 |
case GT_CS3LD:
|
| 416 |
case GT_CS3HD:
|
| 417 |
case GT_BOOTLD:
|
| 418 |
case GT_BOOTHD:
|
| 419 |
case GT_ADERR:
|
| 420 |
/* SDRAM Configuration */
|
| 421 |
case GT_SDRAM_CFG:
|
| 422 |
case GT_SDRAM_OPMODE:
|
| 423 |
case GT_SDRAM_BM:
|
| 424 |
case GT_SDRAM_ADDRDECODE:
|
| 425 |
/* Accept and ignore SDRAM interleave configuration */
|
| 426 |
s->regs[saddr] = val; |
| 427 |
break;
|
| 428 |
|
| 429 |
/* Device Parameters */
|
| 430 |
case GT_DEV_B0:
|
| 431 |
case GT_DEV_B1:
|
| 432 |
case GT_DEV_B2:
|
| 433 |
case GT_DEV_B3:
|
| 434 |
case GT_DEV_BOOT:
|
| 435 |
/* Not implemented */
|
| 436 |
DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); |
| 437 |
break;
|
| 438 |
|
| 439 |
/* ECC */
|
| 440 |
case GT_ECC_ERRDATALO:
|
| 441 |
case GT_ECC_ERRDATAHI:
|
| 442 |
case GT_ECC_MEM:
|
| 443 |
case GT_ECC_CALC:
|
| 444 |
case GT_ECC_ERRADDR:
|
| 445 |
/* Read-only registers, do nothing */
|
| 446 |
break;
|
| 447 |
|
| 448 |
/* DMA Record */
|
| 449 |
case GT_DMA0_CNT:
|
| 450 |
case GT_DMA1_CNT:
|
| 451 |
case GT_DMA2_CNT:
|
| 452 |
case GT_DMA3_CNT:
|
| 453 |
case GT_DMA0_SA:
|
| 454 |
case GT_DMA1_SA:
|
| 455 |
case GT_DMA2_SA:
|
| 456 |
case GT_DMA3_SA:
|
| 457 |
case GT_DMA0_DA:
|
| 458 |
case GT_DMA1_DA:
|
| 459 |
case GT_DMA2_DA:
|
| 460 |
case GT_DMA3_DA:
|
| 461 |
case GT_DMA0_NEXT:
|
| 462 |
case GT_DMA1_NEXT:
|
| 463 |
case GT_DMA2_NEXT:
|
| 464 |
case GT_DMA3_NEXT:
|
| 465 |
case GT_DMA0_CUR:
|
| 466 |
case GT_DMA1_CUR:
|
| 467 |
case GT_DMA2_CUR:
|
| 468 |
case GT_DMA3_CUR:
|
| 469 |
/* Not implemented */
|
| 470 |
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
| 471 |
break;
|
| 472 |
|
| 473 |
/* DMA Channel Control */
|
| 474 |
case GT_DMA0_CTRL:
|
| 475 |
case GT_DMA1_CTRL:
|
| 476 |
case GT_DMA2_CTRL:
|
| 477 |
case GT_DMA3_CTRL:
|
| 478 |
/* Not implemented */
|
| 479 |
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
| 480 |
break;
|
| 481 |
|
| 482 |
/* DMA Arbiter */
|
| 483 |
case GT_DMA_ARB:
|
| 484 |
/* Not implemented */
|
| 485 |
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
| 486 |
break;
|
| 487 |
|
| 488 |
/* Timer/Counter */
|
| 489 |
case GT_TC0:
|
| 490 |
case GT_TC1:
|
| 491 |
case GT_TC2:
|
| 492 |
case GT_TC3:
|
| 493 |
case GT_TC_CONTROL:
|
| 494 |
/* Not implemented */
|
| 495 |
DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); |
| 496 |
break;
|
| 497 |
|
| 498 |
/* PCI Internal */
|
| 499 |
case GT_PCI0_CMD:
|
| 500 |
case GT_PCI1_CMD:
|
| 501 |
s->regs[saddr] = val & 0x0401fc0f;
|
| 502 |
break;
|
| 503 |
case GT_PCI0_TOR:
|
| 504 |
case GT_PCI0_BS_SCS10:
|
| 505 |
case GT_PCI0_BS_SCS32:
|
| 506 |
case GT_PCI0_BS_CS20:
|
| 507 |
case GT_PCI0_BS_CS3BT:
|
| 508 |
case GT_PCI1_IACK:
|
| 509 |
case GT_PCI0_IACK:
|
| 510 |
case GT_PCI0_BARE:
|
| 511 |
case GT_PCI0_PREFMBR:
|
| 512 |
case GT_PCI0_SCS10_BAR:
|
| 513 |
case GT_PCI0_SCS32_BAR:
|
| 514 |
case GT_PCI0_CS20_BAR:
|
| 515 |
case GT_PCI0_CS3BT_BAR:
|
| 516 |
case GT_PCI0_SSCS10_BAR:
|
| 517 |
case GT_PCI0_SSCS32_BAR:
|
| 518 |
case GT_PCI0_SCS3BT_BAR:
|
| 519 |
case GT_PCI1_TOR:
|
| 520 |
case GT_PCI1_BS_SCS10:
|
| 521 |
case GT_PCI1_BS_SCS32:
|
| 522 |
case GT_PCI1_BS_CS20:
|
| 523 |
case GT_PCI1_BS_CS3BT:
|
| 524 |
case GT_PCI1_BARE:
|
| 525 |
case GT_PCI1_PREFMBR:
|
| 526 |
case GT_PCI1_SCS10_BAR:
|
| 527 |
case GT_PCI1_SCS32_BAR:
|
| 528 |
case GT_PCI1_CS20_BAR:
|
| 529 |
case GT_PCI1_CS3BT_BAR:
|
| 530 |
case GT_PCI1_SSCS10_BAR:
|
| 531 |
case GT_PCI1_SSCS32_BAR:
|
| 532 |
case GT_PCI1_SCS3BT_BAR:
|
| 533 |
case GT_PCI1_CFGADDR:
|
| 534 |
case GT_PCI1_CFGDATA:
|
| 535 |
/* not implemented */
|
| 536 |
break;
|
| 537 |
case GT_PCI0_CFGADDR:
|
| 538 |
s->pci.config_reg = val & 0x80fffffc;
|
| 539 |
break;
|
| 540 |
case GT_PCI0_CFGDATA:
|
| 541 |
if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800)) |
| 542 |
val = bswap32(val); |
| 543 |
if (s->pci.config_reg & (1u << 31)) |
| 544 |
pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
|
| 545 |
break;
|
| 546 |
|
| 547 |
/* Interrupts */
|
| 548 |
case GT_INTRCAUSE:
|
| 549 |
/* not really implemented */
|
| 550 |
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
|
| 551 |
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
|
| 552 |
DPRINTF("INTRCAUSE %" PRIx64 "\n", val); |
| 553 |
break;
|
| 554 |
case GT_INTRMASK:
|
| 555 |
s->regs[saddr] = val & 0x3c3ffffe;
|
| 556 |
DPRINTF("INTRMASK %" PRIx64 "\n", val); |
| 557 |
break;
|
| 558 |
case GT_PCI0_ICMASK:
|
| 559 |
s->regs[saddr] = val & 0x03fffffe;
|
| 560 |
DPRINTF("ICMASK %" PRIx64 "\n", val); |
| 561 |
break;
|
| 562 |
case GT_PCI0_SERR0MASK:
|
| 563 |
s->regs[saddr] = val & 0x0000003f;
|
| 564 |
DPRINTF("SERR0MASK %" PRIx64 "\n", val); |
| 565 |
break;
|
| 566 |
|
| 567 |
/* Reserved when only PCI_0 is configured. */
|
| 568 |
case GT_HINTRCAUSE:
|
| 569 |
case GT_CPU_INTSEL:
|
| 570 |
case GT_PCI0_INTSEL:
|
| 571 |
case GT_HINTRMASK:
|
| 572 |
case GT_PCI0_HICMASK:
|
| 573 |
case GT_PCI1_SERR1MASK:
|
| 574 |
/* not implemented */
|
| 575 |
break;
|
| 576 |
|
| 577 |
/* SDRAM Parameters */
|
| 578 |
case GT_SDRAM_B0:
|
| 579 |
case GT_SDRAM_B1:
|
| 580 |
case GT_SDRAM_B2:
|
| 581 |
case GT_SDRAM_B3:
|
| 582 |
/* We don't simulate electrical parameters of the SDRAM.
|
| 583 |
Accept, but ignore the values. */
|
| 584 |
s->regs[saddr] = val; |
| 585 |
break;
|
| 586 |
|
| 587 |
default:
|
| 588 |
DPRINTF ("Bad register offset 0x%x\n", (int)addr); |
| 589 |
break;
|
| 590 |
} |
| 591 |
} |
| 592 |
|
| 593 |
static uint64_t gt64120_readl (void *opaque, |
| 594 |
target_phys_addr_t addr, unsigned size)
|
| 595 |
{
|
| 596 |
GT64120State *s = opaque; |
| 597 |
uint32_t val; |
| 598 |
uint32_t saddr; |
| 599 |
|
| 600 |
saddr = (addr & 0xfff) >> 2; |
| 601 |
switch (saddr) {
|
| 602 |
|
| 603 |
/* CPU Configuration */
|
| 604 |
case GT_MULTI:
|
| 605 |
/* Only one GT64xxx is present on the CPU bus, return
|
| 606 |
the initial value */
|
| 607 |
val = s->regs[saddr]; |
| 608 |
break;
|
| 609 |
|
| 610 |
/* CPU Error Report */
|
| 611 |
case GT_CPUERR_ADDRLO:
|
| 612 |
case GT_CPUERR_ADDRHI:
|
| 613 |
case GT_CPUERR_DATALO:
|
| 614 |
case GT_CPUERR_DATAHI:
|
| 615 |
case GT_CPUERR_PARITY:
|
| 616 |
/* Emulated memory has no error, always return the initial
|
| 617 |
values */
|
| 618 |
val = s->regs[saddr]; |
| 619 |
break;
|
| 620 |
|
| 621 |
/* CPU Sync Barrier */
|
| 622 |
case GT_PCI0SYNC:
|
| 623 |
case GT_PCI1SYNC:
|
| 624 |
/* Reading those register should empty all FIFO on the PCI
|
| 625 |
bus, which are not emulated. The return value should be
|
| 626 |
a random value that should be ignored. */
|
| 627 |
val = 0xc000ffee;
|
| 628 |
break;
|
| 629 |
|
| 630 |
/* ECC */
|
| 631 |
case GT_ECC_ERRDATALO:
|
| 632 |
case GT_ECC_ERRDATAHI:
|
| 633 |
case GT_ECC_MEM:
|
| 634 |
case GT_ECC_CALC:
|
| 635 |
case GT_ECC_ERRADDR:
|
| 636 |
/* Emulated memory has no error, always return the initial
|
| 637 |
values */
|
| 638 |
val = s->regs[saddr]; |
| 639 |
break;
|
| 640 |
|
| 641 |
case GT_CPU:
|
| 642 |
case GT_SCS10LD:
|
| 643 |
case GT_SCS10HD:
|
| 644 |
case GT_SCS32LD:
|
| 645 |
case GT_SCS32HD:
|
| 646 |
case GT_CS20LD:
|
| 647 |
case GT_CS20HD:
|
| 648 |
case GT_CS3BOOTLD:
|
| 649 |
case GT_CS3BOOTHD:
|
| 650 |
case GT_SCS10AR:
|
| 651 |
case GT_SCS32AR:
|
| 652 |
case GT_CS20R:
|
| 653 |
case GT_CS3BOOTR:
|
| 654 |
case GT_PCI0IOLD:
|
| 655 |
case GT_PCI0M0LD:
|
| 656 |
case GT_PCI0M1LD:
|
| 657 |
case GT_PCI1IOLD:
|
| 658 |
case GT_PCI1M0LD:
|
| 659 |
case GT_PCI1M1LD:
|
| 660 |
case GT_PCI0IOHD:
|
| 661 |
case GT_PCI0M0HD:
|
| 662 |
case GT_PCI0M1HD:
|
| 663 |
case GT_PCI1IOHD:
|
| 664 |
case GT_PCI1M0HD:
|
| 665 |
case GT_PCI1M1HD:
|
| 666 |
case GT_PCI0IOREMAP:
|
| 667 |
case GT_PCI0M0REMAP:
|
| 668 |
case GT_PCI0M1REMAP:
|
| 669 |
case GT_PCI1IOREMAP:
|
| 670 |
case GT_PCI1M0REMAP:
|
| 671 |
case GT_PCI1M1REMAP:
|
| 672 |
case GT_ISD:
|
| 673 |
val = s->regs[saddr]; |
| 674 |
break;
|
| 675 |
case GT_PCI0_IACK:
|
| 676 |
/* Read the IRQ number */
|
| 677 |
val = pic_read_irq(isa_pic); |
| 678 |
break;
|
| 679 |
|
| 680 |
/* SDRAM and Device Address Decode */
|
| 681 |
case GT_SCS0LD:
|
| 682 |
case GT_SCS0HD:
|
| 683 |
case GT_SCS1LD:
|
| 684 |
case GT_SCS1HD:
|
| 685 |
case GT_SCS2LD:
|
| 686 |
case GT_SCS2HD:
|
| 687 |
case GT_SCS3LD:
|
| 688 |
case GT_SCS3HD:
|
| 689 |
case GT_CS0LD:
|
| 690 |
case GT_CS0HD:
|
| 691 |
case GT_CS1LD:
|
| 692 |
case GT_CS1HD:
|
| 693 |
case GT_CS2LD:
|
| 694 |
case GT_CS2HD:
|
| 695 |
case GT_CS3LD:
|
| 696 |
case GT_CS3HD:
|
| 697 |
case GT_BOOTLD:
|
| 698 |
case GT_BOOTHD:
|
| 699 |
case GT_ADERR:
|
| 700 |
val = s->regs[saddr]; |
| 701 |
break;
|
| 702 |
|
| 703 |
/* SDRAM Configuration */
|
| 704 |
case GT_SDRAM_CFG:
|
| 705 |
case GT_SDRAM_OPMODE:
|
| 706 |
case GT_SDRAM_BM:
|
| 707 |
case GT_SDRAM_ADDRDECODE:
|
| 708 |
val = s->regs[saddr]; |
| 709 |
break;
|
| 710 |
|
| 711 |
/* SDRAM Parameters */
|
| 712 |
case GT_SDRAM_B0:
|
| 713 |
case GT_SDRAM_B1:
|
| 714 |
case GT_SDRAM_B2:
|
| 715 |
case GT_SDRAM_B3:
|
| 716 |
/* We don't simulate electrical parameters of the SDRAM.
|
| 717 |
Just return the last written value. */
|
| 718 |
val = s->regs[saddr]; |
| 719 |
break;
|
| 720 |
|
| 721 |
/* Device Parameters */
|
| 722 |
case GT_DEV_B0:
|
| 723 |
case GT_DEV_B1:
|
| 724 |
case GT_DEV_B2:
|
| 725 |
case GT_DEV_B3:
|
| 726 |
case GT_DEV_BOOT:
|
| 727 |
val = s->regs[saddr]; |
| 728 |
break;
|
| 729 |
|
| 730 |
/* DMA Record */
|
| 731 |
case GT_DMA0_CNT:
|
| 732 |
case GT_DMA1_CNT:
|
| 733 |
case GT_DMA2_CNT:
|
| 734 |
case GT_DMA3_CNT:
|
| 735 |
case GT_DMA0_SA:
|
| 736 |
case GT_DMA1_SA:
|
| 737 |
case GT_DMA2_SA:
|
| 738 |
case GT_DMA3_SA:
|
| 739 |
case GT_DMA0_DA:
|
| 740 |
case GT_DMA1_DA:
|
| 741 |
case GT_DMA2_DA:
|
| 742 |
case GT_DMA3_DA:
|
| 743 |
case GT_DMA0_NEXT:
|
| 744 |
case GT_DMA1_NEXT:
|
| 745 |
case GT_DMA2_NEXT:
|
| 746 |
case GT_DMA3_NEXT:
|
| 747 |
case GT_DMA0_CUR:
|
| 748 |
case GT_DMA1_CUR:
|
| 749 |
case GT_DMA2_CUR:
|
| 750 |
case GT_DMA3_CUR:
|
| 751 |
val = s->regs[saddr]; |
| 752 |
break;
|
| 753 |
|
| 754 |
/* DMA Channel Control */
|
| 755 |
case GT_DMA0_CTRL:
|
| 756 |
case GT_DMA1_CTRL:
|
| 757 |
case GT_DMA2_CTRL:
|
| 758 |
case GT_DMA3_CTRL:
|
| 759 |
val = s->regs[saddr]; |
| 760 |
break;
|
| 761 |
|
| 762 |
/* DMA Arbiter */
|
| 763 |
case GT_DMA_ARB:
|
| 764 |
val = s->regs[saddr]; |
| 765 |
break;
|
| 766 |
|
| 767 |
/* Timer/Counter */
|
| 768 |
case GT_TC0:
|
| 769 |
case GT_TC1:
|
| 770 |
case GT_TC2:
|
| 771 |
case GT_TC3:
|
| 772 |
case GT_TC_CONTROL:
|
| 773 |
val = s->regs[saddr]; |
| 774 |
break;
|
| 775 |
|
| 776 |
/* PCI Internal */
|
| 777 |
case GT_PCI0_CFGADDR:
|
| 778 |
val = s->pci.config_reg; |
| 779 |
break;
|
| 780 |
case GT_PCI0_CFGDATA:
|
| 781 |
if (!(s->pci.config_reg & (1 << 31))) |
| 782 |
val = 0xffffffff;
|
| 783 |
else
|
| 784 |
val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
|
| 785 |
if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800)) |
| 786 |
val = bswap32(val); |
| 787 |
break;
|
| 788 |
|
| 789 |
case GT_PCI0_CMD:
|
| 790 |
case GT_PCI0_TOR:
|
| 791 |
case GT_PCI0_BS_SCS10:
|
| 792 |
case GT_PCI0_BS_SCS32:
|
| 793 |
case GT_PCI0_BS_CS20:
|
| 794 |
case GT_PCI0_BS_CS3BT:
|
| 795 |
case GT_PCI1_IACK:
|
| 796 |
case GT_PCI0_BARE:
|
| 797 |
case GT_PCI0_PREFMBR:
|
| 798 |
case GT_PCI0_SCS10_BAR:
|
| 799 |
case GT_PCI0_SCS32_BAR:
|
| 800 |
case GT_PCI0_CS20_BAR:
|
| 801 |
case GT_PCI0_CS3BT_BAR:
|
| 802 |
case GT_PCI0_SSCS10_BAR:
|
| 803 |
case GT_PCI0_SSCS32_BAR:
|
| 804 |
case GT_PCI0_SCS3BT_BAR:
|
| 805 |
case GT_PCI1_CMD:
|
| 806 |
case GT_PCI1_TOR:
|
| 807 |
case GT_PCI1_BS_SCS10:
|
| 808 |
case GT_PCI1_BS_SCS32:
|
| 809 |
case GT_PCI1_BS_CS20:
|
| 810 |
case GT_PCI1_BS_CS3BT:
|
| 811 |
case GT_PCI1_BARE:
|
| 812 |
case GT_PCI1_PREFMBR:
|
| 813 |
case GT_PCI1_SCS10_BAR:
|
| 814 |
case GT_PCI1_SCS32_BAR:
|
| 815 |
case GT_PCI1_CS20_BAR:
|
| 816 |
case GT_PCI1_CS3BT_BAR:
|
| 817 |
case GT_PCI1_SSCS10_BAR:
|
| 818 |
case GT_PCI1_SSCS32_BAR:
|
| 819 |
case GT_PCI1_SCS3BT_BAR:
|
| 820 |
case GT_PCI1_CFGADDR:
|
| 821 |
case GT_PCI1_CFGDATA:
|
| 822 |
val = s->regs[saddr]; |
| 823 |
break;
|
| 824 |
|
| 825 |
/* Interrupts */
|
| 826 |
case GT_INTRCAUSE:
|
| 827 |
val = s->regs[saddr]; |
| 828 |
DPRINTF("INTRCAUSE %x\n", val);
|
| 829 |
break;
|
| 830 |
case GT_INTRMASK:
|
| 831 |
val = s->regs[saddr]; |
| 832 |
DPRINTF("INTRMASK %x\n", val);
|
| 833 |
break;
|
| 834 |
case GT_PCI0_ICMASK:
|
| 835 |
val = s->regs[saddr]; |
| 836 |
DPRINTF("ICMASK %x\n", val);
|
| 837 |
break;
|
| 838 |
case GT_PCI0_SERR0MASK:
|
| 839 |
val = s->regs[saddr]; |
| 840 |
DPRINTF("SERR0MASK %x\n", val);
|
| 841 |
break;
|
| 842 |
|
| 843 |
/* Reserved when only PCI_0 is configured. */
|
| 844 |
case GT_HINTRCAUSE:
|
| 845 |
case GT_CPU_INTSEL:
|
| 846 |
case GT_PCI0_INTSEL:
|
| 847 |
case GT_HINTRMASK:
|
| 848 |
case GT_PCI0_HICMASK:
|
| 849 |
case GT_PCI1_SERR1MASK:
|
| 850 |
val = s->regs[saddr]; |
| 851 |
break;
|
| 852 |
|
| 853 |
default:
|
| 854 |
val = s->regs[saddr]; |
| 855 |
DPRINTF ("Bad register offset 0x%x\n", (int)addr); |
| 856 |
break;
|
| 857 |
} |
| 858 |
|
| 859 |
if (!(s->regs[GT_CPU] & 0x00001000)) |
| 860 |
val = bswap32(val); |
| 861 |
|
| 862 |
return val;
|
| 863 |
} |
| 864 |
|
| 865 |
static const MemoryRegionOps isd_mem_ops = { |
| 866 |
.read = gt64120_readl, |
| 867 |
.write = gt64120_writel, |
| 868 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 869 |
}; |
| 870 |
|
| 871 |
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
| 872 |
{
|
| 873 |
int slot;
|
| 874 |
|
| 875 |
slot = (pci_dev->devfn >> 3);
|
| 876 |
|
| 877 |
switch (slot) {
|
| 878 |
/* PIIX4 USB */
|
| 879 |
case 10: |
| 880 |
return 3; |
| 881 |
/* AMD 79C973 Ethernet */
|
| 882 |
case 11: |
| 883 |
return 1; |
| 884 |
/* Crystal 4281 Sound */
|
| 885 |
case 12: |
| 886 |
return 2; |
| 887 |
/* PCI slot 1 to 4 */
|
| 888 |
case 18 ... 21: |
| 889 |
return ((slot - 18) + irq_num) & 0x03; |
| 890 |
/* Unknown device, don't do any translation */
|
| 891 |
default:
|
| 892 |
return irq_num;
|
| 893 |
} |
| 894 |
} |
| 895 |
|
| 896 |
static int pci_irq_levels[4]; |
| 897 |
|
| 898 |
static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) |
| 899 |
{
|
| 900 |
int i, pic_irq, pic_level;
|
| 901 |
qemu_irq *pic = opaque; |
| 902 |
|
| 903 |
pci_irq_levels[irq_num] = level; |
| 904 |
|
| 905 |
/* now we change the pic irq level according to the piix irq mappings */
|
| 906 |
/* XXX: optimize */
|
| 907 |
pic_irq = piix4_dev->config[0x60 + irq_num];
|
| 908 |
if (pic_irq < 16) { |
| 909 |
/* The pic level is the logical OR of all the PCI irqs mapped
|
| 910 |
to it */
|
| 911 |
pic_level = 0;
|
| 912 |
for (i = 0; i < 4; i++) { |
| 913 |
if (pic_irq == piix4_dev->config[0x60 + i]) |
| 914 |
pic_level |= pci_irq_levels[i]; |
| 915 |
} |
| 916 |
qemu_set_irq(pic[pic_irq], pic_level); |
| 917 |
} |
| 918 |
} |
| 919 |
|
| 920 |
|
| 921 |
static void gt64120_reset(void *opaque) |
| 922 |
{
|
| 923 |
GT64120State *s = opaque; |
| 924 |
|
| 925 |
/* FIXME: Malta specific hw assumptions ahead */
|
| 926 |
|
| 927 |
/* CPU Configuration */
|
| 928 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 929 |
s->regs[GT_CPU] = 0x00000000;
|
| 930 |
#else
|
| 931 |
s->regs[GT_CPU] = 0x00001000;
|
| 932 |
#endif
|
| 933 |
s->regs[GT_MULTI] = 0x00000003;
|
| 934 |
|
| 935 |
/* CPU Address decode */
|
| 936 |
s->regs[GT_SCS10LD] = 0x00000000;
|
| 937 |
s->regs[GT_SCS10HD] = 0x00000007;
|
| 938 |
s->regs[GT_SCS32LD] = 0x00000008;
|
| 939 |
s->regs[GT_SCS32HD] = 0x0000000f;
|
| 940 |
s->regs[GT_CS20LD] = 0x000000e0;
|
| 941 |
s->regs[GT_CS20HD] = 0x00000070;
|
| 942 |
s->regs[GT_CS3BOOTLD] = 0x000000f8;
|
| 943 |
s->regs[GT_CS3BOOTHD] = 0x0000007f;
|
| 944 |
|
| 945 |
s->regs[GT_PCI0IOLD] = 0x00000080;
|
| 946 |
s->regs[GT_PCI0IOHD] = 0x0000000f;
|
| 947 |
s->regs[GT_PCI0M0LD] = 0x00000090;
|
| 948 |
s->regs[GT_PCI0M0HD] = 0x0000001f;
|
| 949 |
s->regs[GT_ISD] = 0x000000a0;
|
| 950 |
s->regs[GT_PCI0M1LD] = 0x00000790;
|
| 951 |
s->regs[GT_PCI0M1HD] = 0x0000001f;
|
| 952 |
s->regs[GT_PCI1IOLD] = 0x00000100;
|
| 953 |
s->regs[GT_PCI1IOHD] = 0x0000000f;
|
| 954 |
s->regs[GT_PCI1M0LD] = 0x00000110;
|
| 955 |
s->regs[GT_PCI1M0HD] = 0x0000001f;
|
| 956 |
s->regs[GT_PCI1M1LD] = 0x00000120;
|
| 957 |
s->regs[GT_PCI1M1HD] = 0x0000002f;
|
| 958 |
|
| 959 |
s->regs[GT_SCS10AR] = 0x00000000;
|
| 960 |
s->regs[GT_SCS32AR] = 0x00000008;
|
| 961 |
s->regs[GT_CS20R] = 0x000000e0;
|
| 962 |
s->regs[GT_CS3BOOTR] = 0x000000f8;
|
| 963 |
|
| 964 |
s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
| 965 |
s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
| 966 |
s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
| 967 |
s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
| 968 |
s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
| 969 |
s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
| 970 |
|
| 971 |
/* CPU Error Report */
|
| 972 |
s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
| 973 |
s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
| 974 |
s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
| 975 |
s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
| 976 |
s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
| 977 |
|
| 978 |
/* CPU Sync Barrier */
|
| 979 |
s->regs[GT_PCI0SYNC] = 0x00000000;
|
| 980 |
s->regs[GT_PCI1SYNC] = 0x00000000;
|
| 981 |
|
| 982 |
/* SDRAM and Device Address Decode */
|
| 983 |
s->regs[GT_SCS0LD] = 0x00000000;
|
| 984 |
s->regs[GT_SCS0HD] = 0x00000007;
|
| 985 |
s->regs[GT_SCS1LD] = 0x00000008;
|
| 986 |
s->regs[GT_SCS1HD] = 0x0000000f;
|
| 987 |
s->regs[GT_SCS2LD] = 0x00000010;
|
| 988 |
s->regs[GT_SCS2HD] = 0x00000017;
|
| 989 |
s->regs[GT_SCS3LD] = 0x00000018;
|
| 990 |
s->regs[GT_SCS3HD] = 0x0000001f;
|
| 991 |
s->regs[GT_CS0LD] = 0x000000c0;
|
| 992 |
s->regs[GT_CS0HD] = 0x000000c7;
|
| 993 |
s->regs[GT_CS1LD] = 0x000000c8;
|
| 994 |
s->regs[GT_CS1HD] = 0x000000cf;
|
| 995 |
s->regs[GT_CS2LD] = 0x000000d0;
|
| 996 |
s->regs[GT_CS2HD] = 0x000000df;
|
| 997 |
s->regs[GT_CS3LD] = 0x000000f0;
|
| 998 |
s->regs[GT_CS3HD] = 0x000000fb;
|
| 999 |
s->regs[GT_BOOTLD] = 0x000000fc;
|
| 1000 |
s->regs[GT_BOOTHD] = 0x000000ff;
|
| 1001 |
s->regs[GT_ADERR] = 0xffffffff;
|
| 1002 |
|
| 1003 |
/* SDRAM Configuration */
|
| 1004 |
s->regs[GT_SDRAM_CFG] = 0x00000200;
|
| 1005 |
s->regs[GT_SDRAM_OPMODE] = 0x00000000;
|
| 1006 |
s->regs[GT_SDRAM_BM] = 0x00000007;
|
| 1007 |
s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
|
| 1008 |
|
| 1009 |
/* SDRAM Parameters */
|
| 1010 |
s->regs[GT_SDRAM_B0] = 0x00000005;
|
| 1011 |
s->regs[GT_SDRAM_B1] = 0x00000005;
|
| 1012 |
s->regs[GT_SDRAM_B2] = 0x00000005;
|
| 1013 |
s->regs[GT_SDRAM_B3] = 0x00000005;
|
| 1014 |
|
| 1015 |
/* ECC */
|
| 1016 |
s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
| 1017 |
s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
| 1018 |
s->regs[GT_ECC_MEM] = 0x00000000;
|
| 1019 |
s->regs[GT_ECC_CALC] = 0x00000000;
|
| 1020 |
s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
| 1021 |
|
| 1022 |
/* Device Parameters */
|
| 1023 |
s->regs[GT_DEV_B0] = 0x386fffff;
|
| 1024 |
s->regs[GT_DEV_B1] = 0x386fffff;
|
| 1025 |
s->regs[GT_DEV_B2] = 0x386fffff;
|
| 1026 |
s->regs[GT_DEV_B3] = 0x386fffff;
|
| 1027 |
s->regs[GT_DEV_BOOT] = 0x146fffff;
|
| 1028 |
|
| 1029 |
/* DMA registers are all zeroed at reset */
|
| 1030 |
|
| 1031 |
/* Timer/Counter */
|
| 1032 |
s->regs[GT_TC0] = 0xffffffff;
|
| 1033 |
s->regs[GT_TC1] = 0x00ffffff;
|
| 1034 |
s->regs[GT_TC2] = 0x00ffffff;
|
| 1035 |
s->regs[GT_TC3] = 0x00ffffff;
|
| 1036 |
s->regs[GT_TC_CONTROL] = 0x00000000;
|
| 1037 |
|
| 1038 |
/* PCI Internal */
|
| 1039 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1040 |
s->regs[GT_PCI0_CMD] = 0x00000000;
|
| 1041 |
#else
|
| 1042 |
s->regs[GT_PCI0_CMD] = 0x00010001;
|
| 1043 |
#endif
|
| 1044 |
s->regs[GT_PCI0_TOR] = 0x0000070f;
|
| 1045 |
s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
|
| 1046 |
s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
|
| 1047 |
s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
|
| 1048 |
s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
|
| 1049 |
s->regs[GT_PCI1_IACK] = 0x00000000;
|
| 1050 |
s->regs[GT_PCI0_IACK] = 0x00000000;
|
| 1051 |
s->regs[GT_PCI0_BARE] = 0x0000000f;
|
| 1052 |
s->regs[GT_PCI0_PREFMBR] = 0x00000040;
|
| 1053 |
s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
|
| 1054 |
s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
|
| 1055 |
s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
|
| 1056 |
s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
|
| 1057 |
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
|
| 1058 |
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
|
| 1059 |
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
|
| 1060 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 1061 |
s->regs[GT_PCI1_CMD] = 0x00000000;
|
| 1062 |
#else
|
| 1063 |
s->regs[GT_PCI1_CMD] = 0x00010001;
|
| 1064 |
#endif
|
| 1065 |
s->regs[GT_PCI1_TOR] = 0x0000070f;
|
| 1066 |
s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
|
| 1067 |
s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
|
| 1068 |
s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
|
| 1069 |
s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
|
| 1070 |
s->regs[GT_PCI1_BARE] = 0x0000000f;
|
| 1071 |
s->regs[GT_PCI1_PREFMBR] = 0x00000040;
|
| 1072 |
s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
|
| 1073 |
s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
|
| 1074 |
s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
|
| 1075 |
s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
|
| 1076 |
s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
|
| 1077 |
s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
|
| 1078 |
s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
|
| 1079 |
s->regs[GT_PCI1_CFGADDR] = 0x00000000;
|
| 1080 |
s->regs[GT_PCI1_CFGDATA] = 0x00000000;
|
| 1081 |
s->regs[GT_PCI0_CFGADDR] = 0x00000000;
|
| 1082 |
|
| 1083 |
/* Interrupt registers are all zeroed at reset */
|
| 1084 |
|
| 1085 |
gt64120_isd_mapping(s); |
| 1086 |
gt64120_pci_mapping(s); |
| 1087 |
} |
| 1088 |
|
| 1089 |
PCIBus *gt64120_register(qemu_irq *pic) |
| 1090 |
{
|
| 1091 |
GT64120State *d; |
| 1092 |
PCIHostState *phb; |
| 1093 |
DeviceState *dev; |
| 1094 |
|
| 1095 |
dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
|
| 1096 |
qdev_init_nofail(dev); |
| 1097 |
d = GT64120_PCI_HOST_BRIDGE(dev); |
| 1098 |
phb = &d->pci; |
| 1099 |
phb->bus = pci_register_bus(dev, "pci",
|
| 1100 |
gt64120_pci_set_irq, gt64120_pci_map_irq, |
| 1101 |
pic, |
| 1102 |
get_system_memory(), |
| 1103 |
get_system_io(), |
| 1104 |
PCI_DEVFN(18, 0), 4); |
| 1105 |
memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000); |
| 1106 |
|
| 1107 |
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); |
| 1108 |
return phb->bus;
|
| 1109 |
} |
| 1110 |
|
| 1111 |
static int gt64120_init(SysBusDevice *dev) |
| 1112 |
{
|
| 1113 |
GT64120State *s; |
| 1114 |
|
| 1115 |
s = GT64120_PCI_HOST_BRIDGE(dev); |
| 1116 |
|
| 1117 |
/* FIXME: This value is computed from registers during reset, but some
|
| 1118 |
devices (e.g. VGA card) need to know it when they are registered.
|
| 1119 |
This also mean that changing the register to change the mapping
|
| 1120 |
does not fully work. */
|
| 1121 |
isa_mem_base = 0x10000000;
|
| 1122 |
qemu_register_reset(gt64120_reset, s); |
| 1123 |
return 0; |
| 1124 |
} |
| 1125 |
|
| 1126 |
static int gt64120_pci_init(PCIDevice *d) |
| 1127 |
{
|
| 1128 |
/* FIXME: Malta specific hw assumptions ahead */
|
| 1129 |
pci_set_word(d->config + PCI_COMMAND, 0);
|
| 1130 |
pci_set_word(d->config + PCI_STATUS, |
| 1131 |
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
| 1132 |
pci_config_set_prog_interface(d->config, 0);
|
| 1133 |
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
|
| 1134 |
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
|
| 1135 |
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
|
| 1136 |
pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
|
| 1137 |
pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
|
| 1138 |
pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
|
| 1139 |
pci_set_byte(d->config + 0x3d, 0x01); |
| 1140 |
|
| 1141 |
return 0; |
| 1142 |
} |
| 1143 |
|
| 1144 |
static void gt64120_pci_class_init(ObjectClass *klass, void *data) |
| 1145 |
{
|
| 1146 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 1147 |
|
| 1148 |
k->init = gt64120_pci_init; |
| 1149 |
k->vendor_id = PCI_VENDOR_ID_MARVELL; |
| 1150 |
k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; |
| 1151 |
k->revision = 0x10;
|
| 1152 |
k->class_id = PCI_CLASS_BRIDGE_HOST; |
| 1153 |
} |
| 1154 |
|
| 1155 |
static const TypeInfo gt64120_pci_info = { |
| 1156 |
.name = "gt64120_pci",
|
| 1157 |
.parent = TYPE_PCI_DEVICE, |
| 1158 |
.instance_size = sizeof(PCIDevice),
|
| 1159 |
.class_init = gt64120_pci_class_init, |
| 1160 |
}; |
| 1161 |
|
| 1162 |
static void gt64120_class_init(ObjectClass *klass, void *data) |
| 1163 |
{
|
| 1164 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
| 1165 |
|
| 1166 |
sdc->init = gt64120_init; |
| 1167 |
} |
| 1168 |
|
| 1169 |
static const TypeInfo gt64120_info = { |
| 1170 |
.name = TYPE_GT64120_PCI_HOST_BRIDGE, |
| 1171 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 1172 |
.instance_size = sizeof(GT64120State),
|
| 1173 |
.class_init = gt64120_class_init, |
| 1174 |
}; |
| 1175 |
|
| 1176 |
static void gt64120_pci_register_types(void) |
| 1177 |
{
|
| 1178 |
type_register_static(>64120_info); |
| 1179 |
type_register_static(>64120_pci_info); |
| 1180 |
} |
| 1181 |
|
| 1182 |
type_init(gt64120_pci_register_types) |