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/*
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* NetBSD header file, copied from
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* http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h
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*/
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/*-
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* Copyright (c) 2006 IronPort Systems
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* Copyright (c) 2007 LSI Corp.
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* Copyright (c) 2007 Rajesh Prabhakaran.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef MFI_REG_H
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#define MFI_REG_H
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|
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/*
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* MegaRAID SAS MFI firmware definitions
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*/
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|
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/*
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* Start with the register set. All registers are 32 bits wide.
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* The usual Intel IOP style setup.
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*/
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#define MFI_IMSG0 0x10 /* Inbound message 0 */ |
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#define MFI_IMSG1 0x14 /* Inbound message 1 */ |
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#define MFI_OMSG0 0x18 /* Outbound message 0 */ |
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#define MFI_OMSG1 0x1c /* Outbound message 1 */ |
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#define MFI_IDB 0x20 /* Inbound doorbell */ |
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#define MFI_ISTS 0x24 /* Inbound interrupt status */ |
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#define MFI_IMSK 0x28 /* Inbound interrupt mask */ |
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#define MFI_ODB 0x2c /* Outbound doorbell */ |
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#define MFI_OSTS 0x30 /* Outbound interrupt status */ |
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#define MFI_OMSK 0x34 /* Outbound interrupt mask */ |
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#define MFI_IQP 0x40 /* Inbound queue port */ |
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#define MFI_OQP 0x44 /* Outbound queue port */ |
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/*
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* 1078 specific related register
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*/
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#define MFI_ODR0 0x9c /* outbound doorbell register0 */ |
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#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ |
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#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ |
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#define MFI_IQPL 0xc0 /* Inbound queue port (low bytes) */ |
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#define MFI_IQPH 0xc4 /* Inbound queue port (high bytes) */ |
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#define MFI_DIAG 0xf8 /* Host diag */ |
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#define MFI_SEQ 0xfc /* Sequencer offset */ |
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#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ |
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#define MFI_RMI 0x2 /* reply message interrupt */ |
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#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ |
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#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ |
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/*
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* gen2 specific changes
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*/
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#define MFI_GEN2_EIM 0x00000005 /* gen2 enable interrupt mask */ |
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#define MFI_GEN2_RM 0x00000001 /* reply gen2 message interrupt */ |
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/*
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* skinny specific changes
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*/
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#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ |
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#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ |
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/* Bits for MFI_OSTS */
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#define MFI_OSTS_INTR_VALID 0x00000002 |
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/*
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* Firmware state values. Found in OMSG0 during initialization.
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*/
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#define MFI_FWSTATE_MASK 0xf0000000 |
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#define MFI_FWSTATE_UNDEFINED 0x00000000 |
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#define MFI_FWSTATE_BB_INIT 0x10000000 |
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#define MFI_FWSTATE_FW_INIT 0x40000000 |
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#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 |
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#define MFI_FWSTATE_FW_INIT_2 0x70000000 |
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#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 |
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#define MFI_FWSTATE_BOOT_MSG_PENDING 0x90000000 |
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#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 |
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#define MFI_FWSTATE_READY 0xb0000000 |
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#define MFI_FWSTATE_OPERATIONAL 0xc0000000 |
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#define MFI_FWSTATE_FAULT 0xf0000000 |
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#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 |
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#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff |
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#define MFI_FWSTATE_MSIX_SUPPORTED 0x04000000 |
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#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 |
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/*
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* Control bits to drive the card to ready state. These go into the IDB
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* register.
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*/
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#define MFI_FWINIT_ABORT 0x00000001 /* Abort all pending commands */ |
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#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ |
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#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ |
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#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ |
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#define MFI_FWINIT_HOTPLUG 0x00000010 |
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#define MFI_FWINIT_STOP_ADP 0x00000020 /* Move to operational, stop */ |
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#define MFI_FWINIT_ADP_RESET 0x00000040 /* Reset ADP */ |
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/* MFI Commands */
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typedef enum { |
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MFI_CMD_INIT = 0x00,
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MFI_CMD_LD_READ, |
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MFI_CMD_LD_WRITE, |
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MFI_CMD_LD_SCSI_IO, |
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MFI_CMD_PD_SCSI_IO, |
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MFI_CMD_DCMD, |
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MFI_CMD_ABORT, |
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MFI_CMD_SMP, |
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MFI_CMD_STP |
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} mfi_cmd_t; |
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/* Direct commands */
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typedef enum { |
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MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100,
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MFI_DCMD_CTRL_GET_INFO = 0x01010000,
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MFI_DCMD_CTRL_GET_PROPERTIES = 0x01020100,
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MFI_DCMD_CTRL_SET_PROPERTIES = 0x01020200,
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MFI_DCMD_CTRL_ALARM = 0x01030000,
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MFI_DCMD_CTRL_ALARM_GET = 0x01030100,
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MFI_DCMD_CTRL_ALARM_ENABLE = 0x01030200,
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MFI_DCMD_CTRL_ALARM_DISABLE = 0x01030300,
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MFI_DCMD_CTRL_ALARM_SILENCE = 0x01030400,
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MFI_DCMD_CTRL_ALARM_TEST = 0x01030500,
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MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
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MFI_DCMD_CTRL_EVENT_CLEAR = 0x01040200,
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MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
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MFI_DCMD_CTRL_EVENT_COUNT = 0x01040400,
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MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
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MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
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MFI_DCMD_HIBERNATE_STANDBY = 0x01060000,
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MFI_DCMD_CTRL_GET_TIME = 0x01080101,
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MFI_DCMD_CTRL_SET_TIME = 0x01080102,
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MFI_DCMD_CTRL_BIOS_DATA_GET = 0x010c0100,
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MFI_DCMD_CTRL_BIOS_DATA_SET = 0x010c0200,
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MFI_DCMD_CTRL_FACTORY_DEFAULTS = 0x010d0000,
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MFI_DCMD_CTRL_MFC_DEFAULTS_GET = 0x010e0201,
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MFI_DCMD_CTRL_MFC_DEFAULTS_SET = 0x010e0202,
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MFI_DCMD_CTRL_CACHE_FLUSH = 0x01101000,
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MFI_DCMD_PD_GET_LIST = 0x02010000,
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MFI_DCMD_PD_LIST_QUERY = 0x02010100,
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MFI_DCMD_PD_GET_INFO = 0x02020000,
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MFI_DCMD_PD_STATE_SET = 0x02030100,
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MFI_DCMD_PD_REBUILD = 0x02040100,
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MFI_DCMD_PD_BLINK = 0x02070100,
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MFI_DCMD_PD_UNBLINK = 0x02070200,
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MFI_DCMD_LD_GET_LIST = 0x03010000,
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MFI_DCMD_LD_GET_INFO = 0x03020000,
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MFI_DCMD_LD_GET_PROP = 0x03030000,
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MFI_DCMD_LD_SET_PROP = 0x03040000,
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MFI_DCMD_LD_DELETE = 0x03090000,
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MFI_DCMD_CFG_READ = 0x04010000,
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MFI_DCMD_CFG_ADD = 0x04020000,
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MFI_DCMD_CFG_CLEAR = 0x04030000,
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MFI_DCMD_CFG_FOREIGN_READ = 0x04060100,
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MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
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MFI_DCMD_BBU_STATUS = 0x05010000,
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MFI_DCMD_BBU_CAPACITY_INFO = 0x05020000,
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MFI_DCMD_BBU_DESIGN_INFO = 0x05030000,
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MFI_DCMD_BBU_PROP_GET = 0x05050100,
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MFI_DCMD_CLUSTER = 0x08000000,
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MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
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MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
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} mfi_dcmd_t; |
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/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
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#define MFI_FLUSHCACHE_CTRL 0x01 |
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#define MFI_FLUSHCACHE_DISK 0x02 |
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/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
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#define MFI_SHUTDOWN_SPINDOWN 0x01 |
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/*
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* MFI Frame flags
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*/
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typedef enum { |
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MFI_FRAME_DONT_POST_IN_REPLY_QUEUE = 0x0001,
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MFI_FRAME_SGL64 = 0x0002,
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MFI_FRAME_SENSE64 = 0x0004,
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MFI_FRAME_DIR_WRITE = 0x0008,
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MFI_FRAME_DIR_READ = 0x0010,
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MFI_FRAME_IEEE_SGL = 0x0020,
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} mfi_frame_flags; |
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/* MFI Status codes */
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typedef enum { |
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MFI_STAT_OK = 0x00,
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MFI_STAT_INVALID_CMD, |
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MFI_STAT_INVALID_DCMD, |
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MFI_STAT_INVALID_PARAMETER, |
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MFI_STAT_INVALID_SEQUENCE_NUMBER, |
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MFI_STAT_ABORT_NOT_POSSIBLE, |
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MFI_STAT_APP_HOST_CODE_NOT_FOUND, |
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MFI_STAT_APP_IN_USE, |
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MFI_STAT_APP_NOT_INITIALIZED, |
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MFI_STAT_ARRAY_INDEX_INVALID, |
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MFI_STAT_ARRAY_ROW_NOT_EMPTY, |
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MFI_STAT_CONFIG_RESOURCE_CONFLICT, |
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MFI_STAT_DEVICE_NOT_FOUND, |
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MFI_STAT_DRIVE_TOO_SMALL, |
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MFI_STAT_FLASH_ALLOC_FAIL, |
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MFI_STAT_FLASH_BUSY, |
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MFI_STAT_FLASH_ERROR = 0x10,
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MFI_STAT_FLASH_IMAGE_BAD, |
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MFI_STAT_FLASH_IMAGE_INCOMPLETE, |
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MFI_STAT_FLASH_NOT_OPEN, |
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MFI_STAT_FLASH_NOT_STARTED, |
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MFI_STAT_FLUSH_FAILED, |
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MFI_STAT_HOST_CODE_NOT_FOUNT, |
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MFI_STAT_LD_CC_IN_PROGRESS, |
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MFI_STAT_LD_INIT_IN_PROGRESS, |
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MFI_STAT_LD_LBA_OUT_OF_RANGE, |
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MFI_STAT_LD_MAX_CONFIGURED, |
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MFI_STAT_LD_NOT_OPTIMAL, |
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MFI_STAT_LD_RBLD_IN_PROGRESS, |
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MFI_STAT_LD_RECON_IN_PROGRESS, |
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MFI_STAT_LD_WRONG_RAID_LEVEL, |
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MFI_STAT_MAX_SPARES_EXCEEDED, |
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MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
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MFI_STAT_MFC_HW_ERROR, |
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MFI_STAT_NO_HW_PRESENT, |
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MFI_STAT_NOT_FOUND, |
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MFI_STAT_NOT_IN_ENCL, |
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MFI_STAT_PD_CLEAR_IN_PROGRESS, |
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MFI_STAT_PD_TYPE_WRONG, |
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MFI_STAT_PR_DISABLED, |
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MFI_STAT_ROW_INDEX_INVALID, |
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MFI_STAT_SAS_CONFIG_INVALID_ACTION, |
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MFI_STAT_SAS_CONFIG_INVALID_DATA, |
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MFI_STAT_SAS_CONFIG_INVALID_PAGE, |
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MFI_STAT_SAS_CONFIG_INVALID_TYPE, |
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MFI_STAT_SCSI_DONE_WITH_ERROR, |
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MFI_STAT_SCSI_IO_FAILED, |
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MFI_STAT_SCSI_RESERVATION_CONFLICT, |
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MFI_STAT_SHUTDOWN_FAILED = 0x30,
|
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MFI_STAT_TIME_NOT_SET, |
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MFI_STAT_WRONG_STATE, |
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MFI_STAT_LD_OFFLINE, |
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MFI_STAT_PEER_NOTIFICATION_REJECTED, |
259 |
MFI_STAT_PEER_NOTIFICATION_FAILED, |
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MFI_STAT_RESERVATION_IN_PROGRESS, |
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MFI_STAT_I2C_ERRORS_DETECTED, |
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MFI_STAT_PCI_ERRORS_DETECTED, |
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MFI_STAT_DIAG_FAILED, |
264 |
MFI_STAT_BOOT_MSG_PENDING, |
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MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, |
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MFI_STAT_INVALID_SGL, |
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MFI_STAT_UNSUPPORTED_HW, |
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MFI_STAT_CC_SCHEDULE_DISABLED, |
269 |
MFI_STAT_PD_COPYBACK_IN_PROGRESS, |
270 |
MFI_STAT_MULTIPLE_PDS_IN_ARRAY = 0x40,
|
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MFI_STAT_FW_DOWNLOAD_ERROR, |
272 |
MFI_STAT_FEATURE_SECURITY_NOT_ENABLED, |
273 |
MFI_STAT_LOCK_KEY_ALREADY_EXISTS, |
274 |
MFI_STAT_LOCK_KEY_BACKUP_NOT_ALLOWED, |
275 |
MFI_STAT_LOCK_KEY_VERIFY_NOT_ALLOWED, |
276 |
MFI_STAT_LOCK_KEY_VERIFY_FAILED, |
277 |
MFI_STAT_LOCK_KEY_REKEY_NOT_ALLOWED, |
278 |
MFI_STAT_LOCK_KEY_INVALID, |
279 |
MFI_STAT_LOCK_KEY_ESCROW_INVALID, |
280 |
MFI_STAT_LOCK_KEY_BACKUP_REQUIRED, |
281 |
MFI_STAT_SECURE_LD_EXISTS, |
282 |
MFI_STAT_LD_SECURE_NOT_ALLOWED, |
283 |
MFI_STAT_REPROVISION_NOT_ALLOWED, |
284 |
MFI_STAT_PD_SECURITY_TYPE_WRONG, |
285 |
MFI_STAT_LD_ENCRYPTION_TYPE_INVALID, |
286 |
MFI_STAT_CONFIG_FDE_NON_FDE_MIX_NOT_ALLOWED = 0x50,
|
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MFI_STAT_CONFIG_LD_ENCRYPTION_TYPE_MIX_NOT_ALLOWED, |
288 |
MFI_STAT_SECRET_KEY_NOT_ALLOWED, |
289 |
MFI_STAT_PD_HW_ERRORS_DETECTED, |
290 |
MFI_STAT_LD_CACHE_PINNED, |
291 |
MFI_STAT_POWER_STATE_SET_IN_PROGRESS, |
292 |
MFI_STAT_POWER_STATE_SET_BUSY, |
293 |
MFI_STAT_POWER_STATE_WRONG, |
294 |
MFI_STAT_PR_NO_AVAILABLE_PD_FOUND, |
295 |
MFI_STAT_CTRL_RESET_REQUIRED, |
296 |
MFI_STAT_LOCK_KEY_EKM_NO_BOOT_AGENT, |
297 |
MFI_STAT_SNAP_NO_SPACE, |
298 |
MFI_STAT_SNAP_PARTIAL_FAILURE, |
299 |
MFI_STAT_UPGRADE_KEY_INCOMPATIBLE, |
300 |
MFI_STAT_PFK_INCOMPATIBLE, |
301 |
MFI_STAT_PD_MAX_UNCONFIGURED, |
302 |
MFI_STAT_IO_METRICS_DISABLED = 0x60,
|
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MFI_STAT_AEC_NOT_STOPPED, |
304 |
MFI_STAT_PI_TYPE_WRONG, |
305 |
MFI_STAT_LD_PD_PI_INCOMPATIBLE, |
306 |
MFI_STAT_PI_NOT_ENABLED, |
307 |
MFI_STAT_LD_BLOCK_SIZE_MISMATCH, |
308 |
MFI_STAT_INVALID_STATUS = 0xFF
|
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} mfi_status_t; |
310 |
|
311 |
/* Event classes */
|
312 |
typedef enum { |
313 |
MFI_EVT_CLASS_DEBUG = -2,
|
314 |
MFI_EVT_CLASS_PROGRESS = -1,
|
315 |
MFI_EVT_CLASS_INFO = 0,
|
316 |
MFI_EVT_CLASS_WARNING = 1,
|
317 |
MFI_EVT_CLASS_CRITICAL = 2,
|
318 |
MFI_EVT_CLASS_FATAL = 3,
|
319 |
MFI_EVT_CLASS_DEAD = 4
|
320 |
} mfi_evt_class_t; |
321 |
|
322 |
/* Event locales */
|
323 |
typedef enum { |
324 |
MFI_EVT_LOCALE_LD = 0x0001,
|
325 |
MFI_EVT_LOCALE_PD = 0x0002,
|
326 |
MFI_EVT_LOCALE_ENCL = 0x0004,
|
327 |
MFI_EVT_LOCALE_BBU = 0x0008,
|
328 |
MFI_EVT_LOCALE_SAS = 0x0010,
|
329 |
MFI_EVT_LOCALE_CTRL = 0x0020,
|
330 |
MFI_EVT_LOCALE_CONFIG = 0x0040,
|
331 |
MFI_EVT_LOCALE_CLUSTER = 0x0080,
|
332 |
MFI_EVT_LOCALE_ALL = 0xffff
|
333 |
} mfi_evt_locale_t; |
334 |
|
335 |
/* Event args */
|
336 |
typedef enum { |
337 |
MR_EVT_ARGS_NONE = 0x00,
|
338 |
MR_EVT_ARGS_CDB_SENSE, |
339 |
MR_EVT_ARGS_LD, |
340 |
MR_EVT_ARGS_LD_COUNT, |
341 |
MR_EVT_ARGS_LD_LBA, |
342 |
MR_EVT_ARGS_LD_OWNER, |
343 |
MR_EVT_ARGS_LD_LBA_PD_LBA, |
344 |
MR_EVT_ARGS_LD_PROG, |
345 |
MR_EVT_ARGS_LD_STATE, |
346 |
MR_EVT_ARGS_LD_STRIP, |
347 |
MR_EVT_ARGS_PD, |
348 |
MR_EVT_ARGS_PD_ERR, |
349 |
MR_EVT_ARGS_PD_LBA, |
350 |
MR_EVT_ARGS_PD_LBA_LD, |
351 |
MR_EVT_ARGS_PD_PROG, |
352 |
MR_EVT_ARGS_PD_STATE, |
353 |
MR_EVT_ARGS_PCI, |
354 |
MR_EVT_ARGS_RATE, |
355 |
MR_EVT_ARGS_STR, |
356 |
MR_EVT_ARGS_TIME, |
357 |
MR_EVT_ARGS_ECC, |
358 |
MR_EVT_ARGS_LD_PROP, |
359 |
MR_EVT_ARGS_PD_SPARE, |
360 |
MR_EVT_ARGS_PD_INDEX, |
361 |
MR_EVT_ARGS_DIAG_PASS, |
362 |
MR_EVT_ARGS_DIAG_FAIL, |
363 |
MR_EVT_ARGS_PD_LBA_LBA, |
364 |
MR_EVT_ARGS_PORT_PHY, |
365 |
MR_EVT_ARGS_PD_MISSING, |
366 |
MR_EVT_ARGS_PD_ADDRESS, |
367 |
MR_EVT_ARGS_BITMAP, |
368 |
MR_EVT_ARGS_CONNECTOR, |
369 |
MR_EVT_ARGS_PD_PD, |
370 |
MR_EVT_ARGS_PD_FRU, |
371 |
MR_EVT_ARGS_PD_PATHINFO, |
372 |
MR_EVT_ARGS_PD_POWER_STATE, |
373 |
MR_EVT_ARGS_GENERIC, |
374 |
} mfi_evt_args; |
375 |
|
376 |
/* Event codes */
|
377 |
#define MR_EVT_CFG_CLEARED 0x0004 |
378 |
#define MR_EVT_CTRL_SHUTDOWN 0x002a |
379 |
#define MR_EVT_LD_STATE_CHANGE 0x0051 |
380 |
#define MR_EVT_PD_INSERTED 0x005b |
381 |
#define MR_EVT_PD_REMOVED 0x0070 |
382 |
#define MR_EVT_PD_STATE_CHANGED 0x0072 |
383 |
#define MR_EVT_LD_CREATED 0x008a |
384 |
#define MR_EVT_LD_DELETED 0x008b |
385 |
#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db |
386 |
#define MR_EVT_LD_OFFLINE 0x00fc |
387 |
#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 |
388 |
|
389 |
typedef enum { |
390 |
MR_LD_CACHE_WRITE_BACK = 0x01,
|
391 |
MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
|
392 |
MR_LD_CACHE_READ_AHEAD = 0x04,
|
393 |
MR_LD_CACHE_READ_ADAPTIVE = 0x08,
|
394 |
MR_LD_CACHE_WRITE_CACHE_BAD_BBU = 0x10,
|
395 |
MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
|
396 |
MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
|
397 |
} mfi_ld_cache; |
398 |
|
399 |
typedef enum { |
400 |
MR_PD_CACHE_UNCHANGED = 0,
|
401 |
MR_PD_CACHE_ENABLE = 1,
|
402 |
MR_PD_CACHE_DISABLE = 2
|
403 |
} mfi_pd_cache; |
404 |
|
405 |
typedef enum { |
406 |
MR_PD_QUERY_TYPE_ALL = 0,
|
407 |
MR_PD_QUERY_TYPE_STATE = 1,
|
408 |
MR_PD_QUERY_TYPE_POWER_STATE = 2,
|
409 |
MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
|
410 |
MR_PD_QUERY_TYPE_SPEED = 4,
|
411 |
MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, /*query for system drives */ |
412 |
} mfi_pd_query_type; |
413 |
|
414 |
/*
|
415 |
* Other propertities and definitions
|
416 |
*/
|
417 |
#define MFI_MAX_PD_CHANNELS 2 |
418 |
#define MFI_MAX_LD_CHANNELS 2 |
419 |
#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
|
420 |
#define MFI_MAX_CHANNEL_DEVS 128 |
421 |
#define MFI_DEFAULT_ID -1 |
422 |
#define MFI_MAX_LUN 8 |
423 |
#define MFI_MAX_LD 64 |
424 |
|
425 |
#define MFI_FRAME_SIZE 64 |
426 |
#define MFI_MBOX_SIZE 12 |
427 |
|
428 |
/* Firmware flashing can take 40s */
|
429 |
#define MFI_POLL_TIMEOUT_SECS 50 |
430 |
|
431 |
/* Allow for speedier math calculations */
|
432 |
#define MFI_SECTOR_LEN 512 |
433 |
|
434 |
/* Scatter Gather elements */
|
435 |
struct mfi_sg32 {
|
436 |
uint32_t addr; |
437 |
uint32_t len; |
438 |
} QEMU_PACKED; |
439 |
|
440 |
struct mfi_sg64 {
|
441 |
uint64_t addr; |
442 |
uint32_t len; |
443 |
} QEMU_PACKED; |
444 |
|
445 |
struct mfi_sg_skinny {
|
446 |
uint64_t addr; |
447 |
uint32_t len; |
448 |
uint32_t flag; |
449 |
} QEMU_PACKED; |
450 |
|
451 |
union mfi_sgl {
|
452 |
struct mfi_sg32 sg32[1]; |
453 |
struct mfi_sg64 sg64[1]; |
454 |
struct mfi_sg_skinny sg_skinny[1]; |
455 |
} QEMU_PACKED; |
456 |
|
457 |
/* Message frames. All messages have a common header */
|
458 |
struct mfi_frame_header {
|
459 |
uint8_t frame_cmd; |
460 |
uint8_t sense_len; |
461 |
uint8_t cmd_status; |
462 |
uint8_t scsi_status; |
463 |
uint8_t target_id; |
464 |
uint8_t lun_id; |
465 |
uint8_t cdb_len; |
466 |
uint8_t sge_count; |
467 |
uint64_t context; |
468 |
uint16_t flags; |
469 |
uint16_t timeout; |
470 |
uint32_t data_len; |
471 |
} QEMU_PACKED; |
472 |
|
473 |
struct mfi_init_frame {
|
474 |
struct mfi_frame_header header;
|
475 |
uint32_t qinfo_new_addr_lo; |
476 |
uint32_t qinfo_new_addr_hi; |
477 |
uint32_t qinfo_old_addr_lo; |
478 |
uint32_t qinfo_old_addr_hi; |
479 |
uint32_t reserved[6];
|
480 |
}; |
481 |
|
482 |
#define MFI_IO_FRAME_SIZE 40 |
483 |
struct mfi_io_frame {
|
484 |
struct mfi_frame_header header;
|
485 |
uint32_t sense_addr_lo; |
486 |
uint32_t sense_addr_hi; |
487 |
uint32_t lba_lo; |
488 |
uint32_t lba_hi; |
489 |
union mfi_sgl sgl;
|
490 |
} QEMU_PACKED; |
491 |
|
492 |
#define MFI_PASS_FRAME_SIZE 48 |
493 |
struct mfi_pass_frame {
|
494 |
struct mfi_frame_header header;
|
495 |
uint32_t sense_addr_lo; |
496 |
uint32_t sense_addr_hi; |
497 |
uint8_t cdb[16];
|
498 |
union mfi_sgl sgl;
|
499 |
} QEMU_PACKED; |
500 |
|
501 |
#define MFI_DCMD_FRAME_SIZE 40 |
502 |
struct mfi_dcmd_frame {
|
503 |
struct mfi_frame_header header;
|
504 |
uint32_t opcode; |
505 |
uint8_t mbox[MFI_MBOX_SIZE]; |
506 |
union mfi_sgl sgl;
|
507 |
} QEMU_PACKED; |
508 |
|
509 |
struct mfi_abort_frame {
|
510 |
struct mfi_frame_header header;
|
511 |
uint64_t abort_context; |
512 |
uint32_t abort_mfi_addr_lo; |
513 |
uint32_t abort_mfi_addr_hi; |
514 |
uint32_t reserved1[6];
|
515 |
} QEMU_PACKED; |
516 |
|
517 |
struct mfi_smp_frame {
|
518 |
struct mfi_frame_header header;
|
519 |
uint64_t sas_addr; |
520 |
union {
|
521 |
struct mfi_sg32 sg32[2]; |
522 |
struct mfi_sg64 sg64[2]; |
523 |
} sgl; |
524 |
} QEMU_PACKED; |
525 |
|
526 |
struct mfi_stp_frame {
|
527 |
struct mfi_frame_header header;
|
528 |
uint16_t fis[10];
|
529 |
uint32_t stp_flags; |
530 |
union {
|
531 |
struct mfi_sg32 sg32[2]; |
532 |
struct mfi_sg64 sg64[2]; |
533 |
} sgl; |
534 |
} QEMU_PACKED; |
535 |
|
536 |
union mfi_frame {
|
537 |
struct mfi_frame_header header;
|
538 |
struct mfi_init_frame init;
|
539 |
struct mfi_io_frame io;
|
540 |
struct mfi_pass_frame pass;
|
541 |
struct mfi_dcmd_frame dcmd;
|
542 |
struct mfi_abort_frame abort;
|
543 |
struct mfi_smp_frame smp;
|
544 |
struct mfi_stp_frame stp;
|
545 |
uint64_t raw[8];
|
546 |
uint8_t bytes[MFI_FRAME_SIZE]; |
547 |
}; |
548 |
|
549 |
#define MFI_SENSE_LEN 128 |
550 |
struct mfi_sense {
|
551 |
uint8_t data[MFI_SENSE_LEN]; |
552 |
}; |
553 |
|
554 |
#define MFI_QUEUE_FLAG_CONTEXT64 0x00000002 |
555 |
|
556 |
/* The queue init structure that is passed with the init message */
|
557 |
struct mfi_init_qinfo {
|
558 |
uint32_t flags; |
559 |
uint32_t rq_entries; |
560 |
uint32_t rq_addr_lo; |
561 |
uint32_t rq_addr_hi; |
562 |
uint32_t pi_addr_lo; |
563 |
uint32_t pi_addr_hi; |
564 |
uint32_t ci_addr_lo; |
565 |
uint32_t ci_addr_hi; |
566 |
} QEMU_PACKED; |
567 |
|
568 |
/* Controller properties */
|
569 |
struct mfi_ctrl_props {
|
570 |
uint16_t seq_num; |
571 |
uint16_t pred_fail_poll_interval; |
572 |
uint16_t intr_throttle_cnt; |
573 |
uint16_t intr_throttle_timeout; |
574 |
uint8_t rebuild_rate; |
575 |
uint8_t patrol_read_rate; |
576 |
uint8_t bgi_rate; |
577 |
uint8_t cc_rate; |
578 |
uint8_t recon_rate; |
579 |
uint8_t cache_flush_interval; |
580 |
uint8_t spinup_drv_cnt; |
581 |
uint8_t spinup_delay; |
582 |
uint8_t cluster_enable; |
583 |
uint8_t coercion_mode; |
584 |
uint8_t alarm_enable; |
585 |
uint8_t disable_auto_rebuild; |
586 |
uint8_t disable_battery_warn; |
587 |
uint8_t ecc_bucket_size; |
588 |
uint16_t ecc_bucket_leak_rate; |
589 |
uint8_t restore_hotspare_on_insertion; |
590 |
uint8_t expose_encl_devices; |
591 |
uint8_t maintainPdFailHistory; |
592 |
uint8_t disallowHostRequestReordering; |
593 |
uint8_t abortCCOnError; |
594 |
uint8_t loadBalanceMode; |
595 |
uint8_t disableAutoDetectBackplane; |
596 |
uint8_t snapVDSpace; |
597 |
uint32_t OnOffProperties; |
598 |
/* set TRUE to disable copyBack (0=copyback enabled) */
|
599 |
#define MFI_CTRL_PROP_CopyBackDisabled (1 << 0) |
600 |
#define MFI_CTRL_PROP_SMARTerEnabled (1 << 1) |
601 |
#define MFI_CTRL_PROP_PRCorrectUnconfiguredAreas (1 << 2) |
602 |
#define MFI_CTRL_PROP_UseFdeOnly (1 << 3) |
603 |
#define MFI_CTRL_PROP_DisableNCQ (1 << 4) |
604 |
#define MFI_CTRL_PROP_SSDSMARTerEnabled (1 << 5) |
605 |
#define MFI_CTRL_PROP_SSDPatrolReadEnabled (1 << 6) |
606 |
#define MFI_CTRL_PROP_EnableSpinDownUnconfigured (1 << 7) |
607 |
#define MFI_CTRL_PROP_AutoEnhancedImport (1 << 8) |
608 |
#define MFI_CTRL_PROP_EnableSecretKeyControl (1 << 9) |
609 |
#define MFI_CTRL_PROP_DisableOnlineCtrlReset (1 << 10) |
610 |
#define MFI_CTRL_PROP_AllowBootWithPinnedCache (1 << 11) |
611 |
#define MFI_CTRL_PROP_DisableSpinDownHS (1 << 12) |
612 |
#define MFI_CTRL_PROP_EnableJBOD (1 << 13) |
613 |
|
614 |
uint8_t autoSnapVDSpace; /* % of source LD to be
|
615 |
* reserved for auto snapshot
|
616 |
* in snapshot repository, for
|
617 |
* metadata and user data
|
618 |
* 1=5%, 2=10%, 3=15% and so on
|
619 |
*/
|
620 |
uint8_t viewSpace; /* snapshot writeable VIEWs
|
621 |
* capacity as a % of source LD
|
622 |
* capacity. 0=READ only
|
623 |
* 1=5%, 2=10%, 3=15% and so on
|
624 |
*/
|
625 |
uint16_t spinDownTime; /* # of idle minutes before device
|
626 |
* is spun down (0=use FW defaults)
|
627 |
*/
|
628 |
uint8_t reserved[24];
|
629 |
} QEMU_PACKED; |
630 |
|
631 |
/* PCI information about the card. */
|
632 |
struct mfi_info_pci {
|
633 |
uint16_t vendor; |
634 |
uint16_t device; |
635 |
uint16_t subvendor; |
636 |
uint16_t subdevice; |
637 |
uint8_t reserved[24];
|
638 |
} QEMU_PACKED; |
639 |
|
640 |
/* Host (front end) interface information */
|
641 |
struct mfi_info_host {
|
642 |
uint8_t type; |
643 |
#define MFI_INFO_HOST_PCIX 0x01 |
644 |
#define MFI_INFO_HOST_PCIE 0x02 |
645 |
#define MFI_INFO_HOST_ISCSI 0x04 |
646 |
#define MFI_INFO_HOST_SAS3G 0x08 |
647 |
uint8_t reserved[6];
|
648 |
uint8_t port_count; |
649 |
uint64_t port_addr[8];
|
650 |
} QEMU_PACKED; |
651 |
|
652 |
/* Device (back end) interface information */
|
653 |
struct mfi_info_device {
|
654 |
uint8_t type; |
655 |
#define MFI_INFO_DEV_SPI 0x01 |
656 |
#define MFI_INFO_DEV_SAS3G 0x02 |
657 |
#define MFI_INFO_DEV_SATA1 0x04 |
658 |
#define MFI_INFO_DEV_SATA3G 0x08 |
659 |
#define MFI_INFO_DEV_PCIE 0x10 |
660 |
uint8_t reserved[6];
|
661 |
uint8_t port_count; |
662 |
uint64_t port_addr[8];
|
663 |
} QEMU_PACKED; |
664 |
|
665 |
/* Firmware component information */
|
666 |
struct mfi_info_component {
|
667 |
char name[8]; |
668 |
char version[32]; |
669 |
char build_date[16]; |
670 |
char build_time[16]; |
671 |
} QEMU_PACKED; |
672 |
|
673 |
/* Controller default settings */
|
674 |
struct mfi_defaults {
|
675 |
uint64_t sas_addr; |
676 |
uint8_t phy_polarity; |
677 |
uint8_t background_rate; |
678 |
uint8_t stripe_size; |
679 |
uint8_t flush_time; |
680 |
uint8_t write_back; |
681 |
uint8_t read_ahead; |
682 |
uint8_t cache_when_bbu_bad; |
683 |
uint8_t cached_io; |
684 |
uint8_t smart_mode; |
685 |
uint8_t alarm_disable; |
686 |
uint8_t coercion; |
687 |
uint8_t zrc_config; |
688 |
uint8_t dirty_led_shows_drive_activity; |
689 |
uint8_t bios_continue_on_error; |
690 |
uint8_t spindown_mode; |
691 |
uint8_t allowed_device_types; |
692 |
uint8_t allow_mix_in_enclosure; |
693 |
uint8_t allow_mix_in_ld; |
694 |
uint8_t allow_sata_in_cluster; |
695 |
uint8_t max_chained_enclosures; |
696 |
uint8_t disable_ctrl_r; |
697 |
uint8_t enable_web_bios; |
698 |
uint8_t phy_polarity_split; |
699 |
uint8_t direct_pd_mapping; |
700 |
uint8_t bios_enumerate_lds; |
701 |
uint8_t restored_hot_spare_on_insertion; |
702 |
uint8_t expose_enclosure_devices; |
703 |
uint8_t maintain_pd_fail_history; |
704 |
uint8_t disable_puncture; |
705 |
uint8_t zero_based_enumeration; |
706 |
uint8_t disable_preboot_cli; |
707 |
uint8_t show_drive_led_on_activity; |
708 |
uint8_t cluster_disable; |
709 |
uint8_t sas_disable; |
710 |
uint8_t auto_detect_backplane; |
711 |
uint8_t fde_only; |
712 |
uint8_t delay_during_post; |
713 |
uint8_t resv[19];
|
714 |
} QEMU_PACKED; |
715 |
|
716 |
/* Controller default settings */
|
717 |
struct mfi_bios_data {
|
718 |
uint16_t boot_target_id; |
719 |
uint8_t do_not_int_13; |
720 |
uint8_t continue_on_error; |
721 |
uint8_t verbose; |
722 |
uint8_t geometry; |
723 |
uint8_t expose_all_drives; |
724 |
uint8_t reserved[56];
|
725 |
uint8_t check_sum; |
726 |
} QEMU_PACKED; |
727 |
|
728 |
/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
|
729 |
struct mfi_ctrl_info {
|
730 |
struct mfi_info_pci pci;
|
731 |
struct mfi_info_host host;
|
732 |
struct mfi_info_device device;
|
733 |
|
734 |
/* Firmware components that are present and active. */
|
735 |
uint32_t image_check_word; |
736 |
uint32_t image_component_count; |
737 |
struct mfi_info_component image_component[8]; |
738 |
|
739 |
/* Firmware components that have been flashed but are inactive */
|
740 |
uint32_t pending_image_component_count; |
741 |
struct mfi_info_component pending_image_component[8]; |
742 |
|
743 |
uint8_t max_arms; |
744 |
uint8_t max_spans; |
745 |
uint8_t max_arrays; |
746 |
uint8_t max_lds; |
747 |
char product_name[80]; |
748 |
char serial_number[32]; |
749 |
uint32_t hw_present; |
750 |
#define MFI_INFO_HW_BBU 0x01 |
751 |
#define MFI_INFO_HW_ALARM 0x02 |
752 |
#define MFI_INFO_HW_NVRAM 0x04 |
753 |
#define MFI_INFO_HW_UART 0x08 |
754 |
#define MFI_INFO_HW_MEM 0x10 |
755 |
#define MFI_INFO_HW_FLASH 0x20 |
756 |
uint32_t current_fw_time; |
757 |
uint16_t max_cmds; |
758 |
uint16_t max_sg_elements; |
759 |
uint32_t max_request_size; |
760 |
uint16_t lds_present; |
761 |
uint16_t lds_degraded; |
762 |
uint16_t lds_offline; |
763 |
uint16_t pd_present; |
764 |
uint16_t pd_disks_present; |
765 |
uint16_t pd_disks_pred_failure; |
766 |
uint16_t pd_disks_failed; |
767 |
uint16_t nvram_size; |
768 |
uint16_t memory_size; |
769 |
uint16_t flash_size; |
770 |
uint16_t ram_correctable_errors; |
771 |
uint16_t ram_uncorrectable_errors; |
772 |
uint8_t cluster_allowed; |
773 |
uint8_t cluster_active; |
774 |
uint16_t max_strips_per_io; |
775 |
|
776 |
uint32_t raid_levels; |
777 |
#define MFI_INFO_RAID_0 0x01 |
778 |
#define MFI_INFO_RAID_1 0x02 |
779 |
#define MFI_INFO_RAID_5 0x04 |
780 |
#define MFI_INFO_RAID_1E 0x08 |
781 |
#define MFI_INFO_RAID_6 0x10 |
782 |
|
783 |
uint32_t adapter_ops; |
784 |
#define MFI_INFO_AOPS_RBLD_RATE 0x0001 |
785 |
#define MFI_INFO_AOPS_CC_RATE 0x0002 |
786 |
#define MFI_INFO_AOPS_BGI_RATE 0x0004 |
787 |
#define MFI_INFO_AOPS_RECON_RATE 0x0008 |
788 |
#define MFI_INFO_AOPS_PATROL_RATE 0x0010 |
789 |
#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 |
790 |
#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 |
791 |
#define MFI_INFO_AOPS_BBU 0x0080 |
792 |
#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 |
793 |
#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 |
794 |
#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 |
795 |
#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 |
796 |
#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 |
797 |
#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 |
798 |
#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 |
799 |
|
800 |
uint32_t ld_ops; |
801 |
#define MFI_INFO_LDOPS_READ_POLICY 0x01 |
802 |
#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 |
803 |
#define MFI_INFO_LDOPS_IO_POLICY 0x04 |
804 |
#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 |
805 |
#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 |
806 |
|
807 |
struct {
|
808 |
uint8_t min; |
809 |
uint8_t max; |
810 |
uint8_t reserved[2];
|
811 |
} QEMU_PACKED stripe_sz_ops; |
812 |
|
813 |
uint32_t pd_ops; |
814 |
#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 |
815 |
#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 |
816 |
#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 |
817 |
|
818 |
uint32_t pd_mix_support; |
819 |
#define MFI_INFO_PDMIX_SAS 0x01 |
820 |
#define MFI_INFO_PDMIX_SATA 0x02 |
821 |
#define MFI_INFO_PDMIX_ENCL 0x04 |
822 |
#define MFI_INFO_PDMIX_LD 0x08 |
823 |
#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 |
824 |
|
825 |
uint8_t ecc_bucket_count; |
826 |
uint8_t reserved2[11];
|
827 |
struct mfi_ctrl_props properties;
|
828 |
char package_version[0x60]; |
829 |
uint8_t pad[0x800 - 0x6a0]; |
830 |
} QEMU_PACKED; |
831 |
|
832 |
/* keep track of an event. */
|
833 |
union mfi_evt {
|
834 |
struct {
|
835 |
uint16_t locale; |
836 |
uint8_t reserved; |
837 |
int8_t class; |
838 |
} members; |
839 |
uint32_t word; |
840 |
} QEMU_PACKED; |
841 |
|
842 |
/* event log state. */
|
843 |
struct mfi_evt_log_state {
|
844 |
uint32_t newest_seq_num; |
845 |
uint32_t oldest_seq_num; |
846 |
uint32_t clear_seq_num; |
847 |
uint32_t shutdown_seq_num; |
848 |
uint32_t boot_seq_num; |
849 |
} QEMU_PACKED; |
850 |
|
851 |
struct mfi_progress {
|
852 |
uint16_t progress; |
853 |
uint16_t elapsed_seconds; |
854 |
} QEMU_PACKED; |
855 |
|
856 |
struct mfi_evt_ld {
|
857 |
uint16_t target_id; |
858 |
uint8_t ld_index; |
859 |
uint8_t reserved; |
860 |
} QEMU_PACKED; |
861 |
|
862 |
struct mfi_evt_pd {
|
863 |
uint16_t device_id; |
864 |
uint8_t enclosure_index; |
865 |
uint8_t slot_number; |
866 |
} QEMU_PACKED; |
867 |
|
868 |
/* event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
|
869 |
struct mfi_evt_detail {
|
870 |
uint32_t seq; |
871 |
uint32_t time; |
872 |
uint32_t code; |
873 |
union mfi_evt class;
|
874 |
uint8_t arg_type; |
875 |
uint8_t reserved1[15];
|
876 |
|
877 |
union {
|
878 |
struct {
|
879 |
struct mfi_evt_pd pd;
|
880 |
uint8_t cdb_len; |
881 |
uint8_t sense_len; |
882 |
uint8_t reserved[2];
|
883 |
uint8_t cdb[16];
|
884 |
uint8_t sense[64];
|
885 |
} cdb_sense; |
886 |
|
887 |
struct mfi_evt_ld ld;
|
888 |
|
889 |
struct {
|
890 |
struct mfi_evt_ld ld;
|
891 |
uint64_t count; |
892 |
} ld_count; |
893 |
|
894 |
struct {
|
895 |
uint64_t lba; |
896 |
struct mfi_evt_ld ld;
|
897 |
} ld_lba; |
898 |
|
899 |
struct {
|
900 |
struct mfi_evt_ld ld;
|
901 |
uint32_t pre_owner; |
902 |
uint32_t new_owner; |
903 |
} ld_owner; |
904 |
|
905 |
struct {
|
906 |
uint64_t ld_lba; |
907 |
uint64_t pd_lba; |
908 |
struct mfi_evt_ld ld;
|
909 |
struct mfi_evt_pd pd;
|
910 |
} ld_lba_pd_lba; |
911 |
|
912 |
struct {
|
913 |
struct mfi_evt_ld ld;
|
914 |
struct mfi_progress prog;
|
915 |
} ld_prog; |
916 |
|
917 |
struct {
|
918 |
struct mfi_evt_ld ld;
|
919 |
uint32_t prev_state; |
920 |
uint32_t new_state; |
921 |
} ld_state; |
922 |
|
923 |
struct {
|
924 |
uint64_t strip; |
925 |
struct mfi_evt_ld ld;
|
926 |
} ld_strip; |
927 |
|
928 |
struct mfi_evt_pd pd;
|
929 |
|
930 |
struct {
|
931 |
struct mfi_evt_pd pd;
|
932 |
uint32_t err; |
933 |
} pd_err; |
934 |
|
935 |
struct {
|
936 |
uint64_t lba; |
937 |
struct mfi_evt_pd pd;
|
938 |
} pd_lba; |
939 |
|
940 |
struct {
|
941 |
uint64_t lba; |
942 |
struct mfi_evt_pd pd;
|
943 |
struct mfi_evt_ld ld;
|
944 |
} pd_lba_ld; |
945 |
|
946 |
struct {
|
947 |
struct mfi_evt_pd pd;
|
948 |
struct mfi_progress prog;
|
949 |
} pd_prog; |
950 |
|
951 |
struct {
|
952 |
struct mfi_evt_pd ld;
|
953 |
uint32_t prev_state; |
954 |
uint32_t new_state; |
955 |
} pd_state; |
956 |
|
957 |
struct {
|
958 |
uint16_t venderId; |
959 |
uint16_t deviceId; |
960 |
uint16_t subVenderId; |
961 |
uint16_t subDeviceId; |
962 |
} pci; |
963 |
|
964 |
uint32_t rate; |
965 |
|
966 |
char str[96]; |
967 |
|
968 |
struct {
|
969 |
uint32_t rtc; |
970 |
uint16_t elapsedSeconds; |
971 |
} time; |
972 |
|
973 |
struct {
|
974 |
uint32_t ecar; |
975 |
uint32_t elog; |
976 |
char str[64]; |
977 |
} ecc; |
978 |
|
979 |
uint8_t b[96];
|
980 |
uint16_t s[48];
|
981 |
uint32_t w[24];
|
982 |
uint64_t d[12];
|
983 |
} args; |
984 |
|
985 |
char description[128]; |
986 |
} QEMU_PACKED; |
987 |
|
988 |
struct mfi_evt_list {
|
989 |
uint32_t count; |
990 |
uint32_t reserved; |
991 |
struct mfi_evt_detail event[1]; |
992 |
} QEMU_PACKED; |
993 |
|
994 |
union mfi_pd_ref {
|
995 |
struct {
|
996 |
uint16_t device_id; |
997 |
uint16_t seq_num; |
998 |
} v; |
999 |
uint32_t ref; |
1000 |
} QEMU_PACKED; |
1001 |
|
1002 |
union mfi_pd_ddf_type {
|
1003 |
struct {
|
1004 |
uint16_t pd_type; |
1005 |
#define MFI_PD_DDF_TYPE_FORCED_PD_GUID (1 << 0) |
1006 |
#define MFI_PD_DDF_TYPE_IN_VD (1 << 1) |
1007 |
#define MFI_PD_DDF_TYPE_IS_GLOBAL_SPARE (1 << 2) |
1008 |
#define MFI_PD_DDF_TYPE_IS_SPARE (1 << 3) |
1009 |
#define MFI_PD_DDF_TYPE_IS_FOREIGN (1 << 4) |
1010 |
#define MFI_PD_DDF_TYPE_INTF_SPI (1 << 12) |
1011 |
#define MFI_PD_DDF_TYPE_INTF_SAS (1 << 13) |
1012 |
#define MFI_PD_DDF_TYPE_INTF_SATA1 (1 << 14) |
1013 |
#define MFI_PD_DDF_TYPE_INTF_SATA3G (1 << 15) |
1014 |
uint16_t reserved; |
1015 |
} ddf; |
1016 |
struct {
|
1017 |
uint32_t reserved; |
1018 |
} non_disk; |
1019 |
uint32_t type; |
1020 |
} QEMU_PACKED; |
1021 |
|
1022 |
struct mfi_pd_progress {
|
1023 |
uint32_t active; |
1024 |
#define PD_PROGRESS_ACTIVE_REBUILD (1 << 0) |
1025 |
#define PD_PROGRESS_ACTIVE_PATROL (1 << 1) |
1026 |
#define PD_PROGRESS_ACTIVE_CLEAR (1 << 2) |
1027 |
struct mfi_progress rbld;
|
1028 |
struct mfi_progress patrol;
|
1029 |
struct mfi_progress clear;
|
1030 |
struct mfi_progress reserved[4]; |
1031 |
} QEMU_PACKED; |
1032 |
|
1033 |
struct mfi_pd_info {
|
1034 |
union mfi_pd_ref ref;
|
1035 |
uint8_t inquiry_data[96];
|
1036 |
uint8_t vpd_page83[64];
|
1037 |
uint8_t not_supported; |
1038 |
uint8_t scsi_dev_type; |
1039 |
uint8_t connected_port_bitmap; |
1040 |
uint8_t device_speed; |
1041 |
uint32_t media_err_count; |
1042 |
uint32_t other_err_count; |
1043 |
uint32_t pred_fail_count; |
1044 |
uint32_t last_pred_fail_event_seq_num; |
1045 |
uint16_t fw_state; |
1046 |
uint8_t disable_for_removal; |
1047 |
uint8_t link_speed; |
1048 |
union mfi_pd_ddf_type state;
|
1049 |
struct {
|
1050 |
uint8_t count; |
1051 |
uint8_t is_path_broken; |
1052 |
uint8_t reserved[6];
|
1053 |
uint64_t sas_addr[4];
|
1054 |
} path_info; |
1055 |
uint64_t raw_size; |
1056 |
uint64_t non_coerced_size; |
1057 |
uint64_t coerced_size; |
1058 |
uint16_t encl_device_id; |
1059 |
uint8_t encl_index; |
1060 |
uint8_t slot_number; |
1061 |
struct mfi_pd_progress prog_info;
|
1062 |
uint8_t bad_block_table_full; |
1063 |
uint8_t unusable_in_current_config; |
1064 |
uint8_t vpd_page83_ext[64];
|
1065 |
uint8_t reserved[512-358]; |
1066 |
} QEMU_PACKED; |
1067 |
|
1068 |
struct mfi_pd_address {
|
1069 |
uint16_t device_id; |
1070 |
uint16_t encl_device_id; |
1071 |
uint8_t encl_index; |
1072 |
uint8_t slot_number; |
1073 |
uint8_t scsi_dev_type; |
1074 |
uint8_t connect_port_bitmap; |
1075 |
uint64_t sas_addr[2];
|
1076 |
} QEMU_PACKED; |
1077 |
|
1078 |
#define MFI_MAX_SYS_PDS 240 |
1079 |
struct mfi_pd_list {
|
1080 |
uint32_t size; |
1081 |
uint32_t count; |
1082 |
struct mfi_pd_address addr[MFI_MAX_SYS_PDS];
|
1083 |
} QEMU_PACKED; |
1084 |
|
1085 |
union mfi_ld_ref {
|
1086 |
struct {
|
1087 |
uint8_t target_id; |
1088 |
uint8_t reserved; |
1089 |
uint16_t seq; |
1090 |
} v; |
1091 |
uint32_t ref; |
1092 |
} QEMU_PACKED; |
1093 |
|
1094 |
struct mfi_ld_list {
|
1095 |
uint32_t ld_count; |
1096 |
uint32_t reserved1; |
1097 |
struct {
|
1098 |
union mfi_ld_ref ld;
|
1099 |
uint8_t state; |
1100 |
uint8_t reserved2[3];
|
1101 |
uint64_t size; |
1102 |
} ld_list[MFI_MAX_LD]; |
1103 |
} QEMU_PACKED; |
1104 |
|
1105 |
enum mfi_ld_access {
|
1106 |
MFI_LD_ACCESS_RW = 0,
|
1107 |
MFI_LD_ACCSSS_RO = 2,
|
1108 |
MFI_LD_ACCESS_BLOCKED = 3,
|
1109 |
}; |
1110 |
#define MFI_LD_ACCESS_MASK 3 |
1111 |
|
1112 |
enum mfi_ld_state {
|
1113 |
MFI_LD_STATE_OFFLINE = 0,
|
1114 |
MFI_LD_STATE_PARTIALLY_DEGRADED = 1,
|
1115 |
MFI_LD_STATE_DEGRADED = 2,
|
1116 |
MFI_LD_STATE_OPTIMAL = 3
|
1117 |
}; |
1118 |
|
1119 |
enum mfi_syspd_state {
|
1120 |
MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
|
1121 |
MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
|
1122 |
MFI_PD_STATE_HOT_SPARE = 0x02,
|
1123 |
MFI_PD_STATE_OFFLINE = 0x10,
|
1124 |
MFI_PD_STATE_FAILED = 0x11,
|
1125 |
MFI_PD_STATE_REBUILD = 0x14,
|
1126 |
MFI_PD_STATE_ONLINE = 0x18,
|
1127 |
MFI_PD_STATE_COPYBACK = 0x20,
|
1128 |
MFI_PD_STATE_SYSTEM = 0x40
|
1129 |
}; |
1130 |
|
1131 |
struct mfi_ld_props {
|
1132 |
union mfi_ld_ref ld;
|
1133 |
char name[16]; |
1134 |
uint8_t default_cache_policy; |
1135 |
uint8_t access_policy; |
1136 |
uint8_t disk_cache_policy; |
1137 |
uint8_t current_cache_policy; |
1138 |
uint8_t no_bgi; |
1139 |
uint8_t reserved[7];
|
1140 |
} QEMU_PACKED; |
1141 |
|
1142 |
struct mfi_ld_params {
|
1143 |
uint8_t primary_raid_level; |
1144 |
uint8_t raid_level_qualifier; |
1145 |
uint8_t secondary_raid_level; |
1146 |
uint8_t stripe_size; |
1147 |
uint8_t num_drives; |
1148 |
uint8_t span_depth; |
1149 |
uint8_t state; |
1150 |
uint8_t init_state; |
1151 |
uint8_t is_consistent; |
1152 |
uint8_t reserved[23];
|
1153 |
} QEMU_PACKED; |
1154 |
|
1155 |
struct mfi_ld_progress {
|
1156 |
uint32_t active; |
1157 |
#define MFI_LD_PROGRESS_CC (1<<0) |
1158 |
#define MFI_LD_PROGRESS_BGI (1<<1) |
1159 |
#define MFI_LD_PROGRESS_FGI (1<<2) |
1160 |
#define MFI_LD_PORGRESS_RECON (1<<3) |
1161 |
struct mfi_progress cc;
|
1162 |
struct mfi_progress bgi;
|
1163 |
struct mfi_progress fgi;
|
1164 |
struct mfi_progress recon;
|
1165 |
struct mfi_progress reserved[4]; |
1166 |
} QEMU_PACKED; |
1167 |
|
1168 |
struct mfi_span {
|
1169 |
uint64_t start_block; |
1170 |
uint64_t num_blocks; |
1171 |
uint16_t array_ref; |
1172 |
uint8_t reserved[6];
|
1173 |
} QEMU_PACKED; |
1174 |
|
1175 |
#define MFI_MAX_SPAN_DEPTH 8 |
1176 |
struct mfi_ld_config {
|
1177 |
struct mfi_ld_props properties;
|
1178 |
struct mfi_ld_params params;
|
1179 |
struct mfi_span span[MFI_MAX_SPAN_DEPTH];
|
1180 |
} QEMU_PACKED; |
1181 |
|
1182 |
struct mfi_ld_info {
|
1183 |
struct mfi_ld_config ld_config;
|
1184 |
uint64_t size; |
1185 |
struct mfi_ld_progress progress;
|
1186 |
uint16_t cluster_owner; |
1187 |
uint8_t reconstruct_active; |
1188 |
uint8_t reserved1[1];
|
1189 |
uint8_t vpd_page83[64];
|
1190 |
uint8_t reserved2[16];
|
1191 |
} QEMU_PACKED; |
1192 |
|
1193 |
union mfi_spare_type {
|
1194 |
uint8_t flags; |
1195 |
#define MFI_SPARE_IS_DEDICATED (1 << 0) |
1196 |
#define MFI_SPARE_IS_REVERTABLE (1 << 1) |
1197 |
#define MFI_SPARE_IS_ENCL_AFFINITY (1 << 2) |
1198 |
uint8_t type; |
1199 |
} QEMU_PACKED; |
1200 |
|
1201 |
#define MFI_MAX_ARRAYS 16 |
1202 |
struct mfi_spare {
|
1203 |
union mfi_pd_ref ref;
|
1204 |
union mfi_spare_type spare_type;
|
1205 |
uint8_t reserved[2];
|
1206 |
uint8_t array_count; |
1207 |
uint16_t array_refd[MFI_MAX_ARRAYS]; |
1208 |
} QEMU_PACKED; |
1209 |
|
1210 |
#define MFI_MAX_ROW_SIZE 32 |
1211 |
struct mfi_array {
|
1212 |
uint64_t size; |
1213 |
uint8_t num_drives; |
1214 |
uint8_t reserved; |
1215 |
uint16_t array_ref; |
1216 |
uint8_t pad[20];
|
1217 |
struct {
|
1218 |
union mfi_pd_ref ref;
|
1219 |
uint16_t fw_state; /* enum mfi_syspd_state */
|
1220 |
struct {
|
1221 |
uint8_t pd; |
1222 |
uint8_t slot; |
1223 |
} encl; |
1224 |
} pd[MFI_MAX_ROW_SIZE]; |
1225 |
} QEMU_PACKED; |
1226 |
|
1227 |
struct mfi_config_data {
|
1228 |
uint32_t size; |
1229 |
uint16_t array_count; |
1230 |
uint16_t array_size; |
1231 |
uint16_t log_drv_count; |
1232 |
uint16_t log_drv_size; |
1233 |
uint16_t spares_count; |
1234 |
uint16_t spares_size; |
1235 |
uint8_t reserved[16];
|
1236 |
/*
|
1237 |
struct mfi_array array[];
|
1238 |
struct mfi_ld_config ld[];
|
1239 |
struct mfi_spare spare[];
|
1240 |
*/
|
1241 |
} QEMU_PACKED; |
1242 |
|
1243 |
#define MFI_SCSI_MAX_TARGETS 128 |
1244 |
#define MFI_SCSI_MAX_LUNS 8 |
1245 |
#define MFI_SCSI_INITIATOR_ID 255 |
1246 |
#define MFI_SCSI_MAX_CMDS 8 |
1247 |
#define MFI_SCSI_MAX_CDB_LEN 16 |
1248 |
|
1249 |
#endif /* MFI_REG_H */ |