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1 | 02eb84d0 | Michael S. Tsirkin | /*
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2 | 02eb84d0 | Michael S. Tsirkin | * MSI-X device support
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3 | 02eb84d0 | Michael S. Tsirkin | *
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4 | 02eb84d0 | Michael S. Tsirkin | * This module includes support for MSI-X in pci devices.
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5 | 02eb84d0 | Michael S. Tsirkin | *
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6 | 02eb84d0 | Michael S. Tsirkin | * Author: Michael S. Tsirkin <mst@redhat.com>
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7 | 02eb84d0 | Michael S. Tsirkin | *
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8 | 02eb84d0 | Michael S. Tsirkin | * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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9 | 02eb84d0 | Michael S. Tsirkin | *
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10 | 02eb84d0 | Michael S. Tsirkin | * This work is licensed under the terms of the GNU GPL, version 2. See
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11 | 02eb84d0 | Michael S. Tsirkin | * the COPYING file in the top-level directory.
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12 | 6b620ca3 | Paolo Bonzini | *
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13 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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14 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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15 | 02eb84d0 | Michael S. Tsirkin | */
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16 | 02eb84d0 | Michael S. Tsirkin | |
17 | 02eb84d0 | Michael S. Tsirkin | #include "hw.h" |
18 | 60ba3cc2 | Jan Kiszka | #include "msi.h" |
19 | 02eb84d0 | Michael S. Tsirkin | #include "msix.h" |
20 | 02eb84d0 | Michael S. Tsirkin | #include "pci.h" |
21 | bf1b0071 | Blue Swirl | #include "range.h" |
22 | 02eb84d0 | Michael S. Tsirkin | |
23 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_CAP_LENGTH 12 |
24 | 02eb84d0 | Michael S. Tsirkin | |
25 | 2760952b | Michael S. Tsirkin | /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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26 | 2760952b | Michael S. Tsirkin | #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) |
27 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) |
28 | 5b5cb086 | Michael S. Tsirkin | #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8) |
29 | 02eb84d0 | Michael S. Tsirkin | |
30 | 5a1fc5e8 | Michael S. Tsirkin | /* How much space does an MSIX table need. */
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31 | 5a1fc5e8 | Michael S. Tsirkin | /* The spec requires giving the table structure
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32 | 5a1fc5e8 | Michael S. Tsirkin | * a 4K aligned region all by itself. */
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33 | 5a1fc5e8 | Michael S. Tsirkin | #define MSIX_PAGE_SIZE 0x1000 |
34 | 5a1fc5e8 | Michael S. Tsirkin | /* Reserve second half of the page for pending bits */
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35 | 5a1fc5e8 | Michael S. Tsirkin | #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2) |
36 | 02eb84d0 | Michael S. Tsirkin | #define MSIX_MAX_ENTRIES 32 |
37 | 02eb84d0 | Michael S. Tsirkin | |
38 | 02eb84d0 | Michael S. Tsirkin | |
39 | 02eb84d0 | Michael S. Tsirkin | /* Add MSI-X capability to the config space for the device. */
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40 | 02eb84d0 | Michael S. Tsirkin | /* Given a bar and its size, add MSI-X table on top of it
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41 | 02eb84d0 | Michael S. Tsirkin | * and fill MSI-X capability in the config space.
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42 | 02eb84d0 | Michael S. Tsirkin | * Original bar size must be a power of 2 or 0.
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43 | 02eb84d0 | Michael S. Tsirkin | * New bar size is returned. */
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44 | 02eb84d0 | Michael S. Tsirkin | static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, |
45 | 02eb84d0 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
46 | 02eb84d0 | Michael S. Tsirkin | { |
47 | 02eb84d0 | Michael S. Tsirkin | int config_offset;
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48 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config; |
49 | 02eb84d0 | Michael S. Tsirkin | uint32_t new_size; |
50 | 02eb84d0 | Michael S. Tsirkin | |
51 | 02eb84d0 | Michael S. Tsirkin | if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) |
52 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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53 | 02eb84d0 | Michael S. Tsirkin | if (bar_size > 0x80000000) |
54 | 02eb84d0 | Michael S. Tsirkin | return -ENOSPC;
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55 | 02eb84d0 | Michael S. Tsirkin | |
56 | 02eb84d0 | Michael S. Tsirkin | /* Add space for MSI-X structures */
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57 | 5e520a7d | Blue Swirl | if (!bar_size) {
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58 | 5a1fc5e8 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE; |
59 | 5a1fc5e8 | Michael S. Tsirkin | } else if (bar_size < MSIX_PAGE_SIZE) { |
60 | 5a1fc5e8 | Michael S. Tsirkin | bar_size = MSIX_PAGE_SIZE; |
61 | 5a1fc5e8 | Michael S. Tsirkin | new_size = MSIX_PAGE_SIZE * 2;
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62 | 5a1fc5e8 | Michael S. Tsirkin | } else {
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63 | 02eb84d0 | Michael S. Tsirkin | new_size = bar_size * 2;
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64 | 5a1fc5e8 | Michael S. Tsirkin | } |
65 | 02eb84d0 | Michael S. Tsirkin | |
66 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_bar_size = new_size; |
67 | ca77089d | Isaku Yamahata | config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, |
68 | ca77089d | Isaku Yamahata | 0, MSIX_CAP_LENGTH);
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69 | 02eb84d0 | Michael S. Tsirkin | if (config_offset < 0) |
70 | 02eb84d0 | Michael S. Tsirkin | return config_offset;
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71 | 02eb84d0 | Michael S. Tsirkin | config = pdev->config + config_offset; |
72 | 02eb84d0 | Michael S. Tsirkin | |
73 | 02eb84d0 | Michael S. Tsirkin | pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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74 | 02eb84d0 | Michael S. Tsirkin | /* Table on top of BAR */
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75 | 01731cfb | Jan Kiszka | pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr); |
76 | 02eb84d0 | Michael S. Tsirkin | /* Pending bits on top of that */
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77 | 01731cfb | Jan Kiszka | pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) | |
78 | 5a1fc5e8 | Michael S. Tsirkin | bar_nr); |
79 | 02eb84d0 | Michael S. Tsirkin | pdev->msix_cap = config_offset; |
80 | ebabb67a | Stefan Weil | /* Make flags bit writable. */
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81 | 5b5cb086 | Michael S. Tsirkin | pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | |
82 | 5b5cb086 | Michael S. Tsirkin | MSIX_MASKALL_MASK; |
83 | 50322249 | Michael S. Tsirkin | pdev->msix_function_masked = true;
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84 | 02eb84d0 | Michael S. Tsirkin | return 0; |
85 | 02eb84d0 | Michael S. Tsirkin | } |
86 | 02eb84d0 | Michael S. Tsirkin | |
87 | 95524ae8 | Avi Kivity | static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr, |
88 | 95524ae8 | Avi Kivity | unsigned size)
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89 | 02eb84d0 | Michael S. Tsirkin | { |
90 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
91 | 76f5159d | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
92 | 02eb84d0 | Michael S. Tsirkin | void *page = dev->msix_table_page;
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93 | 02eb84d0 | Michael S. Tsirkin | |
94 | 76f5159d | Michael S. Tsirkin | return pci_get_long(page + offset);
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95 | 02eb84d0 | Michael S. Tsirkin | } |
96 | 02eb84d0 | Michael S. Tsirkin | |
97 | 02eb84d0 | Michael S. Tsirkin | static uint8_t msix_pending_mask(int vector) |
98 | 02eb84d0 | Michael S. Tsirkin | { |
99 | 02eb84d0 | Michael S. Tsirkin | return 1 << (vector % 8); |
100 | 02eb84d0 | Michael S. Tsirkin | } |
101 | 02eb84d0 | Michael S. Tsirkin | |
102 | 02eb84d0 | Michael S. Tsirkin | static uint8_t *msix_pending_byte(PCIDevice *dev, int vector) |
103 | 02eb84d0 | Michael S. Tsirkin | { |
104 | 5a1fc5e8 | Michael S. Tsirkin | return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8; |
105 | 02eb84d0 | Michael S. Tsirkin | } |
106 | 02eb84d0 | Michael S. Tsirkin | |
107 | 02eb84d0 | Michael S. Tsirkin | static int msix_is_pending(PCIDevice *dev, int vector) |
108 | 02eb84d0 | Michael S. Tsirkin | { |
109 | 02eb84d0 | Michael S. Tsirkin | return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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110 | 02eb84d0 | Michael S. Tsirkin | } |
111 | 02eb84d0 | Michael S. Tsirkin | |
112 | 02eb84d0 | Michael S. Tsirkin | static void msix_set_pending(PCIDevice *dev, int vector) |
113 | 02eb84d0 | Michael S. Tsirkin | { |
114 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) |= msix_pending_mask(vector); |
115 | 02eb84d0 | Michael S. Tsirkin | } |
116 | 02eb84d0 | Michael S. Tsirkin | |
117 | 02eb84d0 | Michael S. Tsirkin | static void msix_clr_pending(PCIDevice *dev, int vector) |
118 | 02eb84d0 | Michael S. Tsirkin | { |
119 | 02eb84d0 | Michael S. Tsirkin | *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector); |
120 | 02eb84d0 | Michael S. Tsirkin | } |
121 | 02eb84d0 | Michael S. Tsirkin | |
122 | ae392c41 | Michael S. Tsirkin | static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask) |
123 | 02eb84d0 | Michael S. Tsirkin | { |
124 | ae392c41 | Michael S. Tsirkin | unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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125 | ae392c41 | Michael S. Tsirkin | return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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126 | 5b5cb086 | Michael S. Tsirkin | } |
127 | 5b5cb086 | Michael S. Tsirkin | |
128 | ae392c41 | Michael S. Tsirkin | static bool msix_is_masked(PCIDevice *dev, int vector) |
129 | 5b5cb086 | Michael S. Tsirkin | { |
130 | ae392c41 | Michael S. Tsirkin | return msix_vector_masked(dev, vector, dev->msix_function_masked);
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131 | ae392c41 | Michael S. Tsirkin | } |
132 | ae392c41 | Michael S. Tsirkin | |
133 | ae392c41 | Michael S. Tsirkin | static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked) |
134 | ae392c41 | Michael S. Tsirkin | { |
135 | ae392c41 | Michael S. Tsirkin | bool is_masked = msix_is_masked(dev, vector);
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136 | ae392c41 | Michael S. Tsirkin | if (is_masked == was_masked) {
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137 | ae392c41 | Michael S. Tsirkin | return;
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138 | ae392c41 | Michael S. Tsirkin | } |
139 | ae392c41 | Michael S. Tsirkin | |
140 | ae392c41 | Michael S. Tsirkin | if (!is_masked && msix_is_pending(dev, vector)) {
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141 | 5b5cb086 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
142 | 5b5cb086 | Michael S. Tsirkin | msix_notify(dev, vector); |
143 | 5b5cb086 | Michael S. Tsirkin | } |
144 | 5b5cb086 | Michael S. Tsirkin | } |
145 | 5b5cb086 | Michael S. Tsirkin | |
146 | 50322249 | Michael S. Tsirkin | static void msix_update_function_masked(PCIDevice *dev) |
147 | 50322249 | Michael S. Tsirkin | { |
148 | 50322249 | Michael S. Tsirkin | dev->msix_function_masked = !msix_enabled(dev) || |
149 | 50322249 | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK); |
150 | 50322249 | Michael S. Tsirkin | } |
151 | 50322249 | Michael S. Tsirkin | |
152 | 5b5cb086 | Michael S. Tsirkin | /* Handle MSI-X capability config write. */
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153 | 5b5cb086 | Michael S. Tsirkin | void msix_write_config(PCIDevice *dev, uint32_t addr,
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154 | 5b5cb086 | Michael S. Tsirkin | uint32_t val, int len)
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155 | 5b5cb086 | Michael S. Tsirkin | { |
156 | 5b5cb086 | Michael S. Tsirkin | unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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157 | 5b5cb086 | Michael S. Tsirkin | int vector;
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158 | 50322249 | Michael S. Tsirkin | bool was_masked;
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159 | 5b5cb086 | Michael S. Tsirkin | |
160 | 98a3cb02 | Isaku Yamahata | if (!range_covers_byte(addr, len, enable_pos)) {
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161 | 5b5cb086 | Michael S. Tsirkin | return;
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162 | 5b5cb086 | Michael S. Tsirkin | } |
163 | 5b5cb086 | Michael S. Tsirkin | |
164 | 50322249 | Michael S. Tsirkin | was_masked = dev->msix_function_masked; |
165 | 50322249 | Michael S. Tsirkin | msix_update_function_masked(dev); |
166 | 50322249 | Michael S. Tsirkin | |
167 | 5b5cb086 | Michael S. Tsirkin | if (!msix_enabled(dev)) {
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168 | 5b5cb086 | Michael S. Tsirkin | return;
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169 | 5b5cb086 | Michael S. Tsirkin | } |
170 | 5b5cb086 | Michael S. Tsirkin | |
171 | e407bf13 | Isaku Yamahata | pci_device_deassert_intx(dev); |
172 | 5b5cb086 | Michael S. Tsirkin | |
173 | 50322249 | Michael S. Tsirkin | if (dev->msix_function_masked == was_masked) {
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174 | 5b5cb086 | Michael S. Tsirkin | return;
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175 | 5b5cb086 | Michael S. Tsirkin | } |
176 | 5b5cb086 | Michael S. Tsirkin | |
177 | 5b5cb086 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
178 | ae392c41 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector, |
179 | ae392c41 | Michael S. Tsirkin | msix_vector_masked(dev, vector, was_masked)); |
180 | 5b5cb086 | Michael S. Tsirkin | } |
181 | 02eb84d0 | Michael S. Tsirkin | } |
182 | 02eb84d0 | Michael S. Tsirkin | |
183 | 95524ae8 | Avi Kivity | static void msix_mmio_write(void *opaque, target_phys_addr_t addr, |
184 | 95524ae8 | Avi Kivity | uint64_t val, unsigned size)
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185 | 02eb84d0 | Michael S. Tsirkin | { |
186 | 02eb84d0 | Michael S. Tsirkin | PCIDevice *dev = opaque; |
187 | 76f5159d | Michael S. Tsirkin | unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; |
188 | 01731cfb | Jan Kiszka | int vector = offset / PCI_MSIX_ENTRY_SIZE;
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189 | ae392c41 | Michael S. Tsirkin | bool was_masked;
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190 | 9a93b617 | Michael S. Tsirkin | |
191 | 9a93b617 | Michael S. Tsirkin | /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
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192 | 9a93b617 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr) {
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193 | 9a93b617 | Michael S. Tsirkin | return;
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194 | 9a93b617 | Michael S. Tsirkin | } |
195 | 9a93b617 | Michael S. Tsirkin | |
196 | ae392c41 | Michael S. Tsirkin | was_masked = msix_is_masked(dev, vector); |
197 | 76f5159d | Michael S. Tsirkin | pci_set_long(dev->msix_table_page + offset, val); |
198 | ae392c41 | Michael S. Tsirkin | msix_handle_mask_update(dev, vector, was_masked); |
199 | 02eb84d0 | Michael S. Tsirkin | } |
200 | 02eb84d0 | Michael S. Tsirkin | |
201 | 95524ae8 | Avi Kivity | static const MemoryRegionOps msix_mmio_ops = { |
202 | 95524ae8 | Avi Kivity | .read = msix_mmio_read, |
203 | 95524ae8 | Avi Kivity | .write = msix_mmio_write, |
204 | 95524ae8 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
205 | 95524ae8 | Avi Kivity | .valid = { |
206 | 95524ae8 | Avi Kivity | .min_access_size = 4,
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207 | 95524ae8 | Avi Kivity | .max_access_size = 4,
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208 | 95524ae8 | Avi Kivity | }, |
209 | 02eb84d0 | Michael S. Tsirkin | }; |
210 | 02eb84d0 | Michael S. Tsirkin | |
211 | 95524ae8 | Avi Kivity | static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar) |
212 | 02eb84d0 | Michael S. Tsirkin | { |
213 | 02eb84d0 | Michael S. Tsirkin | uint8_t *config = d->config + d->msix_cap; |
214 | 01731cfb | Jan Kiszka | uint32_t table = pci_get_long(config + PCI_MSIX_TABLE); |
215 | 5a1fc5e8 | Michael S. Tsirkin | uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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216 | 02eb84d0 | Michael S. Tsirkin | /* TODO: for assigned devices, we'll want to make it possible to map
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217 | 02eb84d0 | Michael S. Tsirkin | * pending bits separately in case they are in a separate bar. */
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218 | 02eb84d0 | Michael S. Tsirkin | |
219 | 95524ae8 | Avi Kivity | memory_region_add_subregion(bar, offset, &d->msix_mmio); |
220 | 02eb84d0 | Michael S. Tsirkin | } |
221 | 02eb84d0 | Michael S. Tsirkin | |
222 | ae1be0bb | Michael S. Tsirkin | static void msix_mask_all(struct PCIDevice *dev, unsigned nentries) |
223 | ae1be0bb | Michael S. Tsirkin | { |
224 | ae1be0bb | Michael S. Tsirkin | int vector;
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225 | ae1be0bb | Michael S. Tsirkin | for (vector = 0; vector < nentries; ++vector) { |
226 | 01731cfb | Jan Kiszka | unsigned offset =
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227 | 01731cfb | Jan Kiszka | vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; |
228 | 01731cfb | Jan Kiszka | dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
229 | ae1be0bb | Michael S. Tsirkin | } |
230 | ae1be0bb | Michael S. Tsirkin | } |
231 | ae1be0bb | Michael S. Tsirkin | |
232 | 02eb84d0 | Michael S. Tsirkin | /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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233 | 02eb84d0 | Michael S. Tsirkin | * modified, it should be retrieved with msix_bar_size. */
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234 | 02eb84d0 | Michael S. Tsirkin | int msix_init(struct PCIDevice *dev, unsigned short nentries, |
235 | 95524ae8 | Avi Kivity | MemoryRegion *bar, |
236 | 5a1fc5e8 | Michael S. Tsirkin | unsigned bar_nr, unsigned bar_size) |
237 | 02eb84d0 | Michael S. Tsirkin | { |
238 | 02eb84d0 | Michael S. Tsirkin | int ret;
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239 | 60ba3cc2 | Jan Kiszka | |
240 | 02eb84d0 | Michael S. Tsirkin | /* Nothing to do if MSI is not supported by interrupt controller */
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241 | 60ba3cc2 | Jan Kiszka | if (!msi_supported) {
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242 | 02eb84d0 | Michael S. Tsirkin | return -ENOTSUP;
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243 | 60ba3cc2 | Jan Kiszka | } |
244 | 02eb84d0 | Michael S. Tsirkin | if (nentries > MSIX_MAX_ENTRIES)
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245 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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246 | 02eb84d0 | Michael S. Tsirkin | |
247 | 7267c094 | Anthony Liguori | dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES * |
248 | 02eb84d0 | Michael S. Tsirkin | sizeof *dev->msix_entry_used);
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249 | 02eb84d0 | Michael S. Tsirkin | |
250 | 7267c094 | Anthony Liguori | dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE); |
251 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, nentries); |
252 | 02eb84d0 | Michael S. Tsirkin | |
253 | 95524ae8 | Avi Kivity | memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev, |
254 | 95524ae8 | Avi Kivity | "msix", MSIX_PAGE_SIZE);
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255 | 02eb84d0 | Michael S. Tsirkin | |
256 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = nentries; |
257 | 02eb84d0 | Michael S. Tsirkin | ret = msix_add_config(dev, nentries, bar_nr, bar_size); |
258 | 02eb84d0 | Michael S. Tsirkin | if (ret)
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259 | 02eb84d0 | Michael S. Tsirkin | goto err_config;
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260 | 02eb84d0 | Michael S. Tsirkin | |
261 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present |= QEMU_PCI_CAP_MSIX; |
262 | 95524ae8 | Avi Kivity | msix_mmio_setup(dev, bar); |
263 | 02eb84d0 | Michael S. Tsirkin | return 0; |
264 | 02eb84d0 | Michael S. Tsirkin | |
265 | 02eb84d0 | Michael S. Tsirkin | err_config:
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266 | 3174ecd1 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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267 | 95524ae8 | Avi Kivity | memory_region_destroy(&dev->msix_mmio); |
268 | 7267c094 | Anthony Liguori | g_free(dev->msix_table_page); |
269 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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270 | 7267c094 | Anthony Liguori | g_free(dev->msix_entry_used); |
271 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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272 | 02eb84d0 | Michael S. Tsirkin | return ret;
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273 | 02eb84d0 | Michael S. Tsirkin | } |
274 | 02eb84d0 | Michael S. Tsirkin | |
275 | 98304c84 | Michael S. Tsirkin | static void msix_free_irq_entries(PCIDevice *dev) |
276 | 98304c84 | Michael S. Tsirkin | { |
277 | 98304c84 | Michael S. Tsirkin | int vector;
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278 | 98304c84 | Michael S. Tsirkin | |
279 | 98304c84 | Michael S. Tsirkin | for (vector = 0; vector < dev->msix_entries_nr; ++vector) { |
280 | 98304c84 | Michael S. Tsirkin | dev->msix_entry_used[vector] = 0;
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281 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
282 | 98304c84 | Michael S. Tsirkin | } |
283 | 98304c84 | Michael S. Tsirkin | } |
284 | 98304c84 | Michael S. Tsirkin | |
285 | 02eb84d0 | Michael S. Tsirkin | /* Clean up resources for the device. */
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286 | 95524ae8 | Avi Kivity | int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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287 | 02eb84d0 | Michael S. Tsirkin | { |
288 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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289 | 02eb84d0 | Michael S. Tsirkin | return 0; |
290 | 02eb84d0 | Michael S. Tsirkin | pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH); |
291 | 02eb84d0 | Michael S. Tsirkin | dev->msix_cap = 0;
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292 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
293 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entries_nr = 0;
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294 | 95524ae8 | Avi Kivity | memory_region_del_subregion(bar, &dev->msix_mmio); |
295 | 95524ae8 | Avi Kivity | memory_region_destroy(&dev->msix_mmio); |
296 | 7267c094 | Anthony Liguori | g_free(dev->msix_table_page); |
297 | 02eb84d0 | Michael S. Tsirkin | dev->msix_table_page = NULL;
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298 | 7267c094 | Anthony Liguori | g_free(dev->msix_entry_used); |
299 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used = NULL;
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300 | 02eb84d0 | Michael S. Tsirkin | dev->cap_present &= ~QEMU_PCI_CAP_MSIX; |
301 | 02eb84d0 | Michael S. Tsirkin | return 0; |
302 | 02eb84d0 | Michael S. Tsirkin | } |
303 | 02eb84d0 | Michael S. Tsirkin | |
304 | 02eb84d0 | Michael S. Tsirkin | void msix_save(PCIDevice *dev, QEMUFile *f)
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305 | 02eb84d0 | Michael S. Tsirkin | { |
306 | 9a3e12c8 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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307 | 9a3e12c8 | Michael S. Tsirkin | |
308 | 72755a70 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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309 | 9a3e12c8 | Michael S. Tsirkin | return;
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310 | 72755a70 | Michael S. Tsirkin | } |
311 | 9a3e12c8 | Michael S. Tsirkin | |
312 | 01731cfb | Jan Kiszka | qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
313 | 5a1fc5e8 | Michael S. Tsirkin | qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
314 | 02eb84d0 | Michael S. Tsirkin | } |
315 | 02eb84d0 | Michael S. Tsirkin | |
316 | 02eb84d0 | Michael S. Tsirkin | /* Should be called after restoring the config space. */
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317 | 02eb84d0 | Michael S. Tsirkin | void msix_load(PCIDevice *dev, QEMUFile *f)
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318 | 02eb84d0 | Michael S. Tsirkin | { |
319 | 02eb84d0 | Michael S. Tsirkin | unsigned n = dev->msix_entries_nr;
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320 | 02eb84d0 | Michael S. Tsirkin | |
321 | 98846d73 | Blue Swirl | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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322 | 02eb84d0 | Michael S. Tsirkin | return;
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323 | 98846d73 | Blue Swirl | } |
324 | 02eb84d0 | Michael S. Tsirkin | |
325 | 4bfd1712 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
326 | 01731cfb | Jan Kiszka | qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE); |
327 | 5a1fc5e8 | Michael S. Tsirkin | qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8); |
328 | 50322249 | Michael S. Tsirkin | msix_update_function_masked(dev); |
329 | 02eb84d0 | Michael S. Tsirkin | } |
330 | 02eb84d0 | Michael S. Tsirkin | |
331 | 02eb84d0 | Michael S. Tsirkin | /* Does device support MSI-X? */
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332 | 02eb84d0 | Michael S. Tsirkin | int msix_present(PCIDevice *dev)
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333 | 02eb84d0 | Michael S. Tsirkin | { |
334 | 02eb84d0 | Michael S. Tsirkin | return dev->cap_present & QEMU_PCI_CAP_MSIX;
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335 | 02eb84d0 | Michael S. Tsirkin | } |
336 | 02eb84d0 | Michael S. Tsirkin | |
337 | 02eb84d0 | Michael S. Tsirkin | /* Is MSI-X enabled? */
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338 | 02eb84d0 | Michael S. Tsirkin | int msix_enabled(PCIDevice *dev)
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339 | 02eb84d0 | Michael S. Tsirkin | { |
340 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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341 | 2760952b | Michael S. Tsirkin | (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & |
342 | 02eb84d0 | Michael S. Tsirkin | MSIX_ENABLE_MASK); |
343 | 02eb84d0 | Michael S. Tsirkin | } |
344 | 02eb84d0 | Michael S. Tsirkin | |
345 | 02eb84d0 | Michael S. Tsirkin | /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
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346 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size(PCIDevice *dev) |
347 | 02eb84d0 | Michael S. Tsirkin | { |
348 | 02eb84d0 | Michael S. Tsirkin | return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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349 | 02eb84d0 | Michael S. Tsirkin | dev->msix_bar_size : 0;
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350 | 02eb84d0 | Michael S. Tsirkin | } |
351 | 02eb84d0 | Michael S. Tsirkin | |
352 | 02eb84d0 | Michael S. Tsirkin | /* Send an MSI-X message */
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353 | 02eb84d0 | Michael S. Tsirkin | void msix_notify(PCIDevice *dev, unsigned vector) |
354 | 02eb84d0 | Michael S. Tsirkin | { |
355 | 01731cfb | Jan Kiszka | uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE; |
356 | 02eb84d0 | Michael S. Tsirkin | uint64_t address; |
357 | 02eb84d0 | Michael S. Tsirkin | uint32_t data; |
358 | 02eb84d0 | Michael S. Tsirkin | |
359 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
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360 | 02eb84d0 | Michael S. Tsirkin | return;
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361 | 02eb84d0 | Michael S. Tsirkin | if (msix_is_masked(dev, vector)) {
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362 | 02eb84d0 | Michael S. Tsirkin | msix_set_pending(dev, vector); |
363 | 02eb84d0 | Michael S. Tsirkin | return;
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364 | 02eb84d0 | Michael S. Tsirkin | } |
365 | 02eb84d0 | Michael S. Tsirkin | |
366 | 01731cfb | Jan Kiszka | address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); |
367 | 01731cfb | Jan Kiszka | data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); |
368 | ae5d3eb4 | Alexander Graf | stl_le_phys(address, data); |
369 | 02eb84d0 | Michael S. Tsirkin | } |
370 | 02eb84d0 | Michael S. Tsirkin | |
371 | 02eb84d0 | Michael S. Tsirkin | void msix_reset(PCIDevice *dev)
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372 | 02eb84d0 | Michael S. Tsirkin | { |
373 | 02eb84d0 | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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374 | 02eb84d0 | Michael S. Tsirkin | return;
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375 | 02eb84d0 | Michael S. Tsirkin | msix_free_irq_entries(dev); |
376 | 2760952b | Michael S. Tsirkin | dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &= |
377 | 2760952b | Michael S. Tsirkin | ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; |
378 | 5a1fc5e8 | Michael S. Tsirkin | memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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379 | ae1be0bb | Michael S. Tsirkin | msix_mask_all(dev, dev->msix_entries_nr); |
380 | 02eb84d0 | Michael S. Tsirkin | } |
381 | 02eb84d0 | Michael S. Tsirkin | |
382 | 02eb84d0 | Michael S. Tsirkin | /* PCI spec suggests that devices make it possible for software to configure
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383 | 02eb84d0 | Michael S. Tsirkin | * less vectors than supported by the device, but does not specify a standard
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384 | 02eb84d0 | Michael S. Tsirkin | * mechanism for devices to do so.
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385 | 02eb84d0 | Michael S. Tsirkin | *
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386 | 02eb84d0 | Michael S. Tsirkin | * We support this by asking devices to declare vectors software is going to
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387 | 02eb84d0 | Michael S. Tsirkin | * actually use, and checking this on the notification path. Devices that
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388 | 02eb84d0 | Michael S. Tsirkin | * don't want to follow the spec suggestion can declare all vectors as used. */
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389 | 02eb84d0 | Michael S. Tsirkin | |
390 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as used. */
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391 | 02eb84d0 | Michael S. Tsirkin | int msix_vector_use(PCIDevice *dev, unsigned vector) |
392 | 02eb84d0 | Michael S. Tsirkin | { |
393 | 02eb84d0 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr)
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394 | 02eb84d0 | Michael S. Tsirkin | return -EINVAL;
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395 | 02eb84d0 | Michael S. Tsirkin | dev->msix_entry_used[vector]++; |
396 | 02eb84d0 | Michael S. Tsirkin | return 0; |
397 | 02eb84d0 | Michael S. Tsirkin | } |
398 | 02eb84d0 | Michael S. Tsirkin | |
399 | 02eb84d0 | Michael S. Tsirkin | /* Mark vector as unused. */
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400 | 02eb84d0 | Michael S. Tsirkin | void msix_vector_unuse(PCIDevice *dev, unsigned vector) |
401 | 02eb84d0 | Michael S. Tsirkin | { |
402 | 98304c84 | Michael S. Tsirkin | if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
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403 | 98304c84 | Michael S. Tsirkin | return;
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404 | 98304c84 | Michael S. Tsirkin | } |
405 | 98304c84 | Michael S. Tsirkin | if (--dev->msix_entry_used[vector]) {
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406 | 98304c84 | Michael S. Tsirkin | return;
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407 | 98304c84 | Michael S. Tsirkin | } |
408 | 98304c84 | Michael S. Tsirkin | msix_clr_pending(dev, vector); |
409 | 02eb84d0 | Michael S. Tsirkin | } |
410 | b5f28bca | Michael S. Tsirkin | |
411 | b5f28bca | Michael S. Tsirkin | void msix_unuse_all_vectors(PCIDevice *dev)
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412 | b5f28bca | Michael S. Tsirkin | { |
413 | b5f28bca | Michael S. Tsirkin | if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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414 | b5f28bca | Michael S. Tsirkin | return;
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415 | b5f28bca | Michael S. Tsirkin | msix_free_irq_entries(dev); |
416 | b5f28bca | Michael S. Tsirkin | } |