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1 | 420557e8 | bellard | /*
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2 | 420557e8 | bellard | * QEMU SPARC iommu emulation
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3 | 420557e8 | bellard | *
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4 | 420557e8 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 420557e8 | bellard | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | /* debug iommu */
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27 | 420557e8 | bellard | //#define DEBUG_IOMMU
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28 | 420557e8 | bellard | |
29 | 420557e8 | bellard | /* The IOMMU registers occupy three pages in IO space. */
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30 | 420557e8 | bellard | struct iommu_regs {
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31 | 420557e8 | bellard | /* First page */
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32 | 420557e8 | bellard | volatile unsigned long control; /* IOMMU control */ |
33 | 420557e8 | bellard | volatile unsigned long base; /* Physical base of iopte page table */ |
34 | 420557e8 | bellard | volatile unsigned long _unused1[3]; |
35 | 420557e8 | bellard | volatile unsigned long tlbflush; /* write only */ |
36 | 420557e8 | bellard | volatile unsigned long pageflush; /* write only */ |
37 | 420557e8 | bellard | volatile unsigned long _unused2[1017]; |
38 | 420557e8 | bellard | /* Second page */
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39 | 420557e8 | bellard | volatile unsigned long afsr; /* Async-fault status register */ |
40 | 420557e8 | bellard | volatile unsigned long afar; /* Async-fault physical address */ |
41 | 420557e8 | bellard | volatile unsigned long _unused3[2]; |
42 | 420557e8 | bellard | volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */ |
43 | 420557e8 | bellard | volatile unsigned long sbuscfg1; |
44 | 420557e8 | bellard | volatile unsigned long sbuscfg2; |
45 | 420557e8 | bellard | volatile unsigned long sbuscfg3; |
46 | 420557e8 | bellard | volatile unsigned long mfsr; /* Memory-fault status register */ |
47 | 420557e8 | bellard | volatile unsigned long mfar; /* Memory-fault physical address */ |
48 | 420557e8 | bellard | volatile unsigned long _unused4[1014]; |
49 | 420557e8 | bellard | /* Third page */
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50 | 420557e8 | bellard | volatile unsigned long mid; /* IOMMU module-id */ |
51 | 420557e8 | bellard | }; |
52 | 420557e8 | bellard | |
53 | 420557e8 | bellard | #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
54 | 420557e8 | bellard | #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
55 | 420557e8 | bellard | #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
56 | 420557e8 | bellard | #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
57 | 420557e8 | bellard | #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
58 | 420557e8 | bellard | #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
59 | 420557e8 | bellard | #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
60 | 420557e8 | bellard | #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
61 | 420557e8 | bellard | #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
62 | 420557e8 | bellard | #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
63 | 420557e8 | bellard | #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
64 | 420557e8 | bellard | #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
65 | 420557e8 | bellard | |
66 | 420557e8 | bellard | #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ |
67 | 420557e8 | bellard | #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */ |
68 | 420557e8 | bellard | #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */ |
69 | 420557e8 | bellard | #define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */ |
70 | 420557e8 | bellard | #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ |
71 | 420557e8 | bellard | #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
72 | 420557e8 | bellard | #define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */ |
73 | 420557e8 | bellard | #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ |
74 | 420557e8 | bellard | #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ |
75 | 420557e8 | bellard | #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ |
76 | 420557e8 | bellard | |
77 | 420557e8 | bellard | #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ |
78 | 420557e8 | bellard | #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
79 | 420557e8 | bellard | #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
80 | 420557e8 | bellard | #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
81 | 420557e8 | bellard | produced by this device as pure
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82 | 420557e8 | bellard | physical. */
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83 | 420557e8 | bellard | |
84 | 420557e8 | bellard | #define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */ |
85 | 420557e8 | bellard | #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */ |
86 | 420557e8 | bellard | #define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */ |
87 | 420557e8 | bellard | #define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */ |
88 | 420557e8 | bellard | #define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred |
89 | 420557e8 | bellard | on the even word of the access, low bit
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90 | 420557e8 | bellard | indicated odd word caused the parity error */
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91 | 420557e8 | bellard | #define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */ |
92 | 420557e8 | bellard | #define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */ |
93 | 420557e8 | bellard | #define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */ |
94 | 420557e8 | bellard | |
95 | 420557e8 | bellard | #define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */ |
96 | 420557e8 | bellard | #define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */ |
97 | 420557e8 | bellard | #define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */ |
98 | 420557e8 | bellard | #define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */ |
99 | 420557e8 | bellard | #define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */ |
100 | 420557e8 | bellard | #define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */ |
101 | 420557e8 | bellard | #define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */ |
102 | 420557e8 | bellard | |
103 | 420557e8 | bellard | /* The format of an iopte in the page tables */
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104 | 420557e8 | bellard | #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ |
105 | 420557e8 | bellard | #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */ |
106 | 420557e8 | bellard | #define IOPTE_WRITE 0x00000004 /* Writeable */ |
107 | 420557e8 | bellard | #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
108 | 420557e8 | bellard | #define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
109 | 420557e8 | bellard | |
110 | 420557e8 | bellard | #define PAGE_SHIFT 12 |
111 | 420557e8 | bellard | #define PAGE_SIZE (1 << PAGE_SHIFT) |
112 | 420557e8 | bellard | #define PAGE_MASK (PAGE_SIZE - 1) |
113 | 420557e8 | bellard | |
114 | 420557e8 | bellard | typedef struct IOMMUState { |
115 | 8d5f07fa | bellard | uint32_t addr; |
116 | 420557e8 | bellard | uint32_t regs[sizeof(struct iommu_regs)]; |
117 | 8d5f07fa | bellard | uint32_t iostart; |
118 | 420557e8 | bellard | } IOMMUState; |
119 | 420557e8 | bellard | |
120 | 420557e8 | bellard | static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) |
121 | 420557e8 | bellard | { |
122 | 420557e8 | bellard | IOMMUState *s = opaque; |
123 | 420557e8 | bellard | uint32_t saddr; |
124 | 420557e8 | bellard | |
125 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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126 | 420557e8 | bellard | switch (saddr) {
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127 | 420557e8 | bellard | default:
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128 | 420557e8 | bellard | return s->regs[saddr];
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129 | 420557e8 | bellard | break;
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130 | 420557e8 | bellard | } |
131 | 420557e8 | bellard | return 0; |
132 | 420557e8 | bellard | } |
133 | 420557e8 | bellard | |
134 | 420557e8 | bellard | static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
135 | 420557e8 | bellard | { |
136 | 420557e8 | bellard | IOMMUState *s = opaque; |
137 | 420557e8 | bellard | uint32_t saddr; |
138 | 420557e8 | bellard | |
139 | 8d5f07fa | bellard | saddr = (addr - s->addr) >> 2;
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140 | 420557e8 | bellard | switch (saddr) {
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141 | 8d5f07fa | bellard | case 0: |
142 | 8d5f07fa | bellard | switch (val & IOMMU_CTRL_RNGE) {
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143 | 8d5f07fa | bellard | case IOMMU_RNGE_16MB:
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144 | 8d5f07fa | bellard | s->iostart = 0xff000000;
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145 | 8d5f07fa | bellard | break;
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146 | 8d5f07fa | bellard | case IOMMU_RNGE_32MB:
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147 | 8d5f07fa | bellard | s->iostart = 0xfe000000;
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148 | 8d5f07fa | bellard | break;
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149 | 8d5f07fa | bellard | case IOMMU_RNGE_64MB:
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150 | 8d5f07fa | bellard | s->iostart = 0xfc000000;
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151 | 8d5f07fa | bellard | break;
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152 | 8d5f07fa | bellard | case IOMMU_RNGE_128MB:
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153 | 8d5f07fa | bellard | s->iostart = 0xf8000000;
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154 | 8d5f07fa | bellard | break;
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155 | 8d5f07fa | bellard | case IOMMU_RNGE_256MB:
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156 | 8d5f07fa | bellard | s->iostart = 0xf0000000;
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157 | 8d5f07fa | bellard | break;
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158 | 8d5f07fa | bellard | case IOMMU_RNGE_512MB:
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159 | 8d5f07fa | bellard | s->iostart = 0xe0000000;
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160 | 8d5f07fa | bellard | break;
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161 | 8d5f07fa | bellard | case IOMMU_RNGE_1GB:
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162 | 8d5f07fa | bellard | s->iostart = 0xc0000000;
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163 | 8d5f07fa | bellard | break;
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164 | 8d5f07fa | bellard | default:
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165 | 8d5f07fa | bellard | case IOMMU_RNGE_2GB:
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166 | 8d5f07fa | bellard | s->iostart = 0x80000000;
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167 | 8d5f07fa | bellard | break;
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168 | 8d5f07fa | bellard | } |
169 | 8d5f07fa | bellard | /* Fall through */
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170 | 420557e8 | bellard | default:
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171 | 420557e8 | bellard | s->regs[saddr] = val; |
172 | 420557e8 | bellard | break;
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173 | 420557e8 | bellard | } |
174 | 420557e8 | bellard | } |
175 | 420557e8 | bellard | |
176 | 420557e8 | bellard | static CPUReadMemoryFunc *iommu_mem_read[3] = { |
177 | 420557e8 | bellard | iommu_mem_readw, |
178 | 420557e8 | bellard | iommu_mem_readw, |
179 | 420557e8 | bellard | iommu_mem_readw, |
180 | 420557e8 | bellard | }; |
181 | 420557e8 | bellard | |
182 | 420557e8 | bellard | static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
183 | 420557e8 | bellard | iommu_mem_writew, |
184 | 420557e8 | bellard | iommu_mem_writew, |
185 | 420557e8 | bellard | iommu_mem_writew, |
186 | 420557e8 | bellard | }; |
187 | 420557e8 | bellard | |
188 | e80cfcfc | bellard | uint32_t iommu_translate_local(void *opaque, uint32_t addr)
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189 | 420557e8 | bellard | { |
190 | e80cfcfc | bellard | IOMMUState *s = opaque; |
191 | e80cfcfc | bellard | uint32_t *iopte = (void *)(s->regs[1] << 4), pa; |
192 | 420557e8 | bellard | |
193 | e80cfcfc | bellard | iopte += ((addr - s->iostart) >> PAGE_SHIFT); |
194 | e80cfcfc | bellard | cpu_physical_memory_read((uint32_t)iopte, (void *) &pa, 4); |
195 | 420557e8 | bellard | bswap32s(&pa); |
196 | 420557e8 | bellard | pa = (pa & IOPTE_PAGE) << 4; /* Loose higher bits of 36 */ |
197 | 420557e8 | bellard | return pa + (addr & PAGE_MASK);
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198 | 420557e8 | bellard | } |
199 | 420557e8 | bellard | |
200 | e80cfcfc | bellard | static void iommu_save(QEMUFile *f, void *opaque) |
201 | e80cfcfc | bellard | { |
202 | e80cfcfc | bellard | IOMMUState *s = opaque; |
203 | e80cfcfc | bellard | int i;
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204 | e80cfcfc | bellard | |
205 | e80cfcfc | bellard | qemu_put_be32s(f, &s->addr); |
206 | e80cfcfc | bellard | for (i = 0; i < sizeof(struct iommu_regs); i += 4) |
207 | e80cfcfc | bellard | qemu_put_be32s(f, &s->regs[i]); |
208 | e80cfcfc | bellard | qemu_put_be32s(f, &s->iostart); |
209 | e80cfcfc | bellard | } |
210 | e80cfcfc | bellard | |
211 | e80cfcfc | bellard | static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
212 | e80cfcfc | bellard | { |
213 | e80cfcfc | bellard | IOMMUState *s = opaque; |
214 | e80cfcfc | bellard | int i;
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215 | e80cfcfc | bellard | |
216 | e80cfcfc | bellard | if (version_id != 1) |
217 | e80cfcfc | bellard | return -EINVAL;
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218 | e80cfcfc | bellard | |
219 | e80cfcfc | bellard | qemu_get_be32s(f, &s->addr); |
220 | e80cfcfc | bellard | for (i = 0; i < sizeof(struct iommu_regs); i += 4) |
221 | e80cfcfc | bellard | qemu_put_be32s(f, &s->regs[i]); |
222 | e80cfcfc | bellard | qemu_get_be32s(f, &s->iostart); |
223 | e80cfcfc | bellard | |
224 | e80cfcfc | bellard | return 0; |
225 | e80cfcfc | bellard | } |
226 | e80cfcfc | bellard | |
227 | e80cfcfc | bellard | static void iommu_reset(void *opaque) |
228 | e80cfcfc | bellard | { |
229 | e80cfcfc | bellard | IOMMUState *s = opaque; |
230 | e80cfcfc | bellard | |
231 | e80cfcfc | bellard | memset(s->regs, 0, sizeof(struct iommu_regs)); |
232 | e80cfcfc | bellard | s->iostart = 0;
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233 | e80cfcfc | bellard | } |
234 | e80cfcfc | bellard | |
235 | e80cfcfc | bellard | void *iommu_init(uint32_t addr)
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236 | 420557e8 | bellard | { |
237 | 420557e8 | bellard | IOMMUState *s; |
238 | 8d5f07fa | bellard | int iommu_io_memory;
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239 | 420557e8 | bellard | |
240 | 420557e8 | bellard | s = qemu_mallocz(sizeof(IOMMUState));
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241 | 420557e8 | bellard | if (!s)
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242 | e80cfcfc | bellard | return NULL; |
243 | 420557e8 | bellard | |
244 | 8d5f07fa | bellard | s->addr = addr; |
245 | 8d5f07fa | bellard | |
246 | 420557e8 | bellard | iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
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247 | 8d5f07fa | bellard | cpu_register_physical_memory(addr, sizeof(struct iommu_regs), |
248 | 420557e8 | bellard | iommu_io_memory); |
249 | 420557e8 | bellard | |
250 | e80cfcfc | bellard | register_savevm("iommu", addr, 1, iommu_save, iommu_load, s); |
251 | e80cfcfc | bellard | qemu_register_reset(iommu_reset, s); |
252 | e80cfcfc | bellard | return s;
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253 | 420557e8 | bellard | } |