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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation cpu definitions for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 79aceca5 | bellard | #include "cpu-defs.h" |
26 | 79aceca5 | bellard | |
27 | 9a64fbe4 | bellard | //#define USE_OPEN_FIRMWARE
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28 | 9a64fbe4 | bellard | |
29 | 79aceca5 | bellard | #include "config.h" |
30 | 79aceca5 | bellard | #include <setjmp.h> |
31 | 79aceca5 | bellard | |
32 | 9a64fbe4 | bellard | /* Instruction types */
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33 | 9a64fbe4 | bellard | enum {
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34 | 9a64fbe4 | bellard | PPC_NONE = 0x0000,
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35 | 9a64fbe4 | bellard | PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */ |
36 | 9a64fbe4 | bellard | PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */ |
37 | 9a64fbe4 | bellard | PPC_FLOW = 0x0004, /* CPU has flow control instructions */ |
38 | 9a64fbe4 | bellard | PPC_MEM = 0x0008, /* CPU has virtual memory instructions */ |
39 | 9a64fbe4 | bellard | PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */ |
40 | 9a64fbe4 | bellard | PPC_CACHE = 0x0020, /* CPU has cache control instructions */ |
41 | 9a64fbe4 | bellard | PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */ |
42 | 9a64fbe4 | bellard | PPC_EXTERN = 0x0080, /* CPU has external control instructions */ |
43 | 9a64fbe4 | bellard | PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */ |
44 | 9a64fbe4 | bellard | PPC_CACHE_OPT= 0x0200,
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45 | 9a64fbe4 | bellard | PPC_FLOAT_OPT= 0x0400,
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46 | 9a64fbe4 | bellard | PPC_MEM_OPT = 0x0800,
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47 | 9a64fbe4 | bellard | }; |
48 | 79aceca5 | bellard | |
49 | 9a64fbe4 | bellard | #define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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50 | 9a64fbe4 | bellard | PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT) |
51 | 85c4adf6 | bellard | /* PPC 604 */
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52 | 85c4adf6 | bellard | #define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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53 | 85c4adf6 | bellard | PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT \ |
54 | 85c4adf6 | bellard | PPC_MEM_OPT) |
55 | 9a64fbe4 | bellard | /* PPC 740/745/750/755 (aka G3) has external access instructions */
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56 | 9a64fbe4 | bellard | #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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57 | 9a64fbe4 | bellard | PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT) |
58 | 79aceca5 | bellard | |
59 | 9fddaa0c | bellard | typedef struct ppc_tb_t ppc_tb_t; |
60 | 9fddaa0c | bellard | |
61 | 79aceca5 | bellard | /* Supervisor mode registers */
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62 | 79aceca5 | bellard | /* Machine state register */
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63 | 79aceca5 | bellard | #define MSR_POW 18 |
64 | 79aceca5 | bellard | #define MSR_ILE 16 |
65 | 79aceca5 | bellard | #define MSR_EE 15 |
66 | 79aceca5 | bellard | #define MSR_PR 14 |
67 | 79aceca5 | bellard | #define MSR_FP 13 |
68 | 79aceca5 | bellard | #define MSR_ME 12 |
69 | 79aceca5 | bellard | #define MSR_FE0 11 |
70 | 79aceca5 | bellard | #define MSR_SE 10 |
71 | 79aceca5 | bellard | #define MSR_BE 9 |
72 | 79aceca5 | bellard | #define MSR_FE1 8 |
73 | 79aceca5 | bellard | #define MSR_IP 6 |
74 | 79aceca5 | bellard | #define MSR_IR 5 |
75 | 79aceca5 | bellard | #define MSR_DR 4 |
76 | 79aceca5 | bellard | #define MSR_RI 1 |
77 | 79aceca5 | bellard | #define MSR_LE 0 |
78 | 79aceca5 | bellard | #define msr_pow env->msr[MSR_POW]
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79 | 79aceca5 | bellard | #define msr_ile env->msr[MSR_ILE]
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80 | 79aceca5 | bellard | #define msr_ee env->msr[MSR_EE]
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81 | 79aceca5 | bellard | #define msr_pr env->msr[MSR_PR]
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82 | 79aceca5 | bellard | #define msr_fp env->msr[MSR_FP]
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83 | 79aceca5 | bellard | #define msr_me env->msr[MSR_ME]
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84 | 79aceca5 | bellard | #define msr_fe0 env->msr[MSR_FE0]
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85 | 79aceca5 | bellard | #define msr_se env->msr[MSR_SE]
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86 | 79aceca5 | bellard | #define msr_be env->msr[MSR_BE]
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87 | 79aceca5 | bellard | #define msr_fe1 env->msr[MSR_FE1]
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88 | 79aceca5 | bellard | #define msr_ip env->msr[MSR_IP]
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89 | 79aceca5 | bellard | #define msr_ir env->msr[MSR_IR]
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90 | 79aceca5 | bellard | #define msr_dr env->msr[MSR_DR]
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91 | 79aceca5 | bellard | #define msr_ri env->msr[MSR_RI]
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92 | 79aceca5 | bellard | #define msr_le env->msr[MSR_LE]
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93 | 79aceca5 | bellard | |
94 | 79aceca5 | bellard | /* Segment registers */
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95 | 79aceca5 | bellard | typedef struct CPUPPCState { |
96 | 79aceca5 | bellard | /* general purpose registers */
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97 | 79aceca5 | bellard | uint32_t gpr[32];
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98 | 79aceca5 | bellard | /* floating point registers */
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99 | fb0eaffc | bellard | double fpr[32]; |
100 | 79aceca5 | bellard | /* segment registers */
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101 | 9a64fbe4 | bellard | uint32_t sdr1; |
102 | 9a64fbe4 | bellard | uint32_t sr[16];
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103 | 79aceca5 | bellard | /* XER */
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104 | 9a64fbe4 | bellard | uint8_t xer[4];
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105 | 79aceca5 | bellard | /* Reservation address */
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106 | 79aceca5 | bellard | uint32_t reserve; |
107 | 79aceca5 | bellard | /* machine state register */
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108 | 79aceca5 | bellard | uint8_t msr[32];
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109 | 79aceca5 | bellard | /* condition register */
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110 | 79aceca5 | bellard | uint8_t crf[8];
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111 | 79aceca5 | bellard | /* floating point status and control register */
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112 | 9a64fbe4 | bellard | uint8_t fpscr[8];
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113 | 79aceca5 | bellard | uint32_t nip; |
114 | 9a64fbe4 | bellard | /* special purpose registers */
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115 | 9a64fbe4 | bellard | uint32_t lr; |
116 | 9a64fbe4 | bellard | uint32_t ctr; |
117 | 9a64fbe4 | bellard | /* BATs */
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118 | 9a64fbe4 | bellard | uint32_t DBAT[2][8]; |
119 | 9a64fbe4 | bellard | uint32_t IBAT[2][8]; |
120 | 9a64fbe4 | bellard | /* all others */
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121 | 9a64fbe4 | bellard | uint32_t spr[1024];
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122 | 79aceca5 | bellard | /* qemu dedicated */
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123 | fb0eaffc | bellard | /* temporary float registers */
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124 | fb0eaffc | bellard | double ft0;
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125 | fb0eaffc | bellard | double ft1;
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126 | fb0eaffc | bellard | double ft2;
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127 | 79aceca5 | bellard | int interrupt_request;
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128 | 79aceca5 | bellard | jmp_buf jmp_env; |
129 | 79aceca5 | bellard | int exception_index;
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130 | 79aceca5 | bellard | int error_code;
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131 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
132 | ac9eb073 | bellard | type is stored here */
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133 | 79aceca5 | bellard | int user_mode_only; /* user mode only simulation */ |
134 | 79aceca5 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
135 | 9a64fbe4 | bellard | /* soft mmu support */
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136 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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137 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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138 | d720b93d | bellard | context) */
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139 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
140 | d720b93d | bellard | written */
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141 | d720b93d | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
142 | d720b93d | bellard | memory was written */
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143 | a541f297 | bellard | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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144 | 9a64fbe4 | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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145 | 9a64fbe4 | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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146 | a541f297 | bellard | |
147 | a541f297 | bellard | /* ice debug support */
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148 | a541f297 | bellard | uint32_t breakpoints[MAX_BREAKPOINTS]; |
149 | a541f297 | bellard | int nb_breakpoints;
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150 | 9fddaa0c | bellard | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
151 | 9fddaa0c | bellard | |
152 | 9fddaa0c | bellard | /* Time base and decrementer */
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153 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
154 | 9fddaa0c | bellard | |
155 | 9fddaa0c | bellard | /* Power management */
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156 | 9fddaa0c | bellard | int power_mode;
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157 | a541f297 | bellard | |
158 | 79aceca5 | bellard | /* user data */
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159 | 79aceca5 | bellard | void *opaque;
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160 | 79aceca5 | bellard | } CPUPPCState; |
161 | 79aceca5 | bellard | |
162 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
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163 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
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164 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
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165 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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166 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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167 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
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168 | 79aceca5 | bellard | struct siginfo;
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169 | 79aceca5 | bellard | int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
170 | 79aceca5 | bellard | void *puc);
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171 | 79aceca5 | bellard | |
172 | a541f297 | bellard | void do_interrupt (CPUPPCState *env);
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173 | 9a64fbe4 | bellard | void cpu_loop_exit(void); |
174 | a541f297 | bellard | |
175 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
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176 | a541f297 | bellard | |
177 | a541f297 | bellard | uint32_t _load_xer (CPUPPCState *env); |
178 | a541f297 | bellard | void _store_xer (CPUPPCState *env, uint32_t value);
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179 | a541f297 | bellard | uint32_t _load_msr (CPUPPCState *env); |
180 | a541f297 | bellard | void _store_msr (CPUPPCState *env, uint32_t value);
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181 | a541f297 | bellard | |
182 | 85c4adf6 | bellard | int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
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183 | 85c4adf6 | bellard | |
184 | 9fddaa0c | bellard | /* Time-base and decrementer management */
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185 | 9fddaa0c | bellard | #ifndef NO_CPU_IO_DEFS
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186 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
187 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
188 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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189 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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190 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
191 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
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192 | 9fddaa0c | bellard | #endif
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193 | 79aceca5 | bellard | |
194 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
195 | 79aceca5 | bellard | #include "cpu-all.h" |
196 | 79aceca5 | bellard | |
197 | 79aceca5 | bellard | #define ugpr(n) (env->gpr[n])
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198 | 9a64fbe4 | bellard | #define fprd(n) (env->fpr[n])
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199 | 9a64fbe4 | bellard | #define fprs(n) ((float)env->fpr[n]) |
200 | 9a64fbe4 | bellard | #define fpru(n) ((uint32_t)env->fpr[n])
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201 | 9a64fbe4 | bellard | #define fpri(n) ((int32_t)env->fpr[n])
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202 | 79aceca5 | bellard | |
203 | 79aceca5 | bellard | #define SPR_ENCODE(sprn) \
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204 | 79aceca5 | bellard | (((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
205 | 79aceca5 | bellard | |
206 | 79aceca5 | bellard | /* User mode SPR */
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207 | 79aceca5 | bellard | #define spr(n) env->spr[n]
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208 | 79aceca5 | bellard | #define XER_SO 31 |
209 | 79aceca5 | bellard | #define XER_OV 30 |
210 | 79aceca5 | bellard | #define XER_CA 29 |
211 | 79aceca5 | bellard | #define XER_BC 0 |
212 | 9a64fbe4 | bellard | #define xer_so env->xer[3] |
213 | 9a64fbe4 | bellard | #define xer_ov env->xer[2] |
214 | 9a64fbe4 | bellard | #define xer_ca env->xer[1] |
215 | 9a64fbe4 | bellard | #define xer_bc env->xer[0] |
216 | 79aceca5 | bellard | |
217 | 85c4adf6 | bellard | #define MQ SPR_ENCODE(0) |
218 | 9a64fbe4 | bellard | #define XER SPR_ENCODE(1) |
219 | 85c4adf6 | bellard | #define RTCUR SPR_ENCODE(4) |
220 | 85c4adf6 | bellard | #define RTCLR SPR_ENCODE(5) |
221 | 9a64fbe4 | bellard | #define LR SPR_ENCODE(8) |
222 | 9a64fbe4 | bellard | #define CTR SPR_ENCODE(9) |
223 | 79aceca5 | bellard | /* VEA mode SPR */
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224 | 9a64fbe4 | bellard | #define V_TBL SPR_ENCODE(268) |
225 | 9a64fbe4 | bellard | #define V_TBU SPR_ENCODE(269) |
226 | 79aceca5 | bellard | /* supervisor mode SPR */
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227 | 9a64fbe4 | bellard | #define DSISR SPR_ENCODE(18) |
228 | 9a64fbe4 | bellard | #define DAR SPR_ENCODE(19) |
229 | 85c4adf6 | bellard | #define RTCUW SPR_ENCODE(20) |
230 | 85c4adf6 | bellard | #define RTCLW SPR_ENCODE(21) |
231 | 9a64fbe4 | bellard | #define DECR SPR_ENCODE(22) |
232 | 9a64fbe4 | bellard | #define SDR1 SPR_ENCODE(25) |
233 | 9a64fbe4 | bellard | #define SRR0 SPR_ENCODE(26) |
234 | 9a64fbe4 | bellard | #define SRR1 SPR_ENCODE(27) |
235 | 9a64fbe4 | bellard | #define SPRG0 SPR_ENCODE(272) |
236 | 9a64fbe4 | bellard | #define SPRG1 SPR_ENCODE(273) |
237 | 9a64fbe4 | bellard | #define SPRG2 SPR_ENCODE(274) |
238 | 9a64fbe4 | bellard | #define SPRG3 SPR_ENCODE(275) |
239 | 9a64fbe4 | bellard | #define SPRG4 SPR_ENCODE(276) |
240 | 9a64fbe4 | bellard | #define SPRG5 SPR_ENCODE(277) |
241 | 9a64fbe4 | bellard | #define SPRG6 SPR_ENCODE(278) |
242 | 9a64fbe4 | bellard | #define SPRG7 SPR_ENCODE(279) |
243 | 9a64fbe4 | bellard | #define ASR SPR_ENCODE(280) |
244 | 9a64fbe4 | bellard | #define EAR SPR_ENCODE(282) |
245 | 9a64fbe4 | bellard | #define O_TBL SPR_ENCODE(284) |
246 | 9a64fbe4 | bellard | #define O_TBU SPR_ENCODE(285) |
247 | 9a64fbe4 | bellard | #define PVR SPR_ENCODE(287) |
248 | 9a64fbe4 | bellard | #define IBAT0U SPR_ENCODE(528) |
249 | 9a64fbe4 | bellard | #define IBAT0L SPR_ENCODE(529) |
250 | 9a64fbe4 | bellard | #define IBAT1U SPR_ENCODE(530) |
251 | 9a64fbe4 | bellard | #define IBAT1L SPR_ENCODE(531) |
252 | 9a64fbe4 | bellard | #define IBAT2U SPR_ENCODE(532) |
253 | 9a64fbe4 | bellard | #define IBAT2L SPR_ENCODE(533) |
254 | 9a64fbe4 | bellard | #define IBAT3U SPR_ENCODE(534) |
255 | 9a64fbe4 | bellard | #define IBAT3L SPR_ENCODE(535) |
256 | 9a64fbe4 | bellard | #define DBAT0U SPR_ENCODE(536) |
257 | 9a64fbe4 | bellard | #define DBAT0L SPR_ENCODE(537) |
258 | 9a64fbe4 | bellard | #define DBAT1U SPR_ENCODE(538) |
259 | 9a64fbe4 | bellard | #define DBAT1L SPR_ENCODE(539) |
260 | 9a64fbe4 | bellard | #define DBAT2U SPR_ENCODE(540) |
261 | 9a64fbe4 | bellard | #define DBAT2L SPR_ENCODE(541) |
262 | 9a64fbe4 | bellard | #define DBAT3U SPR_ENCODE(542) |
263 | 9a64fbe4 | bellard | #define DBAT3L SPR_ENCODE(543) |
264 | 9a64fbe4 | bellard | #define IBAT4U SPR_ENCODE(560) |
265 | 9a64fbe4 | bellard | #define IBAT4L SPR_ENCODE(561) |
266 | 9a64fbe4 | bellard | #define IBAT5U SPR_ENCODE(562) |
267 | 9a64fbe4 | bellard | #define IBAT5L SPR_ENCODE(563) |
268 | 9a64fbe4 | bellard | #define IBAT6U SPR_ENCODE(564) |
269 | 9a64fbe4 | bellard | #define IBAT6L SPR_ENCODE(565) |
270 | 9a64fbe4 | bellard | #define IBAT7U SPR_ENCODE(566) |
271 | 9a64fbe4 | bellard | #define IBAT7L SPR_ENCODE(567) |
272 | 9a64fbe4 | bellard | #define DBAT4U SPR_ENCODE(568) |
273 | 9a64fbe4 | bellard | #define DBAT4L SPR_ENCODE(569) |
274 | 9a64fbe4 | bellard | #define DBAT5U SPR_ENCODE(570) |
275 | 9a64fbe4 | bellard | #define DBAT5L SPR_ENCODE(571) |
276 | 9a64fbe4 | bellard | #define DBAT6U SPR_ENCODE(572) |
277 | 9a64fbe4 | bellard | #define DBAT6L SPR_ENCODE(573) |
278 | 9a64fbe4 | bellard | #define DBAT7U SPR_ENCODE(574) |
279 | 9a64fbe4 | bellard | #define DBAT7L SPR_ENCODE(575) |
280 | 85c4adf6 | bellard | #define UMMCR0 SPR_ENCODE(936) |
281 | 85c4adf6 | bellard | #define UPMC1 SPR_ENCODE(937) |
282 | 85c4adf6 | bellard | #define UPMC2 SPR_ENCODE(938) |
283 | 85c4adf6 | bellard | #define USIA SPR_ENCODE(939) |
284 | 85c4adf6 | bellard | #define UMMCR1 SPR_ENCODE(940) |
285 | 85c4adf6 | bellard | #define UPMC3 SPR_ENCODE(941) |
286 | 85c4adf6 | bellard | #define UPMC4 SPR_ENCODE(942) |
287 | 85c4adf6 | bellard | #define MMCR0 SPR_ENCODE(952) |
288 | 85c4adf6 | bellard | #define PMC1 SPR_ENCODE(953) |
289 | 85c4adf6 | bellard | #define PMC2 SPR_ENCODE(954) |
290 | 85c4adf6 | bellard | #define SIA SPR_ENCODE(955) |
291 | 85c4adf6 | bellard | #define MMCR1 SPR_ENCODE(956) |
292 | 85c4adf6 | bellard | #define PMC3 SPR_ENCODE(957) |
293 | 85c4adf6 | bellard | #define PMC4 SPR_ENCODE(958) |
294 | 85c4adf6 | bellard | #define SDA SPR_ENCODE(959) |
295 | 85c4adf6 | bellard | #define DMISS SPR_ENCODE(976) |
296 | 85c4adf6 | bellard | #define DCMP SPR_ENCODE(977) |
297 | 85c4adf6 | bellard | #define DHASH1 SPR_ENCODE(978) |
298 | 85c4adf6 | bellard | #define DHASH2 SPR_ENCODE(979) |
299 | 85c4adf6 | bellard | #define IMISS SPR_ENCODE(980) |
300 | 85c4adf6 | bellard | #define ICMP SPR_ENCODE(981) |
301 | 85c4adf6 | bellard | #define RPA SPR_ENCODE(982) |
302 | 85c4adf6 | bellard | #define TCR SPR_ENCODE(984) |
303 | 85c4adf6 | bellard | #define IBR SPR_ENCODE(986) |
304 | 85c4adf6 | bellard | #define ESASRR SPR_ENCODE(987) |
305 | 85c4adf6 | bellard | #define SEBR SPR_ENCODE(990) |
306 | 85c4adf6 | bellard | #define SER SPR_ENCODE(991) |
307 | 85c4adf6 | bellard | #define HID0 SPR_ENCODE(1008) |
308 | 85c4adf6 | bellard | #define HID1 SPR_ENCODE(1009) |
309 | 85c4adf6 | bellard | #define IABR SPR_ENCODE(1010) |
310 | 85c4adf6 | bellard | #define HID2 SPR_ENCODE(1011) |
311 | 9a64fbe4 | bellard | #define DABR SPR_ENCODE(1013) |
312 | 85c4adf6 | bellard | #define L2PM SPR_ENCODE(1016) |
313 | 85c4adf6 | bellard | #define L2CR SPR_ENCODE(1017) |
314 | 85c4adf6 | bellard | #define ICTC SPR_ENCODE(1019) |
315 | 85c4adf6 | bellard | #define THRM1 SPR_ENCODE(1020) |
316 | 85c4adf6 | bellard | #define THRM2 SPR_ENCODE(1021) |
317 | 85c4adf6 | bellard | #define THRM3 SPR_ENCODE(1022) |
318 | 85c4adf6 | bellard | #define SP SPR_ENCODE(1021) |
319 | ce93da6f | bellard | #define SPR_LP SPR_ENCODE(1022) |
320 | 79aceca5 | bellard | #define DABR_MASK 0xFFFFFFF8 |
321 | 9a64fbe4 | bellard | #define FPECR SPR_ENCODE(1022) |
322 | 9a64fbe4 | bellard | #define PIR SPR_ENCODE(1023) |
323 | 79aceca5 | bellard | |
324 | 9a64fbe4 | bellard | /* Memory access type :
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325 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
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326 | 9a64fbe4 | bellard | */
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327 | 79aceca5 | bellard | enum {
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328 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
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329 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
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330 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
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331 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
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332 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
333 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
334 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
335 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
336 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
337 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
338 | 9a64fbe4 | bellard | }; |
339 | 9a64fbe4 | bellard | |
340 | 9a64fbe4 | bellard | /*****************************************************************************/
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341 | 9a64fbe4 | bellard | /* Exceptions */
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342 | 9a64fbe4 | bellard | enum {
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343 | 9a64fbe4 | bellard | EXCP_NONE = -1,
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344 | 79aceca5 | bellard | /* PPC hardware exceptions : exception vector / 0x100 */
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345 | 79aceca5 | bellard | EXCP_RESET = 0x01, /* System reset */ |
346 | 79aceca5 | bellard | EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
347 | 79aceca5 | bellard | EXCP_DSI = 0x03, /* Impossible memory access */ |
348 | 79aceca5 | bellard | EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
349 | 79aceca5 | bellard | EXCP_EXTERNAL = 0x05, /* External interruption */ |
350 | 79aceca5 | bellard | EXCP_ALIGN = 0x06, /* Alignment exception */ |
351 | 79aceca5 | bellard | EXCP_PROGRAM = 0x07, /* Program exception */ |
352 | 79aceca5 | bellard | EXCP_NO_FP = 0x08, /* No floating point */ |
353 | 79aceca5 | bellard | EXCP_DECR = 0x09, /* Decrementer exception */ |
354 | 79aceca5 | bellard | EXCP_RESA = 0x0A, /* Implementation specific */ |
355 | 79aceca5 | bellard | EXCP_RESB = 0x0B, /* Implementation specific */ |
356 | 79aceca5 | bellard | EXCP_SYSCALL = 0x0C, /* System call */ |
357 | 79aceca5 | bellard | EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
358 | 79aceca5 | bellard | EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
359 | 9a64fbe4 | bellard | /* MPC740/745/750 & IBM 750 */
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360 | 9a64fbe4 | bellard | EXCP_PERF = 0x0F, /* Performance monitor */ |
361 | 9a64fbe4 | bellard | EXCP_IABR = 0x13, /* Instruction address breakpoint */ |
362 | 9a64fbe4 | bellard | EXCP_SMI = 0x14, /* System management interrupt */ |
363 | 9a64fbe4 | bellard | EXCP_THRM = 0x15, /* Thermal management interrupt */ |
364 | 9a64fbe4 | bellard | /* MPC755 */
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365 | 9a64fbe4 | bellard | EXCP_TLBMISS = 0x10, /* Instruction TLB miss */ |
366 | 9a64fbe4 | bellard | EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */ |
367 | 9a64fbe4 | bellard | EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */ |
368 | 9a64fbe4 | bellard | EXCP_PPC_MAX = 0x16,
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369 | 9a64fbe4 | bellard | /* Qemu exception */
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370 | 9a64fbe4 | bellard | EXCP_OFCALL = 0x20, /* Call open-firmware emulator */ |
371 | 9a64fbe4 | bellard | EXCP_RTASCALL = 0x21, /* Call RTAS emulator */ |
372 | 9a64fbe4 | bellard | /* Special cases where we want to stop translation */
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373 | 9a64fbe4 | bellard | EXCP_MTMSR = 0x104, /* mtmsr instruction: */ |
374 | 9a64fbe4 | bellard | /* may change privilege level */
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375 | 9a64fbe4 | bellard | EXCP_BRANCH = 0x108, /* branch instruction */ |
376 | 9a64fbe4 | bellard | EXCP_RFI = 0x10C, /* return from interrupt */ |
377 | 9a64fbe4 | bellard | EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
378 | 9a64fbe4 | bellard | }; |
379 | 9a64fbe4 | bellard | /* Error codes */
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380 | 9a64fbe4 | bellard | enum {
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381 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_DSI */
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382 | 9a64fbe4 | bellard | EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */ |
383 | 9a64fbe4 | bellard | EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */ |
384 | 9a64fbe4 | bellard | EXCP_DSI_PROT = 0x03, /* Memory protection violation */ |
385 | 9a64fbe4 | bellard | EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */ |
386 | 9a64fbe4 | bellard | EXCP_DSI_DABR = 0x05, /* Data address breakpoint */ |
387 | 9a64fbe4 | bellard | /* flags for EXCP_DSI */
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388 | 9a64fbe4 | bellard | EXCP_DSI_DIRECT = 0x10,
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389 | 9a64fbe4 | bellard | EXCP_DSI_STORE = 0x20,
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390 | a541f297 | bellard | EXCP_DSI_ECXW = 0x40,
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391 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ISI */
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392 | 9a64fbe4 | bellard | EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */ |
393 | 9a64fbe4 | bellard | EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */ |
394 | 9a64fbe4 | bellard | EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */ |
395 | 9a64fbe4 | bellard | EXCP_ISI_PROT = 0x04, /* Memory protection violation */ |
396 | a541f297 | bellard | EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from * |
397 | a541f297 | bellard | * a direct store segment */
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398 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ALIGN */
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399 | 9a64fbe4 | bellard | EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
400 | 9a64fbe4 | bellard | EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
401 | 9a64fbe4 | bellard | EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
402 | 9a64fbe4 | bellard | EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
403 | 9a64fbe4 | bellard | EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
404 | 9a64fbe4 | bellard | EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
405 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_PROGRAM */
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406 | 79aceca5 | bellard | /* FP exceptions */
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407 | 9a64fbe4 | bellard | EXCP_FP = 0x10,
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408 | 9a64fbe4 | bellard | EXCP_FP_OX = 0x01, /* FP overflow */ |
409 | 9a64fbe4 | bellard | EXCP_FP_UX = 0x02, /* FP underflow */ |
410 | 9a64fbe4 | bellard | EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
411 | 9a64fbe4 | bellard | EXCP_FP_XX = 0x04, /* FP inexact */ |
412 | 9a64fbe4 | bellard | EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
413 | 9a64fbe4 | bellard | EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
414 | 9a64fbe4 | bellard | EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
415 | 9a64fbe4 | bellard | EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
416 | 9a64fbe4 | bellard | EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
417 | 9a64fbe4 | bellard | EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
418 | 9a64fbe4 | bellard | EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
419 | 9a64fbe4 | bellard | EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
420 | 9a64fbe4 | bellard | EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
421 | 79aceca5 | bellard | /* Invalid instruction */
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422 | 9a64fbe4 | bellard | EXCP_INVAL = 0x20,
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423 | 9a64fbe4 | bellard | EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
424 | 9a64fbe4 | bellard | EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
425 | 9a64fbe4 | bellard | EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
426 | 9a64fbe4 | bellard | EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
427 | 79aceca5 | bellard | /* Privileged instruction */
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428 | 9a64fbe4 | bellard | EXCP_PRIV = 0x30,
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429 | 9a64fbe4 | bellard | EXCP_PRIV_OPC = 0x01,
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430 | 9a64fbe4 | bellard | EXCP_PRIV_REG = 0x02,
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431 | 79aceca5 | bellard | /* Trap */
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432 | 9a64fbe4 | bellard | EXCP_TRAP = 0x40,
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433 | 79aceca5 | bellard | }; |
434 | 79aceca5 | bellard | |
435 | 9a64fbe4 | bellard | /*****************************************************************************/
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436 | 9a64fbe4 | bellard | |
437 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |