root / target-ppc / helper.c @ 0443eaf6
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation helpers for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #include "exec.h" |
21 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
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22 | a541f297 | bellard | #include <time.h> |
23 | 9a64fbe4 | bellard | #include "of.h" |
24 | 9a64fbe4 | bellard | #endif
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25 | 9a64fbe4 | bellard | |
26 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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27 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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28 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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29 | 9a64fbe4 | bellard | |
30 | 9a64fbe4 | bellard | /*****************************************************************************/
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31 | 9a64fbe4 | bellard | /* PPC MMU emulation */
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32 | a541f297 | bellard | |
33 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
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34 | 9a64fbe4 | bellard | static int get_bat (CPUState *env, uint32_t *real, int *prot, |
35 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
36 | 9a64fbe4 | bellard | { |
37 | 9a64fbe4 | bellard | uint32_t *BATlt, *BATut, *BATu, *BATl; |
38 | 9a64fbe4 | bellard | uint32_t base, BEPIl, BEPIu, bl; |
39 | 9a64fbe4 | bellard | int i;
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40 | 9a64fbe4 | bellard | int ret = -1; |
41 | 9a64fbe4 | bellard | |
42 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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43 | 9a64fbe4 | bellard | if (loglevel > 0) { |
44 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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45 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
46 | 9a64fbe4 | bellard | } |
47 | 9a64fbe4 | bellard | #endif
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48 | 9a64fbe4 | bellard | switch (type) {
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49 | 9a64fbe4 | bellard | case ACCESS_CODE:
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50 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
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51 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
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52 | 9a64fbe4 | bellard | break;
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53 | 9a64fbe4 | bellard | default:
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54 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
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55 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
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56 | 9a64fbe4 | bellard | break;
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57 | 9a64fbe4 | bellard | } |
58 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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59 | 9a64fbe4 | bellard | if (loglevel > 0) { |
60 | 9a64fbe4 | bellard | fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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61 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
62 | 9a64fbe4 | bellard | } |
63 | 9a64fbe4 | bellard | #endif
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64 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
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65 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
66 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
67 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
68 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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69 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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70 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
71 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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72 | 9a64fbe4 | bellard | if (loglevel > 0) { |
73 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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74 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
75 | 9a64fbe4 | bellard | *BATu, *BATl); |
76 | 9a64fbe4 | bellard | } |
77 | 9a64fbe4 | bellard | #endif
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78 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
79 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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80 | 9a64fbe4 | bellard | /* BAT matches */
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81 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
82 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
83 | 9a64fbe4 | bellard | /* Get physical address */
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84 | 9a64fbe4 | bellard | *real = (*BATl & 0xF0000000) |
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85 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
86 | a541f297 | bellard | (virtual & 0x0001F000);
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87 | 9a64fbe4 | bellard | if (*BATl & 0x00000001) |
88 | 5f21aef2 | bellard | *prot = PAGE_READ; |
89 | 9a64fbe4 | bellard | if (*BATl & 0x00000002) |
90 | 5f21aef2 | bellard | *prot = PAGE_WRITE | PAGE_READ; |
91 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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92 | 9a64fbe4 | bellard | if (loglevel > 0) { |
93 | 9a64fbe4 | bellard | fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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94 | 5f21aef2 | bellard | i, *real, *prot & PAGE_READ ? 'R' : '-', |
95 | 5f21aef2 | bellard | *prot & PAGE_WRITE ? 'W' : '-'); |
96 | 9a64fbe4 | bellard | } |
97 | 9a64fbe4 | bellard | #endif
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98 | 9a64fbe4 | bellard | ret = 0;
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99 | 9a64fbe4 | bellard | break;
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100 | 9a64fbe4 | bellard | } |
101 | 9a64fbe4 | bellard | } |
102 | 9a64fbe4 | bellard | } |
103 | 9a64fbe4 | bellard | if (ret < 0) { |
104 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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105 | 9a64fbe4 | bellard | printf("no BAT match for 0x%08x:\n", virtual);
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106 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
107 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
108 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
109 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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110 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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111 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
112 | 9a64fbe4 | bellard | printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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113 | 9a64fbe4 | bellard | "0x%08x 0x%08x 0x%08x\n",
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114 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
115 | 9a64fbe4 | bellard | *BATu, *BATl, BEPIu, BEPIl, bl); |
116 | 9a64fbe4 | bellard | } |
117 | 9a64fbe4 | bellard | #endif
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118 | 9a64fbe4 | bellard | } |
119 | 9a64fbe4 | bellard | /* No hit */
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120 | 9a64fbe4 | bellard | return ret;
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121 | 9a64fbe4 | bellard | } |
122 | 9a64fbe4 | bellard | |
123 | 9a64fbe4 | bellard | /* PTE table lookup */
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124 | 9a64fbe4 | bellard | static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
125 | 9a64fbe4 | bellard | int h, int key, int rw) |
126 | 9a64fbe4 | bellard | { |
127 | a541f297 | bellard | uint32_t pte0, pte1, keep = 0, access = 0; |
128 | 9a64fbe4 | bellard | int i, good = -1, store = 0; |
129 | 9a64fbe4 | bellard | int ret = -1; /* No entry found */ |
130 | 9a64fbe4 | bellard | |
131 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
132 | 8df1cd07 | bellard | pte0 = ldl_phys(base + (i * 8));
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133 | 8df1cd07 | bellard | pte1 = ldl_phys(base + (i * 8) + 4); |
134 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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135 | a541f297 | bellard | if (loglevel > 0) { |
136 | a541f297 | bellard | fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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137 | a541f297 | bellard | "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1, |
138 | a541f297 | bellard | pte0 >> 31, h, (pte0 >> 6) & 1, va); |
139 | a541f297 | bellard | } |
140 | 9a64fbe4 | bellard | #endif
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141 | 9a64fbe4 | bellard | /* Check validity and table match */
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142 | 9a64fbe4 | bellard | if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
143 | 9a64fbe4 | bellard | /* Check vsid & api */
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144 | 9a64fbe4 | bellard | if ((pte0 & 0x7FFFFFBF) == va) { |
145 | 9a64fbe4 | bellard | if (good == -1) { |
146 | 9a64fbe4 | bellard | good = i; |
147 | 9a64fbe4 | bellard | keep = pte1; |
148 | 9a64fbe4 | bellard | } else {
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149 | 9a64fbe4 | bellard | /* All matches should have equal RPN, WIMG & PP */
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150 | 9a64fbe4 | bellard | if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
151 | a541f297 | bellard | if (loglevel > 0) |
152 | a541f297 | bellard | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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153 | 9a64fbe4 | bellard | return -1; |
154 | 9a64fbe4 | bellard | } |
155 | 9a64fbe4 | bellard | } |
156 | 9a64fbe4 | bellard | /* Check access rights */
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157 | 9a64fbe4 | bellard | if (key == 0) { |
158 | 5f21aef2 | bellard | access = PAGE_READ; |
159 | 9a64fbe4 | bellard | if ((pte1 & 0x00000003) != 0x3) |
160 | 5f21aef2 | bellard | access |= PAGE_WRITE; |
161 | 9a64fbe4 | bellard | } else {
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162 | 9a64fbe4 | bellard | switch (pte1 & 0x00000003) { |
163 | 9a64fbe4 | bellard | case 0x0: |
164 | a541f297 | bellard | access = 0;
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165 | 9a64fbe4 | bellard | break;
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166 | 9a64fbe4 | bellard | case 0x1: |
167 | 9a64fbe4 | bellard | case 0x3: |
168 | 5f21aef2 | bellard | access = PAGE_READ; |
169 | 9a64fbe4 | bellard | break;
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170 | 9a64fbe4 | bellard | case 0x2: |
171 | 5f21aef2 | bellard | access = PAGE_READ | PAGE_WRITE; |
172 | 9a64fbe4 | bellard | break;
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173 | 9a64fbe4 | bellard | } |
174 | 9a64fbe4 | bellard | } |
175 | a541f297 | bellard | if (ret < 0) { |
176 | 5f21aef2 | bellard | if ((rw == 0 && (access & PAGE_READ)) || |
177 | 5f21aef2 | bellard | (rw == 1 && (access & PAGE_WRITE))) {
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178 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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179 | a541f297 | bellard | if (loglevel > 0) |
180 | a541f297 | bellard | fprintf(logfile, "PTE access granted !\n");
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181 | 9a64fbe4 | bellard | #endif
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182 | 9a64fbe4 | bellard | good = i; |
183 | 9a64fbe4 | bellard | keep = pte1; |
184 | 9a64fbe4 | bellard | ret = 0;
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185 | a541f297 | bellard | } else {
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186 | a541f297 | bellard | /* Access right violation */
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187 | a541f297 | bellard | ret = -2;
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188 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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189 | a541f297 | bellard | if (loglevel > 0) |
190 | a541f297 | bellard | fprintf(logfile, "PTE access rejected\n");
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191 | 9a64fbe4 | bellard | #endif
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192 | 9a64fbe4 | bellard | } |
193 | a541f297 | bellard | *prot = access; |
194 | a541f297 | bellard | } |
195 | 9a64fbe4 | bellard | } |
196 | 9a64fbe4 | bellard | } |
197 | 9a64fbe4 | bellard | } |
198 | 9a64fbe4 | bellard | if (good != -1) { |
199 | 9a64fbe4 | bellard | *RPN = keep & 0xFFFFF000;
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200 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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201 | a541f297 | bellard | if (loglevel > 0) { |
202 | a541f297 | bellard | fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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203 | 9a64fbe4 | bellard | *RPN, *prot, ret); |
204 | a541f297 | bellard | } |
205 | 9a64fbe4 | bellard | #endif
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206 | 9a64fbe4 | bellard | /* Update page flags */
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207 | 9a64fbe4 | bellard | if (!(keep & 0x00000100)) { |
208 | a541f297 | bellard | /* Access flag */
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209 | 9a64fbe4 | bellard | keep |= 0x00000100;
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210 | 9a64fbe4 | bellard | store = 1;
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211 | 9a64fbe4 | bellard | } |
212 | 9a64fbe4 | bellard | if (!(keep & 0x00000080)) { |
213 | a541f297 | bellard | if (rw && ret == 0) { |
214 | a541f297 | bellard | /* Change flag */
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215 | 9a64fbe4 | bellard | keep |= 0x00000080;
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216 | 9a64fbe4 | bellard | store = 1;
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217 | a541f297 | bellard | } else {
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218 | a541f297 | bellard | /* Force page fault for first write access */
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219 | 5f21aef2 | bellard | *prot &= ~PAGE_WRITE; |
220 | 9a64fbe4 | bellard | } |
221 | 9a64fbe4 | bellard | } |
222 | a541f297 | bellard | if (store) {
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223 | 8df1cd07 | bellard | stl_phys_notdirty(base + (good * 8) + 4, keep); |
224 | a541f297 | bellard | } |
225 | 9a64fbe4 | bellard | } |
226 | 9a64fbe4 | bellard | |
227 | 9a64fbe4 | bellard | return ret;
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228 | 79aceca5 | bellard | } |
229 | 79aceca5 | bellard | |
230 | 9a64fbe4 | bellard | static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
231 | 79aceca5 | bellard | { |
232 | 9a64fbe4 | bellard | return (sdr1 & 0xFFFF0000) | (hash & mask); |
233 | 79aceca5 | bellard | } |
234 | 79aceca5 | bellard | |
235 | 9a64fbe4 | bellard | /* Perform segment based translation */
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236 | 9a64fbe4 | bellard | static int get_segment (CPUState *env, uint32_t *real, int *prot, |
237 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
238 | 79aceca5 | bellard | { |
239 | 9a64fbe4 | bellard | uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
240 | 9a64fbe4 | bellard | uint32_t hash, mask; |
241 | 9a64fbe4 | bellard | uint32_t sr; |
242 | 9a64fbe4 | bellard | int key;
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243 | 9a64fbe4 | bellard | int ret = -1, ret2; |
244 | 79aceca5 | bellard | |
245 | 9a64fbe4 | bellard | sr = env->sr[virtual >> 28];
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246 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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247 | a541f297 | bellard | if (loglevel > 0) { |
248 | a541f297 | bellard | fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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249 | a541f297 | bellard | "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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250 | a541f297 | bellard | virtual, virtual >> 28, sr, env->nip,
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251 | a541f297 | bellard | env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
252 | a541f297 | bellard | } |
253 | 9a64fbe4 | bellard | #endif
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254 | a541f297 | bellard | key = (((sr & 0x20000000) && msr_pr == 1) || |
255 | a541f297 | bellard | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
256 | 9a64fbe4 | bellard | if ((sr & 0x80000000) == 0) { |
257 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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258 | a541f297 | bellard | if (loglevel > 0) |
259 | a541f297 | bellard | fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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260 | a541f297 | bellard | key, sr & 0x10000000);
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261 | 9a64fbe4 | bellard | #endif
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262 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
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263 | 9a64fbe4 | bellard | if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
264 | 9a64fbe4 | bellard | /* Page address translation */
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265 | 9a64fbe4 | bellard | vsid = sr & 0x00FFFFFF;
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266 | 9a64fbe4 | bellard | pgidx = (virtual >> 12) & 0xFFFF; |
267 | a541f297 | bellard | sdr = env->sdr1; |
268 | a541f297 | bellard | hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
269 | 9a64fbe4 | bellard | mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
270 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
271 | 9a64fbe4 | bellard | ptem = (vsid << 7) | (pgidx >> 10); |
272 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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273 | a541f297 | bellard | if (loglevel > 0) { |
274 | a541f297 | bellard | fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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275 | a541f297 | bellard | "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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276 | a541f297 | bellard | pg_addr); |
277 | a541f297 | bellard | } |
278 | 9a64fbe4 | bellard | #endif
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279 | 9a64fbe4 | bellard | /* Primary table lookup */
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280 | 9a64fbe4 | bellard | ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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281 | 9a64fbe4 | bellard | if (ret < 0) { |
282 | 9a64fbe4 | bellard | /* Secondary table lookup */
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283 | 9a64fbe4 | bellard | hash = (~hash) & 0x01FFFFC0;
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284 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
285 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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286 | a541f297 | bellard | if (virtual != 0xEFFFFFFF && loglevel > 0) { |
287 | a541f297 | bellard | fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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288 | a541f297 | bellard | "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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289 | a541f297 | bellard | hash, pg_addr); |
290 | a541f297 | bellard | } |
291 | 9a64fbe4 | bellard | #endif
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292 | 9a64fbe4 | bellard | ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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293 | 9a64fbe4 | bellard | if (ret2 != -1) |
294 | 9a64fbe4 | bellard | ret = ret2; |
295 | 9a64fbe4 | bellard | } |
296 | 9a64fbe4 | bellard | } else {
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297 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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298 | a541f297 | bellard | if (loglevel > 0) |
299 | a541f297 | bellard | fprintf(logfile, "No access allowed\n");
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300 | 9a64fbe4 | bellard | #endif
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301 | a541f297 | bellard | ret = -3;
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302 | 9a64fbe4 | bellard | } |
303 | 9a64fbe4 | bellard | } else {
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304 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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305 | a541f297 | bellard | if (loglevel > 0) |
306 | a541f297 | bellard | fprintf(logfile, "direct store...\n");
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307 | 9a64fbe4 | bellard | #endif
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308 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
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309 | 9a64fbe4 | bellard | switch (type) {
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310 | 9a64fbe4 | bellard | case ACCESS_INT:
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311 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
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312 | 9a64fbe4 | bellard | break;
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313 | 9a64fbe4 | bellard | case ACCESS_CODE:
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314 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
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315 | 9a64fbe4 | bellard | return -4; |
316 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
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317 | 9a64fbe4 | bellard | /* Floating point load/store */
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318 | 9a64fbe4 | bellard | return -4; |
319 | 9a64fbe4 | bellard | case ACCESS_RES:
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320 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
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321 | 9a64fbe4 | bellard | return -4; |
322 | 9a64fbe4 | bellard | case ACCESS_CACHE:
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323 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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324 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
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325 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
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326 | 9a64fbe4 | bellard | */
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327 | 9a64fbe4 | bellard | *real = virtual; |
328 | 9a64fbe4 | bellard | return 0; |
329 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
330 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
331 | 9a64fbe4 | bellard | return -4; |
332 | 9a64fbe4 | bellard | default:
|
333 | 9a64fbe4 | bellard | if (logfile) {
|
334 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
335 | 9a64fbe4 | bellard | "address translation\n");
|
336 | 9a64fbe4 | bellard | } |
337 | 9a64fbe4 | bellard | printf("ERROR: instruction should not need "
|
338 | 9a64fbe4 | bellard | "address translation\n");
|
339 | 9a64fbe4 | bellard | return -4; |
340 | 9a64fbe4 | bellard | } |
341 | 9a64fbe4 | bellard | if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
342 | 9a64fbe4 | bellard | *real = virtual; |
343 | 9a64fbe4 | bellard | ret = 2;
|
344 | 9a64fbe4 | bellard | } else {
|
345 | 9a64fbe4 | bellard | ret = -2;
|
346 | 9a64fbe4 | bellard | } |
347 | 79aceca5 | bellard | } |
348 | 9a64fbe4 | bellard | |
349 | 9a64fbe4 | bellard | return ret;
|
350 | 79aceca5 | bellard | } |
351 | 79aceca5 | bellard | |
352 | 9a64fbe4 | bellard | int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
353 | 9a64fbe4 | bellard | uint32_t address, int rw, int access_type) |
354 | 9a64fbe4 | bellard | { |
355 | 9a64fbe4 | bellard | int ret;
|
356 | 514fb8c1 | bellard | #if 0
|
357 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
358 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
359 | 9a64fbe4 | bellard | }
|
360 | 514fb8c1 | bellard | #endif
|
361 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
362 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
363 | 9a64fbe4 | bellard | /* No address translation */
|
364 | a541f297 | bellard | *physical = address & ~0xFFF;
|
365 | 5f21aef2 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
366 | 9a64fbe4 | bellard | ret = 0;
|
367 | 9a64fbe4 | bellard | } else {
|
368 | 9a64fbe4 | bellard | /* Try to find a BAT */
|
369 | 9a64fbe4 | bellard | ret = get_bat(env, physical, prot, address, rw, access_type); |
370 | 9a64fbe4 | bellard | if (ret < 0) { |
371 | 9a64fbe4 | bellard | /* We didn't match any BAT entry */
|
372 | 9a64fbe4 | bellard | ret = get_segment(env, physical, prot, address, rw, access_type); |
373 | 9a64fbe4 | bellard | } |
374 | 9a64fbe4 | bellard | } |
375 | 514fb8c1 | bellard | #if 0
|
376 | a541f297 | bellard | if (loglevel > 0) {
|
377 | a541f297 | bellard | fprintf(logfile, "%s address %08x => %08x\n",
|
378 | a541f297 | bellard | __func__, address, *physical);
|
379 | a541f297 | bellard | }
|
380 | 514fb8c1 | bellard | #endif
|
381 | 9a64fbe4 | bellard | return ret;
|
382 | 9a64fbe4 | bellard | } |
383 | 9a64fbe4 | bellard | |
384 | a6b025d3 | bellard | #if defined(CONFIG_USER_ONLY)
|
385 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
386 | a6b025d3 | bellard | { |
387 | a6b025d3 | bellard | return addr;
|
388 | a6b025d3 | bellard | } |
389 | a6b025d3 | bellard | #else
|
390 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
391 | a6b025d3 | bellard | { |
392 | a6b025d3 | bellard | uint32_t phys_addr; |
393 | a6b025d3 | bellard | int prot;
|
394 | a6b025d3 | bellard | |
395 | a6b025d3 | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
396 | a6b025d3 | bellard | return -1; |
397 | a6b025d3 | bellard | return phys_addr;
|
398 | a6b025d3 | bellard | } |
399 | a6b025d3 | bellard | #endif
|
400 | 9a64fbe4 | bellard | |
401 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
|
402 | 9a64fbe4 | bellard | |
403 | 9a64fbe4 | bellard | #define MMUSUFFIX _mmu
|
404 | 9a64fbe4 | bellard | #define GETPC() (__builtin_return_address(0)) |
405 | 9a64fbe4 | bellard | |
406 | 9a64fbe4 | bellard | #define SHIFT 0 |
407 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
408 | 9a64fbe4 | bellard | |
409 | 9a64fbe4 | bellard | #define SHIFT 1 |
410 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
411 | 9a64fbe4 | bellard | |
412 | 9a64fbe4 | bellard | #define SHIFT 2 |
413 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
414 | 9a64fbe4 | bellard | |
415 | 9a64fbe4 | bellard | #define SHIFT 3 |
416 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
417 | 9a64fbe4 | bellard | |
418 | 9a64fbe4 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
419 | 9a64fbe4 | bellard | NULL, it means that the function was called in C code (i.e. not
|
420 | 9a64fbe4 | bellard | from generated code or from helper.c) */
|
421 | 9a64fbe4 | bellard | /* XXX: fix it to restore all registers */
|
422 | 0fa85d43 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
423 | 9a64fbe4 | bellard | { |
424 | 9a64fbe4 | bellard | TranslationBlock *tb; |
425 | 9a64fbe4 | bellard | CPUState *saved_env; |
426 | a541f297 | bellard | unsigned long pc; |
427 | a541f297 | bellard | int ret;
|
428 | 9a64fbe4 | bellard | |
429 | 9a64fbe4 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
430 | 9a64fbe4 | bellard | generated code */
|
431 | 9a64fbe4 | bellard | saved_env = env; |
432 | 9a64fbe4 | bellard | env = cpu_single_env; |
433 | b769d8fe | bellard | #if 0
|
434 | 9a64fbe4 | bellard | {
|
435 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
436 | 9a64fbe4 | bellard | int index;
|
437 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
438 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
439 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
440 | 4b3686fa | bellard | if (loglevel) {
|
441 | 4b3686fa | bellard | fprintf(logfile,
|
442 | 4b3686fa | bellard | "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
443 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
444 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
445 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
446 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
447 | 4b3686fa | bellard | }
|
448 | 9a64fbe4 | bellard | }
|
449 | b769d8fe | bellard | #endif
|
450 | a541f297 | bellard | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
451 | 9a64fbe4 | bellard | if (ret) {
|
452 | 9a64fbe4 | bellard | if (retaddr) {
|
453 | 9a64fbe4 | bellard | /* now we have a real cpu fault */
|
454 | 9a64fbe4 | bellard | pc = (unsigned long)retaddr; |
455 | 9a64fbe4 | bellard | tb = tb_find_pc(pc); |
456 | 9a64fbe4 | bellard | if (tb) {
|
457 | 9a64fbe4 | bellard | /* the PC is inside the translated code. It means that we have
|
458 | 9a64fbe4 | bellard | a virtual CPU fault */
|
459 | b324e814 | bellard | cpu_restore_state(tb, env, pc, NULL);
|
460 | 9a64fbe4 | bellard | } |
461 | 9a64fbe4 | bellard | } |
462 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
463 | 9a64fbe4 | bellard | } |
464 | b769d8fe | bellard | #if 0
|
465 | 9a64fbe4 | bellard | {
|
466 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
467 | 9a64fbe4 | bellard | int index;
|
468 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
469 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
470 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
471 | 9a64fbe4 | bellard | printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
472 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
473 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
474 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
475 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
476 | 9a64fbe4 | bellard | }
|
477 | b769d8fe | bellard | #endif
|
478 | 9a64fbe4 | bellard | env = saved_env; |
479 | 9a64fbe4 | bellard | } |
480 | 9a64fbe4 | bellard | |
481 | a541f297 | bellard | void cpu_ppc_init_mmu(CPUState *env)
|
482 | 9a64fbe4 | bellard | { |
483 | 9a64fbe4 | bellard | /* Nothing to do: all translation are disabled */
|
484 | 9a64fbe4 | bellard | } |
485 | 9a64fbe4 | bellard | #endif
|
486 | 9a64fbe4 | bellard | |
487 | 9a64fbe4 | bellard | /* Perform address translation */
|
488 | 9a64fbe4 | bellard | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
489 | a541f297 | bellard | int is_user, int is_softmmu) |
490 | 9a64fbe4 | bellard | { |
491 | 9a64fbe4 | bellard | uint32_t physical; |
492 | 9a64fbe4 | bellard | int prot;
|
493 | 9a64fbe4 | bellard | int exception = 0, error_code = 0; |
494 | a541f297 | bellard | int access_type;
|
495 | 9a64fbe4 | bellard | int ret = 0; |
496 | 9a64fbe4 | bellard | |
497 | b769d8fe | bellard | if (rw == 2) { |
498 | b769d8fe | bellard | /* code access */
|
499 | b769d8fe | bellard | rw = 0;
|
500 | b769d8fe | bellard | access_type = ACCESS_CODE; |
501 | b769d8fe | bellard | } else {
|
502 | b769d8fe | bellard | /* data access */
|
503 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
504 | b769d8fe | bellard | correctly */
|
505 | b769d8fe | bellard | access_type = ACCESS_INT; |
506 | b769d8fe | bellard | // access_type = env->access_type;
|
507 | b769d8fe | bellard | } |
508 | 9a64fbe4 | bellard | if (env->user_mode_only) {
|
509 | 9a64fbe4 | bellard | /* user mode only emulation */
|
510 | 1ef59d0a | bellard | ret = -2;
|
511 | 9a64fbe4 | bellard | goto do_fault;
|
512 | 9a64fbe4 | bellard | } |
513 | 9a64fbe4 | bellard | ret = get_physical_address(env, &physical, &prot, |
514 | 9a64fbe4 | bellard | address, rw, access_type); |
515 | 9a64fbe4 | bellard | if (ret == 0) { |
516 | a541f297 | bellard | ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
517 | a541f297 | bellard | is_user, is_softmmu); |
518 | 9a64fbe4 | bellard | } else if (ret < 0) { |
519 | 9a64fbe4 | bellard | do_fault:
|
520 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
521 | a541f297 | bellard | if (loglevel > 0) |
522 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
523 | 9a64fbe4 | bellard | #endif
|
524 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
525 | 9a64fbe4 | bellard | exception = EXCP_ISI; |
526 | 9a64fbe4 | bellard | switch (ret) {
|
527 | 9a64fbe4 | bellard | case -1: |
528 | 9a64fbe4 | bellard | /* No matches in page tables */
|
529 | 9a64fbe4 | bellard | error_code = EXCP_ISI_TRANSLATE; |
530 | 9a64fbe4 | bellard | break;
|
531 | 9a64fbe4 | bellard | case -2: |
532 | 9a64fbe4 | bellard | /* Access rights violation */
|
533 | 9a64fbe4 | bellard | error_code = EXCP_ISI_PROT; |
534 | 9a64fbe4 | bellard | break;
|
535 | 9a64fbe4 | bellard | case -3: |
536 | a541f297 | bellard | /* No execute protection violation */
|
537 | 9a64fbe4 | bellard | error_code = EXCP_ISI_NOEXEC; |
538 | 9a64fbe4 | bellard | break;
|
539 | 9a64fbe4 | bellard | case -4: |
540 | 9a64fbe4 | bellard | /* Direct store exception */
|
541 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
542 | a541f297 | bellard | error_code = EXCP_ISI_DIRECT; |
543 | 9a64fbe4 | bellard | break;
|
544 | 9a64fbe4 | bellard | } |
545 | 9a64fbe4 | bellard | } else {
|
546 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
547 | 9a64fbe4 | bellard | switch (ret) {
|
548 | 9a64fbe4 | bellard | case -1: |
549 | 9a64fbe4 | bellard | /* No matches in page tables */
|
550 | 9a64fbe4 | bellard | error_code = EXCP_DSI_TRANSLATE; |
551 | 9a64fbe4 | bellard | break;
|
552 | 9a64fbe4 | bellard | case -2: |
553 | 9a64fbe4 | bellard | /* Access rights violation */
|
554 | 9a64fbe4 | bellard | error_code = EXCP_DSI_PROT; |
555 | 9a64fbe4 | bellard | break;
|
556 | 9a64fbe4 | bellard | case -4: |
557 | 9a64fbe4 | bellard | /* Direct store exception */
|
558 | 9a64fbe4 | bellard | switch (access_type) {
|
559 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
560 | 9a64fbe4 | bellard | /* Floating point load/store */
|
561 | 9a64fbe4 | bellard | exception = EXCP_ALIGN; |
562 | 9a64fbe4 | bellard | error_code = EXCP_ALIGN_FP; |
563 | 9a64fbe4 | bellard | break;
|
564 | 9a64fbe4 | bellard | case ACCESS_RES:
|
565 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
566 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
567 | 9a64fbe4 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
568 | 9a64fbe4 | bellard | break;
|
569 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
570 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
571 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
572 | a541f297 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | |
573 | a541f297 | bellard | EXCP_DSI_ECXW; |
574 | 9a64fbe4 | bellard | break;
|
575 | 9a64fbe4 | bellard | default:
|
576 | a541f297 | bellard | printf("DSI: invalid exception (%d)\n", ret);
|
577 | 9a64fbe4 | bellard | exception = EXCP_PROGRAM; |
578 | 9a64fbe4 | bellard | error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
579 | 9a64fbe4 | bellard | break;
|
580 | 9a64fbe4 | bellard | } |
581 | 9a64fbe4 | bellard | } |
582 | 9a64fbe4 | bellard | if (rw)
|
583 | 9a64fbe4 | bellard | error_code |= EXCP_DSI_STORE; |
584 | a541f297 | bellard | /* Store fault address */
|
585 | a541f297 | bellard | env->spr[DAR] = address; |
586 | 9a64fbe4 | bellard | } |
587 | 9a64fbe4 | bellard | #if 0
|
588 | 9a64fbe4 | bellard | printf("%s: set exception to %d %02x\n",
|
589 | 9a64fbe4 | bellard | __func__, exception, error_code);
|
590 | 9a64fbe4 | bellard | #endif
|
591 | 9a64fbe4 | bellard | env->exception_index = exception; |
592 | 9a64fbe4 | bellard | env->error_code = error_code; |
593 | 9a64fbe4 | bellard | ret = 1;
|
594 | 9a64fbe4 | bellard | } |
595 | 9a64fbe4 | bellard | return ret;
|
596 | 9a64fbe4 | bellard | } |
597 | 9a64fbe4 | bellard | |
598 | a541f297 | bellard | uint32_t _load_xer (CPUState *env) |
599 | 79aceca5 | bellard | { |
600 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
601 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
602 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
603 | 79aceca5 | bellard | (xer_bc << XER_BC); |
604 | 79aceca5 | bellard | } |
605 | 79aceca5 | bellard | |
606 | a541f297 | bellard | void _store_xer (CPUState *env, uint32_t value)
|
607 | 79aceca5 | bellard | { |
608 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
609 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
610 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
611 | 79aceca5 | bellard | xer_bc = (value >> XER_BC) & 0x1f;
|
612 | 79aceca5 | bellard | } |
613 | 79aceca5 | bellard | |
614 | a541f297 | bellard | uint32_t _load_msr (CPUState *env) |
615 | 79aceca5 | bellard | { |
616 | 79aceca5 | bellard | return (msr_pow << MSR_POW) |
|
617 | 79aceca5 | bellard | (msr_ile << MSR_ILE) | |
618 | 79aceca5 | bellard | (msr_ee << MSR_EE) | |
619 | 79aceca5 | bellard | (msr_pr << MSR_PR) | |
620 | 79aceca5 | bellard | (msr_fp << MSR_FP) | |
621 | 79aceca5 | bellard | (msr_me << MSR_ME) | |
622 | 79aceca5 | bellard | (msr_fe0 << MSR_FE0) | |
623 | 79aceca5 | bellard | (msr_se << MSR_SE) | |
624 | 79aceca5 | bellard | (msr_be << MSR_BE) | |
625 | 79aceca5 | bellard | (msr_fe1 << MSR_FE1) | |
626 | 79aceca5 | bellard | (msr_ip << MSR_IP) | |
627 | 79aceca5 | bellard | (msr_ir << MSR_IR) | |
628 | 79aceca5 | bellard | (msr_dr << MSR_DR) | |
629 | 79aceca5 | bellard | (msr_ri << MSR_RI) | |
630 | 79aceca5 | bellard | (msr_le << MSR_LE); |
631 | 79aceca5 | bellard | } |
632 | 79aceca5 | bellard | |
633 | a541f297 | bellard | void _store_msr (CPUState *env, uint32_t value)
|
634 | 79aceca5 | bellard | { |
635 | 4b3686fa | bellard | #if 0 // TRY
|
636 | 1ef59d0a | bellard | if (((value >> MSR_IR) & 0x01) != msr_ir ||
|
637 | 4b3686fa | bellard | ((value >> MSR_DR) & 0x01) != msr_dr)
|
638 | 4b3686fa | bellard | {
|
639 | a541f297 | bellard | /* Flush all tlb when changing translation mode or privilege level */
|
640 | 1ef59d0a | bellard | tlb_flush(env, 1);
|
641 | a541f297 | bellard | }
|
642 | 4b3686fa | bellard | #endif
|
643 | 9a64fbe4 | bellard | msr_pow = (value >> MSR_POW) & 0x03;
|
644 | 9a64fbe4 | bellard | msr_ile = (value >> MSR_ILE) & 0x01;
|
645 | 9a64fbe4 | bellard | msr_ee = (value >> MSR_EE) & 0x01;
|
646 | 9a64fbe4 | bellard | msr_pr = (value >> MSR_PR) & 0x01;
|
647 | 9a64fbe4 | bellard | msr_fp = (value >> MSR_FP) & 0x01;
|
648 | 9a64fbe4 | bellard | msr_me = (value >> MSR_ME) & 0x01;
|
649 | 9a64fbe4 | bellard | msr_fe0 = (value >> MSR_FE0) & 0x01;
|
650 | 9a64fbe4 | bellard | msr_se = (value >> MSR_SE) & 0x01;
|
651 | 9a64fbe4 | bellard | msr_be = (value >> MSR_BE) & 0x01;
|
652 | 9a64fbe4 | bellard | msr_fe1 = (value >> MSR_FE1) & 0x01;
|
653 | 9a64fbe4 | bellard | msr_ip = (value >> MSR_IP) & 0x01;
|
654 | 9a64fbe4 | bellard | msr_ir = (value >> MSR_IR) & 0x01;
|
655 | 9a64fbe4 | bellard | msr_dr = (value >> MSR_DR) & 0x01;
|
656 | 9a64fbe4 | bellard | msr_ri = (value >> MSR_RI) & 0x01;
|
657 | 9a64fbe4 | bellard | msr_le = (value >> MSR_LE) & 0x01;
|
658 | 18fba28c | bellard | /* XXX: should enter PM state if msr_pow has been set */
|
659 | 79aceca5 | bellard | } |
660 | 79aceca5 | bellard | |
661 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
662 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
663 | 79aceca5 | bellard | { |
664 | 18fba28c | bellard | env->exception_index = -1;
|
665 | 18fba28c | bellard | } |
666 | 9a64fbe4 | bellard | #else
|
667 | 18fba28c | bellard | void do_interrupt (CPUState *env)
|
668 | 18fba28c | bellard | { |
669 | 9a64fbe4 | bellard | uint32_t msr; |
670 | 18fba28c | bellard | int excp;
|
671 | 79aceca5 | bellard | |
672 | 18fba28c | bellard | excp = env->exception_index; |
673 | a541f297 | bellard | msr = _load_msr(env); |
674 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
675 | a541f297 | bellard | if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
676 | 9a64fbe4 | bellard | { |
677 | 9a64fbe4 | bellard | if (loglevel > 0) { |
678 | 9a64fbe4 | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
679 | 9a64fbe4 | bellard | env->nip, excp << 8, env->error_code);
|
680 | b769d8fe | bellard | } |
681 | a541f297 | bellard | if (loglevel > 0) |
682 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
683 | 79aceca5 | bellard | } |
684 | 9a64fbe4 | bellard | #endif
|
685 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
686 | b769d8fe | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
687 | b769d8fe | bellard | env->nip, excp << 8, env->error_code);
|
688 | b769d8fe | bellard | } |
689 | 9a64fbe4 | bellard | /* Generate informations in save/restore registers */
|
690 | 9a64fbe4 | bellard | switch (excp) {
|
691 | 9a64fbe4 | bellard | case EXCP_OFCALL:
|
692 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
|
693 | 9a64fbe4 | bellard | env->gpr[3] = OF_client_entry((void *)env->gpr[3]); |
694 | 9a64fbe4 | bellard | #endif
|
695 | 9a64fbe4 | bellard | return;
|
696 | 9a64fbe4 | bellard | case EXCP_RTASCALL:
|
697 | 9a64fbe4 | bellard | #if defined (USE_OPEN_FIRMWARE)
|
698 | 9a64fbe4 | bellard | printf("RTAS call !\n");
|
699 | 9a64fbe4 | bellard | env->gpr[3] = RTAS_entry((void *)env->gpr[3]); |
700 | 9a64fbe4 | bellard | printf("RTAS call done\n");
|
701 | 9a64fbe4 | bellard | #endif
|
702 | 9a64fbe4 | bellard | return;
|
703 | 9a64fbe4 | bellard | case EXCP_NONE:
|
704 | 9a64fbe4 | bellard | /* Do nothing */
|
705 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
706 | 9a64fbe4 | bellard | printf("%s: escape EXCP_NONE\n", __func__);
|
707 | 9a64fbe4 | bellard | #endif
|
708 | 9a64fbe4 | bellard | return;
|
709 | 9a64fbe4 | bellard | case EXCP_RESET:
|
710 | 9a64fbe4 | bellard | if (msr_ip)
|
711 | 9a64fbe4 | bellard | excp += 0xFFC00;
|
712 | 9a64fbe4 | bellard | goto store_next;
|
713 | 9a64fbe4 | bellard | case EXCP_MACHINE_CHECK:
|
714 | 9a64fbe4 | bellard | if (msr_me == 0) { |
715 | 4b3686fa | bellard | cpu_abort(env, "Machine check exception while not allowed\n");
|
716 | 79aceca5 | bellard | } |
717 | 9a64fbe4 | bellard | msr_me = 0;
|
718 | 9a64fbe4 | bellard | break;
|
719 | 9a64fbe4 | bellard | case EXCP_DSI:
|
720 | 9a64fbe4 | bellard | /* Store exception cause */
|
721 | 9a64fbe4 | bellard | /* data location address has been stored
|
722 | 9a64fbe4 | bellard | * when the fault has been detected
|
723 | 9a64fbe4 | bellard | */
|
724 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
725 | a541f297 | bellard | env->spr[DSISR] = 0;
|
726 | a541f297 | bellard | if (env->error_code & EXCP_DSI_TRANSLATE)
|
727 | a541f297 | bellard | env->spr[DSISR] |= 0x40000000;
|
728 | a541f297 | bellard | else if (env->error_code & EXCP_DSI_PROT) |
729 | a541f297 | bellard | env->spr[DSISR] |= 0x08000000;
|
730 | a541f297 | bellard | else if (env->error_code & EXCP_DSI_NOTSUP) { |
731 | a541f297 | bellard | env->spr[DSISR] |= 0x80000000;
|
732 | a541f297 | bellard | if (env->error_code & EXCP_DSI_DIRECT)
|
733 | a541f297 | bellard | env->spr[DSISR] |= 0x04000000;
|
734 | a541f297 | bellard | } |
735 | a541f297 | bellard | if (env->error_code & EXCP_DSI_STORE)
|
736 | a541f297 | bellard | env->spr[DSISR] |= 0x02000000;
|
737 | a541f297 | bellard | if ((env->error_code & 0xF) == EXCP_DSI_DABR) |
738 | a541f297 | bellard | env->spr[DSISR] |= 0x00400000;
|
739 | a541f297 | bellard | if (env->error_code & EXCP_DSI_ECXW)
|
740 | a541f297 | bellard | env->spr[DSISR] |= 0x00100000;
|
741 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
742 | a541f297 | bellard | if (loglevel) {
|
743 | a541f297 | bellard | fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
744 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR]); |
745 | a541f297 | bellard | } else {
|
746 | a541f297 | bellard | printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
747 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR], env->nip); |
748 | a541f297 | bellard | } |
749 | a541f297 | bellard | #endif
|
750 | a541f297 | bellard | goto store_next;
|
751 | 9a64fbe4 | bellard | case EXCP_ISI:
|
752 | 9a64fbe4 | bellard | /* Store exception cause */
|
753 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
754 | 9a64fbe4 | bellard | if (env->error_code == EXCP_ISI_TRANSLATE)
|
755 | 9a64fbe4 | bellard | msr |= 0x40000000;
|
756 | 9a64fbe4 | bellard | else if (env->error_code == EXCP_ISI_NOEXEC || |
757 | a541f297 | bellard | env->error_code == EXCP_ISI_GUARD || |
758 | a541f297 | bellard | env->error_code == EXCP_ISI_DIRECT) |
759 | 9a64fbe4 | bellard | msr |= 0x10000000;
|
760 | 9a64fbe4 | bellard | else
|
761 | 9a64fbe4 | bellard | msr |= 0x08000000;
|
762 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
763 | a541f297 | bellard | if (loglevel) {
|
764 | a541f297 | bellard | fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
765 | a541f297 | bellard | msr, env->nip); |
766 | a541f297 | bellard | } else {
|
767 | a541f297 | bellard | printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
768 | a541f297 | bellard | msr, env->nip, env->spr[V_TBL]); |
769 | a541f297 | bellard | } |
770 | a541f297 | bellard | #endif
|
771 | 9a64fbe4 | bellard | goto store_next;
|
772 | 9a64fbe4 | bellard | case EXCP_EXTERNAL:
|
773 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
774 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
775 | 9a64fbe4 | bellard | if (loglevel > 0) { |
776 | 9a64fbe4 | bellard | fprintf(logfile, "Skipping hardware interrupt\n");
|
777 | 79aceca5 | bellard | } |
778 | 9a64fbe4 | bellard | #endif
|
779 | a541f297 | bellard | /* Requeue it */
|
780 | 9fddaa0c | bellard | do_raise_exception(EXCP_EXTERNAL); |
781 | 9a64fbe4 | bellard | return;
|
782 | 79aceca5 | bellard | } |
783 | 9a64fbe4 | bellard | goto store_next;
|
784 | 9a64fbe4 | bellard | case EXCP_ALIGN:
|
785 | 9a64fbe4 | bellard | /* Store exception cause */
|
786 | 9a64fbe4 | bellard | /* Get rS/rD and rA from faulting opcode */
|
787 | 9a64fbe4 | bellard | env->spr[DSISR] |= |
788 | 0fa85d43 | bellard | (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
789 | 9a64fbe4 | bellard | /* data location address has been stored
|
790 | 9a64fbe4 | bellard | * when the fault has been detected
|
791 | 9a64fbe4 | bellard | */
|
792 | 9a64fbe4 | bellard | goto store_current;
|
793 | 9a64fbe4 | bellard | case EXCP_PROGRAM:
|
794 | 9a64fbe4 | bellard | msr &= ~0xFFFF0000;
|
795 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
796 | 9a64fbe4 | bellard | case EXCP_FP:
|
797 | 9a64fbe4 | bellard | if (msr_fe0 == 0 && msr_fe1 == 0) { |
798 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
799 | 9a64fbe4 | bellard | printf("Ignore floating point exception\n");
|
800 | 9a64fbe4 | bellard | #endif
|
801 | 9a64fbe4 | bellard | return;
|
802 | 79aceca5 | bellard | } |
803 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
804 | 9a64fbe4 | bellard | /* Set FX */
|
805 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
806 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
807 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
808 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
809 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
810 | 9a64fbe4 | bellard | break;
|
811 | 9a64fbe4 | bellard | case EXCP_INVAL:
|
812 | 4b3686fa | bellard | // printf("Invalid instruction at 0x%08x\n", env->nip);
|
813 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
814 | 9a64fbe4 | bellard | break;
|
815 | 9a64fbe4 | bellard | case EXCP_PRIV:
|
816 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
817 | 9a64fbe4 | bellard | break;
|
818 | 9a64fbe4 | bellard | case EXCP_TRAP:
|
819 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
820 | 9a64fbe4 | bellard | break;
|
821 | 9a64fbe4 | bellard | default:
|
822 | 9a64fbe4 | bellard | /* Should never occur */
|
823 | 9a64fbe4 | bellard | break;
|
824 | 79aceca5 | bellard | } |
825 | 9a64fbe4 | bellard | msr |= 0x00010000;
|
826 | 9a64fbe4 | bellard | goto store_current;
|
827 | 9a64fbe4 | bellard | case EXCP_NO_FP:
|
828 | 9a64fbe4 | bellard | goto store_current;
|
829 | 9a64fbe4 | bellard | case EXCP_DECR:
|
830 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
831 | 9a64fbe4 | bellard | /* Requeue it */
|
832 | 9fddaa0c | bellard | do_raise_exception(EXCP_DECR); |
833 | 9a64fbe4 | bellard | return;
|
834 | 9a64fbe4 | bellard | } |
835 | 9a64fbe4 | bellard | goto store_next;
|
836 | 9a64fbe4 | bellard | case EXCP_SYSCALL:
|
837 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
838 | b769d8fe | bellard | fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
839 | b769d8fe | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
840 | b769d8fe | bellard | env->gpr[5], env->gpr[6]); |
841 | b769d8fe | bellard | if (env->gpr[0] == 4 && env->gpr[3] == 1) { |
842 | b769d8fe | bellard | int len, addr, i;
|
843 | b769d8fe | bellard | uint8_t c; |
844 | b769d8fe | bellard | |
845 | b769d8fe | bellard | fprintf(logfile, "write: ");
|
846 | b769d8fe | bellard | addr = env->gpr[4];
|
847 | b769d8fe | bellard | len = env->gpr[5];
|
848 | b769d8fe | bellard | if (len > 64) |
849 | b769d8fe | bellard | len = 64;
|
850 | b769d8fe | bellard | for(i = 0; i < len; i++) { |
851 | b769d8fe | bellard | c = 0;
|
852 | b769d8fe | bellard | cpu_memory_rw_debug(env, addr + i, &c, 1, 0); |
853 | b769d8fe | bellard | if (c < 32 || c > 126) |
854 | b769d8fe | bellard | c = '.';
|
855 | b769d8fe | bellard | fprintf(logfile, "%c", c);
|
856 | b769d8fe | bellard | } |
857 | b769d8fe | bellard | fprintf(logfile, "\n");
|
858 | b769d8fe | bellard | } |
859 | b769d8fe | bellard | } |
860 | 9a64fbe4 | bellard | goto store_next;
|
861 | 9a64fbe4 | bellard | case EXCP_TRACE:
|
862 | 9a64fbe4 | bellard | goto store_next;
|
863 | 9a64fbe4 | bellard | case EXCP_FP_ASSIST:
|
864 | 9a64fbe4 | bellard | goto store_next;
|
865 | 9a64fbe4 | bellard | case EXCP_MTMSR:
|
866 | 9a64fbe4 | bellard | /* Nothing to do */
|
867 | 9a64fbe4 | bellard | return;
|
868 | 9a64fbe4 | bellard | case EXCP_BRANCH:
|
869 | 9a64fbe4 | bellard | /* Nothing to do */
|
870 | 9a64fbe4 | bellard | return;
|
871 | 9a64fbe4 | bellard | case EXCP_RFI:
|
872 | 9a64fbe4 | bellard | /* Restore user-mode state */
|
873 | a541f297 | bellard | tb_flush(env); |
874 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
875 | a541f297 | bellard | if (msr_pr == 1) |
876 | a541f297 | bellard | printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
877 | 9a64fbe4 | bellard | #endif
|
878 | 9a64fbe4 | bellard | return;
|
879 | 9a64fbe4 | bellard | store_current:
|
880 | 9a64fbe4 | bellard | /* SRR0 is set to current instruction */
|
881 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip - 4;
|
882 | 9a64fbe4 | bellard | break;
|
883 | 9a64fbe4 | bellard | store_next:
|
884 | 9a64fbe4 | bellard | /* SRR0 is set to next instruction */
|
885 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip; |
886 | 9a64fbe4 | bellard | break;
|
887 | 9a64fbe4 | bellard | } |
888 | 9a64fbe4 | bellard | env->spr[SRR1] = msr; |
889 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
890 | 9a64fbe4 | bellard | msr_pow = 0;
|
891 | 9a64fbe4 | bellard | msr_ee = 0;
|
892 | 9a64fbe4 | bellard | msr_pr = 0;
|
893 | 9a64fbe4 | bellard | msr_fp = 0;
|
894 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
895 | 9a64fbe4 | bellard | msr_se = 0;
|
896 | 9a64fbe4 | bellard | msr_be = 0;
|
897 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
898 | 9a64fbe4 | bellard | msr_ir = 0;
|
899 | 9a64fbe4 | bellard | msr_dr = 0;
|
900 | 9a64fbe4 | bellard | msr_ri = 0;
|
901 | 9a64fbe4 | bellard | msr_le = msr_ile; |
902 | 9a64fbe4 | bellard | /* Jump to handler */
|
903 | 9a64fbe4 | bellard | env->nip = excp << 8;
|
904 | 9a64fbe4 | bellard | env->exception_index = EXCP_NONE; |
905 | 9a64fbe4 | bellard | /* Invalidate all TLB as we may have changed translation mode */
|
906 | 1ef59d0a | bellard | tlb_flush(env, 1);
|
907 | 9a64fbe4 | bellard | /* ensure that no TB jump will be modified as
|
908 | 9a64fbe4 | bellard | the program flow was changed */
|
909 | 9a64fbe4 | bellard | #ifdef __sparc__
|
910 | 9a64fbe4 | bellard | tmp_T0 = 0;
|
911 | 9a64fbe4 | bellard | #else
|
912 | 9a64fbe4 | bellard | T0 = 0;
|
913 | 9a64fbe4 | bellard | #endif
|
914 | 9fddaa0c | bellard | env->exception_index = -1;
|
915 | fb0eaffc | bellard | } |
916 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |