root / target-ppc / op_helper.c @ 0443eaf6
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1 | 9a64fbe4 | bellard | /*
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2 | 9a64fbe4 | bellard | * PPC emulation helpers for qemu.
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3 | 9a64fbe4 | bellard | *
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4 | 9a64fbe4 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 9a64fbe4 | bellard | *
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6 | 9a64fbe4 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9a64fbe4 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9a64fbe4 | bellard | * License as published by the Free Software Foundation; either
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9 | 9a64fbe4 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9a64fbe4 | bellard | *
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11 | 9a64fbe4 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9a64fbe4 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9a64fbe4 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9a64fbe4 | bellard | * Lesser General Public License for more details.
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15 | 9a64fbe4 | bellard | *
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16 | 9a64fbe4 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 9a64fbe4 | bellard | * License along with this library; if not, write to the Free Software
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18 | 9a64fbe4 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 9a64fbe4 | bellard | */
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20 | 9a64fbe4 | bellard | #include <math.h> |
21 | 9a64fbe4 | bellard | #include "exec.h" |
22 | 9a64fbe4 | bellard | |
23 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
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24 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
25 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
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26 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
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27 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
28 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
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29 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
30 | 9a64fbe4 | bellard | #endif
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31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | /*****************************************************************************/
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33 | 9a64fbe4 | bellard | /* Exceptions processing helpers */
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34 | 9fddaa0c | bellard | void cpu_loop_exit(void) |
35 | 9a64fbe4 | bellard | { |
36 | 9fddaa0c | bellard | longjmp(env->jmp_env, 1);
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37 | 9a64fbe4 | bellard | } |
38 | 9a64fbe4 | bellard | |
39 | 9fddaa0c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
40 | 9a64fbe4 | bellard | { |
41 | 9fddaa0c | bellard | #if 0
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42 | 9fddaa0c | bellard | printf("Raise exception %3x code : %d\n", exception, error_code);
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43 | 9fddaa0c | bellard | #endif
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44 | 9fddaa0c | bellard | switch (exception) {
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45 | 9fddaa0c | bellard | case EXCP_EXTERNAL:
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46 | 9fddaa0c | bellard | case EXCP_DECR:
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47 | 9fddaa0c | bellard | printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
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48 | 9fddaa0c | bellard | if (msr_ee == 0) |
49 | 9fddaa0c | bellard | return;
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50 | 9fddaa0c | bellard | break;
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51 | 9fddaa0c | bellard | case EXCP_PROGRAM:
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52 | 9fddaa0c | bellard | if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0) |
53 | 9fddaa0c | bellard | return;
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54 | 9fddaa0c | bellard | break;
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55 | 9fddaa0c | bellard | default:
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56 | 9fddaa0c | bellard | break;
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57 | 9a64fbe4 | bellard | } |
58 | 9fddaa0c | bellard | env->exception_index = exception; |
59 | 9fddaa0c | bellard | env->error_code = error_code; |
60 | 9a64fbe4 | bellard | cpu_loop_exit(); |
61 | 9a64fbe4 | bellard | } |
62 | 9fddaa0c | bellard | |
63 | 9fddaa0c | bellard | void do_raise_exception (uint32_t exception)
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64 | 9fddaa0c | bellard | { |
65 | 9fddaa0c | bellard | do_raise_exception_err(exception, 0);
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66 | 9a64fbe4 | bellard | } |
67 | 9a64fbe4 | bellard | |
68 | 9a64fbe4 | bellard | /*****************************************************************************/
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69 | 9a64fbe4 | bellard | /* Helpers for "fat" micro operations */
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70 | 9a64fbe4 | bellard | /* Special registers load and store */
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71 | 9a64fbe4 | bellard | void do_load_cr (void) |
72 | 9a64fbe4 | bellard | { |
73 | 9a64fbe4 | bellard | T0 = (env->crf[0] << 28) | |
74 | 9a64fbe4 | bellard | (env->crf[1] << 24) | |
75 | 9a64fbe4 | bellard | (env->crf[2] << 20) | |
76 | 9a64fbe4 | bellard | (env->crf[3] << 16) | |
77 | 9a64fbe4 | bellard | (env->crf[4] << 12) | |
78 | 9a64fbe4 | bellard | (env->crf[5] << 8) | |
79 | 9a64fbe4 | bellard | (env->crf[6] << 4) | |
80 | 9a64fbe4 | bellard | (env->crf[7] << 0); |
81 | 9a64fbe4 | bellard | } |
82 | 9a64fbe4 | bellard | |
83 | 9a64fbe4 | bellard | void do_store_cr (uint32_t mask)
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84 | 9a64fbe4 | bellard | { |
85 | 9a64fbe4 | bellard | int i, sh;
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86 | 9a64fbe4 | bellard | |
87 | 9a64fbe4 | bellard | for (i = 0, sh = 7; i < 8; i++, sh --) { |
88 | 9a64fbe4 | bellard | if (mask & (1 << sh)) |
89 | 9a64fbe4 | bellard | env->crf[i] = (T0 >> (sh * 4)) & 0xF; |
90 | 9a64fbe4 | bellard | } |
91 | 9a64fbe4 | bellard | } |
92 | 9a64fbe4 | bellard | |
93 | 9a64fbe4 | bellard | void do_load_xer (void) |
94 | 9a64fbe4 | bellard | { |
95 | 9a64fbe4 | bellard | T0 = (xer_so << XER_SO) | |
96 | 9a64fbe4 | bellard | (xer_ov << XER_OV) | |
97 | 9a64fbe4 | bellard | (xer_ca << XER_CA) | |
98 | 9a64fbe4 | bellard | (xer_bc << XER_BC); |
99 | 9a64fbe4 | bellard | } |
100 | 9a64fbe4 | bellard | |
101 | 9a64fbe4 | bellard | void do_store_xer (void) |
102 | 9a64fbe4 | bellard | { |
103 | 9a64fbe4 | bellard | xer_so = (T0 >> XER_SO) & 0x01;
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104 | 9a64fbe4 | bellard | xer_ov = (T0 >> XER_OV) & 0x01;
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105 | 9a64fbe4 | bellard | xer_ca = (T0 >> XER_CA) & 0x01;
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106 | 9a64fbe4 | bellard | xer_bc = (T0 >> XER_BC) & 0x1f;
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107 | 9a64fbe4 | bellard | } |
108 | 9a64fbe4 | bellard | |
109 | 9a64fbe4 | bellard | void do_load_msr (void) |
110 | 9a64fbe4 | bellard | { |
111 | 9a64fbe4 | bellard | T0 = (msr_pow << MSR_POW) | |
112 | 9a64fbe4 | bellard | (msr_ile << MSR_ILE) | |
113 | 9a64fbe4 | bellard | (msr_ee << MSR_EE) | |
114 | 9a64fbe4 | bellard | (msr_pr << MSR_PR) | |
115 | 9a64fbe4 | bellard | (msr_fp << MSR_FP) | |
116 | 9a64fbe4 | bellard | (msr_me << MSR_ME) | |
117 | 9a64fbe4 | bellard | (msr_fe0 << MSR_FE0) | |
118 | 9a64fbe4 | bellard | (msr_se << MSR_SE) | |
119 | 9a64fbe4 | bellard | (msr_be << MSR_BE) | |
120 | 9a64fbe4 | bellard | (msr_fe1 << MSR_FE1) | |
121 | 9a64fbe4 | bellard | (msr_ip << MSR_IP) | |
122 | 9a64fbe4 | bellard | (msr_ir << MSR_IR) | |
123 | 9a64fbe4 | bellard | (msr_dr << MSR_DR) | |
124 | 9a64fbe4 | bellard | (msr_ri << MSR_RI) | |
125 | 9a64fbe4 | bellard | (msr_le << MSR_LE); |
126 | 9a64fbe4 | bellard | } |
127 | 9a64fbe4 | bellard | |
128 | 9a64fbe4 | bellard | void do_store_msr (void) |
129 | 9a64fbe4 | bellard | { |
130 | 4b3686fa | bellard | #if 1 // TRY |
131 | 9a64fbe4 | bellard | if (((T0 >> MSR_IR) & 0x01) != msr_ir || |
132 | 4b3686fa | bellard | ((T0 >> MSR_DR) & 0x01) != msr_dr ||
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133 | 4b3686fa | bellard | ((T0 >> MSR_PR) & 0x01) != msr_pr)
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134 | 4b3686fa | bellard | { |
135 | 9a64fbe4 | bellard | do_tlbia(); |
136 | 9a64fbe4 | bellard | } |
137 | 4b3686fa | bellard | #endif
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138 | 9a64fbe4 | bellard | msr_pow = (T0 >> MSR_POW) & 0x03;
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139 | 9a64fbe4 | bellard | msr_ile = (T0 >> MSR_ILE) & 0x01;
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140 | 9a64fbe4 | bellard | msr_ee = (T0 >> MSR_EE) & 0x01;
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141 | 9a64fbe4 | bellard | msr_pr = (T0 >> MSR_PR) & 0x01;
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142 | 9a64fbe4 | bellard | msr_fp = (T0 >> MSR_FP) & 0x01;
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143 | 9a64fbe4 | bellard | msr_me = (T0 >> MSR_ME) & 0x01;
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144 | 9a64fbe4 | bellard | msr_fe0 = (T0 >> MSR_FE0) & 0x01;
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145 | 9a64fbe4 | bellard | msr_se = (T0 >> MSR_SE) & 0x01;
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146 | 9a64fbe4 | bellard | msr_be = (T0 >> MSR_BE) & 0x01;
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147 | 9a64fbe4 | bellard | msr_fe1 = (T0 >> MSR_FE1) & 0x01;
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148 | 9a64fbe4 | bellard | msr_ip = (T0 >> MSR_IP) & 0x01;
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149 | 9a64fbe4 | bellard | msr_ir = (T0 >> MSR_IR) & 0x01;
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150 | 9a64fbe4 | bellard | msr_dr = (T0 >> MSR_DR) & 0x01;
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151 | 9a64fbe4 | bellard | msr_ri = (T0 >> MSR_RI) & 0x01;
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152 | 9a64fbe4 | bellard | msr_le = (T0 >> MSR_LE) & 0x01;
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153 | 9a64fbe4 | bellard | } |
154 | 9a64fbe4 | bellard | |
155 | 9a64fbe4 | bellard | /* shift right arithmetic helper */
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156 | 9a64fbe4 | bellard | void do_sraw (void) |
157 | 9a64fbe4 | bellard | { |
158 | 9a64fbe4 | bellard | int32_t ret; |
159 | 9a64fbe4 | bellard | |
160 | 9a64fbe4 | bellard | xer_ca = 0;
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161 | 9a64fbe4 | bellard | if (T1 & 0x20) { |
162 | 9a64fbe4 | bellard | ret = (-1) * (T0 >> 31); |
163 | 4b3686fa | bellard | if (ret < 0 && (T0 & ~0x80000000) != 0) |
164 | 9a64fbe4 | bellard | xer_ca = 1;
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165 | 4b3686fa | bellard | #if 1 // TRY |
166 | 4b3686fa | bellard | } else if (T1 == 0) { |
167 | 4b3686fa | bellard | ret = T0; |
168 | 4b3686fa | bellard | #endif
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169 | 9a64fbe4 | bellard | } else {
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170 | 9a64fbe4 | bellard | ret = (int32_t)T0 >> (T1 & 0x1f);
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171 | 9a64fbe4 | bellard | if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0) |
172 | 9a64fbe4 | bellard | xer_ca = 1;
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173 | 9a64fbe4 | bellard | } |
174 | 4b3686fa | bellard | T0 = ret; |
175 | 9a64fbe4 | bellard | } |
176 | 9a64fbe4 | bellard | |
177 | 9a64fbe4 | bellard | /* Floating point operations helpers */
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178 | 9a64fbe4 | bellard | void do_load_fpscr (void) |
179 | 9a64fbe4 | bellard | { |
180 | 9a64fbe4 | bellard | /* The 32 MSB of the target fpr are undefined.
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181 | 9a64fbe4 | bellard | * They'll be zero...
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182 | 9a64fbe4 | bellard | */
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183 | 9a64fbe4 | bellard | union {
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184 | 9a64fbe4 | bellard | double d;
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185 | 9a64fbe4 | bellard | struct {
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186 | 9a64fbe4 | bellard | uint32_t u[2];
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187 | 9a64fbe4 | bellard | } s; |
188 | 9a64fbe4 | bellard | } u; |
189 | 9a64fbe4 | bellard | int i;
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190 | 9a64fbe4 | bellard | |
191 | 9a64fbe4 | bellard | u.s.u[0] = 0; |
192 | 9a64fbe4 | bellard | u.s.u[1] = 0; |
193 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) |
194 | 9a64fbe4 | bellard | u.s.u[1] |= env->fpscr[i] << (4 * i); |
195 | 9a64fbe4 | bellard | FT0 = u.d; |
196 | 9a64fbe4 | bellard | } |
197 | 9a64fbe4 | bellard | |
198 | 9a64fbe4 | bellard | void do_store_fpscr (uint32_t mask)
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199 | 9a64fbe4 | bellard | { |
200 | 9a64fbe4 | bellard | /*
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201 | 9a64fbe4 | bellard | * We use only the 32 LSB of the incoming fpr
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202 | 9a64fbe4 | bellard | */
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203 | 9a64fbe4 | bellard | union {
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204 | 9a64fbe4 | bellard | double d;
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205 | 9a64fbe4 | bellard | struct {
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206 | 9a64fbe4 | bellard | uint32_t u[2];
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207 | 9a64fbe4 | bellard | } s; |
208 | 9a64fbe4 | bellard | } u; |
209 | 9a64fbe4 | bellard | int i;
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210 | 9a64fbe4 | bellard | |
211 | 9a64fbe4 | bellard | u.d = FT0; |
212 | 9a64fbe4 | bellard | if (mask & 0x80) |
213 | 9a64fbe4 | bellard | env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9); |
214 | 9a64fbe4 | bellard | for (i = 1; i < 7; i++) { |
215 | 9a64fbe4 | bellard | if (mask & (1 << (7 - i))) |
216 | 9a64fbe4 | bellard | env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF; |
217 | 9a64fbe4 | bellard | } |
218 | 9a64fbe4 | bellard | /* TODO: update FEX & VX */
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219 | 9a64fbe4 | bellard | /* Set rounding mode */
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220 | 9a64fbe4 | bellard | switch (env->fpscr[0] & 0x3) { |
221 | 9a64fbe4 | bellard | case 0: |
222 | 9a64fbe4 | bellard | /* Best approximation (round to nearest) */
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223 | 9a64fbe4 | bellard | fesetround(FE_TONEAREST); |
224 | 9a64fbe4 | bellard | break;
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225 | 9a64fbe4 | bellard | case 1: |
226 | 9a64fbe4 | bellard | /* Smaller magnitude (round toward zero) */
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227 | 9a64fbe4 | bellard | fesetround(FE_TOWARDZERO); |
228 | 9a64fbe4 | bellard | break;
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229 | 9a64fbe4 | bellard | case 2: |
230 | 9a64fbe4 | bellard | /* Round toward +infinite */
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231 | 9a64fbe4 | bellard | fesetround(FE_UPWARD); |
232 | 9a64fbe4 | bellard | break;
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233 | 9a64fbe4 | bellard | case 3: |
234 | 9a64fbe4 | bellard | /* Round toward -infinite */
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235 | 9a64fbe4 | bellard | fesetround(FE_DOWNWARD); |
236 | 9a64fbe4 | bellard | break;
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237 | 9a64fbe4 | bellard | } |
238 | 9a64fbe4 | bellard | } |
239 | 9a64fbe4 | bellard | |
240 | 9a64fbe4 | bellard | void do_fctiw (void) |
241 | 9a64fbe4 | bellard | { |
242 | 9a64fbe4 | bellard | union {
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243 | 9a64fbe4 | bellard | double d;
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244 | 9a64fbe4 | bellard | uint64_t i; |
245 | 9a64fbe4 | bellard | } *p = (void *)&FT1;
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246 | 9a64fbe4 | bellard | |
247 | 9a64fbe4 | bellard | if (FT0 > (double)0x7FFFFFFF) |
248 | 9a64fbe4 | bellard | p->i = 0x7FFFFFFFULL << 32; |
249 | 9a64fbe4 | bellard | else if (FT0 < -(double)0x80000000) |
250 | 9a64fbe4 | bellard | p->i = 0x80000000ULL << 32; |
251 | 9a64fbe4 | bellard | else
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252 | 9a64fbe4 | bellard | p->i = 0;
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253 | 9a64fbe4 | bellard | p->i |= (uint32_t)FT0; |
254 | 9a64fbe4 | bellard | FT0 = p->d; |
255 | 9a64fbe4 | bellard | } |
256 | 9a64fbe4 | bellard | |
257 | 9a64fbe4 | bellard | void do_fctiwz (void) |
258 | 9a64fbe4 | bellard | { |
259 | 9a64fbe4 | bellard | union {
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260 | 9a64fbe4 | bellard | double d;
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261 | 9a64fbe4 | bellard | uint64_t i; |
262 | 9a64fbe4 | bellard | } *p = (void *)&FT1;
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263 | 9a64fbe4 | bellard | int cround = fegetround();
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264 | 9a64fbe4 | bellard | |
265 | 9a64fbe4 | bellard | fesetround(FE_TOWARDZERO); |
266 | 9a64fbe4 | bellard | if (FT0 > (double)0x7FFFFFFF) |
267 | 9a64fbe4 | bellard | p->i = 0x7FFFFFFFULL << 32; |
268 | 9a64fbe4 | bellard | else if (FT0 < -(double)0x80000000) |
269 | 9a64fbe4 | bellard | p->i = 0x80000000ULL << 32; |
270 | 9a64fbe4 | bellard | else
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271 | 9a64fbe4 | bellard | p->i = 0;
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272 | 9a64fbe4 | bellard | p->i |= (uint32_t)FT0; |
273 | 9a64fbe4 | bellard | FT0 = p->d; |
274 | 9a64fbe4 | bellard | fesetround(cround); |
275 | 9a64fbe4 | bellard | } |
276 | 9a64fbe4 | bellard | |
277 | 4b3686fa | bellard | void do_fnmadd (void) |
278 | 4b3686fa | bellard | { |
279 | 4b3686fa | bellard | FT0 = -((FT0 * FT1) + FT2); |
280 | 4b3686fa | bellard | } |
281 | 4b3686fa | bellard | |
282 | 4b3686fa | bellard | void do_fnmsub (void) |
283 | 4b3686fa | bellard | { |
284 | 4b3686fa | bellard | FT0 = -((FT0 * FT1) - FT2); |
285 | 4b3686fa | bellard | } |
286 | 4b3686fa | bellard | |
287 | 1ef59d0a | bellard | void do_fnmadds (void) |
288 | 1ef59d0a | bellard | { |
289 | 4b3686fa | bellard | FT0 = -((FTS0 * FTS1) + FTS2); |
290 | 1ef59d0a | bellard | } |
291 | 1ef59d0a | bellard | |
292 | 1ef59d0a | bellard | void do_fnmsubs (void) |
293 | 1ef59d0a | bellard | { |
294 | 4b3686fa | bellard | FT0 = -((FTS0 * FTS1) - FTS2); |
295 | 1ef59d0a | bellard | } |
296 | 1ef59d0a | bellard | |
297 | 9a64fbe4 | bellard | void do_fsqrt (void) |
298 | 9a64fbe4 | bellard | { |
299 | 9a64fbe4 | bellard | FT0 = sqrt(FT0); |
300 | 9a64fbe4 | bellard | } |
301 | 9a64fbe4 | bellard | |
302 | 9a64fbe4 | bellard | void do_fsqrts (void) |
303 | 9a64fbe4 | bellard | { |
304 | 9a64fbe4 | bellard | FT0 = (float)sqrt((float)FT0); |
305 | 9a64fbe4 | bellard | } |
306 | 9a64fbe4 | bellard | |
307 | 9a64fbe4 | bellard | void do_fres (void) |
308 | 9a64fbe4 | bellard | { |
309 | 9a64fbe4 | bellard | FT0 = 1.0 / FT0; |
310 | 9a64fbe4 | bellard | } |
311 | 9a64fbe4 | bellard | |
312 | 9a64fbe4 | bellard | void do_fsqrte (void) |
313 | 9a64fbe4 | bellard | { |
314 | 9a64fbe4 | bellard | FT0 = 1.0 / sqrt(FT0); |
315 | 9a64fbe4 | bellard | } |
316 | 9a64fbe4 | bellard | |
317 | 9a64fbe4 | bellard | void do_fsel (void) |
318 | 9a64fbe4 | bellard | { |
319 | 9a64fbe4 | bellard | if (FT0 >= 0) |
320 | 9a64fbe4 | bellard | FT0 = FT2; |
321 | 9a64fbe4 | bellard | else
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322 | 9a64fbe4 | bellard | FT0 = FT1; |
323 | 9a64fbe4 | bellard | } |
324 | 9a64fbe4 | bellard | |
325 | 9a64fbe4 | bellard | void do_fcmpu (void) |
326 | 9a64fbe4 | bellard | { |
327 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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328 | 9a64fbe4 | bellard | T0 = 0x01;
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329 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
330 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
331 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
332 | 9a64fbe4 | bellard | T0 = 0x08;
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333 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
334 | 9a64fbe4 | bellard | T0 = 0x04;
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335 | 9a64fbe4 | bellard | } else {
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336 | 9a64fbe4 | bellard | T0 = 0x02;
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337 | 9a64fbe4 | bellard | } |
338 | 4b3686fa | bellard | env->fpscr[3] = T0;
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339 | 9a64fbe4 | bellard | } |
340 | 9a64fbe4 | bellard | |
341 | 9a64fbe4 | bellard | void do_fcmpo (void) |
342 | 9a64fbe4 | bellard | { |
343 | 9a64fbe4 | bellard | env->fpscr[4] &= ~0x1; |
344 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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345 | 9a64fbe4 | bellard | T0 = 0x01;
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346 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
347 | 9a64fbe4 | bellard | /* I don't know how to test "quiet" nan... */
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348 | 9a64fbe4 | bellard | if (0 /* || ! quiet_nan(...) */) { |
349 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
350 | 9a64fbe4 | bellard | if (!(env->fpscr[1] & 0x8)) |
351 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
352 | 9a64fbe4 | bellard | } else {
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353 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
354 | 9a64fbe4 | bellard | } |
355 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
356 | 9a64fbe4 | bellard | T0 = 0x08;
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357 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
358 | 9a64fbe4 | bellard | T0 = 0x04;
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359 | 9a64fbe4 | bellard | } else {
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360 | 9a64fbe4 | bellard | T0 = 0x02;
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361 | 9a64fbe4 | bellard | } |
362 | 4b3686fa | bellard | env->fpscr[3] = T0;
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363 | 9a64fbe4 | bellard | } |
364 | 9a64fbe4 | bellard | |
365 | 9a64fbe4 | bellard | void do_fabs (void) |
366 | 9a64fbe4 | bellard | { |
367 | 9a64fbe4 | bellard | FT0 = fabsl(FT0); |
368 | 9a64fbe4 | bellard | } |
369 | 9a64fbe4 | bellard | |
370 | 9a64fbe4 | bellard | void do_fnabs (void) |
371 | 9a64fbe4 | bellard | { |
372 | 9a64fbe4 | bellard | FT0 = -fabsl(FT0); |
373 | 9a64fbe4 | bellard | } |
374 | 9a64fbe4 | bellard | |
375 | 9a64fbe4 | bellard | /* Instruction cache invalidation helper */
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376 | 985a19d6 | bellard | #define ICACHE_LINE_SIZE 32 |
377 | 985a19d6 | bellard | |
378 | 4b3686fa | bellard | void do_check_reservation (void) |
379 | 4b3686fa | bellard | { |
380 | 18fba28c | bellard | if ((env->reserve & ~0x03) == T0) |
381 | 4b3686fa | bellard | env->reserve = -1;
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382 | 4b3686fa | bellard | } |
383 | 4b3686fa | bellard | |
384 | 9a64fbe4 | bellard | void do_icbi (void) |
385 | 9a64fbe4 | bellard | { |
386 | 985a19d6 | bellard | /* Invalidate one cache line */
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387 | 985a19d6 | bellard | T0 &= ~(ICACHE_LINE_SIZE - 1);
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388 | 985a19d6 | bellard | tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE); |
389 | 9a64fbe4 | bellard | } |
390 | 9a64fbe4 | bellard | |
391 | 9a64fbe4 | bellard | /* TLB invalidation helpers */
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392 | 9a64fbe4 | bellard | void do_tlbia (void) |
393 | 9a64fbe4 | bellard | { |
394 | ad081323 | bellard | tlb_flush(env, 1);
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395 | 9a64fbe4 | bellard | } |
396 | 9a64fbe4 | bellard | |
397 | 9a64fbe4 | bellard | void do_tlbie (void) |
398 | 9a64fbe4 | bellard | { |
399 | 9a64fbe4 | bellard | tlb_flush_page(env, T0); |
400 | 9a64fbe4 | bellard | } |
401 | 9a64fbe4 | bellard | |
402 | 4b3686fa | bellard | void do_store_sr (uint32_t srnum)
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403 | 4b3686fa | bellard | { |
404 | 4b3686fa | bellard | #if defined (DEBUG_OP)
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405 | 4b3686fa | bellard | dump_store_sr(srnum); |
406 | 4b3686fa | bellard | #endif
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407 | 4b3686fa | bellard | #if 0 // TRY
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408 | 4b3686fa | bellard | {
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409 | 4b3686fa | bellard | uint32_t base, page;
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410 | 4b3686fa | bellard |
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411 | 4b3686fa | bellard | base = srnum << 28;
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412 | 4b3686fa | bellard | for (page = base; page != base + 0x100000000; page += 0x1000)
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413 | 4b3686fa | bellard | tlb_flush_page(env, page);
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414 | 4b3686fa | bellard | }
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415 | 4b3686fa | bellard | #else
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416 | 4b3686fa | bellard | tlb_flush(env, 1);
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417 | 4b3686fa | bellard | #endif
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418 | 4b3686fa | bellard | env->sr[srnum] = T0; |
419 | 4b3686fa | bellard | } |
420 | 4b3686fa | bellard | |
421 | 4b3686fa | bellard | /* For BATs, we may not invalidate any TLBs if the change is only on
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422 | 4b3686fa | bellard | * protection bits for user mode.
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423 | 4b3686fa | bellard | */
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424 | 4b3686fa | bellard | void do_store_ibat (int ul, int nr) |
425 | 4b3686fa | bellard | { |
426 | 4b3686fa | bellard | #if defined (DEBUG_OP)
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427 | 4b3686fa | bellard | dump_store_ibat(ul, nr); |
428 | 4b3686fa | bellard | #endif
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429 | 4b3686fa | bellard | #if 0 // TRY
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430 | 4b3686fa | bellard | {
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431 | 4b3686fa | bellard | uint32_t base, length, page;
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432 | 4b3686fa | bellard | |
433 | 4b3686fa | bellard | base = env->IBAT[0][nr];
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434 | 4b3686fa | bellard | length = (((base >> 2) & 0x000007FF) + 1) << 17;
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435 | 4b3686fa | bellard | base &= 0xFFFC0000;
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436 | 4b3686fa | bellard | for (page = base; page != base + length; page += 0x1000)
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437 | 4b3686fa | bellard | tlb_flush_page(env, page);
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438 | 4b3686fa | bellard | }
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439 | 4b3686fa | bellard | #else
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440 | 4b3686fa | bellard | tlb_flush(env, 1);
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441 | 4b3686fa | bellard | #endif
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442 | 4b3686fa | bellard | env->IBAT[ul][nr] = T0; |
443 | 4b3686fa | bellard | } |
444 | 4b3686fa | bellard | |
445 | 4b3686fa | bellard | void do_store_dbat (int ul, int nr) |
446 | 4b3686fa | bellard | { |
447 | 4b3686fa | bellard | #if defined (DEBUG_OP)
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448 | 4b3686fa | bellard | dump_store_dbat(ul, nr); |
449 | 4b3686fa | bellard | #endif
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450 | 4b3686fa | bellard | #if 0 // TRY
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451 | 4b3686fa | bellard | {
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452 | 4b3686fa | bellard | uint32_t base, length, page;
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453 | 4b3686fa | bellard | base = env->DBAT[0][nr];
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454 | 4b3686fa | bellard | length = (((base >> 2) & 0x000007FF) + 1) << 17;
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455 | 4b3686fa | bellard | base &= 0xFFFC0000;
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456 | 4b3686fa | bellard | for (page = base; page != base + length; page += 0x1000)
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457 | 4b3686fa | bellard | tlb_flush_page(env, page);
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458 | 4b3686fa | bellard | }
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459 | 4b3686fa | bellard | #else
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460 | 4b3686fa | bellard | tlb_flush(env, 1);
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461 | 4b3686fa | bellard | #endif
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462 | 4b3686fa | bellard | env->DBAT[ul][nr] = T0; |
463 | 4b3686fa | bellard | } |
464 | 4b3686fa | bellard | |
465 | 9a64fbe4 | bellard | /*****************************************************************************/
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466 | 9a64fbe4 | bellard | /* Special helpers for debug */
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467 | a541f297 | bellard | void dump_state (void) |
468 | a541f297 | bellard | { |
469 | 7fe48483 | bellard | // cpu_dump_state(env, stdout, fprintf, 0);
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470 | a541f297 | bellard | } |
471 | a541f297 | bellard | |
472 | 9a64fbe4 | bellard | void dump_rfi (void) |
473 | 9a64fbe4 | bellard | { |
474 | 9a64fbe4 | bellard | #if 0
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475 | 4b3686fa | bellard | printf("Return from interrupt => 0x%08x\n", env->nip);
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476 | 7fe48483 | bellard | // cpu_dump_state(env, stdout, fprintf, 0);
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477 | 9a64fbe4 | bellard | #endif
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478 | 9a64fbe4 | bellard | } |
479 | 9a64fbe4 | bellard | |
480 | 9a64fbe4 | bellard | void dump_store_sr (int srnum) |
481 | 9a64fbe4 | bellard | { |
482 | 9a64fbe4 | bellard | #if 0
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483 | 9a64fbe4 | bellard | printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
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484 | 9a64fbe4 | bellard | #endif
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485 | 9a64fbe4 | bellard | } |
486 | 9a64fbe4 | bellard | |
487 | 9a64fbe4 | bellard | static void _dump_store_bat (char ID, int ul, int nr) |
488 | 9a64fbe4 | bellard | { |
489 | 9a64fbe4 | bellard | printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
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490 | 9a64fbe4 | bellard | ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip); |
491 | 9a64fbe4 | bellard | } |
492 | 9a64fbe4 | bellard | |
493 | 9a64fbe4 | bellard | void dump_store_ibat (int ul, int nr) |
494 | 9a64fbe4 | bellard | { |
495 | 9a64fbe4 | bellard | _dump_store_bat('I', ul, nr);
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496 | 9a64fbe4 | bellard | } |
497 | 9a64fbe4 | bellard | |
498 | 9a64fbe4 | bellard | void dump_store_dbat (int ul, int nr) |
499 | 9a64fbe4 | bellard | { |
500 | 9a64fbe4 | bellard | _dump_store_bat('D', ul, nr);
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501 | 9a64fbe4 | bellard | } |
502 | 9a64fbe4 | bellard | |
503 | 9a64fbe4 | bellard | void dump_store_tb (int ul) |
504 | 9a64fbe4 | bellard | { |
505 | 9a64fbe4 | bellard | printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0); |
506 | 9a64fbe4 | bellard | } |
507 | 9a64fbe4 | bellard | |
508 | 9a64fbe4 | bellard | void dump_update_tb(uint32_t param)
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509 | 9a64fbe4 | bellard | { |
510 | 9a64fbe4 | bellard | #if 0
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511 | 9a64fbe4 | bellard | printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
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512 | 9a64fbe4 | bellard | #endif
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513 | 9a64fbe4 | bellard | } |