root / target-ppc / op_mem.h @ 0443eaf6
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1 | 9a64fbe4 | bellard | /* External helpers */
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2 | 9a64fbe4 | bellard | void glue(do_lsw, MEMSUFFIX) (int dst); |
3 | 9a64fbe4 | bellard | void glue(do_stsw, MEMSUFFIX) (int src); |
4 | 9a64fbe4 | bellard | |
5 | 0fa85d43 | bellard | static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA) |
6 | 9a64fbe4 | bellard | { |
7 | ac9eb073 | bellard | uint16_t tmp = glue(lduw, MEMSUFFIX)(EA); |
8 | 9a64fbe4 | bellard | return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8); |
9 | 9a64fbe4 | bellard | } |
10 | 9a64fbe4 | bellard | |
11 | 0fa85d43 | bellard | static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA) |
12 | 9a64fbe4 | bellard | { |
13 | ac9eb073 | bellard | uint32_t tmp = glue(ldl, MEMSUFFIX)(EA); |
14 | 9a64fbe4 | bellard | return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) | |
15 | 9a64fbe4 | bellard | ((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24); |
16 | 9a64fbe4 | bellard | } |
17 | 9a64fbe4 | bellard | |
18 | 0fa85d43 | bellard | static inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t data) |
19 | 9a64fbe4 | bellard | { |
20 | 9a64fbe4 | bellard | uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8); |
21 | ac9eb073 | bellard | glue(stw, MEMSUFFIX)(EA, tmp); |
22 | 9a64fbe4 | bellard | } |
23 | 9a64fbe4 | bellard | |
24 | 0fa85d43 | bellard | static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data) |
25 | 9a64fbe4 | bellard | { |
26 | 9a64fbe4 | bellard | uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) | |
27 | 9a64fbe4 | bellard | ((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24); |
28 | ac9eb073 | bellard | glue(stl, MEMSUFFIX)(EA, tmp); |
29 | 9a64fbe4 | bellard | } |
30 | 9a64fbe4 | bellard | |
31 | 9a64fbe4 | bellard | /*** Integer load ***/
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32 | 9a64fbe4 | bellard | #define PPC_LD_OP(name, op) \
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33 | 9a64fbe4 | bellard | PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
34 | 9a64fbe4 | bellard | { \ |
35 | 0fa85d43 | bellard | T1 = glue(op, MEMSUFFIX)(T0); \ |
36 | 9a64fbe4 | bellard | RETURN(); \ |
37 | 9a64fbe4 | bellard | } |
38 | 9a64fbe4 | bellard | |
39 | 9a64fbe4 | bellard | #define PPC_ST_OP(name, op) \
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40 | 9a64fbe4 | bellard | PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
41 | 9a64fbe4 | bellard | { \ |
42 | 0fa85d43 | bellard | glue(op, MEMSUFFIX)(T0, T1); \ |
43 | 9a64fbe4 | bellard | RETURN(); \ |
44 | 9a64fbe4 | bellard | } |
45 | 9a64fbe4 | bellard | |
46 | ac9eb073 | bellard | PPC_LD_OP(bz, ldub); |
47 | ac9eb073 | bellard | PPC_LD_OP(ha, ldsw); |
48 | ac9eb073 | bellard | PPC_LD_OP(hz, lduw); |
49 | ac9eb073 | bellard | PPC_LD_OP(wz, ldl); |
50 | 9a64fbe4 | bellard | |
51 | 9a64fbe4 | bellard | /*** Integer store ***/
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52 | ac9eb073 | bellard | PPC_ST_OP(b, stb); |
53 | ac9eb073 | bellard | PPC_ST_OP(h, stw); |
54 | ac9eb073 | bellard | PPC_ST_OP(w, stl); |
55 | 9a64fbe4 | bellard | |
56 | 9a64fbe4 | bellard | /*** Integer load and store with byte reverse ***/
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57 | ac9eb073 | bellard | PPC_LD_OP(hbr, ld16r); |
58 | ac9eb073 | bellard | PPC_LD_OP(wbr, ld32r); |
59 | ac9eb073 | bellard | PPC_ST_OP(hbr, st16r); |
60 | ac9eb073 | bellard | PPC_ST_OP(wbr, st32r); |
61 | 9a64fbe4 | bellard | |
62 | 9a64fbe4 | bellard | /*** Integer load and store multiple ***/
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63 | 9a64fbe4 | bellard | PPC_OP(glue(lmw, MEMSUFFIX)) |
64 | 9a64fbe4 | bellard | { |
65 | 9a64fbe4 | bellard | int dst = PARAM(1); |
66 | 9a64fbe4 | bellard | |
67 | 9a64fbe4 | bellard | for (; dst < 32; dst++, T0 += 4) { |
68 | 0fa85d43 | bellard | ugpr(dst) = glue(ldl, MEMSUFFIX)(T0); |
69 | 9a64fbe4 | bellard | } |
70 | 9a64fbe4 | bellard | RETURN(); |
71 | 9a64fbe4 | bellard | } |
72 | 9a64fbe4 | bellard | |
73 | 9a64fbe4 | bellard | PPC_OP(glue(stmw, MEMSUFFIX)) |
74 | 9a64fbe4 | bellard | { |
75 | 9a64fbe4 | bellard | int src = PARAM(1); |
76 | 9a64fbe4 | bellard | |
77 | 9a64fbe4 | bellard | for (; src < 32; src++, T0 += 4) { |
78 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, ugpr(src)); |
79 | 9a64fbe4 | bellard | } |
80 | 9a64fbe4 | bellard | RETURN(); |
81 | 9a64fbe4 | bellard | } |
82 | 9a64fbe4 | bellard | |
83 | 9a64fbe4 | bellard | /*** Integer load and store strings ***/
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84 | 9a64fbe4 | bellard | PPC_OP(glue(lswi, MEMSUFFIX)) |
85 | 9a64fbe4 | bellard | { |
86 | 9a64fbe4 | bellard | glue(do_lsw, MEMSUFFIX)(PARAM(1));
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87 | 9a64fbe4 | bellard | RETURN(); |
88 | 9a64fbe4 | bellard | } |
89 | 9a64fbe4 | bellard | |
90 | 9a64fbe4 | bellard | /* PPC32 specification says we must generate an exception if
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91 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
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92 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
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93 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
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94 | 9a64fbe4 | bellard | */
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95 | 9a64fbe4 | bellard | PPC_OP(glue(lswx, MEMSUFFIX)) |
96 | 9a64fbe4 | bellard | { |
97 | 9a64fbe4 | bellard | if (T1 > 0) { |
98 | 9a64fbe4 | bellard | if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) || |
99 | 9a64fbe4 | bellard | (PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) { |
100 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
101 | 9a64fbe4 | bellard | } else {
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102 | 9a64fbe4 | bellard | glue(do_lsw, MEMSUFFIX)(PARAM(1));
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103 | 9a64fbe4 | bellard | } |
104 | 9a64fbe4 | bellard | } |
105 | 9a64fbe4 | bellard | RETURN(); |
106 | 9a64fbe4 | bellard | } |
107 | 9a64fbe4 | bellard | |
108 | 9a64fbe4 | bellard | PPC_OP(glue(stsw, MEMSUFFIX)) |
109 | 9a64fbe4 | bellard | { |
110 | 9a64fbe4 | bellard | glue(do_stsw, MEMSUFFIX)(PARAM(1));
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111 | 9a64fbe4 | bellard | RETURN(); |
112 | 9a64fbe4 | bellard | } |
113 | 9a64fbe4 | bellard | |
114 | 9a64fbe4 | bellard | /*** Floating-point store ***/
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115 | 9a64fbe4 | bellard | #define PPC_STF_OP(name, op) \
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116 | 9a64fbe4 | bellard | PPC_OP(glue(glue(st, name), MEMSUFFIX)) \ |
117 | 9a64fbe4 | bellard | { \ |
118 | 0fa85d43 | bellard | glue(op, MEMSUFFIX)(T0, FT1); \ |
119 | 9a64fbe4 | bellard | RETURN(); \ |
120 | 9a64fbe4 | bellard | } |
121 | 9a64fbe4 | bellard | |
122 | 9a64fbe4 | bellard | PPC_STF_OP(fd, stfq); |
123 | 9a64fbe4 | bellard | PPC_STF_OP(fs, stfl); |
124 | 9a64fbe4 | bellard | |
125 | 9a64fbe4 | bellard | /*** Floating-point load ***/
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126 | 9a64fbe4 | bellard | #define PPC_LDF_OP(name, op) \
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127 | 9a64fbe4 | bellard | PPC_OP(glue(glue(l, name), MEMSUFFIX)) \ |
128 | 9a64fbe4 | bellard | { \ |
129 | 0fa85d43 | bellard | FT1 = glue(op, MEMSUFFIX)(T0); \ |
130 | 9a64fbe4 | bellard | RETURN(); \ |
131 | 9a64fbe4 | bellard | } |
132 | 9a64fbe4 | bellard | |
133 | 9a64fbe4 | bellard | PPC_LDF_OP(fd, ldfq); |
134 | 9a64fbe4 | bellard | PPC_LDF_OP(fs, ldfl); |
135 | 9a64fbe4 | bellard | |
136 | 985a19d6 | bellard | /* Load and set reservation */
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137 | 985a19d6 | bellard | PPC_OP(glue(lwarx, MEMSUFFIX)) |
138 | 985a19d6 | bellard | { |
139 | 985a19d6 | bellard | if (T0 & 0x03) { |
140 | 9fddaa0c | bellard | do_raise_exception(EXCP_ALIGN); |
141 | 985a19d6 | bellard | } else {
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142 | 0fa85d43 | bellard | T1 = glue(ldl, MEMSUFFIX)(T0); |
143 | 28fbe299 | bellard | regs->reserve = T0; |
144 | 985a19d6 | bellard | } |
145 | 985a19d6 | bellard | RETURN(); |
146 | 985a19d6 | bellard | } |
147 | 985a19d6 | bellard | |
148 | 9a64fbe4 | bellard | /* Store with reservation */
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149 | 9a64fbe4 | bellard | PPC_OP(glue(stwcx, MEMSUFFIX)) |
150 | 9a64fbe4 | bellard | { |
151 | 9a64fbe4 | bellard | if (T0 & 0x03) { |
152 | 9fddaa0c | bellard | do_raise_exception(EXCP_ALIGN); |
153 | 9a64fbe4 | bellard | } else {
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154 | 9a64fbe4 | bellard | if (regs->reserve != T0) {
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155 | 9a64fbe4 | bellard | env->crf[0] = xer_ov;
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156 | 9a64fbe4 | bellard | } else {
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157 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
158 | 9a64fbe4 | bellard | env->crf[0] = xer_ov | 0x02; |
159 | 9a64fbe4 | bellard | } |
160 | 9a64fbe4 | bellard | } |
161 | 9a64fbe4 | bellard | regs->reserve = 0;
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162 | 9a64fbe4 | bellard | RETURN(); |
163 | 9a64fbe4 | bellard | } |
164 | 9a64fbe4 | bellard | |
165 | 9a64fbe4 | bellard | PPC_OP(glue(dcbz, MEMSUFFIX)) |
166 | 9a64fbe4 | bellard | { |
167 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x00, 0); |
168 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x04, 0); |
169 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x08, 0); |
170 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x0C, 0); |
171 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x10, 0); |
172 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x14, 0); |
173 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x18, 0); |
174 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0 + 0x1C, 0); |
175 | 9a64fbe4 | bellard | RETURN(); |
176 | 9a64fbe4 | bellard | } |
177 | 9a64fbe4 | bellard | |
178 | 9a64fbe4 | bellard | /* External access */
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179 | 9a64fbe4 | bellard | PPC_OP(glue(eciwx, MEMSUFFIX)) |
180 | 9a64fbe4 | bellard | { |
181 | 0fa85d43 | bellard | T1 = glue(ldl, MEMSUFFIX)(T0); |
182 | 9a64fbe4 | bellard | RETURN(); |
183 | 9a64fbe4 | bellard | } |
184 | 9a64fbe4 | bellard | |
185 | 9a64fbe4 | bellard | PPC_OP(glue(ecowx, MEMSUFFIX)) |
186 | 9a64fbe4 | bellard | { |
187 | 0fa85d43 | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
188 | 9a64fbe4 | bellard | RETURN(); |
189 | 9a64fbe4 | bellard | } |
190 | 9a64fbe4 | bellard | |
191 | 9a64fbe4 | bellard | #undef MEMSUFFIX |