Sparse fixes: truncation by cast
Fix Sparse warnings about constant truncation caused by cast
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6737 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: remove obsolete old_op_count profiler field
Since we don't generate any "old op" anymore, the old_op_countis unneeded.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6614 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to callee save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to calle save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
Add "static"
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6588 c046a42c-6fe2-441c-8c8c-71466251a162
Fix DEBUG_TCGV compile error.
Don't call TCGV_LOW on arg2. This section of code falls under
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
R13 is reserved for small data area pointer by SVR4 PPC ABI
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Remove all traces of powerpc
According to $GCC/gcc/config/rs6000/rs6000-c.c _ARCH_PPC is theubiquitous define which should be used to test whether gcc targetsPowerPC, on 64bit platforms _ARCH_PPC64 will be also defined.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6301 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: remove tcg_global_reg2_new_hack()
This patch removes the unused tcg_global_reg2_new_hack() function, whichwas added in r4438 to work around a register shortage problem regardingdyngen. The only ever user of this function was removed in r4577.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>...
TCG: Fix documentation of qemu_ld/st ops
The functions defined in tcg/tcg-op.h have no _i32 or _i64 suffix,qemu_ld64 and qemu_st64 were missing from the list, and there areno 'plain' qemu_ld/qemu_st ops.
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: kill two warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6029 c046a42c-6fe2-441c-8c8c-71466251a162
TCG x86/x86-64: use move with zero-extend for loads/stores
Starting with version 4.3, gcc returns the result of a function inrax/eax/ax/al instead of rax/eax, depending of the return type. Asa consequence we should use a zero extend moe in TCG loads/stores....
Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TARGET_LONG_BITS warning in TCG
Looking at tcg/tcg.c:828, the bug that the warning indicated would show up asincorrect PC shown in log, only on 32 bit big endian host emulating a 64 bittarget, -d op flag enabled. Now that dyngen is gone, the patch can be applied....
Introduce and use cache-utils.[ch]
Thanks to Segher Boessenkool and Holis Blanchard.
AIX and Darwin cache inquiry:http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html
Auxiliary vectors:http://manugarg.googlepages.com/aboutelfauxiliaryvectors
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 64-bit targets compilation on ARM host.
Only fix compilation, probably doesn't run.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
Some cleanups after dyngen removal
1. hostregs_helper.h: fix comment2. translate-all.c: rename dyngen_code(_search_pc) to tcg_gen_code(_search_pc)3. tcg.c: - rename dyngen_table_op_count to tcg_table_op_count - no need to generate a log of dyngen ops generated...
this patch removes some now unused things after dyngen removal.
1. dyngen-exec.h: op_param, op _jmp and some associated macros are now unused;2. Makefile.target: tcg-dyngen is not needed anymore2. tcg/tcg-op.h, tcg/tcg-opc.h: gen-op.h is dead...
Some fixes for TCG debugging
This fixes a few things after Paul's improvements for TCG debugging:
- change TCGv_i64 field name to something different from TCGv_i32 - fix things in tcg that the above change made visible.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
Remove a few dyngen and dyngen related code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5914 c046a42c-6fe2-441c-8c8c-71466251a162
arm: Don't potentially overwrite input registers in add2, sub2.
According to malc TCG will often genereate an add2/sub2/mul2 with lowhalf of the output in the same register as high half of one of theinputs, so account for that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
Don't rely on ARM tcg_out_goto() generating just a single insn.
Otherwise when tb_exit generates a jump beyond the pc-relative range,tcg_out_goto() spans two/three instructions and we load the tb returnvalue from a wrong address. This is #ifdefed out currently because...
Use libgcc __clear_cache to clean icache, when available.
Calling the clear cache syscall directly generates an illegal instructionon some (armv4) kernels.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
Fix alignment of 64bit args
Unbreaks sparc and mips64el. (Reported by Thiemo Seufer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5815 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary AIX support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
Fix alignment problem with some 64bit load/store instructions
LD/STD/LWA require displacement to be multiple of 4, providetcg_out_ldsta which checks the supplied displacement and fallsback on indexed variant when the check fails. All uses ofLD/STD/LWA outside of tcg_out_ldst appear to be safe....
Mention output overlaps.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5619 c046a42c-6fe2-441c-8c8c-71466251a162
Fix rotri_i64 typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5609 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5607 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-op.h: reorder _i64 instructions common to 32- and 64-bit targets
Use the same order as the _i32 version (pure code move). Suggested byLaurent Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5606 c046a42c-6fe2-441c-8c8c-71466251a162
64-bit target subfi fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5602 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: add a subfi wrapper
Add a subfi (subtract from immediate) wrapper, useful for the PPC target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5599 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: _i64 TCG immediate instructions cleanup
Move addi_i64, muli_i64 and subi_i64 out of #if TCG_TARGET_REG_BITSas both implementations are strictly identical. Use the sameoptimisation (ie when imm == 0) for addi_i64 and subi_64 than the32-bit version....
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: add tcg_const_local_tl()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5504 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: add logical operations found on alpha and powerpc processors
- andc_i32/i64 t0, t1, t2- eqv_i32/i64 t0, t1, t2- nand_i32/i64 t0, t1, t2- nor_i32/i64 t0, t1, t2- orc_i32/i64 t0, t1, t2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5501 c046a42c-6fe2-441c-8c8c-71466251a162
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Optimize 64 bit bswap
Use rldimi instead of rldicr/or pair, saves us one instruction.Suggested by Hollis Blanchard.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tcg_gen_concat32_i64 on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5306 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid clobbering input register in qemu_ld64+bswap+useronly case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat32_i64 and concat_tl_i64 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5282 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
Display TCGCond name in tcg dumper (original patch by Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5208 c046a42c-6fe2-441c-8c8c-71466251a162
Use 64 bit loads for tlb addend only if addend size is 64 bits
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
Fix stack alignment on Sparc32 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5202 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: Use x86-64 zero extension instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5180 c046a42c-6fe2-441c-8c8c-71466251a162
Implement TCG sign extension ops for x86-64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5179 c046a42c-6fe2-441c-8c8c-71466251a162
Revert "TCG: enable debug"
This reverts commit 5166, commited by error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5169 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: enable debug
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5166 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Relax qemu_ld/st constraints for !SOFTMMU case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162
Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162
Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wmissing-prototypes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5022 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 64 bit constant generation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 32 bit address overflow
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
Restore AREG0 after calls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc code generator update (fix qemu_ld & qemu_st)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc code generator update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary MacOS X on PPC32 support
Big thanks to BlueSwirl for Sparc failure analysis.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64
Avoids nasty warnings about flush_icache_range from gcc4 and inabilityto compile [cpu-]exec.c with gcc3 and -O, also the function is muchtoo large to be candidate for inlining anyway.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
Immediate versions of some operations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162
Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
Set the L field of CMP[L][I] when dealing with 64 bit quantities
This (along with previous 2 commits) makes X86_64 work on ppc64 too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162
Fix preprocessor guard condition
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162
Remove leftover from previous way to load 64 bit constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4958 c046a42c-6fe2-441c-8c8c-71466251a162
Special-case some paths inside tcg_out_tlb_read
a. Use 32bit arithmetics in TARGET_LONG_BITS 32 caseb. Optimize byte access case in TARGET_LONG_BITS 64 case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4955 c046a42c-6fe2-441c-8c8c-71466251a162
Fix the opcode value of LWA
That should teach one to not blindly trust documentation that will(out of the blue) use decimal and binary representation for numbers inthe same chart for no apparent reason and without any prefixes, sigh..
Unbreaks MIPS.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4954 c046a42c-6fe2-441c-8c8c-71466251a162
Try to avoid glibc global register mangling, again
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
Relax memory operations constraints
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
Fix qemu_ld64 constraint list
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4949 c046a42c-6fe2-441c-8c8c-71466251a162
Use proper offset for LR save slot
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4948 c046a42c-6fe2-441c-8c8c-71466251a162
Reduce amount of space reserved for tb jump
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4947 c046a42c-6fe2-441c-8c8c-71466251a162
Fix and improve 64 bit immediate loading
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4946 c046a42c-6fe2-441c-8c8c-71466251a162
Fix EXTSW arguments
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4945 c046a42c-6fe2-441c-8c8c-71466251a162
Use proper value for TCG_TARGET_CALL_STACK_OFFSET
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4941 c046a42c-6fe2-441c-8c8c-71466251a162
Emit and use adhoc function descriptor for code_gen_prologue on PPC64
Thus avoiding fragile inline assembly hackery to call into generatedcode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4939 c046a42c-6fe2-441c-8c8c-71466251a162
Remove neg_i32 debugging leftover
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4935 c046a42c-6fe2-441c-8c8c-71466251a162
Provide extNs_M instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
Remove stray "i" from mul_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4933 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary PPC64/Linux host support
ppc64.ld from Heikki Lindholm's patchhttp://marc.info/?l=qemu-devel&m=114086179024634&w=2
Issues:x86_64 tripple faults shortly after decompressing the kernelNo immediate versions of most 64 bit operationsMore......
64 bit signed comparison fix (Juergen Lock)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4855 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
Fuse EQ and NE handling in tcg_out_brcond2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress bogus compiler warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
Shuffle contents of tcg_target_reg_alloc_order
Move reserved/volatile registers down. Currently qemu_ld/stXX aremarked with TCG_OPF_CALL_CLOBBER and since memory accesses arefrequent and R3 through R12 are volatile moving this down results inless spills and tighter generated code....
Save LR into proper place on callers stack frame
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
Reimplement brcond2 and refactor brcond
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162