root / hw / usb-uhci.c @ 0510224e
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1 | bb36d470 | bellard | /*
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2 | bb36d470 | bellard | * USB UHCI controller emulation
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3 | bb36d470 | bellard | *
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4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | bb36d470 | bellard | *
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6 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
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9 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
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12 | bb36d470 | bellard | *
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13 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | bb36d470 | bellard | * all copies or substantial portions of the Software.
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15 | bb36d470 | bellard | *
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16 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | bb36d470 | bellard | * THE SOFTWARE.
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23 | bb36d470 | bellard | */
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24 | bb36d470 | bellard | #include "vl.h" |
25 | bb36d470 | bellard | |
26 | bb36d470 | bellard | //#define DEBUG
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27 | bb36d470 | bellard | //#define DEBUG_PACKET
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28 | bb36d470 | bellard | |
29 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
30 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
31 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
32 | bb36d470 | bellard | |
33 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
34 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
35 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
36 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
37 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
38 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
39 | bb36d470 | bellard | |
40 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
41 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
42 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
43 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
44 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
45 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
46 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
47 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
48 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
49 | bb36d470 | bellard | |
50 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
51 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
52 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
53 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
54 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
55 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
56 | bb36d470 | bellard | |
57 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
58 | bb36d470 | bellard | |
59 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
60 | bb36d470 | bellard | |
61 | bb36d470 | bellard | #define NB_PORTS 2 |
62 | bb36d470 | bellard | |
63 | bb36d470 | bellard | typedef struct UHCIPort { |
64 | bb36d470 | bellard | USBPort port; |
65 | bb36d470 | bellard | uint16_t ctrl; |
66 | bb36d470 | bellard | } UHCIPort; |
67 | bb36d470 | bellard | |
68 | bb36d470 | bellard | typedef struct UHCIState { |
69 | bb36d470 | bellard | PCIDevice dev; |
70 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
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71 | bb36d470 | bellard | uint16_t status; |
72 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
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73 | bb36d470 | bellard | uint16_t frnum; /* frame number */
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74 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
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75 | bb36d470 | bellard | uint8_t sof_timing; |
76 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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77 | bb36d470 | bellard | QEMUTimer *frame_timer; |
78 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
79 | bb36d470 | bellard | } UHCIState; |
80 | bb36d470 | bellard | |
81 | bb36d470 | bellard | typedef struct UHCI_TD { |
82 | bb36d470 | bellard | uint32_t link; |
83 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
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84 | bb36d470 | bellard | uint32_t token; |
85 | bb36d470 | bellard | uint32_t buffer; |
86 | bb36d470 | bellard | } UHCI_TD; |
87 | bb36d470 | bellard | |
88 | bb36d470 | bellard | typedef struct UHCI_QH { |
89 | bb36d470 | bellard | uint32_t link; |
90 | bb36d470 | bellard | uint32_t el_link; |
91 | bb36d470 | bellard | } UHCI_QH; |
92 | bb36d470 | bellard | |
93 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev); |
94 | bb36d470 | bellard | |
95 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
96 | bb36d470 | bellard | { |
97 | bb36d470 | bellard | int level;
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98 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
99 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
100 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
101 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
102 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
103 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
104 | bb36d470 | bellard | level = 1;
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105 | bb36d470 | bellard | } else {
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106 | bb36d470 | bellard | level = 0;
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107 | bb36d470 | bellard | } |
108 | f04308e4 | bellard | pci_set_irq(&s->dev, 3, level);
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109 | bb36d470 | bellard | } |
110 | bb36d470 | bellard | |
111 | bb36d470 | bellard | static void uhci_reset(UHCIState *s) |
112 | bb36d470 | bellard | { |
113 | bb36d470 | bellard | uint8_t *pci_conf; |
114 | bb36d470 | bellard | int i;
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115 | bb36d470 | bellard | UHCIPort *port; |
116 | bb36d470 | bellard | |
117 | bb36d470 | bellard | pci_conf = s->dev.config; |
118 | bb36d470 | bellard | |
119 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
120 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
121 | bb36d470 | bellard | s->cmd = 0;
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122 | bb36d470 | bellard | s->status = 0;
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123 | bb36d470 | bellard | s->status2 = 0;
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124 | bb36d470 | bellard | s->intr = 0;
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125 | bb36d470 | bellard | s->fl_base_addr = 0;
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126 | bb36d470 | bellard | s->sof_timing = 64;
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127 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
128 | bb36d470 | bellard | port = &s->ports[i]; |
129 | bb36d470 | bellard | port->ctrl = 0x0080;
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130 | a594cfbf | bellard | if (port->port.dev)
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131 | a594cfbf | bellard | uhci_attach(&port->port, port->port.dev); |
132 | bb36d470 | bellard | } |
133 | bb36d470 | bellard | } |
134 | bb36d470 | bellard | |
135 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
136 | bb36d470 | bellard | { |
137 | bb36d470 | bellard | UHCIState *s = opaque; |
138 | bb36d470 | bellard | |
139 | bb36d470 | bellard | addr &= 0x1f;
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140 | bb36d470 | bellard | switch(addr) {
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141 | bb36d470 | bellard | case 0x0c: |
142 | bb36d470 | bellard | s->sof_timing = val; |
143 | bb36d470 | bellard | break;
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144 | bb36d470 | bellard | } |
145 | bb36d470 | bellard | } |
146 | bb36d470 | bellard | |
147 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
148 | bb36d470 | bellard | { |
149 | bb36d470 | bellard | UHCIState *s = opaque; |
150 | bb36d470 | bellard | uint32_t val; |
151 | bb36d470 | bellard | |
152 | bb36d470 | bellard | addr &= 0x1f;
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153 | bb36d470 | bellard | switch(addr) {
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154 | bb36d470 | bellard | case 0x0c: |
155 | bb36d470 | bellard | val = s->sof_timing; |
156 | d80cfb3f | pbrook | break;
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157 | bb36d470 | bellard | default:
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158 | bb36d470 | bellard | val = 0xff;
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159 | bb36d470 | bellard | break;
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160 | bb36d470 | bellard | } |
161 | bb36d470 | bellard | return val;
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162 | bb36d470 | bellard | } |
163 | bb36d470 | bellard | |
164 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
165 | bb36d470 | bellard | { |
166 | bb36d470 | bellard | UHCIState *s = opaque; |
167 | bb36d470 | bellard | |
168 | bb36d470 | bellard | addr &= 0x1f;
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169 | bb36d470 | bellard | #ifdef DEBUG
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170 | bb36d470 | bellard | printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
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171 | bb36d470 | bellard | #endif
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172 | bb36d470 | bellard | switch(addr) {
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173 | bb36d470 | bellard | case 0x00: |
174 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
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175 | bb36d470 | bellard | /* start frame processing */
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176 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
177 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
178 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
179 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
180 | bb36d470 | bellard | } |
181 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
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182 | bb36d470 | bellard | UHCIPort *port; |
183 | bb36d470 | bellard | USBDevice *dev; |
184 | bb36d470 | bellard | int i;
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185 | bb36d470 | bellard | |
186 | bb36d470 | bellard | /* send reset on the USB bus */
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187 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
188 | bb36d470 | bellard | port = &s->ports[i]; |
189 | a594cfbf | bellard | dev = port->port.dev; |
190 | bb36d470 | bellard | if (dev) {
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191 | bb36d470 | bellard | dev->handle_packet(dev, |
192 | bb36d470 | bellard | USB_MSG_RESET, 0, 0, NULL, 0); |
193 | bb36d470 | bellard | } |
194 | bb36d470 | bellard | } |
195 | bb36d470 | bellard | uhci_reset(s); |
196 | bb36d470 | bellard | return;
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197 | bb36d470 | bellard | } |
198 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
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199 | bb36d470 | bellard | uhci_reset(s); |
200 | bb36d470 | bellard | return;
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201 | bb36d470 | bellard | } |
202 | bb36d470 | bellard | s->cmd = val; |
203 | bb36d470 | bellard | break;
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204 | bb36d470 | bellard | case 0x02: |
205 | bb36d470 | bellard | s->status &= ~val; |
206 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
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207 | bb36d470 | bellard | register to distinguish between IOC and SPD */
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208 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
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209 | bb36d470 | bellard | s->status2 = 0;
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210 | bb36d470 | bellard | uhci_update_irq(s); |
211 | bb36d470 | bellard | break;
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212 | bb36d470 | bellard | case 0x04: |
213 | bb36d470 | bellard | s->intr = val; |
214 | bb36d470 | bellard | uhci_update_irq(s); |
215 | bb36d470 | bellard | break;
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216 | bb36d470 | bellard | case 0x06: |
217 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
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218 | bb36d470 | bellard | s->frnum = val & 0x7ff;
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219 | bb36d470 | bellard | break;
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220 | bb36d470 | bellard | case 0x10 ... 0x1f: |
221 | bb36d470 | bellard | { |
222 | bb36d470 | bellard | UHCIPort *port; |
223 | bb36d470 | bellard | USBDevice *dev; |
224 | bb36d470 | bellard | int n;
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225 | bb36d470 | bellard | |
226 | bb36d470 | bellard | n = (addr >> 1) & 7; |
227 | bb36d470 | bellard | if (n >= NB_PORTS)
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228 | bb36d470 | bellard | return;
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229 | bb36d470 | bellard | port = &s->ports[n]; |
230 | a594cfbf | bellard | dev = port->port.dev; |
231 | bb36d470 | bellard | if (dev) {
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232 | bb36d470 | bellard | /* port reset */
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233 | bb36d470 | bellard | if ( (val & UHCI_PORT_RESET) &&
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234 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
235 | bb36d470 | bellard | dev->handle_packet(dev, |
236 | bb36d470 | bellard | USB_MSG_RESET, 0, 0, NULL, 0); |
237 | bb36d470 | bellard | } |
238 | bb36d470 | bellard | } |
239 | bb36d470 | bellard | port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
240 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
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241 | bb36d470 | bellard | port->ctrl &= ~(val & 0x000a);
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242 | bb36d470 | bellard | } |
243 | bb36d470 | bellard | break;
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244 | bb36d470 | bellard | } |
245 | bb36d470 | bellard | } |
246 | bb36d470 | bellard | |
247 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
248 | bb36d470 | bellard | { |
249 | bb36d470 | bellard | UHCIState *s = opaque; |
250 | bb36d470 | bellard | uint32_t val; |
251 | bb36d470 | bellard | |
252 | bb36d470 | bellard | addr &= 0x1f;
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253 | bb36d470 | bellard | switch(addr) {
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254 | bb36d470 | bellard | case 0x00: |
255 | bb36d470 | bellard | val = s->cmd; |
256 | bb36d470 | bellard | break;
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257 | bb36d470 | bellard | case 0x02: |
258 | bb36d470 | bellard | val = s->status; |
259 | bb36d470 | bellard | break;
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260 | bb36d470 | bellard | case 0x04: |
261 | bb36d470 | bellard | val = s->intr; |
262 | bb36d470 | bellard | break;
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263 | bb36d470 | bellard | case 0x06: |
264 | bb36d470 | bellard | val = s->frnum; |
265 | bb36d470 | bellard | break;
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266 | bb36d470 | bellard | case 0x10 ... 0x1f: |
267 | bb36d470 | bellard | { |
268 | bb36d470 | bellard | UHCIPort *port; |
269 | bb36d470 | bellard | int n;
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270 | bb36d470 | bellard | n = (addr >> 1) & 7; |
271 | bb36d470 | bellard | if (n >= NB_PORTS)
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272 | bb36d470 | bellard | goto read_default;
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273 | bb36d470 | bellard | port = &s->ports[n]; |
274 | bb36d470 | bellard | val = port->ctrl; |
275 | bb36d470 | bellard | } |
276 | bb36d470 | bellard | break;
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277 | bb36d470 | bellard | default:
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278 | bb36d470 | bellard | read_default:
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279 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
280 | bb36d470 | bellard | break;
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281 | bb36d470 | bellard | } |
282 | bb36d470 | bellard | #ifdef DEBUG
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283 | bb36d470 | bellard | printf("uhci readw port=0x%04x val=0x%04x\n", addr, val);
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284 | bb36d470 | bellard | #endif
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285 | bb36d470 | bellard | return val;
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286 | bb36d470 | bellard | } |
287 | bb36d470 | bellard | |
288 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
289 | bb36d470 | bellard | { |
290 | bb36d470 | bellard | UHCIState *s = opaque; |
291 | bb36d470 | bellard | |
292 | bb36d470 | bellard | addr &= 0x1f;
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293 | bb36d470 | bellard | #ifdef DEBUG
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294 | bb36d470 | bellard | printf("uhci writel port=0x%04x val=0x%08x\n", addr, val);
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295 | bb36d470 | bellard | #endif
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296 | bb36d470 | bellard | switch(addr) {
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297 | bb36d470 | bellard | case 0x08: |
298 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
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299 | bb36d470 | bellard | break;
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300 | bb36d470 | bellard | } |
301 | bb36d470 | bellard | } |
302 | bb36d470 | bellard | |
303 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
304 | bb36d470 | bellard | { |
305 | bb36d470 | bellard | UHCIState *s = opaque; |
306 | bb36d470 | bellard | uint32_t val; |
307 | bb36d470 | bellard | |
308 | bb36d470 | bellard | addr &= 0x1f;
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309 | bb36d470 | bellard | switch(addr) {
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310 | bb36d470 | bellard | case 0x08: |
311 | bb36d470 | bellard | val = s->fl_base_addr; |
312 | bb36d470 | bellard | break;
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313 | bb36d470 | bellard | default:
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314 | bb36d470 | bellard | val = 0xffffffff;
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315 | bb36d470 | bellard | break;
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316 | bb36d470 | bellard | } |
317 | bb36d470 | bellard | return val;
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318 | bb36d470 | bellard | } |
319 | bb36d470 | bellard | |
320 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev) |
321 | bb36d470 | bellard | { |
322 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
323 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
324 | bb36d470 | bellard | |
325 | bb36d470 | bellard | if (dev) {
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326 | a594cfbf | bellard | if (port->port.dev) {
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327 | bb36d470 | bellard | usb_attach(port1, NULL);
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328 | bb36d470 | bellard | } |
329 | bb36d470 | bellard | /* set connect status */
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330 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
331 | 61064870 | pbrook | |
332 | bb36d470 | bellard | /* update speed */
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333 | bb36d470 | bellard | if (dev->speed == USB_SPEED_LOW)
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334 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_LSDA; |
335 | bb36d470 | bellard | else
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336 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_LSDA; |
337 | a594cfbf | bellard | port->port.dev = dev; |
338 | bb36d470 | bellard | /* send the attach message */
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339 | bb36d470 | bellard | dev->handle_packet(dev, |
340 | bb36d470 | bellard | USB_MSG_ATTACH, 0, 0, NULL, 0); |
341 | bb36d470 | bellard | } else {
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342 | bb36d470 | bellard | /* set connect status */
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343 | 61064870 | pbrook | if (port->ctrl & UHCI_PORT_CCS) {
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344 | 61064870 | pbrook | port->ctrl &= ~UHCI_PORT_CCS; |
345 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CSC; |
346 | bb36d470 | bellard | } |
347 | bb36d470 | bellard | /* disable port */
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348 | bb36d470 | bellard | if (port->ctrl & UHCI_PORT_EN) {
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349 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_EN; |
350 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_ENC; |
351 | bb36d470 | bellard | } |
352 | a594cfbf | bellard | dev = port->port.dev; |
353 | bb36d470 | bellard | if (dev) {
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354 | bb36d470 | bellard | /* send the detach message */
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355 | bb36d470 | bellard | dev->handle_packet(dev, |
356 | bb36d470 | bellard | USB_MSG_DETACH, 0, 0, NULL, 0); |
357 | bb36d470 | bellard | } |
358 | a594cfbf | bellard | port->port.dev = NULL;
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359 | bb36d470 | bellard | } |
360 | bb36d470 | bellard | } |
361 | bb36d470 | bellard | |
362 | bb36d470 | bellard | static int uhci_broadcast_packet(UHCIState *s, uint8_t pid, |
363 | bb36d470 | bellard | uint8_t devaddr, uint8_t devep, |
364 | bb36d470 | bellard | uint8_t *data, int len)
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365 | bb36d470 | bellard | { |
366 | bb36d470 | bellard | UHCIPort *port; |
367 | bb36d470 | bellard | USBDevice *dev; |
368 | bb36d470 | bellard | int i, ret;
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369 | bb36d470 | bellard | |
370 | bb36d470 | bellard | #ifdef DEBUG_PACKET
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371 | bb36d470 | bellard | { |
372 | bb36d470 | bellard | const char *pidstr; |
373 | bb36d470 | bellard | switch(pid) {
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374 | bb36d470 | bellard | case USB_TOKEN_SETUP: pidstr = "SETUP"; break; |
375 | bb36d470 | bellard | case USB_TOKEN_IN: pidstr = "IN"; break; |
376 | bb36d470 | bellard | case USB_TOKEN_OUT: pidstr = "OUT"; break; |
377 | bb36d470 | bellard | default: pidstr = "?"; break; |
378 | bb36d470 | bellard | } |
379 | bb36d470 | bellard | printf("frame %d: pid=%s addr=0x%02x ep=%d len=%d\n",
|
380 | bb36d470 | bellard | s->frnum, pidstr, devaddr, devep, len); |
381 | bb36d470 | bellard | if (pid != USB_TOKEN_IN) {
|
382 | bb36d470 | bellard | printf(" data_out=");
|
383 | bb36d470 | bellard | for(i = 0; i < len; i++) { |
384 | bb36d470 | bellard | printf(" %02x", data[i]);
|
385 | bb36d470 | bellard | } |
386 | bb36d470 | bellard | printf("\n");
|
387 | bb36d470 | bellard | } |
388 | bb36d470 | bellard | } |
389 | bb36d470 | bellard | #endif
|
390 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
391 | bb36d470 | bellard | port = &s->ports[i]; |
392 | a594cfbf | bellard | dev = port->port.dev; |
393 | bb36d470 | bellard | if (dev && (port->ctrl & UHCI_PORT_EN)) {
|
394 | bb36d470 | bellard | ret = dev->handle_packet(dev, pid, |
395 | bb36d470 | bellard | devaddr, devep, |
396 | bb36d470 | bellard | data, len); |
397 | bb36d470 | bellard | if (ret != USB_RET_NODEV) {
|
398 | bb36d470 | bellard | #ifdef DEBUG_PACKET
|
399 | bb36d470 | bellard | { |
400 | bb36d470 | bellard | printf(" ret=%d ", ret);
|
401 | bb36d470 | bellard | if (pid == USB_TOKEN_IN && ret > 0) { |
402 | bb36d470 | bellard | printf("data_in=");
|
403 | bb36d470 | bellard | for(i = 0; i < ret; i++) { |
404 | bb36d470 | bellard | printf(" %02x", data[i]);
|
405 | bb36d470 | bellard | } |
406 | bb36d470 | bellard | } |
407 | bb36d470 | bellard | printf("\n");
|
408 | bb36d470 | bellard | } |
409 | bb36d470 | bellard | #endif
|
410 | bb36d470 | bellard | return ret;
|
411 | bb36d470 | bellard | } |
412 | bb36d470 | bellard | } |
413 | bb36d470 | bellard | } |
414 | bb36d470 | bellard | return USB_RET_NODEV;
|
415 | bb36d470 | bellard | } |
416 | bb36d470 | bellard | |
417 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
418 | bb36d470 | bellard | 0 if TD successful
|
419 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
420 | bb36d470 | bellard | */
|
421 | bb36d470 | bellard | static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask) |
422 | bb36d470 | bellard | { |
423 | bb36d470 | bellard | uint8_t pid; |
424 | bb36d470 | bellard | uint8_t buf[1280];
|
425 | bb36d470 | bellard | int len, max_len, err, ret;
|
426 | bb36d470 | bellard | |
427 | bb36d470 | bellard | if (td->ctrl & TD_CTRL_IOC) {
|
428 | bb36d470 | bellard | *int_mask |= 0x01;
|
429 | bb36d470 | bellard | } |
430 | bb36d470 | bellard | |
431 | bb36d470 | bellard | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
432 | bb36d470 | bellard | return 1; |
433 | bb36d470 | bellard | |
434 | bb36d470 | bellard | /* TD is active */
|
435 | bb36d470 | bellard | max_len = ((td->token >> 21) + 1) & 0x7ff; |
436 | bb36d470 | bellard | pid = td->token & 0xff;
|
437 | bb36d470 | bellard | switch(pid) {
|
438 | bb36d470 | bellard | case USB_TOKEN_OUT:
|
439 | bb36d470 | bellard | case USB_TOKEN_SETUP:
|
440 | bb36d470 | bellard | cpu_physical_memory_read(td->buffer, buf, max_len); |
441 | bb36d470 | bellard | ret = uhci_broadcast_packet(s, pid, |
442 | bb36d470 | bellard | (td->token >> 8) & 0x7f, |
443 | bb36d470 | bellard | (td->token >> 15) & 0xf, |
444 | bb36d470 | bellard | buf, max_len); |
445 | bb36d470 | bellard | len = max_len; |
446 | bb36d470 | bellard | break;
|
447 | bb36d470 | bellard | case USB_TOKEN_IN:
|
448 | bb36d470 | bellard | ret = uhci_broadcast_packet(s, pid, |
449 | bb36d470 | bellard | (td->token >> 8) & 0x7f, |
450 | bb36d470 | bellard | (td->token >> 15) & 0xf, |
451 | bb36d470 | bellard | buf, max_len); |
452 | bb36d470 | bellard | if (ret >= 0) { |
453 | bb36d470 | bellard | len = ret; |
454 | bb36d470 | bellard | if (len > max_len) {
|
455 | bb36d470 | bellard | len = max_len; |
456 | bb36d470 | bellard | ret = USB_RET_BABBLE; |
457 | bb36d470 | bellard | } |
458 | bb36d470 | bellard | if (len > 0) { |
459 | bb36d470 | bellard | /* write the data back */
|
460 | bb36d470 | bellard | cpu_physical_memory_write(td->buffer, buf, len); |
461 | bb36d470 | bellard | } |
462 | bb36d470 | bellard | } else {
|
463 | bb36d470 | bellard | len = 0;
|
464 | bb36d470 | bellard | } |
465 | bb36d470 | bellard | break;
|
466 | bb36d470 | bellard | default:
|
467 | bb36d470 | bellard | /* invalid pid : frame interrupted */
|
468 | bb36d470 | bellard | s->status |= UHCI_STS_HCPERR; |
469 | bb36d470 | bellard | uhci_update_irq(s); |
470 | bb36d470 | bellard | return -1; |
471 | bb36d470 | bellard | } |
472 | bb36d470 | bellard | if (td->ctrl & TD_CTRL_IOS)
|
473 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
474 | bb36d470 | bellard | if (ret >= 0) { |
475 | bb36d470 | bellard | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
476 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
477 | bb36d470 | bellard | if (pid == USB_TOKEN_IN &&
|
478 | bb36d470 | bellard | (td->ctrl & TD_CTRL_SPD) && |
479 | bb36d470 | bellard | len < max_len) { |
480 | bb36d470 | bellard | *int_mask |= 0x02;
|
481 | bb36d470 | bellard | /* short packet: do not update QH */
|
482 | bb36d470 | bellard | return 1; |
483 | bb36d470 | bellard | } else {
|
484 | bb36d470 | bellard | /* success */
|
485 | bb36d470 | bellard | return 0; |
486 | bb36d470 | bellard | } |
487 | bb36d470 | bellard | } else {
|
488 | bb36d470 | bellard | switch(ret) {
|
489 | bb36d470 | bellard | default:
|
490 | bb36d470 | bellard | case USB_RET_NODEV:
|
491 | bb36d470 | bellard | do_timeout:
|
492 | bb36d470 | bellard | td->ctrl |= TD_CTRL_TIMEOUT; |
493 | bb36d470 | bellard | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
494 | bb36d470 | bellard | if (err != 0) { |
495 | bb36d470 | bellard | err--; |
496 | bb36d470 | bellard | if (err == 0) { |
497 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
498 | bb36d470 | bellard | s->status |= UHCI_STS_USBERR; |
499 | bb36d470 | bellard | uhci_update_irq(s); |
500 | bb36d470 | bellard | } |
501 | bb36d470 | bellard | } |
502 | bb36d470 | bellard | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
503 | bb36d470 | bellard | (err << TD_CTRL_ERROR_SHIFT); |
504 | bb36d470 | bellard | return 1; |
505 | bb36d470 | bellard | case USB_RET_NAK:
|
506 | bb36d470 | bellard | td->ctrl |= TD_CTRL_NAK; |
507 | bb36d470 | bellard | if (pid == USB_TOKEN_SETUP)
|
508 | bb36d470 | bellard | goto do_timeout;
|
509 | bb36d470 | bellard | return 1; |
510 | bb36d470 | bellard | case USB_RET_STALL:
|
511 | bb36d470 | bellard | td->ctrl |= TD_CTRL_STALL; |
512 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
513 | bb36d470 | bellard | return 1; |
514 | bb36d470 | bellard | case USB_RET_BABBLE:
|
515 | bb36d470 | bellard | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
516 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
517 | bb36d470 | bellard | /* frame interrupted */
|
518 | bb36d470 | bellard | return -1; |
519 | bb36d470 | bellard | } |
520 | bb36d470 | bellard | } |
521 | bb36d470 | bellard | } |
522 | bb36d470 | bellard | |
523 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
524 | bb36d470 | bellard | { |
525 | bb36d470 | bellard | UHCIState *s = opaque; |
526 | bb36d470 | bellard | int64_t expire_time; |
527 | bb36d470 | bellard | uint32_t frame_addr, link, old_td_ctrl, val; |
528 | bb36d470 | bellard | int int_mask, cnt, ret;
|
529 | bb36d470 | bellard | UHCI_TD td; |
530 | bb36d470 | bellard | UHCI_QH qh; |
531 | bb36d470 | bellard | |
532 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
533 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
534 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
535 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
536 | bb36d470 | bellard | return;
|
537 | bb36d470 | bellard | } |
538 | bb36d470 | bellard | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
539 | bb36d470 | bellard | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
540 | bb36d470 | bellard | le32_to_cpus(&link); |
541 | bb36d470 | bellard | int_mask = 0;
|
542 | bb36d470 | bellard | cnt = FRAME_MAX_LOOPS; |
543 | bb36d470 | bellard | while ((link & 1) == 0) { |
544 | bb36d470 | bellard | if (--cnt == 0) |
545 | bb36d470 | bellard | break;
|
546 | bb36d470 | bellard | /* valid frame */
|
547 | bb36d470 | bellard | if (link & 2) { |
548 | bb36d470 | bellard | /* QH */
|
549 | bb36d470 | bellard | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
550 | bb36d470 | bellard | le32_to_cpus(&qh.link); |
551 | bb36d470 | bellard | le32_to_cpus(&qh.el_link); |
552 | bb36d470 | bellard | depth_first:
|
553 | bb36d470 | bellard | if (qh.el_link & 1) { |
554 | bb36d470 | bellard | /* no element : go to next entry */
|
555 | bb36d470 | bellard | link = qh.link; |
556 | bb36d470 | bellard | } else if (qh.el_link & 2) { |
557 | bb36d470 | bellard | /* QH */
|
558 | bb36d470 | bellard | link = qh.el_link; |
559 | bb36d470 | bellard | } else {
|
560 | bb36d470 | bellard | /* TD */
|
561 | bb36d470 | bellard | if (--cnt == 0) |
562 | bb36d470 | bellard | break;
|
563 | bb36d470 | bellard | cpu_physical_memory_read(qh.el_link & ~0xf,
|
564 | bb36d470 | bellard | (uint8_t *)&td, sizeof(td));
|
565 | bb36d470 | bellard | le32_to_cpus(&td.link); |
566 | bb36d470 | bellard | le32_to_cpus(&td.ctrl); |
567 | bb36d470 | bellard | le32_to_cpus(&td.token); |
568 | bb36d470 | bellard | le32_to_cpus(&td.buffer); |
569 | bb36d470 | bellard | old_td_ctrl = td.ctrl; |
570 | bb36d470 | bellard | ret = uhci_handle_td(s, &td, &int_mask); |
571 | bb36d470 | bellard | /* update the status bits of the TD */
|
572 | bb36d470 | bellard | if (old_td_ctrl != td.ctrl) {
|
573 | bb36d470 | bellard | val = cpu_to_le32(td.ctrl); |
574 | bb36d470 | bellard | cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
575 | bb36d470 | bellard | (const uint8_t *)&val,
|
576 | bb36d470 | bellard | sizeof(val));
|
577 | bb36d470 | bellard | } |
578 | bb36d470 | bellard | if (ret < 0) |
579 | bb36d470 | bellard | break; /* interrupted frame */ |
580 | bb36d470 | bellard | if (ret == 0) { |
581 | bb36d470 | bellard | /* update qh element link */
|
582 | bb36d470 | bellard | qh.el_link = td.link; |
583 | bb36d470 | bellard | val = cpu_to_le32(qh.el_link); |
584 | bb36d470 | bellard | cpu_physical_memory_write((link & ~0xf) + 4, |
585 | bb36d470 | bellard | (const uint8_t *)&val,
|
586 | bb36d470 | bellard | sizeof(val));
|
587 | bb36d470 | bellard | if (qh.el_link & 4) { |
588 | bb36d470 | bellard | /* depth first */
|
589 | bb36d470 | bellard | goto depth_first;
|
590 | bb36d470 | bellard | } |
591 | bb36d470 | bellard | } |
592 | bb36d470 | bellard | /* go to next entry */
|
593 | bb36d470 | bellard | link = qh.link; |
594 | bb36d470 | bellard | } |
595 | bb36d470 | bellard | } else {
|
596 | bb36d470 | bellard | /* TD */
|
597 | bb36d470 | bellard | cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
598 | bb36d470 | bellard | le32_to_cpus(&td.link); |
599 | bb36d470 | bellard | le32_to_cpus(&td.ctrl); |
600 | bb36d470 | bellard | le32_to_cpus(&td.token); |
601 | bb36d470 | bellard | le32_to_cpus(&td.buffer); |
602 | bb36d470 | bellard | old_td_ctrl = td.ctrl; |
603 | bb36d470 | bellard | ret = uhci_handle_td(s, &td, &int_mask); |
604 | bb36d470 | bellard | /* update the status bits of the TD */
|
605 | bb36d470 | bellard | if (old_td_ctrl != td.ctrl) {
|
606 | bb36d470 | bellard | val = cpu_to_le32(td.ctrl); |
607 | bb36d470 | bellard | cpu_physical_memory_write((link & ~0xf) + 4, |
608 | bb36d470 | bellard | (const uint8_t *)&val,
|
609 | bb36d470 | bellard | sizeof(val));
|
610 | bb36d470 | bellard | } |
611 | bb36d470 | bellard | if (ret < 0) |
612 | bb36d470 | bellard | break; /* interrupted frame */ |
613 | bb36d470 | bellard | link = td.link; |
614 | bb36d470 | bellard | } |
615 | bb36d470 | bellard | } |
616 | bb36d470 | bellard | s->frnum = (s->frnum + 1) & 0x7ff; |
617 | bb36d470 | bellard | if (int_mask) {
|
618 | bb36d470 | bellard | s->status2 |= int_mask; |
619 | bb36d470 | bellard | s->status |= UHCI_STS_USBINT; |
620 | bb36d470 | bellard | uhci_update_irq(s); |
621 | bb36d470 | bellard | } |
622 | bb36d470 | bellard | /* prepare the timer for the next frame */
|
623 | bb36d470 | bellard | expire_time = qemu_get_clock(vm_clock) + |
624 | bb36d470 | bellard | (ticks_per_sec / FRAME_TIMER_FREQ); |
625 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, expire_time); |
626 | bb36d470 | bellard | } |
627 | bb36d470 | bellard | |
628 | bb36d470 | bellard | static void uhci_map(PCIDevice *pci_dev, int region_num, |
629 | bb36d470 | bellard | uint32_t addr, uint32_t size, int type)
|
630 | bb36d470 | bellard | { |
631 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
632 | bb36d470 | bellard | |
633 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
634 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
635 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
636 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
637 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
638 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
639 | bb36d470 | bellard | } |
640 | bb36d470 | bellard | |
641 | 0d92ed30 | pbrook | void usb_uhci_init(PCIBus *bus, int devfn) |
642 | bb36d470 | bellard | { |
643 | bb36d470 | bellard | UHCIState *s; |
644 | bb36d470 | bellard | uint8_t *pci_conf; |
645 | bb36d470 | bellard | int i;
|
646 | bb36d470 | bellard | |
647 | bb36d470 | bellard | s = (UHCIState *)pci_register_device(bus, |
648 | bb36d470 | bellard | "USB-UHCI", sizeof(UHCIState), |
649 | 502a5395 | pbrook | devfn, NULL, NULL); |
650 | bb36d470 | bellard | pci_conf = s->dev.config; |
651 | bb36d470 | bellard | pci_conf[0x00] = 0x86; |
652 | bb36d470 | bellard | pci_conf[0x01] = 0x80; |
653 | bb36d470 | bellard | pci_conf[0x02] = 0x20; |
654 | bb36d470 | bellard | pci_conf[0x03] = 0x70; |
655 | bb36d470 | bellard | pci_conf[0x08] = 0x01; // revision number |
656 | bb36d470 | bellard | pci_conf[0x09] = 0x00; |
657 | bb36d470 | bellard | pci_conf[0x0a] = 0x03; |
658 | bb36d470 | bellard | pci_conf[0x0b] = 0x0c; |
659 | bb36d470 | bellard | pci_conf[0x0e] = 0x00; // header_type |
660 | f04308e4 | bellard | pci_conf[0x3d] = 4; // interrupt pin 3 |
661 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
662 | bb36d470 | bellard | |
663 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
664 | 0d92ed30 | pbrook | qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
665 | bb36d470 | bellard | } |
666 | bb36d470 | bellard | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
667 | bb36d470 | bellard | |
668 | bb36d470 | bellard | uhci_reset(s); |
669 | bb36d470 | bellard | |
670 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
671 | 38ca0f6d | pbrook | to rely on this. */
|
672 | 38ca0f6d | pbrook | pci_register_io_region(&s->dev, 4, 0x20, |
673 | bb36d470 | bellard | PCI_ADDRESS_SPACE_IO, uhci_map); |
674 | bb36d470 | bellard | } |