Archipelago » qemu

/*

 *  Alpha emulation cpu translation for qemu.

 *

 *  Copyright (c) 2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdint.h>

#include <stdlib.h>

#include <stdio.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "host-utils.h"

#include "tcg-op.h"

#include "qemu-common.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

#undef ALPHA_DEBUG_DISAS

#define CONFIG_SOFTFLOAT_INLINE

#ifdef ALPHA_DEBUG_DISAS

#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)

#else

#  define LOG_DISAS(...) do { } while (0)

#endif

typedef struct DisasContext DisasContext;

struct DisasContext {

    uint64_t pc;

    int mem_idx;

#if !defined (CONFIG_USER_ONLY)

    int pal_mode;

#endif

    CPUAlphaState *env;

    uint32_t amask;

    /* Current rounding mode for this TB.  */

    int tb_rm;

    /* Current flush-to-zero setting for this TB.  */

    int tb_ftz;

};

/* global register indexes */

static TCGv_ptr cpu_env;

static TCGv cpu_ir[31];

static TCGv cpu_fir[31];

static TCGv cpu_pc;

static TCGv cpu_lock;

#ifdef CONFIG_USER_ONLY

static TCGv cpu_uniq;

#endif

/* register names */

static char cpu_reg_names[10*4+21*5 + 10*5+21*6];

#include "gen-icount.h"

static void alpha_translate_init(void)

{

    int i;

    char *p;

    static int done_init = 0;

    if (done_init)

        return;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    p = cpu_reg_names;

    for (i = 0; i < 31; i++) {

        sprintf(p, "ir%d", i);

        cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                           offsetof(CPUState, ir[i]), p);

        p += (i < 10) ? 4 : 5;

        sprintf(p, "fir%d", i);

        cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                            offsetof(CPUState, fir[i]), p);

        p += (i < 10) ? 5 : 6;

    }

    cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,

                                    offsetof(CPUState, pc), "pc");

    cpu_lock = tcg_global_mem_new_i64(TCG_AREG0,

                                      offsetof(CPUState, lock), "lock");

#ifdef CONFIG_USER_ONLY

    cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0,

                                      offsetof(CPUState, unique), "uniq");

#endif

    /* register helpers */

#define GEN_HELPER 2

#include "helper.h"

    done_init = 1;

}

static inline void gen_excp(DisasContext *ctx, int exception, int error_code)

{

    TCGv_i32 tmp1, tmp2;

    tcg_gen_movi_i64(cpu_pc, ctx->pc);

    tmp1 = tcg_const_i32(exception);

    tmp2 = tcg_const_i32(error_code);

    gen_helper_excp(tmp1, tmp2);

    tcg_temp_free_i32(tmp2);

    tcg_temp_free_i32(tmp1);

}

static inline void gen_invalid(DisasContext *ctx)

{

    gen_excp(ctx, EXCP_OPCDEC, 0);

}

static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    tcg_gen_qemu_ld32u(tmp, t1, flags);

    tcg_gen_trunc_i64_i32(tmp32, tmp);

    gen_helper_memory_to_f(t0, tmp32);

    tcg_temp_free_i32(tmp32);

    tcg_temp_free(tmp);

}

static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    tcg_gen_qemu_ld64(tmp, t1, flags);

    gen_helper_memory_to_g(t0, tmp);

    tcg_temp_free(tmp);

}

static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    tcg_gen_qemu_ld32u(tmp, t1, flags);

    tcg_gen_trunc_i64_i32(tmp32, tmp);

    gen_helper_memory_to_s(t0, tmp32);

    tcg_temp_free_i32(tmp32);

    tcg_temp_free(tmp);

}

static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)

{

    tcg_gen_mov_i64(cpu_lock, t1);

    tcg_gen_qemu_ld32s(t0, t1, flags);

}

static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)

{

    tcg_gen_mov_i64(cpu_lock, t1);

    tcg_gen_qemu_ld64(t0, t1, flags);

}

static inline void gen_load_mem(DisasContext *ctx,

                                void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,

                                                          int flags),

                                int ra, int rb, int32_t disp16, int fp,

                                int clear)

{

    TCGv addr;

    if (unlikely(ra == 31))

        return;

    addr = tcg_temp_new();

    if (rb != 31) {

        tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);

        if (clear)

            tcg_gen_andi_i64(addr, addr, ~0x7);

    } else {

        if (clear)

            disp16 &= ~0x7;

        tcg_gen_movi_i64(addr, disp16);

    }

    if (fp)

        tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx);

    else

        tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);

    tcg_temp_free(addr);

}

static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)

{

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    TCGv tmp = tcg_temp_new();

    gen_helper_f_to_memory(tmp32, t0);

    tcg_gen_extu_i32_i64(tmp, tmp32);

    tcg_gen_qemu_st32(tmp, t1, flags);

    tcg_temp_free(tmp);

    tcg_temp_free_i32(tmp32);

}

static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    gen_helper_g_to_memory(tmp, t0);

    tcg_gen_qemu_st64(tmp, t1, flags);

    tcg_temp_free(tmp);

}

static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)

{

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    TCGv tmp = tcg_temp_new();

    gen_helper_s_to_memory(tmp32, t0);

    tcg_gen_extu_i32_i64(tmp, tmp32);

    tcg_gen_qemu_st32(tmp, t1, flags);

    tcg_temp_free(tmp);

    tcg_temp_free_i32(tmp32);

}

static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);

    tcg_gen_qemu_st32(t0, t1, flags);

    tcg_gen_movi_i64(t0, 1);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_movi_i64(t0, 0);

    gen_set_label(l2);

    tcg_gen_movi_i64(cpu_lock, -1);

}

static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);

    tcg_gen_qemu_st64(t0, t1, flags);

    tcg_gen_movi_i64(t0, 1);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_movi_i64(t0, 0);

    gen_set_label(l2);

    tcg_gen_movi_i64(cpu_lock, -1);

}

static inline void gen_store_mem(DisasContext *ctx,

                                 void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,

                                                            int flags),

                                 int ra, int rb, int32_t disp16, int fp,

                                 int clear, int local)

{

    TCGv addr;

    if (local)

        addr = tcg_temp_local_new();

    else

        addr = tcg_temp_new();

    if (rb != 31) {

        tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);

        if (clear)

            tcg_gen_andi_i64(addr, addr, ~0x7);

    } else {

        if (clear)

            disp16 &= ~0x7;

        tcg_gen_movi_i64(addr, disp16);

    }

    if (ra != 31) {

        if (fp)

            tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx);

        else

            tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);

    } else {

        TCGv zero;

        if (local)

            zero = tcg_const_local_i64(0);

        else

            zero = tcg_const_i64(0);

        tcg_gen_qemu_store(zero, addr, ctx->mem_idx);

        tcg_temp_free(zero);

    }

    tcg_temp_free(addr);

}

static void gen_bcond_pcload(DisasContext *ctx, int32_t disp, int lab_true)

{

    int lab_over = gen_new_label();

    tcg_gen_movi_i64(cpu_pc, ctx->pc);

    tcg_gen_br(lab_over);

    gen_set_label(lab_true);

    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));

    gen_set_label(lab_over);

}

static void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,

                      int32_t disp, int mask)

{

    int lab_true = gen_new_label();

    if (likely(ra != 31)) {

        if (mask) {

            TCGv tmp = tcg_temp_new();

            tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);

            tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);

            tcg_temp_free(tmp);

        } else {

            tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, lab_true);

        }

    } else {

        /* Very uncommon case - Do not bother to optimize.  */

        TCGv tmp = tcg_const_i64(0);

        tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);

        tcg_temp_free(tmp);

    }

    gen_bcond_pcload(ctx, disp, lab_true);

}

/* Generate a forward TCG branch to LAB_TRUE if RA cmp 0.0.

   This is complicated by the fact that -0.0 compares the same as +0.0.  */

static void gen_fbcond_internal(TCGCond cond, TCGv src, int lab_true)

{

    int lab_false = -1;

    uint64_t mzero = 1ull << 63;

    TCGv tmp;

    switch (cond) {

    case TCG_COND_LE:

    case TCG_COND_GT:

        /* For <= or >, the -0.0 value directly compares the way we want.  */

        tcg_gen_brcondi_i64(cond, src, 0, lab_true);

        break;

    case TCG_COND_EQ:

    case TCG_COND_NE:

        /* For == or !=, we can simply mask off the sign bit and compare.  */

        /* ??? Assume that the temporary is reclaimed at the branch.  */

        tmp = tcg_temp_new();

        tcg_gen_andi_i64(tmp, src, mzero - 1);

        tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);

        break;

    case TCG_COND_GE:

        /* For >=, emit two branches to the destination.  */

        tcg_gen_brcondi_i64(cond, src, 0, lab_true);

        tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_true);

        break;

    case TCG_COND_LT:

        /* For <, first filter out -0.0 to what will be the fallthru.  */

        lab_false = gen_new_label();

        tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_false);

        tcg_gen_brcondi_i64(cond, src, 0, lab_true);

        gen_set_label(lab_false);

        break;

    default:

        abort();

    }

}

static void gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp)

{

    int lab_true;

    if (unlikely(ra == 31)) {

        /* Very uncommon case, but easier to optimize it to an integer

           comparison than continuing with the floating point comparison.  */

        gen_bcond(ctx, cond, ra, disp, 0);

        return;

    }

    lab_true = gen_new_label();

    gen_fbcond_internal(cond, cpu_fir[ra], lab_true);

    gen_bcond_pcload(ctx, disp, lab_true);

}

static void gen_cmov(TCGCond cond, int ra, int rb, int rc,

                     int islit, uint8_t lit, int mask)

{

    TCGCond inv_cond = tcg_invert_cond(cond);

    int l1;

    if (unlikely(rc == 31))

        return;

    l1 = gen_new_label();

    if (ra != 31) {

        if (mask) {

            TCGv tmp = tcg_temp_new();

            tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);

            tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);

            tcg_temp_free(tmp);

        } else

            tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);

    } else {

        /* Very uncommon case - Do not bother to optimize.  */

        TCGv tmp = tcg_const_i64(0);

        tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);

        tcg_temp_free(tmp);

    }

    if (islit)

        tcg_gen_movi_i64(cpu_ir[rc], lit);

    else

        tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);

    gen_set_label(l1);

}

static void gen_fcmov(TCGCond cond, int ra, int rb, int rc)

{

    TCGv va = cpu_fir[ra];

    int l1;

    if (unlikely(rc == 31))

        return;

    if (unlikely(ra == 31)) {

        /* ??? Assume that the temporary is reclaimed at the branch.  */

        va = tcg_const_i64(0);

    }

    l1 = gen_new_label();

    gen_fbcond_internal(tcg_invert_cond(cond), va, l1);

    if (rb != 31)

        tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[rb]);

    else

        tcg_gen_movi_i64(cpu_fir[rc], 0);

    gen_set_label(l1);

}

#define QUAL_RM_N       0x080   /* Round mode nearest even */

#define QUAL_RM_C       0x000   /* Round mode chopped */

#define QUAL_RM_M       0x040   /* Round mode minus infinity */

#define QUAL_RM_D       0x0c0   /* Round mode dynamic */

#define QUAL_RM_MASK    0x0c0

#define QUAL_U          0x100   /* Underflow enable (fp output) */

#define QUAL_V          0x100   /* Overflow enable (int output) */

#define QUAL_S          0x400   /* Software completion enable */

#define QUAL_I          0x200   /* Inexact detection enable */

static void gen_qual_roundmode(DisasContext *ctx, int fn11)

{

    TCGv_i32 tmp;

    fn11 &= QUAL_RM_MASK;

    if (fn11 == ctx->tb_rm) {

        return;

    }

    ctx->tb_rm = fn11;

    tmp = tcg_temp_new_i32();

    switch (fn11) {

    case QUAL_RM_N:

        tcg_gen_movi_i32(tmp, float_round_nearest_even);

        break;

    case QUAL_RM_C:

        tcg_gen_movi_i32(tmp, float_round_to_zero);

        break;

    case QUAL_RM_M:

        tcg_gen_movi_i32(tmp, float_round_down);

        break;

    case QUAL_RM_D:

        tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round));

        break;

    }

#if defined(CONFIG_SOFTFLOAT_INLINE)

    /* ??? The "softfloat.h" interface is to call set_float_rounding_mode.

       With CONFIG_SOFTFLOAT that expands to an out-of-line call that just

       sets the one field.  */

    tcg_gen_st8_i32(tmp, cpu_env,

                    offsetof(CPUState, fp_status.float_rounding_mode));

#else

    gen_helper_setroundmode(tmp);

#endif

    tcg_temp_free_i32(tmp);

}

static void gen_qual_flushzero(DisasContext *ctx, int fn11)

{

    TCGv_i32 tmp;

    fn11 &= QUAL_U;

    if (fn11 == ctx->tb_ftz) {

        return;

    }

    ctx->tb_ftz = fn11;

    tmp = tcg_temp_new_i32();

    if (fn11) {

        /* Underflow is enabled, use the FPCR setting.  */

        tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero));

    } else {

        /* Underflow is disabled, force flush-to-zero.  */

        tcg_gen_movi_i32(tmp, 1);

    }

#if defined(CONFIG_SOFTFLOAT_INLINE)

    tcg_gen_st8_i32(tmp, cpu_env,

                    offsetof(CPUState, fp_status.flush_to_zero));

#else

    gen_helper_setflushzero(tmp);

#endif

    tcg_temp_free_i32(tmp);

}

static TCGv gen_ieee_input(int reg, int fn11, int is_cmp)

{

    TCGv val = tcg_temp_new();

    if (reg == 31) {

        tcg_gen_movi_i64(val, 0);

    } else if (fn11 & QUAL_S) {

        gen_helper_ieee_input_s(val, cpu_fir[reg]);

    } else if (is_cmp) {

        gen_helper_ieee_input_cmp(val, cpu_fir[reg]);

    } else {

        gen_helper_ieee_input(val, cpu_fir[reg]);

    }

    return val;

}

static void gen_fp_exc_clear(void)

{

#if defined(CONFIG_SOFTFLOAT_INLINE)

    TCGv_i32 zero = tcg_const_i32(0);

    tcg_gen_st8_i32(zero, cpu_env,

                    offsetof(CPUState, fp_status.float_exception_flags));

    tcg_temp_free_i32(zero);

#else

    gen_helper_fp_exc_clear();

#endif

}

static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)

{

    /* ??? We ought to be able to do something with imprecise exceptions.

       E.g. notice we're still in the trap shadow of something within the

       TB and do not generate the code to signal the exception; end the TB

       when an exception is forced to arrive, either by consumption of a

       register value or TRAPB or EXCB.  */

    TCGv_i32 exc = tcg_temp_new_i32();

    TCGv_i32 reg;

#if defined(CONFIG_SOFTFLOAT_INLINE)

    tcg_gen_ld8u_i32(exc, cpu_env,

                     offsetof(CPUState, fp_status.float_exception_flags));

#else

    gen_helper_fp_exc_get(exc);

#endif

    if (ignore) {

        tcg_gen_andi_i32(exc, exc, ~ignore);

    }

    /* ??? Pass in the regno of the destination so that the helper can

       set EXC_MASK, which contains a bitmask of destination registers

       that have caused arithmetic traps.  A simple userspace emulation

       does not require this.  We do need it for a guest kernel's entArith,

       or if we were to do something clever with imprecise exceptions.  */

    reg = tcg_const_i32(rc + 32);

    if (fn11 & QUAL_S) {

        gen_helper_fp_exc_raise_s(exc, reg);

    } else {

        gen_helper_fp_exc_raise(exc, reg);

    }

    tcg_temp_free_i32(reg);

    tcg_temp_free_i32(exc);

}

static inline void gen_fp_exc_raise(int rc, int fn11)

{

    gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);

}

static void gen_fcvtql(int rb, int rc)

{

    if (unlikely(rc == 31)) {

        return;

    }

    if (unlikely(rb == 31)) {

        tcg_gen_movi_i64(cpu_fir[rc], 0);

    } else {

        TCGv tmp = tcg_temp_new();

        tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000);

        tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF);

        tcg_gen_shli_i64(tmp, tmp, 32);

        tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29);

        tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp);

        tcg_temp_free(tmp);

    }

}

static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc)

{

    if (rb != 31) {

        int lab = gen_new_label();

        TCGv tmp = tcg_temp_new();

        tcg_gen_ext32s_i64(tmp, cpu_fir[rb]);

        tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab);

        gen_excp(ctx, EXCP_ARITH, EXC_M_IOV);

        gen_set_label(lab);

    }

    gen_fcvtql(rb, rc);

}

#define FARITH2(name)                                   \

static inline void glue(gen_f, name)(int rb, int rc)    \

{                                                       \

    if (unlikely(rc == 31)) {                           \

        return;                                         \

    }                                                   \

    if (rb != 31) {                                     \

        gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \

    } else {                                                \

        TCGv tmp = tcg_const_i64(0);                    \

        gen_helper_ ## name (cpu_fir[rc], tmp);         \

        tcg_temp_free(tmp);                             \

    }                                                   \

}

FARITH2(cvtlq)

/* ??? VAX instruction qualifiers ignored.  */

FARITH2(sqrtf)

FARITH2(sqrtg)

FARITH2(cvtgf)

FARITH2(cvtgq)

FARITH2(cvtqf)

FARITH2(cvtqg)

static void gen_ieee_arith2(DisasContext *ctx, void (*helper)(TCGv, TCGv),

                            int rb, int rc, int fn11)

{

    TCGv vb;

    /* ??? This is wrong: the instruction is not a nop, it still may

       raise exceptions.  */

    if (unlikely(rc == 31)) {

        return;

    }

    gen_qual_roundmode(ctx, fn11);

    gen_qual_flushzero(ctx, fn11);

    gen_fp_exc_clear();

    vb = gen_ieee_input(rb, fn11, 0);

    helper(cpu_fir[rc], vb);

    tcg_temp_free(vb);

    gen_fp_exc_raise(rc, fn11);

}

#define IEEE_ARITH2(name)                                       \

static inline void glue(gen_f, name)(DisasContext *ctx,         \

                                     int rb, int rc, int fn11)  \

{                                                               \

    gen_ieee_arith2(ctx, gen_helper_##name, rb, rc, fn11);      \

}

IEEE_ARITH2(sqrts)

IEEE_ARITH2(sqrtt)

IEEE_ARITH2(cvtst)

IEEE_ARITH2(cvtts)

static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)

{

    TCGv vb;

    int ignore = 0;

    /* ??? This is wrong: the instruction is not a nop, it still may

       raise exceptions.  */

    if (unlikely(rc == 31)) {

        return;

    }

    /* No need to set flushzero, since we have an integer output.  */

    gen_fp_exc_clear();

    vb = gen_ieee_input(rb, fn11, 0);

    /* Almost all integer conversions use cropped rounding, and most

       also do not have integer overflow enabled.  Special case that.  */

    switch (fn11) {

    case QUAL_RM_C:

        gen_helper_cvttq_c(cpu_fir[rc], vb);

        break;

    case QUAL_V | QUAL_RM_C:

    case QUAL_S | QUAL_V | QUAL_RM_C:

        ignore = float_flag_inexact;

        /* FALLTHRU */

    case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:

        gen_helper_cvttq_svic(cpu_fir[rc], vb);

        break;

    default:

        gen_qual_roundmode(ctx, fn11);

        gen_helper_cvttq(cpu_fir[rc], vb);

        ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);

        ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);

        break;

    }

    tcg_temp_free(vb);

    gen_fp_exc_raise_ignore(rc, fn11, ignore);

}

static void gen_ieee_intcvt(DisasContext *ctx, void (*helper)(TCGv, TCGv),

                            int rb, int rc, int fn11)

{

    TCGv vb;

    /* ??? This is wrong: the instruction is not a nop, it still may

       raise exceptions.  */

    if (unlikely(rc == 31)) {

        return;

    }

    gen_qual_roundmode(ctx, fn11);

    if (rb == 31) {

        vb = tcg_const_i64(0);

    } else {

        vb = cpu_fir[rb];

    }

    /* The only exception that can be raised by integer conversion

       is inexact.  Thus we only need to worry about exceptions when

       inexact handling is requested.  */

    if (fn11 & QUAL_I) {

        gen_fp_exc_clear();

        helper(cpu_fir[rc], vb);

        gen_fp_exc_raise(rc, fn11);

    } else {

        helper(cpu_fir[rc], vb);

    }

    if (rb == 31) {

        tcg_temp_free(vb);

    }

}

#define IEEE_INTCVT(name)                                       \

static inline void glue(gen_f, name)(DisasContext *ctx,         \

                                     int rb, int rc, int fn11)  \

{                                                               \

    gen_ieee_intcvt(ctx, gen_helper_##name, rb, rc, fn11);      \

}

IEEE_INTCVT(cvtqs)

IEEE_INTCVT(cvtqt)

#define FARITH3(name)                                           \

static inline void glue(gen_f, name)(int ra, int rb, int rc)    \

{                                                               \

    TCGv va, vb;                                                \

                                                                \

    if (unlikely(rc == 31)) {                                   \

        return;                                                 \

    }                                                           \

    if (ra == 31) {                                             \

        va = tcg_const_i64(0);                                  \

    } else {                                                    \

        va = cpu_fir[ra];                                       \

    }                                                           \

    if (rb == 31) {                                             \

        vb = tcg_const_i64(0);                                  \

    } else {                                                    \

        vb = cpu_fir[rb];                                       \

    }                                                           \

                                                                \

    gen_helper_ ## name (cpu_fir[rc], va, vb);                  \

                                                                \

    if (ra == 31) {                                             \

        tcg_temp_free(va);                                      \

    }                                                           \

    if (rb == 31) {                                             \

        tcg_temp_free(vb);                                      \

    }                                                           \

}

/* ??? Ought to expand these inline; simple masking operations.  */

FARITH3(cpys)

FARITH3(cpysn)

FARITH3(cpyse)

/* ??? VAX instruction qualifiers ignored.  */

FARITH3(addf)

FARITH3(subf)

FARITH3(mulf)

FARITH3(divf)

FARITH3(addg)

FARITH3(subg)

FARITH3(mulg)

FARITH3(divg)

FARITH3(cmpgeq)

FARITH3(cmpglt)

FARITH3(cmpgle)

static void gen_ieee_arith3(DisasContext *ctx,

                            void (*helper)(TCGv, TCGv, TCGv),

                            int ra, int rb, int rc, int fn11)

{

    TCGv va, vb;

    /* ??? This is wrong: the instruction is not a nop, it still may

       raise exceptions.  */

    if (unlikely(rc == 31)) {

        return;

    }

    gen_qual_roundmode(ctx, fn11);

    gen_qual_flushzero(ctx, fn11);

    gen_fp_exc_clear();

    va = gen_ieee_input(ra, fn11, 0);

    vb = gen_ieee_input(rb, fn11, 0);

    helper(cpu_fir[rc], va, vb);

    tcg_temp_free(va);

    tcg_temp_free(vb);

    gen_fp_exc_raise(rc, fn11);

}

#define IEEE_ARITH3(name)                                               \

static inline void glue(gen_f, name)(DisasContext *ctx,                 \

                                     int ra, int rb, int rc, int fn11)  \

{                                                                       \

    gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11);          \

}

IEEE_ARITH3(adds)

IEEE_ARITH3(subs)

IEEE_ARITH3(muls)

IEEE_ARITH3(divs)

IEEE_ARITH3(addt)

IEEE_ARITH3(subt)

IEEE_ARITH3(mult)

IEEE_ARITH3(divt)

static void gen_ieee_compare(DisasContext *ctx,

                             void (*helper)(TCGv, TCGv, TCGv),

                             int ra, int rb, int rc, int fn11)

{

    TCGv va, vb;

    /* ??? This is wrong: the instruction is not a nop, it still may

       raise exceptions.  */

    if (unlikely(rc == 31)) {

        return;

    }

    gen_fp_exc_clear();

    va = gen_ieee_input(ra, fn11, 1);

    vb = gen_ieee_input(rb, fn11, 1);

    helper(cpu_fir[rc], va, vb);

    tcg_temp_free(va);

    tcg_temp_free(vb);

    gen_fp_exc_raise(rc, fn11);

}

#define IEEE_CMP3(name)                                                 \

static inline void glue(gen_f, name)(DisasContext *ctx,                 \

                                     int ra, int rb, int rc, int fn11)  \

{                                                                       \

    gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11);         \

}

IEEE_CMP3(cmptun)

IEEE_CMP3(cmpteq)

IEEE_CMP3(cmptlt)

IEEE_CMP3(cmptle)

static inline uint64_t zapnot_mask(uint8_t lit)

{

    uint64_t mask = 0;

    int i;

    for (i = 0; i < 8; ++i) {

        if ((lit >> i) & 1)

            mask |= 0xffull << (i * 8);

    }

    return mask;

}

/* Implement zapnot with an immediate operand, which expands to some

   form of immediate AND.  This is a basic building block in the

   definition of many of the other byte manipulation instructions.  */

static void gen_zapnoti(TCGv dest, TCGv src, uint8_t lit)

{

    switch (lit) {

    case 0x00:

        tcg_gen_movi_i64(dest, 0);

        break;

    case 0x01:

        tcg_gen_ext8u_i64(dest, src);

        break;

    case 0x03:

        tcg_gen_ext16u_i64(dest, src);

        break;

    case 0x0f:

        tcg_gen_ext32u_i64(dest, src);

        break;

    case 0xff:

        tcg_gen_mov_i64(dest, src);

        break;

    default:

        tcg_gen_andi_i64 (dest, src, zapnot_mask (lit));

        break;

    }

}

static inline void gen_zapnot(int ra, int rb, int rc, int islit, uint8_t lit)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else if (islit)

        gen_zapnoti(cpu_ir[rc], cpu_ir[ra], lit);

    else

        gen_helper_zapnot (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

}

static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else if (islit)

        gen_zapnoti(cpu_ir[rc], cpu_ir[ra], ~lit);

    else

        gen_helper_zap (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);

}

/* EXTWH, EXTLH, EXTQH */

static void gen_ext_h(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else {

        if (islit) {

            lit = (64 - (lit & 7) * 8) & 0x3f;

            tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit);

        } else {

            TCGv tmp1 = tcg_temp_new();

            tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);

            tcg_gen_shli_i64(tmp1, tmp1, 3);

            tcg_gen_neg_i64(tmp1, tmp1);

            tcg_gen_andi_i64(tmp1, tmp1, 0x3f);

            tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);

            tcg_temp_free(tmp1);

        }

        gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);

    }

}

/* EXTBL, EXTWL, EXTLL, EXTQL */

static void gen_ext_l(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else {

        if (islit) {

            tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);

        } else {

            TCGv tmp = tcg_temp_new();

            tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);

            tcg_gen_shli_i64(tmp, tmp, 3);

            tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);

            tcg_temp_free(tmp);

        }

        gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);

    }

}

/* INSWH, INSLH, INSQH */

static void gen_ins_h(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31) || (islit && (lit & 7) == 0))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else {

        TCGv tmp = tcg_temp_new();

        /* The instruction description has us left-shift the byte mask

           and extract bits <15:8> and apply that zap at the end.  This

           is equivalent to simply performing the zap first and shifting

           afterward.  */

        gen_zapnoti (tmp, cpu_ir[ra], byte_mask);

        if (islit) {

            /* Note that we have handled the lit==0 case above.  */

            tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8);

        } else {

            TCGv shift = tcg_temp_new();

            /* If (B & 7) == 0, we need to shift by 64 and leave a zero.

               Do this portably by splitting the shift into two parts:

               shift_count-1 and 1.  Arrange for the -1 by using

               ones-complement instead of twos-complement in the negation:

               ~((B & 7) * 8) & 63.  */

            tcg_gen_andi_i64(shift, cpu_ir[rb], 7);

            tcg_gen_shli_i64(shift, shift, 3);

            tcg_gen_not_i64(shift, shift);

            tcg_gen_andi_i64(shift, shift, 0x3f);

            tcg_gen_shr_i64(cpu_ir[rc], tmp, shift);

            tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);

            tcg_temp_free(shift);

        }

        tcg_temp_free(tmp);

    }

}

/* INSBL, INSWL, INSLL, INSQL */

static void gen_ins_l(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else {

        TCGv tmp = tcg_temp_new();

        /* The instruction description has us left-shift the byte mask

           the same number of byte slots as the data and apply the zap

           at the end.  This is equivalent to simply performing the zap

           first and shifting afterward.  */

        gen_zapnoti (tmp, cpu_ir[ra], byte_mask);

        if (islit) {

            tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8);

        } else {

            TCGv shift = tcg_temp_new();

            tcg_gen_andi_i64(shift, cpu_ir[rb], 7);

            tcg_gen_shli_i64(shift, shift, 3);

            tcg_gen_shl_i64(cpu_ir[rc], tmp, shift);

            tcg_temp_free(shift);

        }

        tcg_temp_free(tmp);

    }

}

/* MSKWH, MSKLH, MSKQH */

static void gen_msk_h(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else if (islit) {

        gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8));

    } else {

        TCGv shift = tcg_temp_new();

        TCGv mask = tcg_temp_new();

        /* The instruction description is as above, where the byte_mask

           is shifted left, and then we extract bits <15:8>.  This can be

           emulated with a right-shift on the expanded byte mask.  This

           requires extra care because for an input <2:0> == 0 we need a

           shift of 64 bits in order to generate a zero.  This is done by

           splitting the shift into two parts, the variable shift - 1

           followed by a constant 1 shift.  The code we expand below is

           equivalent to ~((B & 7) * 8) & 63.  */

        tcg_gen_andi_i64(shift, cpu_ir[rb], 7);

        tcg_gen_shli_i64(shift, shift, 3);

        tcg_gen_not_i64(shift, shift);

        tcg_gen_andi_i64(shift, shift, 0x3f);

        tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));

        tcg_gen_shr_i64(mask, mask, shift);

        tcg_gen_shri_i64(mask, mask, 1);

        tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);

        tcg_temp_free(mask);

        tcg_temp_free(shift);

    }

}

/* MSKBL, MSKWL, MSKLL, MSKQL */

static void gen_msk_l(int ra, int rb, int rc, int islit,

                      uint8_t lit, uint8_t byte_mask)

{

    if (unlikely(rc == 31))

        return;

    else if (unlikely(ra == 31))

        tcg_gen_movi_i64(cpu_ir[rc], 0);

    else if (islit) {

        gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));

    } else {

        TCGv shift = tcg_temp_new();

        TCGv mask = tcg_temp_new();

        tcg_gen_andi_i64(shift, cpu_ir[rb], 7);

        tcg_gen_shli_i64(shift, shift, 3);

        tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));

        tcg_gen_shl_i64(mask, mask, shift);

        tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);

        tcg_temp_free(mask);

        tcg_temp_free(shift);

    }

}

/* Code to call arith3 helpers */

#define ARITH3(name)                                                  \

static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\

                                    uint8_t lit)                      \

{                                                                     \

    if (unlikely(rc == 31))                                           \

        return;                                                       \

                                                                      \

    if (ra != 31) {                                                   \

        if (islit) {                                                  \

            TCGv tmp = tcg_const_i64(lit);                            \

            gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp);         \

            tcg_temp_free(tmp);                                       \

        } else                                                        \

            gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \

    } else {                                                          \

        TCGv tmp1 = tcg_const_i64(0);                                 \

        if (islit) {                                                  \

            TCGv tmp2 = tcg_const_i64(lit);                           \

            gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2);             \

            tcg_temp_free(tmp2);                                      \

        } else                                                        \

            gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]);       \

        tcg_temp_free(tmp1);                                          \

    }                                                                 \

}

ARITH3(cmpbge)

ARITH3(addlv)

ARITH3(sublv)

ARITH3(addqv)

ARITH3(subqv)

ARITH3(umulh)

ARITH3(mullv)

ARITH3(mulqv)

ARITH3(minub8)

ARITH3(minsb8)

ARITH3(minuw4)

ARITH3(minsw4)

ARITH3(maxub8)

ARITH3(maxsb8)

ARITH3(maxuw4)

ARITH3(maxsw4)

ARITH3(perr)

#define MVIOP2(name)                                    \

static inline void glue(gen_, name)(int rb, int rc)     \

{                                                       \

    if (unlikely(rc == 31))                             \

        return;                                         \

    if (unlikely(rb == 31))                             \

        tcg_gen_movi_i64(cpu_ir[rc], 0);                \

    else                                                \

        gen_helper_ ## name (cpu_ir[rc], cpu_ir[rb]);   \

}

MVIOP2(pklb)

MVIOP2(pkwb)

MVIOP2(unpkbl)

MVIOP2(unpkbw)

static void gen_cmp(TCGCond cond, int ra, int rb, int rc,

                    int islit, uint8_t lit)

{

    TCGv va, vb;

    if (unlikely(rc == 31)) {

        return;

    }

    if (ra == 31) {

        va = tcg_const_i64(0);

    } else {

        va = cpu_ir[ra];

    }

    if (islit) {

        vb = tcg_const_i64(lit);

    } else {

        vb = cpu_ir[rb];

    }

    tcg_gen_setcond_i64(cond, cpu_ir[rc], va, vb);

    if (ra == 31) {

        tcg_temp_free(va);

    }

    if (islit) {

        tcg_temp_free(vb);

    }

}

static inline int translate_one(DisasContext *ctx, uint32_t insn)

{

    uint32_t palcode;

    int32_t disp21, disp16, disp12;

    uint16_t fn11;

    uint8_t opc, ra, rb, rc, fpfn, fn7, fn2, islit, real_islit;

    uint8_t lit;

    int ret;

    /* Decode all instruction fields */

    opc = insn >> 26;

    ra = (insn >> 21) & 0x1F;

    rb = (insn >> 16) & 0x1F;

    rc = insn & 0x1F;

    real_islit = islit = (insn >> 12) & 1;

    if (rb == 31 && !islit) {

        islit = 1;

        lit = 0;

    } else

        lit = (insn >> 13) & 0xFF;

    palcode = insn & 0x03FFFFFF;

    disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;

    disp16 = (int16_t)(insn & 0x0000FFFF);

    disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;

    fn11 = (insn >> 5) & 0x000007FF;

    fpfn = fn11 & 0x3F;

    fn7 = (insn >> 5) & 0x0000007F;

    fn2 = (insn >> 5) & 0x00000003;

    ret = 0;

    LOG_DISAS("opc %02x ra %2d rb %2d rc %2d disp16 %6d\n",

              opc, ra, rb, rc, disp16);

    switch (opc) {

    case 0x00:

        /* CALL_PAL */

#ifdef CONFIG_USER_ONLY

        if (palcode == 0x9E) {

            /* RDUNIQUE */

            tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq);

            break;

        } else if (palcode == 0x9F) {

            /* WRUNIQUE */

            tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]);

            break;

        }

#endif

        if (palcode >= 0x80 && palcode < 0xC0) {

            /* Unprivileged PAL call */

            gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x3F) << 6), 0);

            ret = 3;

            break;

        }

#ifndef CONFIG_USER_ONLY

        if (palcode < 0x40) {

            /* Privileged PAL code */

            if (ctx->mem_idx & 1)

                goto invalid_opc;

            gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);

        }

#endif

        /* Invalid PAL call */

        goto invalid_opc;

    case 0x01:

        /* OPC01 */

        goto invalid_opc;

    case 0x02:

        /* OPC02 */

        goto invalid_opc;

    case 0x03:

        /* OPC03 */

        goto invalid_opc;

    case 0x04:

        /* OPC04 */

        goto invalid_opc;

    case 0x05:

        /* OPC05 */

        goto invalid_opc;

    case 0x06:

        /* OPC06 */

        goto invalid_opc;

    case 0x07:

        /* OPC07 */

        goto invalid_opc;

    case 0x08:

        /* LDA */

        if (likely(ra != 31)) {

            if (rb != 31)

                tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);

            else

                tcg_gen_movi_i64(cpu_ir[ra], disp16);

        }

        break;

    case 0x09:

        /* LDAH */

        if (likely(ra != 31)) {

            if (rb != 31)

                tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);

            else

                tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);

        }

        break;

    case 0x0A:

        /* LDBU */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);

        break;

    case 0x0B:

        /* LDQ_U */

        gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);

        break;

    case 0x0C:

        /* LDWU */

        if (!(ctx->amask & AMASK_BWX))

            goto invalid_opc;

        gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);

        break;

    case 0x0D:

        /* STW */

        gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0);

        break;

    case 0x0E:

        /* STB */

        gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0);

        break;

    case 0x0F:

        /* STQ_U */

        gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0);

        break;

    case 0x10:

        switch (fn7) {

        case 0x00: