root / hw / pxa2xx_lcd.c @ 067d01de
History | View | Annotate | Download (26.9 kB)
1 | a171fe39 | balrog | /*
|
---|---|---|---|
2 | a171fe39 | balrog | * Intel XScale PXA255/270 LCDC emulation.
|
3 | a171fe39 | balrog | *
|
4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
|
5 | a171fe39 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
|
6 | a171fe39 | balrog | *
|
7 | a171fe39 | balrog | * This code is licensed under the GPLv2.
|
8 | a171fe39 | balrog | */
|
9 | a171fe39 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "console.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | e27f01ef | balrog | #include "pixel_ops.h" |
14 | 87ecb68b | pbrook | /* FIXME: For graphic_rotate. Should probably be done in common code. */
|
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 714fa308 | pbrook | #include "framebuffer.h" |
17 | a171fe39 | balrog | |
18 | bc24a225 | Paul Brook | struct PXA2xxLCDState {
|
19 | a171fe39 | balrog | qemu_irq irq; |
20 | a171fe39 | balrog | int irqlevel;
|
21 | a171fe39 | balrog | |
22 | a171fe39 | balrog | int invalidated;
|
23 | a171fe39 | balrog | DisplayState *ds; |
24 | a171fe39 | balrog | drawfn *line_fn[2];
|
25 | a171fe39 | balrog | int dest_width;
|
26 | a171fe39 | balrog | int xres, yres;
|
27 | a171fe39 | balrog | int pal_for;
|
28 | a171fe39 | balrog | int transp;
|
29 | a171fe39 | balrog | enum {
|
30 | a171fe39 | balrog | pxa_lcdc_2bpp = 1,
|
31 | a171fe39 | balrog | pxa_lcdc_4bpp = 2,
|
32 | a171fe39 | balrog | pxa_lcdc_8bpp = 3,
|
33 | a171fe39 | balrog | pxa_lcdc_16bpp = 4,
|
34 | a171fe39 | balrog | pxa_lcdc_18bpp = 5,
|
35 | a171fe39 | balrog | pxa_lcdc_18pbpp = 6,
|
36 | a171fe39 | balrog | pxa_lcdc_19bpp = 7,
|
37 | a171fe39 | balrog | pxa_lcdc_19pbpp = 8,
|
38 | a171fe39 | balrog | pxa_lcdc_24bpp = 9,
|
39 | a171fe39 | balrog | pxa_lcdc_25bpp = 10,
|
40 | a171fe39 | balrog | } bpp; |
41 | a171fe39 | balrog | |
42 | a171fe39 | balrog | uint32_t control[6];
|
43 | a171fe39 | balrog | uint32_t status[2];
|
44 | a171fe39 | balrog | uint32_t ovl1c[2];
|
45 | a171fe39 | balrog | uint32_t ovl2c[2];
|
46 | a171fe39 | balrog | uint32_t ccr; |
47 | a171fe39 | balrog | uint32_t cmdcr; |
48 | a171fe39 | balrog | uint32_t trgbr; |
49 | a171fe39 | balrog | uint32_t tcr; |
50 | a171fe39 | balrog | uint32_t liidr; |
51 | a171fe39 | balrog | uint8_t bscntr; |
52 | a171fe39 | balrog | |
53 | a171fe39 | balrog | struct {
|
54 | a171fe39 | balrog | target_phys_addr_t branch; |
55 | a171fe39 | balrog | int up;
|
56 | a171fe39 | balrog | uint8_t palette[1024];
|
57 | a171fe39 | balrog | uint8_t pbuffer[1024];
|
58 | bc24a225 | Paul Brook | void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
|
59 | a171fe39 | balrog | int *miny, int *maxy); |
60 | a171fe39 | balrog | |
61 | a171fe39 | balrog | target_phys_addr_t descriptor; |
62 | a171fe39 | balrog | target_phys_addr_t source; |
63 | a171fe39 | balrog | uint32_t id; |
64 | a171fe39 | balrog | uint32_t command; |
65 | a171fe39 | balrog | } dma_ch[7];
|
66 | a171fe39 | balrog | |
67 | 38641a52 | balrog | qemu_irq vsync_cb; |
68 | a171fe39 | balrog | int orientation;
|
69 | a171fe39 | balrog | }; |
70 | a171fe39 | balrog | |
71 | bc24a225 | Paul Brook | typedef struct __attribute__ ((__packed__)) { |
72 | a171fe39 | balrog | uint32_t fdaddr; |
73 | a171fe39 | balrog | uint32_t fsaddr; |
74 | a171fe39 | balrog | uint32_t fidr; |
75 | a171fe39 | balrog | uint32_t ldcmd; |
76 | bc24a225 | Paul Brook | } PXAFrameDescriptor; |
77 | a171fe39 | balrog | |
78 | a171fe39 | balrog | #define LCCR0 0x000 /* LCD Controller Control register 0 */ |
79 | a171fe39 | balrog | #define LCCR1 0x004 /* LCD Controller Control register 1 */ |
80 | a171fe39 | balrog | #define LCCR2 0x008 /* LCD Controller Control register 2 */ |
81 | a171fe39 | balrog | #define LCCR3 0x00c /* LCD Controller Control register 3 */ |
82 | a171fe39 | balrog | #define LCCR4 0x010 /* LCD Controller Control register 4 */ |
83 | a171fe39 | balrog | #define LCCR5 0x014 /* LCD Controller Control register 5 */ |
84 | a171fe39 | balrog | |
85 | a171fe39 | balrog | #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ |
86 | a171fe39 | balrog | #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ |
87 | a171fe39 | balrog | #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ |
88 | a171fe39 | balrog | #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ |
89 | a171fe39 | balrog | #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ |
90 | a171fe39 | balrog | #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ |
91 | a171fe39 | balrog | #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ |
92 | a171fe39 | balrog | |
93 | a171fe39 | balrog | #define LCSR1 0x034 /* LCD Controller Status register 1 */ |
94 | a171fe39 | balrog | #define LCSR0 0x038 /* LCD Controller Status register 0 */ |
95 | a171fe39 | balrog | #define LIIDR 0x03c /* LCD Controller Interrupt ID register */ |
96 | a171fe39 | balrog | |
97 | a171fe39 | balrog | #define TRGBR 0x040 /* TMED RGB Seed register */ |
98 | a171fe39 | balrog | #define TCR 0x044 /* TMED Control register */ |
99 | a171fe39 | balrog | |
100 | a171fe39 | balrog | #define OVL1C1 0x050 /* Overlay 1 Control register 1 */ |
101 | a171fe39 | balrog | #define OVL1C2 0x060 /* Overlay 1 Control register 2 */ |
102 | a171fe39 | balrog | #define OVL2C1 0x070 /* Overlay 2 Control register 1 */ |
103 | a171fe39 | balrog | #define OVL2C2 0x080 /* Overlay 2 Control register 2 */ |
104 | a171fe39 | balrog | #define CCR 0x090 /* Cursor Control register */ |
105 | a171fe39 | balrog | |
106 | a171fe39 | balrog | #define CMDCR 0x100 /* Command Control register */ |
107 | a171fe39 | balrog | #define PRSR 0x104 /* Panel Read Status register */ |
108 | a171fe39 | balrog | |
109 | a171fe39 | balrog | #define PXA_LCDDMA_CHANS 7 |
110 | a171fe39 | balrog | #define DMA_FDADR 0x00 /* Frame Descriptor Address register */ |
111 | a171fe39 | balrog | #define DMA_FSADR 0x04 /* Frame Source Address register */ |
112 | a171fe39 | balrog | #define DMA_FIDR 0x08 /* Frame ID register */ |
113 | a171fe39 | balrog | #define DMA_LDCMD 0x0c /* Command register */ |
114 | a171fe39 | balrog | |
115 | a171fe39 | balrog | /* LCD Buffer Strength Control register */
|
116 | a171fe39 | balrog | #define BSCNTR 0x04000054 |
117 | a171fe39 | balrog | |
118 | a171fe39 | balrog | /* Bitfield masks */
|
119 | a171fe39 | balrog | #define LCCR0_ENB (1 << 0) |
120 | a171fe39 | balrog | #define LCCR0_CMS (1 << 1) |
121 | a171fe39 | balrog | #define LCCR0_SDS (1 << 2) |
122 | a171fe39 | balrog | #define LCCR0_LDM (1 << 3) |
123 | a171fe39 | balrog | #define LCCR0_SOFM0 (1 << 4) |
124 | a171fe39 | balrog | #define LCCR0_IUM (1 << 5) |
125 | a171fe39 | balrog | #define LCCR0_EOFM0 (1 << 6) |
126 | a171fe39 | balrog | #define LCCR0_PAS (1 << 7) |
127 | a171fe39 | balrog | #define LCCR0_DPD (1 << 9) |
128 | a171fe39 | balrog | #define LCCR0_DIS (1 << 10) |
129 | a171fe39 | balrog | #define LCCR0_QDM (1 << 11) |
130 | a171fe39 | balrog | #define LCCR0_PDD (0xff << 12) |
131 | a171fe39 | balrog | #define LCCR0_BSM0 (1 << 20) |
132 | a171fe39 | balrog | #define LCCR0_OUM (1 << 21) |
133 | a171fe39 | balrog | #define LCCR0_LCDT (1 << 22) |
134 | a171fe39 | balrog | #define LCCR0_RDSTM (1 << 23) |
135 | a171fe39 | balrog | #define LCCR0_CMDIM (1 << 24) |
136 | a171fe39 | balrog | #define LCCR0_OUC (1 << 25) |
137 | a171fe39 | balrog | #define LCCR0_LDDALT (1 << 26) |
138 | a171fe39 | balrog | #define LCCR1_PPL(x) ((x) & 0x3ff) |
139 | a171fe39 | balrog | #define LCCR2_LPP(x) ((x) & 0x3ff) |
140 | a171fe39 | balrog | #define LCCR3_API (15 << 16) |
141 | a171fe39 | balrog | #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) |
142 | a171fe39 | balrog | #define LCCR3_PDFOR(x) (((x) >> 30) & 3) |
143 | a171fe39 | balrog | #define LCCR4_K1(x) (((x) >> 0) & 7) |
144 | a171fe39 | balrog | #define LCCR4_K2(x) (((x) >> 3) & 7) |
145 | a171fe39 | balrog | #define LCCR4_K3(x) (((x) >> 6) & 7) |
146 | a171fe39 | balrog | #define LCCR4_PALFOR(x) (((x) >> 15) & 3) |
147 | a171fe39 | balrog | #define LCCR5_SOFM(ch) (1 << (ch - 1)) |
148 | a171fe39 | balrog | #define LCCR5_EOFM(ch) (1 << (ch + 7)) |
149 | a171fe39 | balrog | #define LCCR5_BSM(ch) (1 << (ch + 15)) |
150 | a171fe39 | balrog | #define LCCR5_IUM(ch) (1 << (ch + 23)) |
151 | a171fe39 | balrog | #define OVLC1_EN (1 << 31) |
152 | a171fe39 | balrog | #define CCR_CEN (1 << 31) |
153 | a171fe39 | balrog | #define FBR_BRA (1 << 0) |
154 | a171fe39 | balrog | #define FBR_BINT (1 << 1) |
155 | a171fe39 | balrog | #define FBR_SRCADDR (0xfffffff << 4) |
156 | a171fe39 | balrog | #define LCSR0_LDD (1 << 0) |
157 | a171fe39 | balrog | #define LCSR0_SOF0 (1 << 1) |
158 | a171fe39 | balrog | #define LCSR0_BER (1 << 2) |
159 | a171fe39 | balrog | #define LCSR0_ABC (1 << 3) |
160 | a171fe39 | balrog | #define LCSR0_IU0 (1 << 4) |
161 | a171fe39 | balrog | #define LCSR0_IU1 (1 << 5) |
162 | a171fe39 | balrog | #define LCSR0_OU (1 << 6) |
163 | a171fe39 | balrog | #define LCSR0_QD (1 << 7) |
164 | a171fe39 | balrog | #define LCSR0_EOF0 (1 << 8) |
165 | a171fe39 | balrog | #define LCSR0_BS0 (1 << 9) |
166 | a171fe39 | balrog | #define LCSR0_SINT (1 << 10) |
167 | a171fe39 | balrog | #define LCSR0_RDST (1 << 11) |
168 | a171fe39 | balrog | #define LCSR0_CMDINT (1 << 12) |
169 | a171fe39 | balrog | #define LCSR0_BERCH(x) (((x) & 7) << 28) |
170 | a171fe39 | balrog | #define LCSR1_SOF(ch) (1 << (ch - 1)) |
171 | a171fe39 | balrog | #define LCSR1_EOF(ch) (1 << (ch + 7)) |
172 | a171fe39 | balrog | #define LCSR1_BS(ch) (1 << (ch + 15)) |
173 | a171fe39 | balrog | #define LCSR1_IU(ch) (1 << (ch + 23)) |
174 | a171fe39 | balrog | #define LDCMD_LENGTH(x) ((x) & 0x001ffffc) |
175 | a171fe39 | balrog | #define LDCMD_EOFINT (1 << 21) |
176 | a171fe39 | balrog | #define LDCMD_SOFINT (1 << 22) |
177 | a171fe39 | balrog | #define LDCMD_PAL (1 << 26) |
178 | a171fe39 | balrog | |
179 | a171fe39 | balrog | /* Route internal interrupt lines to the global IC */
|
180 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s) |
181 | a171fe39 | balrog | { |
182 | a171fe39 | balrog | int level = 0; |
183 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
184 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0); |
185 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM); |
186 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1)); |
187 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM); |
188 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM); |
189 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0); |
190 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0); |
191 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM); |
192 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM); |
193 | a171fe39 | balrog | level |= (s->status[1] & ~s->control[5]); |
194 | a171fe39 | balrog | |
195 | a171fe39 | balrog | qemu_set_irq(s->irq, !!level); |
196 | a171fe39 | balrog | s->irqlevel = level; |
197 | a171fe39 | balrog | } |
198 | a171fe39 | balrog | |
199 | a171fe39 | balrog | /* Set Branch Status interrupt high and poke associated registers */
|
200 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch) |
201 | a171fe39 | balrog | { |
202 | a171fe39 | balrog | int unmasked;
|
203 | a171fe39 | balrog | if (ch == 0) { |
204 | a171fe39 | balrog | s->status[0] |= LCSR0_BS0;
|
205 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_BSM0);
|
206 | a171fe39 | balrog | } else {
|
207 | a171fe39 | balrog | s->status[1] |= LCSR1_BS(ch);
|
208 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_BSM(ch));
|
209 | a171fe39 | balrog | } |
210 | a171fe39 | balrog | |
211 | a171fe39 | balrog | if (unmasked) {
|
212 | a171fe39 | balrog | if (s->irqlevel)
|
213 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
|
214 | a171fe39 | balrog | else
|
215 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
216 | a171fe39 | balrog | } |
217 | a171fe39 | balrog | } |
218 | a171fe39 | balrog | |
219 | a171fe39 | balrog | /* Set Start Of Frame Status interrupt high and poke associated registers */
|
220 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch) |
221 | a171fe39 | balrog | { |
222 | a171fe39 | balrog | int unmasked;
|
223 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
|
224 | a171fe39 | balrog | return;
|
225 | a171fe39 | balrog | |
226 | a171fe39 | balrog | if (ch == 0) { |
227 | a171fe39 | balrog | s->status[0] |= LCSR0_SOF0;
|
228 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_SOFM0);
|
229 | a171fe39 | balrog | } else {
|
230 | a171fe39 | balrog | s->status[1] |= LCSR1_SOF(ch);
|
231 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_SOFM(ch));
|
232 | a171fe39 | balrog | } |
233 | a171fe39 | balrog | |
234 | a171fe39 | balrog | if (unmasked) {
|
235 | a171fe39 | balrog | if (s->irqlevel)
|
236 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
|
237 | a171fe39 | balrog | else
|
238 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
239 | a171fe39 | balrog | } |
240 | a171fe39 | balrog | } |
241 | a171fe39 | balrog | |
242 | a171fe39 | balrog | /* Set End Of Frame Status interrupt high and poke associated registers */
|
243 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch) |
244 | a171fe39 | balrog | { |
245 | a171fe39 | balrog | int unmasked;
|
246 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
|
247 | a171fe39 | balrog | return;
|
248 | a171fe39 | balrog | |
249 | a171fe39 | balrog | if (ch == 0) { |
250 | a171fe39 | balrog | s->status[0] |= LCSR0_EOF0;
|
251 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_EOFM0);
|
252 | a171fe39 | balrog | } else {
|
253 | a171fe39 | balrog | s->status[1] |= LCSR1_EOF(ch);
|
254 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_EOFM(ch));
|
255 | a171fe39 | balrog | } |
256 | a171fe39 | balrog | |
257 | a171fe39 | balrog | if (unmasked) {
|
258 | a171fe39 | balrog | if (s->irqlevel)
|
259 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
|
260 | a171fe39 | balrog | else
|
261 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
262 | a171fe39 | balrog | } |
263 | a171fe39 | balrog | } |
264 | a171fe39 | balrog | |
265 | a171fe39 | balrog | /* Set Bus Error Status interrupt high and poke associated registers */
|
266 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch) |
267 | a171fe39 | balrog | { |
268 | a171fe39 | balrog | s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
|
269 | a171fe39 | balrog | if (s->irqlevel)
|
270 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
|
271 | a171fe39 | balrog | else
|
272 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
273 | a171fe39 | balrog | } |
274 | a171fe39 | balrog | |
275 | a171fe39 | balrog | /* Set Read Status interrupt high and poke associated registers */
|
276 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s) |
277 | a171fe39 | balrog | { |
278 | a171fe39 | balrog | s->status[0] |= LCSR0_RDST;
|
279 | a171fe39 | balrog | if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
280 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
|
281 | a171fe39 | balrog | } |
282 | a171fe39 | balrog | |
283 | a171fe39 | balrog | /* Load new Frame Descriptors from DMA */
|
284 | bc24a225 | Paul Brook | static void pxa2xx_descriptor_load(PXA2xxLCDState *s) |
285 | a171fe39 | balrog | { |
286 | bc24a225 | Paul Brook | PXAFrameDescriptor desc; |
287 | a171fe39 | balrog | target_phys_addr_t descptr; |
288 | a171fe39 | balrog | int i;
|
289 | a171fe39 | balrog | |
290 | a171fe39 | balrog | for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { |
291 | a171fe39 | balrog | s->dma_ch[i].source = 0;
|
292 | a171fe39 | balrog | |
293 | a171fe39 | balrog | if (!s->dma_ch[i].up)
|
294 | a171fe39 | balrog | continue;
|
295 | a171fe39 | balrog | |
296 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BRA) {
|
297 | a171fe39 | balrog | descptr = s->dma_ch[i].branch & FBR_SRCADDR; |
298 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BINT)
|
299 | a171fe39 | balrog | pxa2xx_dma_bs_set(s, i); |
300 | a171fe39 | balrog | s->dma_ch[i].branch &= ~FBR_BRA; |
301 | a171fe39 | balrog | } else
|
302 | a171fe39 | balrog | descptr = s->dma_ch[i].descriptor; |
303 | a171fe39 | balrog | |
304 | d95b2f8d | balrog | if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
|
305 | b0457b69 | pbrook | sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
|
306 | a171fe39 | balrog | continue;
|
307 | a171fe39 | balrog | |
308 | d7585251 | pbrook | cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc)); |
309 | d7585251 | pbrook | s->dma_ch[i].descriptor = tswap32(desc.fdaddr); |
310 | d7585251 | pbrook | s->dma_ch[i].source = tswap32(desc.fsaddr); |
311 | d7585251 | pbrook | s->dma_ch[i].id = tswap32(desc.fidr); |
312 | d7585251 | pbrook | s->dma_ch[i].command = tswap32(desc.ldcmd); |
313 | a171fe39 | balrog | } |
314 | a171fe39 | balrog | } |
315 | a171fe39 | balrog | |
316 | a171fe39 | balrog | static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
317 | a171fe39 | balrog | { |
318 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
319 | a171fe39 | balrog | int ch;
|
320 | a171fe39 | balrog | |
321 | a171fe39 | balrog | switch (offset) {
|
322 | a171fe39 | balrog | case LCCR0:
|
323 | a171fe39 | balrog | return s->control[0]; |
324 | a171fe39 | balrog | case LCCR1:
|
325 | a171fe39 | balrog | return s->control[1]; |
326 | a171fe39 | balrog | case LCCR2:
|
327 | a171fe39 | balrog | return s->control[2]; |
328 | a171fe39 | balrog | case LCCR3:
|
329 | a171fe39 | balrog | return s->control[3]; |
330 | a171fe39 | balrog | case LCCR4:
|
331 | a171fe39 | balrog | return s->control[4]; |
332 | a171fe39 | balrog | case LCCR5:
|
333 | a171fe39 | balrog | return s->control[5]; |
334 | a171fe39 | balrog | |
335 | a171fe39 | balrog | case OVL1C1:
|
336 | a171fe39 | balrog | return s->ovl1c[0]; |
337 | a171fe39 | balrog | case OVL1C2:
|
338 | a171fe39 | balrog | return s->ovl1c[1]; |
339 | a171fe39 | balrog | case OVL2C1:
|
340 | a171fe39 | balrog | return s->ovl2c[0]; |
341 | a171fe39 | balrog | case OVL2C2:
|
342 | a171fe39 | balrog | return s->ovl2c[1]; |
343 | a171fe39 | balrog | |
344 | a171fe39 | balrog | case CCR:
|
345 | a171fe39 | balrog | return s->ccr;
|
346 | a171fe39 | balrog | |
347 | a171fe39 | balrog | case CMDCR:
|
348 | a171fe39 | balrog | return s->cmdcr;
|
349 | a171fe39 | balrog | |
350 | a171fe39 | balrog | case TRGBR:
|
351 | a171fe39 | balrog | return s->trgbr;
|
352 | a171fe39 | balrog | case TCR:
|
353 | a171fe39 | balrog | return s->tcr;
|
354 | a171fe39 | balrog | |
355 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
356 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
357 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
358 | a171fe39 | balrog | goto fail;
|
359 | a171fe39 | balrog | |
360 | a171fe39 | balrog | switch (offset & 0xf) { |
361 | a171fe39 | balrog | case DMA_FDADR:
|
362 | a171fe39 | balrog | return s->dma_ch[ch].descriptor;
|
363 | a171fe39 | balrog | case DMA_FSADR:
|
364 | a171fe39 | balrog | return s->dma_ch[ch].source;
|
365 | a171fe39 | balrog | case DMA_FIDR:
|
366 | a171fe39 | balrog | return s->dma_ch[ch].id;
|
367 | a171fe39 | balrog | case DMA_LDCMD:
|
368 | a171fe39 | balrog | return s->dma_ch[ch].command;
|
369 | a171fe39 | balrog | default:
|
370 | a171fe39 | balrog | goto fail;
|
371 | a171fe39 | balrog | } |
372 | a171fe39 | balrog | |
373 | a171fe39 | balrog | case FBR0:
|
374 | a171fe39 | balrog | return s->dma_ch[0].branch; |
375 | a171fe39 | balrog | case FBR1:
|
376 | a171fe39 | balrog | return s->dma_ch[1].branch; |
377 | a171fe39 | balrog | case FBR2:
|
378 | a171fe39 | balrog | return s->dma_ch[2].branch; |
379 | a171fe39 | balrog | case FBR3:
|
380 | a171fe39 | balrog | return s->dma_ch[3].branch; |
381 | a171fe39 | balrog | case FBR4:
|
382 | a171fe39 | balrog | return s->dma_ch[4].branch; |
383 | a171fe39 | balrog | case FBR5:
|
384 | a171fe39 | balrog | return s->dma_ch[5].branch; |
385 | a171fe39 | balrog | case FBR6:
|
386 | a171fe39 | balrog | return s->dma_ch[6].branch; |
387 | a171fe39 | balrog | |
388 | a171fe39 | balrog | case BSCNTR:
|
389 | a171fe39 | balrog | return s->bscntr;
|
390 | a171fe39 | balrog | |
391 | a171fe39 | balrog | case PRSR:
|
392 | a171fe39 | balrog | return 0; |
393 | a171fe39 | balrog | |
394 | a171fe39 | balrog | case LCSR0:
|
395 | a171fe39 | balrog | return s->status[0]; |
396 | a171fe39 | balrog | case LCSR1:
|
397 | a171fe39 | balrog | return s->status[1]; |
398 | a171fe39 | balrog | case LIIDR:
|
399 | a171fe39 | balrog | return s->liidr;
|
400 | a171fe39 | balrog | |
401 | a171fe39 | balrog | default:
|
402 | a171fe39 | balrog | fail:
|
403 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
404 | a171fe39 | balrog | } |
405 | a171fe39 | balrog | |
406 | a171fe39 | balrog | return 0; |
407 | a171fe39 | balrog | } |
408 | a171fe39 | balrog | |
409 | a171fe39 | balrog | static void pxa2xx_lcdc_write(void *opaque, |
410 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
411 | a171fe39 | balrog | { |
412 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
413 | a171fe39 | balrog | int ch;
|
414 | a171fe39 | balrog | |
415 | a171fe39 | balrog | switch (offset) {
|
416 | a171fe39 | balrog | case LCCR0:
|
417 | a171fe39 | balrog | /* ACK Quick Disable done */
|
418 | a171fe39 | balrog | if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) |
419 | a171fe39 | balrog | s->status[0] |= LCSR0_QD;
|
420 | a171fe39 | balrog | |
421 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) |
422 | a171fe39 | balrog | printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
|
423 | a171fe39 | balrog | |
424 | a171fe39 | balrog | if ((s->control[3] & LCCR3_API) && |
425 | a171fe39 | balrog | (value & LCCR0_ENB) && !(value & LCCR0_LCDT)) |
426 | a171fe39 | balrog | s->status[0] |= LCSR0_ABC;
|
427 | a171fe39 | balrog | |
428 | a171fe39 | balrog | s->control[0] = value & 0x07ffffff; |
429 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
430 | a171fe39 | balrog | |
431 | a171fe39 | balrog | s->dma_ch[0].up = !!(value & LCCR0_ENB);
|
432 | a171fe39 | balrog | s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS); |
433 | a171fe39 | balrog | break;
|
434 | a171fe39 | balrog | |
435 | a171fe39 | balrog | case LCCR1:
|
436 | a171fe39 | balrog | s->control[1] = value;
|
437 | a171fe39 | balrog | break;
|
438 | a171fe39 | balrog | |
439 | a171fe39 | balrog | case LCCR2:
|
440 | a171fe39 | balrog | s->control[2] = value;
|
441 | a171fe39 | balrog | break;
|
442 | a171fe39 | balrog | |
443 | a171fe39 | balrog | case LCCR3:
|
444 | a171fe39 | balrog | s->control[3] = value & 0xefffffff; |
445 | a171fe39 | balrog | s->bpp = LCCR3_BPP(value); |
446 | a171fe39 | balrog | break;
|
447 | a171fe39 | balrog | |
448 | a171fe39 | balrog | case LCCR4:
|
449 | a171fe39 | balrog | s->control[4] = value & 0x83ff81ff; |
450 | a171fe39 | balrog | break;
|
451 | a171fe39 | balrog | |
452 | a171fe39 | balrog | case LCCR5:
|
453 | a171fe39 | balrog | s->control[5] = value & 0x3f3f3f3f; |
454 | a171fe39 | balrog | break;
|
455 | a171fe39 | balrog | |
456 | a171fe39 | balrog | case OVL1C1:
|
457 | a171fe39 | balrog | if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
458 | a171fe39 | balrog | printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
459 | a171fe39 | balrog | |
460 | a171fe39 | balrog | s->ovl1c[0] = value & 0x80ffffff; |
461 | a171fe39 | balrog | s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); |
462 | a171fe39 | balrog | break;
|
463 | a171fe39 | balrog | |
464 | a171fe39 | balrog | case OVL1C2:
|
465 | a171fe39 | balrog | s->ovl1c[1] = value & 0x000fffff; |
466 | a171fe39 | balrog | break;
|
467 | a171fe39 | balrog | |
468 | a171fe39 | balrog | case OVL2C1:
|
469 | a171fe39 | balrog | if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
470 | a171fe39 | balrog | printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
471 | a171fe39 | balrog | |
472 | a171fe39 | balrog | s->ovl2c[0] = value & 0x80ffffff; |
473 | a171fe39 | balrog | s->dma_ch[2].up = !!(value & OVLC1_EN);
|
474 | a171fe39 | balrog | s->dma_ch[3].up = !!(value & OVLC1_EN);
|
475 | a171fe39 | balrog | s->dma_ch[4].up = !!(value & OVLC1_EN);
|
476 | a171fe39 | balrog | break;
|
477 | a171fe39 | balrog | |
478 | a171fe39 | balrog | case OVL2C2:
|
479 | a171fe39 | balrog | s->ovl2c[1] = value & 0x007fffff; |
480 | a171fe39 | balrog | break;
|
481 | a171fe39 | balrog | |
482 | a171fe39 | balrog | case CCR:
|
483 | a171fe39 | balrog | if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
484 | a171fe39 | balrog | printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
485 | a171fe39 | balrog | |
486 | a171fe39 | balrog | s->ccr = value & 0x81ffffe7;
|
487 | a171fe39 | balrog | s->dma_ch[5].up = !!(value & CCR_CEN);
|
488 | a171fe39 | balrog | break;
|
489 | a171fe39 | balrog | |
490 | a171fe39 | balrog | case CMDCR:
|
491 | a171fe39 | balrog | s->cmdcr = value & 0xff;
|
492 | a171fe39 | balrog | break;
|
493 | a171fe39 | balrog | |
494 | a171fe39 | balrog | case TRGBR:
|
495 | a171fe39 | balrog | s->trgbr = value & 0x00ffffff;
|
496 | a171fe39 | balrog | break;
|
497 | a171fe39 | balrog | |
498 | a171fe39 | balrog | case TCR:
|
499 | a171fe39 | balrog | s->tcr = value & 0x7fff;
|
500 | a171fe39 | balrog | break;
|
501 | a171fe39 | balrog | |
502 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
503 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
504 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
505 | a171fe39 | balrog | goto fail;
|
506 | a171fe39 | balrog | |
507 | a171fe39 | balrog | switch (offset & 0xf) { |
508 | a171fe39 | balrog | case DMA_FDADR:
|
509 | a171fe39 | balrog | s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
510 | a171fe39 | balrog | break;
|
511 | a171fe39 | balrog | |
512 | a171fe39 | balrog | default:
|
513 | a171fe39 | balrog | goto fail;
|
514 | a171fe39 | balrog | } |
515 | a171fe39 | balrog | break;
|
516 | a171fe39 | balrog | |
517 | a171fe39 | balrog | case FBR0:
|
518 | a171fe39 | balrog | s->dma_ch[0].branch = value & 0xfffffff3; |
519 | a171fe39 | balrog | break;
|
520 | a171fe39 | balrog | case FBR1:
|
521 | a171fe39 | balrog | s->dma_ch[1].branch = value & 0xfffffff3; |
522 | a171fe39 | balrog | break;
|
523 | a171fe39 | balrog | case FBR2:
|
524 | a171fe39 | balrog | s->dma_ch[2].branch = value & 0xfffffff3; |
525 | a171fe39 | balrog | break;
|
526 | a171fe39 | balrog | case FBR3:
|
527 | a171fe39 | balrog | s->dma_ch[3].branch = value & 0xfffffff3; |
528 | a171fe39 | balrog | break;
|
529 | a171fe39 | balrog | case FBR4:
|
530 | a171fe39 | balrog | s->dma_ch[4].branch = value & 0xfffffff3; |
531 | a171fe39 | balrog | break;
|
532 | a171fe39 | balrog | case FBR5:
|
533 | a171fe39 | balrog | s->dma_ch[5].branch = value & 0xfffffff3; |
534 | a171fe39 | balrog | break;
|
535 | a171fe39 | balrog | case FBR6:
|
536 | a171fe39 | balrog | s->dma_ch[6].branch = value & 0xfffffff3; |
537 | a171fe39 | balrog | break;
|
538 | a171fe39 | balrog | |
539 | a171fe39 | balrog | case BSCNTR:
|
540 | a171fe39 | balrog | s->bscntr = value & 0xf;
|
541 | a171fe39 | balrog | break;
|
542 | a171fe39 | balrog | |
543 | a171fe39 | balrog | case PRSR:
|
544 | a171fe39 | balrog | break;
|
545 | a171fe39 | balrog | |
546 | a171fe39 | balrog | case LCSR0:
|
547 | a171fe39 | balrog | s->status[0] &= ~(value & 0xfff); |
548 | a171fe39 | balrog | if (value & LCSR0_BER)
|
549 | a171fe39 | balrog | s->status[0] &= ~LCSR0_BERCH(7); |
550 | a171fe39 | balrog | break;
|
551 | a171fe39 | balrog | |
552 | a171fe39 | balrog | case LCSR1:
|
553 | a171fe39 | balrog | s->status[1] &= ~(value & 0x3e3f3f); |
554 | a171fe39 | balrog | break;
|
555 | a171fe39 | balrog | |
556 | a171fe39 | balrog | default:
|
557 | a171fe39 | balrog | fail:
|
558 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
559 | a171fe39 | balrog | } |
560 | a171fe39 | balrog | } |
561 | a171fe39 | balrog | |
562 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = { |
563 | a171fe39 | balrog | pxa2xx_lcdc_read, |
564 | a171fe39 | balrog | pxa2xx_lcdc_read, |
565 | a171fe39 | balrog | pxa2xx_lcdc_read |
566 | a171fe39 | balrog | }; |
567 | a171fe39 | balrog | |
568 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = { |
569 | a171fe39 | balrog | pxa2xx_lcdc_write, |
570 | a171fe39 | balrog | pxa2xx_lcdc_write, |
571 | a171fe39 | balrog | pxa2xx_lcdc_write |
572 | a171fe39 | balrog | }; |
573 | a171fe39 | balrog | |
574 | a171fe39 | balrog | /* Load new palette for a given DMA channel, convert to internal format */
|
575 | bc24a225 | Paul Brook | static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp) |
576 | a171fe39 | balrog | { |
577 | a171fe39 | balrog | int i, n, format, r, g, b, alpha;
|
578 | a171fe39 | balrog | uint32_t *dest, *src; |
579 | a171fe39 | balrog | s->pal_for = LCCR4_PALFOR(s->control[4]);
|
580 | a171fe39 | balrog | format = s->pal_for; |
581 | a171fe39 | balrog | |
582 | a171fe39 | balrog | switch (bpp) {
|
583 | a171fe39 | balrog | case pxa_lcdc_2bpp:
|
584 | a171fe39 | balrog | n = 4;
|
585 | a171fe39 | balrog | break;
|
586 | a171fe39 | balrog | case pxa_lcdc_4bpp:
|
587 | a171fe39 | balrog | n = 16;
|
588 | a171fe39 | balrog | break;
|
589 | a171fe39 | balrog | case pxa_lcdc_8bpp:
|
590 | a171fe39 | balrog | n = 256;
|
591 | a171fe39 | balrog | break;
|
592 | a171fe39 | balrog | default:
|
593 | a171fe39 | balrog | format = 0;
|
594 | a171fe39 | balrog | return;
|
595 | a171fe39 | balrog | } |
596 | a171fe39 | balrog | |
597 | a171fe39 | balrog | src = (uint32_t *) s->dma_ch[ch].pbuffer; |
598 | a171fe39 | balrog | dest = (uint32_t *) s->dma_ch[ch].palette; |
599 | a171fe39 | balrog | alpha = r = g = b = 0;
|
600 | a171fe39 | balrog | |
601 | a171fe39 | balrog | for (i = 0; i < n; i ++) { |
602 | a171fe39 | balrog | switch (format) {
|
603 | a171fe39 | balrog | case 0: /* 16 bpp, no transparency */ |
604 | a171fe39 | balrog | alpha = 0;
|
605 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
606 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
607 | a171fe39 | balrog | else {
|
608 | a171fe39 | balrog | r = (*src & 0xf800) >> 8; |
609 | a171fe39 | balrog | g = (*src & 0x07e0) >> 3; |
610 | a171fe39 | balrog | b = (*src & 0x001f) << 3; |
611 | a171fe39 | balrog | } |
612 | a171fe39 | balrog | break;
|
613 | a171fe39 | balrog | case 1: /* 16 bpp plus transparency */ |
614 | a171fe39 | balrog | alpha = *src & (1 << 24); |
615 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
616 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
617 | a171fe39 | balrog | else {
|
618 | a171fe39 | balrog | r = (*src & 0xf800) >> 8; |
619 | a171fe39 | balrog | g = (*src & 0x07e0) >> 3; |
620 | a171fe39 | balrog | b = (*src & 0x001f) << 3; |
621 | a171fe39 | balrog | } |
622 | a171fe39 | balrog | break;
|
623 | a171fe39 | balrog | case 2: /* 18 bpp plus transparency */ |
624 | a171fe39 | balrog | alpha = *src & (1 << 24); |
625 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
626 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
627 | a171fe39 | balrog | else {
|
628 | a171fe39 | balrog | r = (*src & 0xf80000) >> 16; |
629 | a171fe39 | balrog | g = (*src & 0x00fc00) >> 8; |
630 | a171fe39 | balrog | b = (*src & 0x0000f8);
|
631 | a171fe39 | balrog | } |
632 | a171fe39 | balrog | break;
|
633 | a171fe39 | balrog | case 3: /* 24 bpp plus transparency */ |
634 | a171fe39 | balrog | alpha = *src & (1 << 24); |
635 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
636 | a171fe39 | balrog | r = g = b = *src & 0xff;
|
637 | a171fe39 | balrog | else {
|
638 | a171fe39 | balrog | r = (*src & 0xff0000) >> 16; |
639 | a171fe39 | balrog | g = (*src & 0x00ff00) >> 8; |
640 | a171fe39 | balrog | b = (*src & 0x0000ff);
|
641 | a171fe39 | balrog | } |
642 | a171fe39 | balrog | break;
|
643 | a171fe39 | balrog | } |
644 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
645 | a171fe39 | balrog | case 8: |
646 | a171fe39 | balrog | *dest = rgb_to_pixel8(r, g, b) | alpha; |
647 | a171fe39 | balrog | break;
|
648 | a171fe39 | balrog | case 15: |
649 | a171fe39 | balrog | *dest = rgb_to_pixel15(r, g, b) | alpha; |
650 | a171fe39 | balrog | break;
|
651 | a171fe39 | balrog | case 16: |
652 | a171fe39 | balrog | *dest = rgb_to_pixel16(r, g, b) | alpha; |
653 | a171fe39 | balrog | break;
|
654 | a171fe39 | balrog | case 24: |
655 | a171fe39 | balrog | *dest = rgb_to_pixel24(r, g, b) | alpha; |
656 | a171fe39 | balrog | break;
|
657 | a171fe39 | balrog | case 32: |
658 | a171fe39 | balrog | *dest = rgb_to_pixel32(r, g, b) | alpha; |
659 | a171fe39 | balrog | break;
|
660 | a171fe39 | balrog | } |
661 | a171fe39 | balrog | src ++; |
662 | a171fe39 | balrog | dest ++; |
663 | a171fe39 | balrog | } |
664 | a171fe39 | balrog | } |
665 | a171fe39 | balrog | |
666 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s, |
667 | 714fa308 | pbrook | target_phys_addr_t addr, int *miny, int *maxy) |
668 | a171fe39 | balrog | { |
669 | 714fa308 | pbrook | int src_width, dest_width;
|
670 | b9d38e95 | Blue Swirl | drawfn fn = NULL;
|
671 | a171fe39 | balrog | if (s->dest_width)
|
672 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
673 | a171fe39 | balrog | if (!fn)
|
674 | a171fe39 | balrog | return;
|
675 | a171fe39 | balrog | |
676 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
677 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
678 | a171fe39 | balrog | src_width *= 3;
|
679 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
680 | a171fe39 | balrog | src_width *= 4;
|
681 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
682 | a171fe39 | balrog | src_width *= 2;
|
683 | a171fe39 | balrog | |
684 | a171fe39 | balrog | dest_width = s->xres * s->dest_width; |
685 | 714fa308 | pbrook | *miny = 0;
|
686 | 714fa308 | pbrook | framebuffer_update_display(s->ds, |
687 | 714fa308 | pbrook | addr, s->xres, s->yres, |
688 | 714fa308 | pbrook | src_width, dest_width, s->dest_width, |
689 | 714fa308 | pbrook | s->invalidated, |
690 | 714fa308 | pbrook | fn, s->dma_ch[0].palette, miny, maxy);
|
691 | a171fe39 | balrog | } |
692 | a171fe39 | balrog | |
693 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s, |
694 | 714fa308 | pbrook | target_phys_addr_t addr, int *miny, int *maxy) |
695 | a171fe39 | balrog | { |
696 | 714fa308 | pbrook | int src_width, dest_width;
|
697 | b9d38e95 | Blue Swirl | drawfn fn = NULL;
|
698 | a171fe39 | balrog | if (s->dest_width)
|
699 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
700 | a171fe39 | balrog | if (!fn)
|
701 | a171fe39 | balrog | return;
|
702 | a171fe39 | balrog | |
703 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
704 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
705 | a171fe39 | balrog | src_width *= 3;
|
706 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
707 | a171fe39 | balrog | src_width *= 4;
|
708 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
709 | a171fe39 | balrog | src_width *= 2;
|
710 | a171fe39 | balrog | |
711 | a171fe39 | balrog | dest_width = s->yres * s->dest_width; |
712 | 714fa308 | pbrook | *miny = 0;
|
713 | 714fa308 | pbrook | framebuffer_update_display(s->ds, |
714 | 714fa308 | pbrook | addr, s->xres, s->yres, |
715 | 714fa308 | pbrook | src_width, s->dest_width, -dest_width, |
716 | 714fa308 | pbrook | s->invalidated, |
717 | 714fa308 | pbrook | fn, s->dma_ch[0].palette,
|
718 | 714fa308 | pbrook | miny, maxy); |
719 | a171fe39 | balrog | } |
720 | a171fe39 | balrog | |
721 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_resize(PXA2xxLCDState *s) |
722 | a171fe39 | balrog | { |
723 | a171fe39 | balrog | int width, height;
|
724 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
725 | a171fe39 | balrog | return;
|
726 | a171fe39 | balrog | |
727 | a171fe39 | balrog | width = LCCR1_PPL(s->control[1]) + 1; |
728 | a171fe39 | balrog | height = LCCR2_LPP(s->control[2]) + 1; |
729 | a171fe39 | balrog | |
730 | a171fe39 | balrog | if (width != s->xres || height != s->yres) {
|
731 | a171fe39 | balrog | if (s->orientation)
|
732 | 3023f332 | aliguori | qemu_console_resize(s->ds, height, width); |
733 | a171fe39 | balrog | else
|
734 | 3023f332 | aliguori | qemu_console_resize(s->ds, width, height); |
735 | a171fe39 | balrog | s->invalidated = 1;
|
736 | a171fe39 | balrog | s->xres = width; |
737 | a171fe39 | balrog | s->yres = height; |
738 | a171fe39 | balrog | } |
739 | a171fe39 | balrog | } |
740 | a171fe39 | balrog | |
741 | a171fe39 | balrog | static void pxa2xx_update_display(void *opaque) |
742 | a171fe39 | balrog | { |
743 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
744 | a171fe39 | balrog | target_phys_addr_t fbptr; |
745 | a171fe39 | balrog | int miny, maxy;
|
746 | a171fe39 | balrog | int ch;
|
747 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
748 | a171fe39 | balrog | return;
|
749 | a171fe39 | balrog | |
750 | a171fe39 | balrog | pxa2xx_descriptor_load(s); |
751 | a171fe39 | balrog | |
752 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
753 | a171fe39 | balrog | miny = s->yres; |
754 | a171fe39 | balrog | maxy = 0;
|
755 | a171fe39 | balrog | s->transp = s->dma_ch[2].up || s->dma_ch[3].up; |
756 | a171fe39 | balrog | /* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
757 | a171fe39 | balrog | for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++) |
758 | a171fe39 | balrog | if (s->dma_ch[ch].up) {
|
759 | a171fe39 | balrog | if (!s->dma_ch[ch].source) {
|
760 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
761 | a171fe39 | balrog | continue;
|
762 | a171fe39 | balrog | } |
763 | a171fe39 | balrog | fbptr = s->dma_ch[ch].source; |
764 | d95b2f8d | balrog | if (!(fbptr >= PXA2XX_SDRAM_BASE &&
|
765 | b0457b69 | pbrook | fbptr <= PXA2XX_SDRAM_BASE + ram_size)) { |
766 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
767 | a171fe39 | balrog | continue;
|
768 | a171fe39 | balrog | } |
769 | a171fe39 | balrog | |
770 | a171fe39 | balrog | if (s->dma_ch[ch].command & LDCMD_PAL) {
|
771 | 714fa308 | pbrook | cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer, |
772 | 714fa308 | pbrook | MAX(LDCMD_LENGTH(s->dma_ch[ch].command), |
773 | 714fa308 | pbrook | sizeof(s->dma_ch[ch].pbuffer)));
|
774 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
775 | a171fe39 | balrog | } else {
|
776 | a171fe39 | balrog | /* Do we need to reparse palette */
|
777 | a171fe39 | balrog | if (LCCR4_PALFOR(s->control[4]) != s->pal_for) |
778 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
779 | a171fe39 | balrog | |
780 | a171fe39 | balrog | /* ACK frame start */
|
781 | a171fe39 | balrog | pxa2xx_dma_sof_set(s, ch); |
782 | a171fe39 | balrog | |
783 | 714fa308 | pbrook | s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy); |
784 | a171fe39 | balrog | s->invalidated = 0;
|
785 | a171fe39 | balrog | |
786 | a171fe39 | balrog | /* ACK frame completed */
|
787 | a171fe39 | balrog | pxa2xx_dma_eof_set(s, ch); |
788 | a171fe39 | balrog | } |
789 | a171fe39 | balrog | } |
790 | a171fe39 | balrog | |
791 | a171fe39 | balrog | if (s->control[0] & LCCR0_DIS) { |
792 | a171fe39 | balrog | /* ACK last frame completed */
|
793 | a171fe39 | balrog | s->control[0] &= ~LCCR0_ENB;
|
794 | a171fe39 | balrog | s->status[0] |= LCSR0_LDD;
|
795 | a171fe39 | balrog | } |
796 | a171fe39 | balrog | |
797 | 714fa308 | pbrook | if (miny >= 0) { |
798 | 714fa308 | pbrook | if (s->orientation)
|
799 | 714fa308 | pbrook | dpy_update(s->ds, miny, 0, maxy, s->xres);
|
800 | 714fa308 | pbrook | else
|
801 | 714fa308 | pbrook | dpy_update(s->ds, 0, miny, s->xres, maxy);
|
802 | 714fa308 | pbrook | } |
803 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
804 | a171fe39 | balrog | |
805 | 38641a52 | balrog | qemu_irq_raise(s->vsync_cb); |
806 | a171fe39 | balrog | } |
807 | a171fe39 | balrog | |
808 | a171fe39 | balrog | static void pxa2xx_invalidate_display(void *opaque) |
809 | a171fe39 | balrog | { |
810 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
811 | a171fe39 | balrog | s->invalidated = 1;
|
812 | a171fe39 | balrog | } |
813 | a171fe39 | balrog | |
814 | a171fe39 | balrog | static void pxa2xx_screen_dump(void *opaque, const char *filename) |
815 | a171fe39 | balrog | { |
816 | a171fe39 | balrog | /* TODO */
|
817 | a171fe39 | balrog | } |
818 | a171fe39 | balrog | |
819 | 9596ebb7 | pbrook | static void pxa2xx_lcdc_orientation(void *opaque, int angle) |
820 | a171fe39 | balrog | { |
821 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
822 | a171fe39 | balrog | |
823 | a171fe39 | balrog | if (angle) {
|
824 | a171fe39 | balrog | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
|
825 | a171fe39 | balrog | } else {
|
826 | a171fe39 | balrog | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
|
827 | a171fe39 | balrog | } |
828 | a171fe39 | balrog | |
829 | a171fe39 | balrog | s->orientation = angle; |
830 | a171fe39 | balrog | s->xres = s->yres = -1;
|
831 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
832 | a171fe39 | balrog | } |
833 | a171fe39 | balrog | |
834 | aa941b94 | balrog | static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) |
835 | aa941b94 | balrog | { |
836 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
837 | aa941b94 | balrog | int i;
|
838 | aa941b94 | balrog | |
839 | aa941b94 | balrog | qemu_put_be32(f, s->irqlevel); |
840 | aa941b94 | balrog | qemu_put_be32(f, s->transp); |
841 | aa941b94 | balrog | |
842 | aa941b94 | balrog | for (i = 0; i < 6; i ++) |
843 | aa941b94 | balrog | qemu_put_be32s(f, &s->control[i]); |
844 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
845 | aa941b94 | balrog | qemu_put_be32s(f, &s->status[i]); |
846 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
847 | aa941b94 | balrog | qemu_put_be32s(f, &s->ovl1c[i]); |
848 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
849 | aa941b94 | balrog | qemu_put_be32s(f, &s->ovl2c[i]); |
850 | aa941b94 | balrog | qemu_put_be32s(f, &s->ccr); |
851 | aa941b94 | balrog | qemu_put_be32s(f, &s->cmdcr); |
852 | aa941b94 | balrog | qemu_put_be32s(f, &s->trgbr); |
853 | aa941b94 | balrog | qemu_put_be32s(f, &s->tcr); |
854 | aa941b94 | balrog | qemu_put_be32s(f, &s->liidr); |
855 | aa941b94 | balrog | qemu_put_8s(f, &s->bscntr); |
856 | aa941b94 | balrog | |
857 | aa941b94 | balrog | for (i = 0; i < 7; i ++) { |
858 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].branch); |
859 | aa941b94 | balrog | qemu_put_byte(f, s->dma_ch[i].up); |
860 | aa941b94 | balrog | qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
861 | aa941b94 | balrog | |
862 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].descriptor); |
863 | aa941b94 | balrog | qemu_put_betl(f, s->dma_ch[i].source); |
864 | aa941b94 | balrog | qemu_put_be32s(f, &s->dma_ch[i].id); |
865 | aa941b94 | balrog | qemu_put_be32s(f, &s->dma_ch[i].command); |
866 | aa941b94 | balrog | } |
867 | aa941b94 | balrog | } |
868 | aa941b94 | balrog | |
869 | aa941b94 | balrog | static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) |
870 | aa941b94 | balrog | { |
871 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
872 | aa941b94 | balrog | int i;
|
873 | aa941b94 | balrog | |
874 | aa941b94 | balrog | s->irqlevel = qemu_get_be32(f); |
875 | aa941b94 | balrog | s->transp = qemu_get_be32(f); |
876 | aa941b94 | balrog | |
877 | aa941b94 | balrog | for (i = 0; i < 6; i ++) |
878 | aa941b94 | balrog | qemu_get_be32s(f, &s->control[i]); |
879 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
880 | aa941b94 | balrog | qemu_get_be32s(f, &s->status[i]); |
881 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
882 | aa941b94 | balrog | qemu_get_be32s(f, &s->ovl1c[i]); |
883 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
884 | aa941b94 | balrog | qemu_get_be32s(f, &s->ovl2c[i]); |
885 | aa941b94 | balrog | qemu_get_be32s(f, &s->ccr); |
886 | aa941b94 | balrog | qemu_get_be32s(f, &s->cmdcr); |
887 | aa941b94 | balrog | qemu_get_be32s(f, &s->trgbr); |
888 | aa941b94 | balrog | qemu_get_be32s(f, &s->tcr); |
889 | aa941b94 | balrog | qemu_get_be32s(f, &s->liidr); |
890 | aa941b94 | balrog | qemu_get_8s(f, &s->bscntr); |
891 | aa941b94 | balrog | |
892 | aa941b94 | balrog | for (i = 0; i < 7; i ++) { |
893 | aa941b94 | balrog | s->dma_ch[i].branch = qemu_get_betl(f); |
894 | aa941b94 | balrog | s->dma_ch[i].up = qemu_get_byte(f); |
895 | aa941b94 | balrog | qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
896 | aa941b94 | balrog | |
897 | aa941b94 | balrog | s->dma_ch[i].descriptor = qemu_get_betl(f); |
898 | aa941b94 | balrog | s->dma_ch[i].source = qemu_get_betl(f); |
899 | aa941b94 | balrog | qemu_get_be32s(f, &s->dma_ch[i].id); |
900 | aa941b94 | balrog | qemu_get_be32s(f, &s->dma_ch[i].command); |
901 | aa941b94 | balrog | } |
902 | aa941b94 | balrog | |
903 | aa941b94 | balrog | s->bpp = LCCR3_BPP(s->control[3]);
|
904 | aa941b94 | balrog | s->xres = s->yres = s->pal_for = -1;
|
905 | aa941b94 | balrog | |
906 | aa941b94 | balrog | return 0; |
907 | aa941b94 | balrog | } |
908 | aa941b94 | balrog | |
909 | a171fe39 | balrog | #define BITS 8 |
910 | a171fe39 | balrog | #include "pxa2xx_template.h" |
911 | a171fe39 | balrog | #define BITS 15 |
912 | a171fe39 | balrog | #include "pxa2xx_template.h" |
913 | a171fe39 | balrog | #define BITS 16 |
914 | a171fe39 | balrog | #include "pxa2xx_template.h" |
915 | a171fe39 | balrog | #define BITS 24 |
916 | a171fe39 | balrog | #include "pxa2xx_template.h" |
917 | a171fe39 | balrog | #define BITS 32 |
918 | a171fe39 | balrog | #include "pxa2xx_template.h" |
919 | a171fe39 | balrog | |
920 | bc24a225 | Paul Brook | PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) |
921 | a171fe39 | balrog | { |
922 | a171fe39 | balrog | int iomemtype;
|
923 | bc24a225 | Paul Brook | PXA2xxLCDState *s; |
924 | a171fe39 | balrog | |
925 | bc24a225 | Paul Brook | s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
|
926 | a171fe39 | balrog | s->invalidated = 1;
|
927 | a171fe39 | balrog | s->irq = irq; |
928 | a171fe39 | balrog | |
929 | a171fe39 | balrog | pxa2xx_lcdc_orientation(s, graphic_rotate); |
930 | a171fe39 | balrog | |
931 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn, |
932 | a171fe39 | balrog | pxa2xx_lcdc_writefn, s); |
933 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
934 | a171fe39 | balrog | |
935 | 3023f332 | aliguori | s->ds = graphic_console_init(pxa2xx_update_display, |
936 | 3023f332 | aliguori | pxa2xx_invalidate_display, |
937 | 3023f332 | aliguori | pxa2xx_screen_dump, NULL, s);
|
938 | a171fe39 | balrog | |
939 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
940 | a171fe39 | balrog | case 0: |
941 | a171fe39 | balrog | s->dest_width = 0;
|
942 | a171fe39 | balrog | break;
|
943 | a171fe39 | balrog | case 8: |
944 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_8;
|
945 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_8t;
|
946 | a171fe39 | balrog | s->dest_width = 1;
|
947 | a171fe39 | balrog | break;
|
948 | a171fe39 | balrog | case 15: |
949 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_15;
|
950 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_15t;
|
951 | a171fe39 | balrog | s->dest_width = 2;
|
952 | a171fe39 | balrog | break;
|
953 | a171fe39 | balrog | case 16: |
954 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_16;
|
955 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_16t;
|
956 | a171fe39 | balrog | s->dest_width = 2;
|
957 | a171fe39 | balrog | break;
|
958 | a171fe39 | balrog | case 24: |
959 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_24;
|
960 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_24t;
|
961 | a171fe39 | balrog | s->dest_width = 3;
|
962 | a171fe39 | balrog | break;
|
963 | a171fe39 | balrog | case 32: |
964 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_32;
|
965 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_32t;
|
966 | a171fe39 | balrog | s->dest_width = 4;
|
967 | a171fe39 | balrog | break;
|
968 | a171fe39 | balrog | default:
|
969 | a171fe39 | balrog | fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
970 | a171fe39 | balrog | exit(1);
|
971 | a171fe39 | balrog | } |
972 | aa941b94 | balrog | |
973 | aa941b94 | balrog | register_savevm("pxa2xx_lcdc", 0, 0, |
974 | aa941b94 | balrog | pxa2xx_lcdc_save, pxa2xx_lcdc_load, s); |
975 | aa941b94 | balrog | |
976 | a171fe39 | balrog | return s;
|
977 | a171fe39 | balrog | } |
978 | a171fe39 | balrog | |
979 | bc24a225 | Paul Brook | void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
|
980 | 38641a52 | balrog | { |
981 | 38641a52 | balrog | s->vsync_cb = handler; |
982 | a171fe39 | balrog | } |