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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 translation
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 2c0262af | bellard | #include <stdarg.h> |
20 | 2c0262af | bellard | #include <stdlib.h> |
21 | 2c0262af | bellard | #include <stdio.h> |
22 | 2c0262af | bellard | #include <string.h> |
23 | 2c0262af | bellard | #include <inttypes.h> |
24 | 2c0262af | bellard | #include <signal.h> |
25 | 2c0262af | bellard | |
26 | 2c0262af | bellard | #include "cpu.h" |
27 | 2c0262af | bellard | #include "exec-all.h" |
28 | 2c0262af | bellard | #include "disas.h" |
29 | 57fec1fe | bellard | #include "tcg-op.h" |
30 | 2c0262af | bellard | |
31 | a7812ae4 | pbrook | #include "helper.h" |
32 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | |
35 | 2c0262af | bellard | #define PREFIX_REPZ 0x01 |
36 | 2c0262af | bellard | #define PREFIX_REPNZ 0x02 |
37 | 2c0262af | bellard | #define PREFIX_LOCK 0x04 |
38 | 2c0262af | bellard | #define PREFIX_DATA 0x08 |
39 | 2c0262af | bellard | #define PREFIX_ADR 0x10 |
40 | 2c0262af | bellard | |
41 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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42 | 14ce26e7 | bellard | #define X86_64_ONLY(x) x
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43 | 001faf32 | Blue Swirl | #define X86_64_DEF(...) __VA_ARGS__
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44 | 14ce26e7 | bellard | #define CODE64(s) ((s)->code64)
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45 | 14ce26e7 | bellard | #define REX_X(s) ((s)->rex_x)
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46 | 14ce26e7 | bellard | #define REX_B(s) ((s)->rex_b)
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47 | 14ce26e7 | bellard | /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
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48 | 14ce26e7 | bellard | #if 1 |
49 | 14ce26e7 | bellard | #define BUGGY_64(x) NULL |
50 | 14ce26e7 | bellard | #endif
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51 | 14ce26e7 | bellard | #else
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52 | 14ce26e7 | bellard | #define X86_64_ONLY(x) NULL |
53 | 001faf32 | Blue Swirl | #define X86_64_DEF(...)
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54 | 14ce26e7 | bellard | #define CODE64(s) 0 |
55 | 14ce26e7 | bellard | #define REX_X(s) 0 |
56 | 14ce26e7 | bellard | #define REX_B(s) 0 |
57 | 14ce26e7 | bellard | #endif
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58 | 14ce26e7 | bellard | |
59 | 57fec1fe | bellard | //#define MACRO_TEST 1
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60 | 57fec1fe | bellard | |
61 | 57fec1fe | bellard | /* global register indexes */
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62 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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63 | a7812ae4 | pbrook | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
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64 | a7812ae4 | pbrook | static TCGv_i32 cpu_cc_op;
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65 | 1e4840bf | bellard | /* local temps */
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66 | 1e4840bf | bellard | static TCGv cpu_T[2], cpu_T3; |
67 | 57fec1fe | bellard | /* local register indexes (only used inside old micro ops) */
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68 | a7812ae4 | pbrook | static TCGv cpu_tmp0, cpu_tmp4;
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69 | a7812ae4 | pbrook | static TCGv_ptr cpu_ptr0, cpu_ptr1;
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70 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
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71 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp1_i64;
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72 | b6abf97d | bellard | static TCGv cpu_tmp5, cpu_tmp6;
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73 | 57fec1fe | bellard | |
74 | 2e70f6ef | pbrook | #include "gen-icount.h" |
75 | 2e70f6ef | pbrook | |
76 | 57fec1fe | bellard | #ifdef TARGET_X86_64
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77 | 57fec1fe | bellard | static int x86_64_hregs; |
78 | ae063a68 | bellard | #endif
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79 | ae063a68 | bellard | |
80 | 2c0262af | bellard | typedef struct DisasContext { |
81 | 2c0262af | bellard | /* current insn context */
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82 | 2c0262af | bellard | int override; /* -1 if no override */ |
83 | 2c0262af | bellard | int prefix;
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84 | 2c0262af | bellard | int aflag, dflag;
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85 | 14ce26e7 | bellard | target_ulong pc; /* pc = eip + cs_base */
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86 | 2c0262af | bellard | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
87 | 2c0262af | bellard | static state change (stop translation) */
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88 | 2c0262af | bellard | /* current block context */
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89 | 14ce26e7 | bellard | target_ulong cs_base; /* base of CS segment */
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90 | 2c0262af | bellard | int pe; /* protected mode */ |
91 | 2c0262af | bellard | int code32; /* 32 bit code segment */ |
92 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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93 | 14ce26e7 | bellard | int lma; /* long mode active */ |
94 | 14ce26e7 | bellard | int code64; /* 64 bit code segment */ |
95 | 14ce26e7 | bellard | int rex_x, rex_b;
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96 | 14ce26e7 | bellard | #endif
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97 | 2c0262af | bellard | int ss32; /* 32 bit stack segment */ |
98 | 2c0262af | bellard | int cc_op; /* current CC operation */ |
99 | 2c0262af | bellard | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
100 | 2c0262af | bellard | int f_st; /* currently unused */ |
101 | 2c0262af | bellard | int vm86; /* vm86 mode */ |
102 | 2c0262af | bellard | int cpl;
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103 | 2c0262af | bellard | int iopl;
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104 | 2c0262af | bellard | int tf; /* TF cpu flag */ |
105 | 34865134 | bellard | int singlestep_enabled; /* "hardware" single step enabled */ |
106 | 2c0262af | bellard | int jmp_opt; /* use direct block chaining for direct jumps */ |
107 | 2c0262af | bellard | int mem_index; /* select memory access functions */ |
108 | c068688b | j_mayer | uint64_t flags; /* all execution flags */
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109 | 2c0262af | bellard | struct TranslationBlock *tb;
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110 | 2c0262af | bellard | int popl_esp_hack; /* for correct popl with esp base handling */ |
111 | 14ce26e7 | bellard | int rip_offset; /* only used in x86_64, but left for simplicity */ |
112 | 14ce26e7 | bellard | int cpuid_features;
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113 | 3d7374c5 | bellard | int cpuid_ext_features;
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114 | e771edab | aurel32 | int cpuid_ext2_features;
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115 | 12e26b75 | bellard | int cpuid_ext3_features;
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116 | 2c0262af | bellard | } DisasContext; |
117 | 2c0262af | bellard | |
118 | 2c0262af | bellard | static void gen_eob(DisasContext *s); |
119 | 14ce26e7 | bellard | static void gen_jmp(DisasContext *s, target_ulong eip); |
120 | 14ce26e7 | bellard | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); |
121 | 2c0262af | bellard | |
122 | 2c0262af | bellard | /* i386 arith/logic operations */
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123 | 2c0262af | bellard | enum {
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124 | 5fafdf24 | ths | OP_ADDL, |
125 | 5fafdf24 | ths | OP_ORL, |
126 | 5fafdf24 | ths | OP_ADCL, |
127 | 2c0262af | bellard | OP_SBBL, |
128 | 5fafdf24 | ths | OP_ANDL, |
129 | 5fafdf24 | ths | OP_SUBL, |
130 | 5fafdf24 | ths | OP_XORL, |
131 | 2c0262af | bellard | OP_CMPL, |
132 | 2c0262af | bellard | }; |
133 | 2c0262af | bellard | |
134 | 2c0262af | bellard | /* i386 shift ops */
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135 | 2c0262af | bellard | enum {
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136 | 5fafdf24 | ths | OP_ROL, |
137 | 5fafdf24 | ths | OP_ROR, |
138 | 5fafdf24 | ths | OP_RCL, |
139 | 5fafdf24 | ths | OP_RCR, |
140 | 5fafdf24 | ths | OP_SHL, |
141 | 5fafdf24 | ths | OP_SHR, |
142 | 2c0262af | bellard | OP_SHL1, /* undocumented */
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143 | 2c0262af | bellard | OP_SAR = 7,
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144 | 2c0262af | bellard | }; |
145 | 2c0262af | bellard | |
146 | 8e1c85e3 | bellard | enum {
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147 | 8e1c85e3 | bellard | JCC_O, |
148 | 8e1c85e3 | bellard | JCC_B, |
149 | 8e1c85e3 | bellard | JCC_Z, |
150 | 8e1c85e3 | bellard | JCC_BE, |
151 | 8e1c85e3 | bellard | JCC_S, |
152 | 8e1c85e3 | bellard | JCC_P, |
153 | 8e1c85e3 | bellard | JCC_L, |
154 | 8e1c85e3 | bellard | JCC_LE, |
155 | 8e1c85e3 | bellard | }; |
156 | 8e1c85e3 | bellard | |
157 | 2c0262af | bellard | /* operand size */
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158 | 2c0262af | bellard | enum {
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159 | 2c0262af | bellard | OT_BYTE = 0,
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160 | 2c0262af | bellard | OT_WORD, |
161 | 5fafdf24 | ths | OT_LONG, |
162 | 2c0262af | bellard | OT_QUAD, |
163 | 2c0262af | bellard | }; |
164 | 2c0262af | bellard | |
165 | 2c0262af | bellard | enum {
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166 | 2c0262af | bellard | /* I386 int registers */
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167 | 2c0262af | bellard | OR_EAX, /* MUST be even numbered */
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168 | 2c0262af | bellard | OR_ECX, |
169 | 2c0262af | bellard | OR_EDX, |
170 | 2c0262af | bellard | OR_EBX, |
171 | 2c0262af | bellard | OR_ESP, |
172 | 2c0262af | bellard | OR_EBP, |
173 | 2c0262af | bellard | OR_ESI, |
174 | 2c0262af | bellard | OR_EDI, |
175 | 14ce26e7 | bellard | |
176 | 14ce26e7 | bellard | OR_TMP0 = 16, /* temporary operand register */ |
177 | 2c0262af | bellard | OR_TMP1, |
178 | 2c0262af | bellard | OR_A0, /* temporary register used when doing address evaluation */
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179 | 2c0262af | bellard | }; |
180 | 2c0262af | bellard | |
181 | 57fec1fe | bellard | static inline void gen_op_movl_T0_0(void) |
182 | 57fec1fe | bellard | { |
183 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], 0); |
184 | 57fec1fe | bellard | } |
185 | 57fec1fe | bellard | |
186 | 57fec1fe | bellard | static inline void gen_op_movl_T0_im(int32_t val) |
187 | 57fec1fe | bellard | { |
188 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
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189 | 57fec1fe | bellard | } |
190 | 57fec1fe | bellard | |
191 | 57fec1fe | bellard | static inline void gen_op_movl_T0_imu(uint32_t val) |
192 | 57fec1fe | bellard | { |
193 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
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194 | 57fec1fe | bellard | } |
195 | 57fec1fe | bellard | |
196 | 57fec1fe | bellard | static inline void gen_op_movl_T1_im(int32_t val) |
197 | 57fec1fe | bellard | { |
198 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
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199 | 57fec1fe | bellard | } |
200 | 57fec1fe | bellard | |
201 | 57fec1fe | bellard | static inline void gen_op_movl_T1_imu(uint32_t val) |
202 | 57fec1fe | bellard | { |
203 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
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204 | 57fec1fe | bellard | } |
205 | 57fec1fe | bellard | |
206 | 57fec1fe | bellard | static inline void gen_op_movl_A0_im(uint32_t val) |
207 | 57fec1fe | bellard | { |
208 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_A0, val); |
209 | 57fec1fe | bellard | } |
210 | 57fec1fe | bellard | |
211 | 57fec1fe | bellard | #ifdef TARGET_X86_64
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212 | 57fec1fe | bellard | static inline void gen_op_movq_A0_im(int64_t val) |
213 | 57fec1fe | bellard | { |
214 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_A0, val); |
215 | 57fec1fe | bellard | } |
216 | 57fec1fe | bellard | #endif
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217 | 57fec1fe | bellard | |
218 | 57fec1fe | bellard | static inline void gen_movtl_T0_im(target_ulong val) |
219 | 57fec1fe | bellard | { |
220 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
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221 | 57fec1fe | bellard | } |
222 | 57fec1fe | bellard | |
223 | 57fec1fe | bellard | static inline void gen_movtl_T1_im(target_ulong val) |
224 | 57fec1fe | bellard | { |
225 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
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226 | 57fec1fe | bellard | } |
227 | 57fec1fe | bellard | |
228 | 57fec1fe | bellard | static inline void gen_op_andl_T0_ffff(void) |
229 | 57fec1fe | bellard | { |
230 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
231 | 57fec1fe | bellard | } |
232 | 57fec1fe | bellard | |
233 | 57fec1fe | bellard | static inline void gen_op_andl_T0_im(uint32_t val) |
234 | 57fec1fe | bellard | { |
235 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); |
236 | 57fec1fe | bellard | } |
237 | 57fec1fe | bellard | |
238 | 57fec1fe | bellard | static inline void gen_op_movl_T0_T1(void) |
239 | 57fec1fe | bellard | { |
240 | 57fec1fe | bellard | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
241 | 57fec1fe | bellard | } |
242 | 57fec1fe | bellard | |
243 | 57fec1fe | bellard | static inline void gen_op_andl_A0_ffff(void) |
244 | 57fec1fe | bellard | { |
245 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
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246 | 57fec1fe | bellard | } |
247 | 57fec1fe | bellard | |
248 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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249 | 14ce26e7 | bellard | |
250 | 14ce26e7 | bellard | #define NB_OP_SIZES 4 |
251 | 14ce26e7 | bellard | |
252 | 14ce26e7 | bellard | #else /* !TARGET_X86_64 */ |
253 | 14ce26e7 | bellard | |
254 | 14ce26e7 | bellard | #define NB_OP_SIZES 3 |
255 | 14ce26e7 | bellard | |
256 | 14ce26e7 | bellard | #endif /* !TARGET_X86_64 */ |
257 | 14ce26e7 | bellard | |
258 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN)
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259 | 57fec1fe | bellard | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
260 | 57fec1fe | bellard | #define REG_H_OFFSET (sizeof(target_ulong) - 2) |
261 | 57fec1fe | bellard | #define REG_W_OFFSET (sizeof(target_ulong) - 2) |
262 | 57fec1fe | bellard | #define REG_L_OFFSET (sizeof(target_ulong) - 4) |
263 | 57fec1fe | bellard | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) |
264 | 14ce26e7 | bellard | #else
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265 | 57fec1fe | bellard | #define REG_B_OFFSET 0 |
266 | 57fec1fe | bellard | #define REG_H_OFFSET 1 |
267 | 57fec1fe | bellard | #define REG_W_OFFSET 0 |
268 | 57fec1fe | bellard | #define REG_L_OFFSET 0 |
269 | 57fec1fe | bellard | #define REG_LH_OFFSET 4 |
270 | 14ce26e7 | bellard | #endif
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271 | 57fec1fe | bellard | |
272 | 1e4840bf | bellard | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
273 | 57fec1fe | bellard | { |
274 | 57fec1fe | bellard | switch(ot) {
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275 | 57fec1fe | bellard | case OT_BYTE:
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276 | 57fec1fe | bellard | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { |
277 | 1e4840bf | bellard | tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); |
278 | 57fec1fe | bellard | } else {
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279 | 1e4840bf | bellard | tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
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280 | 57fec1fe | bellard | } |
281 | 57fec1fe | bellard | break;
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282 | 57fec1fe | bellard | case OT_WORD:
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283 | 1e4840bf | bellard | tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
284 | 57fec1fe | bellard | break;
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285 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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286 | 57fec1fe | bellard | case OT_LONG:
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287 | 1e4840bf | bellard | tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
288 | 57fec1fe | bellard | /* high part of register set to zero */
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289 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, 0);
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290 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); |
291 | 57fec1fe | bellard | break;
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292 | 57fec1fe | bellard | default:
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293 | 57fec1fe | bellard | case OT_QUAD:
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294 | 1e4840bf | bellard | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); |
295 | 57fec1fe | bellard | break;
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296 | 57fec1fe | bellard | #else
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297 | 57fec1fe | bellard | default:
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298 | 57fec1fe | bellard | case OT_LONG:
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299 | 1e4840bf | bellard | tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
300 | 57fec1fe | bellard | break;
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301 | 14ce26e7 | bellard | #endif
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302 | 57fec1fe | bellard | } |
303 | 57fec1fe | bellard | } |
304 | 2c0262af | bellard | |
305 | 57fec1fe | bellard | static inline void gen_op_mov_reg_T0(int ot, int reg) |
306 | 57fec1fe | bellard | { |
307 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, reg, cpu_T[0]);
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308 | 57fec1fe | bellard | } |
309 | 57fec1fe | bellard | |
310 | 57fec1fe | bellard | static inline void gen_op_mov_reg_T1(int ot, int reg) |
311 | 57fec1fe | bellard | { |
312 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, reg, cpu_T[1]);
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313 | 57fec1fe | bellard | } |
314 | 57fec1fe | bellard | |
315 | 57fec1fe | bellard | static inline void gen_op_mov_reg_A0(int size, int reg) |
316 | 57fec1fe | bellard | { |
317 | 57fec1fe | bellard | switch(size) {
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318 | 57fec1fe | bellard | case 0: |
319 | 57fec1fe | bellard | tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
320 | 57fec1fe | bellard | break;
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321 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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322 | 57fec1fe | bellard | case 1: |
323 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
324 | 57fec1fe | bellard | /* high part of register set to zero */
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325 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, 0);
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326 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); |
327 | 57fec1fe | bellard | break;
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328 | 57fec1fe | bellard | default:
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329 | 57fec1fe | bellard | case 2: |
330 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); |
331 | 57fec1fe | bellard | break;
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332 | 14ce26e7 | bellard | #else
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333 | 57fec1fe | bellard | default:
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334 | 57fec1fe | bellard | case 1: |
335 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
336 | 57fec1fe | bellard | break;
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337 | 14ce26e7 | bellard | #endif
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338 | 57fec1fe | bellard | } |
339 | 57fec1fe | bellard | } |
340 | 57fec1fe | bellard | |
341 | 1e4840bf | bellard | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
342 | 57fec1fe | bellard | { |
343 | 57fec1fe | bellard | switch(ot) {
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344 | 57fec1fe | bellard | case OT_BYTE:
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345 | 57fec1fe | bellard | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { |
346 | 57fec1fe | bellard | goto std_case;
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347 | 57fec1fe | bellard | } else {
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348 | 1e4840bf | bellard | tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
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349 | 57fec1fe | bellard | } |
350 | 57fec1fe | bellard | break;
|
351 | 57fec1fe | bellard | default:
|
352 | 57fec1fe | bellard | std_case:
|
353 | 1e4840bf | bellard | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); |
354 | 57fec1fe | bellard | break;
|
355 | 57fec1fe | bellard | } |
356 | 57fec1fe | bellard | } |
357 | 57fec1fe | bellard | |
358 | 1e4840bf | bellard | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
359 | 1e4840bf | bellard | { |
360 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); |
361 | 1e4840bf | bellard | } |
362 | 1e4840bf | bellard | |
363 | 57fec1fe | bellard | static inline void gen_op_movl_A0_reg(int reg) |
364 | 57fec1fe | bellard | { |
365 | 57fec1fe | bellard | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
366 | 57fec1fe | bellard | } |
367 | 57fec1fe | bellard | |
368 | 57fec1fe | bellard | static inline void gen_op_addl_A0_im(int32_t val) |
369 | 57fec1fe | bellard | { |
370 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); |
371 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
372 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
373 | 14ce26e7 | bellard | #endif
|
374 | 57fec1fe | bellard | } |
375 | 2c0262af | bellard | |
376 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
377 | 57fec1fe | bellard | static inline void gen_op_addq_A0_im(int64_t val) |
378 | 57fec1fe | bellard | { |
379 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); |
380 | 57fec1fe | bellard | } |
381 | 14ce26e7 | bellard | #endif
|
382 | 57fec1fe | bellard | |
383 | 57fec1fe | bellard | static void gen_add_A0_im(DisasContext *s, int val) |
384 | 57fec1fe | bellard | { |
385 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
386 | 57fec1fe | bellard | if (CODE64(s))
|
387 | 57fec1fe | bellard | gen_op_addq_A0_im(val); |
388 | 57fec1fe | bellard | else
|
389 | 57fec1fe | bellard | #endif
|
390 | 57fec1fe | bellard | gen_op_addl_A0_im(val); |
391 | 57fec1fe | bellard | } |
392 | 2c0262af | bellard | |
393 | 57fec1fe | bellard | static inline void gen_op_addl_T0_T1(void) |
394 | 2c0262af | bellard | { |
395 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
396 | 57fec1fe | bellard | } |
397 | 57fec1fe | bellard | |
398 | 57fec1fe | bellard | static inline void gen_op_jmp_T0(void) |
399 | 57fec1fe | bellard | { |
400 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
|
401 | 57fec1fe | bellard | } |
402 | 57fec1fe | bellard | |
403 | 6e0d8677 | bellard | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
404 | 57fec1fe | bellard | { |
405 | 6e0d8677 | bellard | switch(size) {
|
406 | 6e0d8677 | bellard | case 0: |
407 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
408 | 6e0d8677 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
409 | 6e0d8677 | bellard | tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
410 | 6e0d8677 | bellard | break;
|
411 | 6e0d8677 | bellard | case 1: |
412 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
413 | 6e0d8677 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
414 | 6e0d8677 | bellard | #ifdef TARGET_X86_64
|
415 | 6e0d8677 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
|
416 | 6e0d8677 | bellard | #endif
|
417 | 6e0d8677 | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
418 | 6e0d8677 | bellard | break;
|
419 | 6e0d8677 | bellard | #ifdef TARGET_X86_64
|
420 | 6e0d8677 | bellard | case 2: |
421 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
422 | 6e0d8677 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
423 | 6e0d8677 | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
424 | 6e0d8677 | bellard | break;
|
425 | 6e0d8677 | bellard | #endif
|
426 | 6e0d8677 | bellard | } |
427 | 57fec1fe | bellard | } |
428 | 57fec1fe | bellard | |
429 | 6e0d8677 | bellard | static inline void gen_op_add_reg_T0(int size, int reg) |
430 | 57fec1fe | bellard | { |
431 | 6e0d8677 | bellard | switch(size) {
|
432 | 6e0d8677 | bellard | case 0: |
433 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
434 | 6e0d8677 | bellard | tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
|
435 | 6e0d8677 | bellard | tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
436 | 6e0d8677 | bellard | break;
|
437 | 6e0d8677 | bellard | case 1: |
438 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
439 | 6e0d8677 | bellard | tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
|
440 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
441 | 6e0d8677 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
|
442 | 14ce26e7 | bellard | #endif
|
443 | 6e0d8677 | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
444 | 6e0d8677 | bellard | break;
|
445 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
446 | 6e0d8677 | bellard | case 2: |
447 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
448 | 6e0d8677 | bellard | tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
|
449 | 6e0d8677 | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
450 | 6e0d8677 | bellard | break;
|
451 | 14ce26e7 | bellard | #endif
|
452 | 6e0d8677 | bellard | } |
453 | 6e0d8677 | bellard | } |
454 | 57fec1fe | bellard | |
455 | 57fec1fe | bellard | static inline void gen_op_set_cc_op(int32_t val) |
456 | 57fec1fe | bellard | { |
457 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, val); |
458 | 57fec1fe | bellard | } |
459 | 57fec1fe | bellard | |
460 | 57fec1fe | bellard | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
461 | 57fec1fe | bellard | { |
462 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
463 | 57fec1fe | bellard | if (shift != 0) |
464 | 57fec1fe | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
465 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
466 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
467 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
468 | 14ce26e7 | bellard | #endif
|
469 | 57fec1fe | bellard | } |
470 | 2c0262af | bellard | |
471 | 57fec1fe | bellard | static inline void gen_op_movl_A0_seg(int reg) |
472 | 57fec1fe | bellard | { |
473 | 57fec1fe | bellard | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET); |
474 | 57fec1fe | bellard | } |
475 | 2c0262af | bellard | |
476 | 57fec1fe | bellard | static inline void gen_op_addl_A0_seg(int reg) |
477 | 57fec1fe | bellard | { |
478 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); |
479 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
480 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
481 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
482 | 57fec1fe | bellard | #endif
|
483 | 57fec1fe | bellard | } |
484 | 2c0262af | bellard | |
485 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
486 | 57fec1fe | bellard | static inline void gen_op_movq_A0_seg(int reg) |
487 | 57fec1fe | bellard | { |
488 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); |
489 | 57fec1fe | bellard | } |
490 | 14ce26e7 | bellard | |
491 | 57fec1fe | bellard | static inline void gen_op_addq_A0_seg(int reg) |
492 | 57fec1fe | bellard | { |
493 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); |
494 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
495 | 57fec1fe | bellard | } |
496 | 57fec1fe | bellard | |
497 | 57fec1fe | bellard | static inline void gen_op_movq_A0_reg(int reg) |
498 | 57fec1fe | bellard | { |
499 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); |
500 | 57fec1fe | bellard | } |
501 | 57fec1fe | bellard | |
502 | 57fec1fe | bellard | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) |
503 | 57fec1fe | bellard | { |
504 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
505 | 57fec1fe | bellard | if (shift != 0) |
506 | 57fec1fe | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
507 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
508 | 57fec1fe | bellard | } |
509 | 14ce26e7 | bellard | #endif
|
510 | 14ce26e7 | bellard | |
511 | 57fec1fe | bellard | static inline void gen_op_lds_T0_A0(int idx) |
512 | 57fec1fe | bellard | { |
513 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
514 | 57fec1fe | bellard | switch(idx & 3) { |
515 | 57fec1fe | bellard | case 0: |
516 | 57fec1fe | bellard | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
|
517 | 57fec1fe | bellard | break;
|
518 | 57fec1fe | bellard | case 1: |
519 | 57fec1fe | bellard | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
|
520 | 57fec1fe | bellard | break;
|
521 | 57fec1fe | bellard | default:
|
522 | 57fec1fe | bellard | case 2: |
523 | 57fec1fe | bellard | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
|
524 | 57fec1fe | bellard | break;
|
525 | 57fec1fe | bellard | } |
526 | 57fec1fe | bellard | } |
527 | 2c0262af | bellard | |
528 | 1e4840bf | bellard | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
529 | 57fec1fe | bellard | { |
530 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
531 | 57fec1fe | bellard | switch(idx & 3) { |
532 | 57fec1fe | bellard | case 0: |
533 | 1e4840bf | bellard | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
534 | 57fec1fe | bellard | break;
|
535 | 57fec1fe | bellard | case 1: |
536 | 1e4840bf | bellard | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
537 | 57fec1fe | bellard | break;
|
538 | 57fec1fe | bellard | case 2: |
539 | 1e4840bf | bellard | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
540 | 57fec1fe | bellard | break;
|
541 | 57fec1fe | bellard | default:
|
542 | 57fec1fe | bellard | case 3: |
543 | a7812ae4 | pbrook | /* Should never happen on 32-bit targets. */
|
544 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
545 | 1e4840bf | bellard | tcg_gen_qemu_ld64(t0, a0, mem_index); |
546 | a7812ae4 | pbrook | #endif
|
547 | 57fec1fe | bellard | break;
|
548 | 57fec1fe | bellard | } |
549 | 57fec1fe | bellard | } |
550 | 2c0262af | bellard | |
551 | 1e4840bf | bellard | /* XXX: always use ldu or lds */
|
552 | 1e4840bf | bellard | static inline void gen_op_ld_T0_A0(int idx) |
553 | 1e4840bf | bellard | { |
554 | 1e4840bf | bellard | gen_op_ld_v(idx, cpu_T[0], cpu_A0);
|
555 | 1e4840bf | bellard | } |
556 | 1e4840bf | bellard | |
557 | 57fec1fe | bellard | static inline void gen_op_ldu_T0_A0(int idx) |
558 | 57fec1fe | bellard | { |
559 | 1e4840bf | bellard | gen_op_ld_v(idx, cpu_T[0], cpu_A0);
|
560 | 57fec1fe | bellard | } |
561 | 2c0262af | bellard | |
562 | 57fec1fe | bellard | static inline void gen_op_ld_T1_A0(int idx) |
563 | 57fec1fe | bellard | { |
564 | 1e4840bf | bellard | gen_op_ld_v(idx, cpu_T[1], cpu_A0);
|
565 | 1e4840bf | bellard | } |
566 | 1e4840bf | bellard | |
567 | 1e4840bf | bellard | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) |
568 | 1e4840bf | bellard | { |
569 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
570 | 57fec1fe | bellard | switch(idx & 3) { |
571 | 57fec1fe | bellard | case 0: |
572 | 1e4840bf | bellard | tcg_gen_qemu_st8(t0, a0, mem_index); |
573 | 57fec1fe | bellard | break;
|
574 | 57fec1fe | bellard | case 1: |
575 | 1e4840bf | bellard | tcg_gen_qemu_st16(t0, a0, mem_index); |
576 | 57fec1fe | bellard | break;
|
577 | 57fec1fe | bellard | case 2: |
578 | 1e4840bf | bellard | tcg_gen_qemu_st32(t0, a0, mem_index); |
579 | 57fec1fe | bellard | break;
|
580 | 57fec1fe | bellard | default:
|
581 | 57fec1fe | bellard | case 3: |
582 | a7812ae4 | pbrook | /* Should never happen on 32-bit targets. */
|
583 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
584 | 1e4840bf | bellard | tcg_gen_qemu_st64(t0, a0, mem_index); |
585 | a7812ae4 | pbrook | #endif
|
586 | 57fec1fe | bellard | break;
|
587 | 57fec1fe | bellard | } |
588 | 57fec1fe | bellard | } |
589 | 4f31916f | bellard | |
590 | 57fec1fe | bellard | static inline void gen_op_st_T0_A0(int idx) |
591 | 57fec1fe | bellard | { |
592 | 1e4840bf | bellard | gen_op_st_v(idx, cpu_T[0], cpu_A0);
|
593 | 57fec1fe | bellard | } |
594 | 4f31916f | bellard | |
595 | 57fec1fe | bellard | static inline void gen_op_st_T1_A0(int idx) |
596 | 57fec1fe | bellard | { |
597 | 1e4840bf | bellard | gen_op_st_v(idx, cpu_T[1], cpu_A0);
|
598 | 57fec1fe | bellard | } |
599 | 4f31916f | bellard | |
600 | 14ce26e7 | bellard | static inline void gen_jmp_im(target_ulong pc) |
601 | 14ce26e7 | bellard | { |
602 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, pc); |
603 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); |
604 | 14ce26e7 | bellard | } |
605 | 14ce26e7 | bellard | |
606 | 2c0262af | bellard | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
607 | 2c0262af | bellard | { |
608 | 2c0262af | bellard | int override;
|
609 | 2c0262af | bellard | |
610 | 2c0262af | bellard | override = s->override; |
611 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
612 | 14ce26e7 | bellard | if (s->aflag == 2) { |
613 | 14ce26e7 | bellard | if (override >= 0) { |
614 | 57fec1fe | bellard | gen_op_movq_A0_seg(override); |
615 | 57fec1fe | bellard | gen_op_addq_A0_reg_sN(0, R_ESI);
|
616 | 14ce26e7 | bellard | } else {
|
617 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESI); |
618 | 14ce26e7 | bellard | } |
619 | 14ce26e7 | bellard | } else
|
620 | 14ce26e7 | bellard | #endif
|
621 | 2c0262af | bellard | if (s->aflag) {
|
622 | 2c0262af | bellard | /* 32 bit address */
|
623 | 2c0262af | bellard | if (s->addseg && override < 0) |
624 | 2c0262af | bellard | override = R_DS; |
625 | 2c0262af | bellard | if (override >= 0) { |
626 | 57fec1fe | bellard | gen_op_movl_A0_seg(override); |
627 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
628 | 2c0262af | bellard | } else {
|
629 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
630 | 2c0262af | bellard | } |
631 | 2c0262af | bellard | } else {
|
632 | 2c0262af | bellard | /* 16 address, always override */
|
633 | 2c0262af | bellard | if (override < 0) |
634 | 2c0262af | bellard | override = R_DS; |
635 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
636 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
637 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
638 | 2c0262af | bellard | } |
639 | 2c0262af | bellard | } |
640 | 2c0262af | bellard | |
641 | 2c0262af | bellard | static inline void gen_string_movl_A0_EDI(DisasContext *s) |
642 | 2c0262af | bellard | { |
643 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
644 | 14ce26e7 | bellard | if (s->aflag == 2) { |
645 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_EDI); |
646 | 14ce26e7 | bellard | } else
|
647 | 14ce26e7 | bellard | #endif
|
648 | 2c0262af | bellard | if (s->aflag) {
|
649 | 2c0262af | bellard | if (s->addseg) {
|
650 | 57fec1fe | bellard | gen_op_movl_A0_seg(R_ES); |
651 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
652 | 2c0262af | bellard | } else {
|
653 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
654 | 2c0262af | bellard | } |
655 | 2c0262af | bellard | } else {
|
656 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
657 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
658 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_ES); |
659 | 2c0262af | bellard | } |
660 | 2c0262af | bellard | } |
661 | 2c0262af | bellard | |
662 | 6e0d8677 | bellard | static inline void gen_op_movl_T0_Dshift(int ot) |
663 | 6e0d8677 | bellard | { |
664 | 6e0d8677 | bellard | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
|
665 | 6e0d8677 | bellard | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
666 | 2c0262af | bellard | }; |
667 | 2c0262af | bellard | |
668 | 6e0d8677 | bellard | static void gen_extu(int ot, TCGv reg) |
669 | 6e0d8677 | bellard | { |
670 | 6e0d8677 | bellard | switch(ot) {
|
671 | 6e0d8677 | bellard | case OT_BYTE:
|
672 | 6e0d8677 | bellard | tcg_gen_ext8u_tl(reg, reg); |
673 | 6e0d8677 | bellard | break;
|
674 | 6e0d8677 | bellard | case OT_WORD:
|
675 | 6e0d8677 | bellard | tcg_gen_ext16u_tl(reg, reg); |
676 | 6e0d8677 | bellard | break;
|
677 | 6e0d8677 | bellard | case OT_LONG:
|
678 | 6e0d8677 | bellard | tcg_gen_ext32u_tl(reg, reg); |
679 | 6e0d8677 | bellard | break;
|
680 | 6e0d8677 | bellard | default:
|
681 | 6e0d8677 | bellard | break;
|
682 | 6e0d8677 | bellard | } |
683 | 6e0d8677 | bellard | } |
684 | 3b46e624 | ths | |
685 | 6e0d8677 | bellard | static void gen_exts(int ot, TCGv reg) |
686 | 6e0d8677 | bellard | { |
687 | 6e0d8677 | bellard | switch(ot) {
|
688 | 6e0d8677 | bellard | case OT_BYTE:
|
689 | 6e0d8677 | bellard | tcg_gen_ext8s_tl(reg, reg); |
690 | 6e0d8677 | bellard | break;
|
691 | 6e0d8677 | bellard | case OT_WORD:
|
692 | 6e0d8677 | bellard | tcg_gen_ext16s_tl(reg, reg); |
693 | 6e0d8677 | bellard | break;
|
694 | 6e0d8677 | bellard | case OT_LONG:
|
695 | 6e0d8677 | bellard | tcg_gen_ext32s_tl(reg, reg); |
696 | 6e0d8677 | bellard | break;
|
697 | 6e0d8677 | bellard | default:
|
698 | 6e0d8677 | bellard | break;
|
699 | 6e0d8677 | bellard | } |
700 | 6e0d8677 | bellard | } |
701 | 2c0262af | bellard | |
702 | 6e0d8677 | bellard | static inline void gen_op_jnz_ecx(int size, int label1) |
703 | 6e0d8677 | bellard | { |
704 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); |
705 | 6e0d8677 | bellard | gen_extu(size + 1, cpu_tmp0);
|
706 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
|
707 | 6e0d8677 | bellard | } |
708 | 6e0d8677 | bellard | |
709 | 6e0d8677 | bellard | static inline void gen_op_jz_ecx(int size, int label1) |
710 | 6e0d8677 | bellard | { |
711 | 6e0d8677 | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); |
712 | 6e0d8677 | bellard | gen_extu(size + 1, cpu_tmp0);
|
713 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
|
714 | 6e0d8677 | bellard | } |
715 | 2c0262af | bellard | |
716 | a7812ae4 | pbrook | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
717 | a7812ae4 | pbrook | { |
718 | a7812ae4 | pbrook | switch (ot) {
|
719 | a7812ae4 | pbrook | case 0: gen_helper_inb(v, n); break; |
720 | a7812ae4 | pbrook | case 1: gen_helper_inw(v, n); break; |
721 | a7812ae4 | pbrook | case 2: gen_helper_inl(v, n); break; |
722 | a7812ae4 | pbrook | } |
723 | 2c0262af | bellard | |
724 | a7812ae4 | pbrook | } |
725 | 2c0262af | bellard | |
726 | a7812ae4 | pbrook | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
727 | a7812ae4 | pbrook | { |
728 | a7812ae4 | pbrook | switch (ot) {
|
729 | a7812ae4 | pbrook | case 0: gen_helper_outb(v, n); break; |
730 | a7812ae4 | pbrook | case 1: gen_helper_outw(v, n); break; |
731 | a7812ae4 | pbrook | case 2: gen_helper_outl(v, n); break; |
732 | a7812ae4 | pbrook | } |
733 | a7812ae4 | pbrook | |
734 | a7812ae4 | pbrook | } |
735 | f115e911 | bellard | |
736 | b8b6a50b | bellard | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
737 | b8b6a50b | bellard | uint32_t svm_flags) |
738 | f115e911 | bellard | { |
739 | b8b6a50b | bellard | int state_saved;
|
740 | b8b6a50b | bellard | target_ulong next_eip; |
741 | b8b6a50b | bellard | |
742 | b8b6a50b | bellard | state_saved = 0;
|
743 | f115e911 | bellard | if (s->pe && (s->cpl > s->iopl || s->vm86)) {
|
744 | f115e911 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
745 | f115e911 | bellard | gen_op_set_cc_op(s->cc_op); |
746 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
747 | b8b6a50b | bellard | state_saved = 1;
|
748 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
749 | a7812ae4 | pbrook | switch (ot) {
|
750 | a7812ae4 | pbrook | case 0: gen_helper_check_iob(cpu_tmp2_i32); break; |
751 | a7812ae4 | pbrook | case 1: gen_helper_check_iow(cpu_tmp2_i32); break; |
752 | a7812ae4 | pbrook | case 2: gen_helper_check_iol(cpu_tmp2_i32); break; |
753 | a7812ae4 | pbrook | } |
754 | b8b6a50b | bellard | } |
755 | 872929aa | bellard | if(s->flags & HF_SVMI_MASK) {
|
756 | b8b6a50b | bellard | if (!state_saved) {
|
757 | b8b6a50b | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
758 | b8b6a50b | bellard | gen_op_set_cc_op(s->cc_op); |
759 | b8b6a50b | bellard | gen_jmp_im(cur_eip); |
760 | b8b6a50b | bellard | state_saved = 1;
|
761 | b8b6a50b | bellard | } |
762 | b8b6a50b | bellard | svm_flags |= (1 << (4 + ot)); |
763 | b8b6a50b | bellard | next_eip = s->pc - s->cs_base; |
764 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
765 | a7812ae4 | pbrook | gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags), |
766 | a7812ae4 | pbrook | tcg_const_i32(next_eip - cur_eip)); |
767 | f115e911 | bellard | } |
768 | f115e911 | bellard | } |
769 | f115e911 | bellard | |
770 | 2c0262af | bellard | static inline void gen_movs(DisasContext *s, int ot) |
771 | 2c0262af | bellard | { |
772 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
773 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
774 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
775 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
776 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
777 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_ESI); |
778 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_EDI); |
779 | 2c0262af | bellard | } |
780 | 2c0262af | bellard | |
781 | 2c0262af | bellard | static inline void gen_update_cc_op(DisasContext *s) |
782 | 2c0262af | bellard | { |
783 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
784 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
785 | 2c0262af | bellard | s->cc_op = CC_OP_DYNAMIC; |
786 | 2c0262af | bellard | } |
787 | 2c0262af | bellard | } |
788 | 2c0262af | bellard | |
789 | b6abf97d | bellard | static void gen_op_update1_cc(void) |
790 | b6abf97d | bellard | { |
791 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_src); |
792 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
793 | b6abf97d | bellard | } |
794 | b6abf97d | bellard | |
795 | b6abf97d | bellard | static void gen_op_update2_cc(void) |
796 | b6abf97d | bellard | { |
797 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
798 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
799 | b6abf97d | bellard | } |
800 | b6abf97d | bellard | |
801 | b6abf97d | bellard | static inline void gen_op_cmpl_T0_T1_cc(void) |
802 | b6abf97d | bellard | { |
803 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
804 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
805 | b6abf97d | bellard | } |
806 | b6abf97d | bellard | |
807 | b6abf97d | bellard | static inline void gen_op_testl_T0_T1_cc(void) |
808 | b6abf97d | bellard | { |
809 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_src); |
810 | b6abf97d | bellard | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
811 | b6abf97d | bellard | } |
812 | b6abf97d | bellard | |
813 | b6abf97d | bellard | static void gen_op_update_neg_cc(void) |
814 | b6abf97d | bellard | { |
815 | b6abf97d | bellard | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
|
816 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
817 | b6abf97d | bellard | } |
818 | b6abf97d | bellard | |
819 | 8e1c85e3 | bellard | /* compute eflags.C to reg */
|
820 | 8e1c85e3 | bellard | static void gen_compute_eflags_c(TCGv reg) |
821 | 8e1c85e3 | bellard | { |
822 | a7812ae4 | pbrook | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op); |
823 | 8e1c85e3 | bellard | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
824 | 8e1c85e3 | bellard | } |
825 | 8e1c85e3 | bellard | |
826 | 8e1c85e3 | bellard | /* compute all eflags to cc_src */
|
827 | 8e1c85e3 | bellard | static void gen_compute_eflags(TCGv reg) |
828 | 8e1c85e3 | bellard | { |
829 | a7812ae4 | pbrook | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op); |
830 | 8e1c85e3 | bellard | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
831 | 8e1c85e3 | bellard | } |
832 | 8e1c85e3 | bellard | |
833 | 1e4840bf | bellard | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
834 | 8e1c85e3 | bellard | { |
835 | 1e4840bf | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
836 | 1e4840bf | bellard | gen_op_set_cc_op(s->cc_op); |
837 | 1e4840bf | bellard | switch(jcc_op) {
|
838 | 8e1c85e3 | bellard | case JCC_O:
|
839 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_T[0]);
|
840 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); |
841 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
842 | 8e1c85e3 | bellard | break;
|
843 | 8e1c85e3 | bellard | case JCC_B:
|
844 | 8e1c85e3 | bellard | gen_compute_eflags_c(cpu_T[0]);
|
845 | 8e1c85e3 | bellard | break;
|
846 | 8e1c85e3 | bellard | case JCC_Z:
|
847 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_T[0]);
|
848 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); |
849 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
850 | 8e1c85e3 | bellard | break;
|
851 | 8e1c85e3 | bellard | case JCC_BE:
|
852 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_tmp0); |
853 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); |
854 | 8e1c85e3 | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
855 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
856 | 8e1c85e3 | bellard | break;
|
857 | 8e1c85e3 | bellard | case JCC_S:
|
858 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_T[0]);
|
859 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); |
860 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
861 | 8e1c85e3 | bellard | break;
|
862 | 8e1c85e3 | bellard | case JCC_P:
|
863 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_T[0]);
|
864 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); |
865 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
866 | 8e1c85e3 | bellard | break;
|
867 | 8e1c85e3 | bellard | case JCC_L:
|
868 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_tmp0); |
869 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
870 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ |
871 | 8e1c85e3 | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
872 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
873 | 8e1c85e3 | bellard | break;
|
874 | 8e1c85e3 | bellard | default:
|
875 | 8e1c85e3 | bellard | case JCC_LE:
|
876 | 8e1c85e3 | bellard | gen_compute_eflags(cpu_tmp0); |
877 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
878 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ |
879 | 8e1c85e3 | bellard | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ |
880 | 8e1c85e3 | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
881 | 8e1c85e3 | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
882 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); |
883 | 8e1c85e3 | bellard | break;
|
884 | 8e1c85e3 | bellard | } |
885 | 8e1c85e3 | bellard | } |
886 | 8e1c85e3 | bellard | |
887 | 8e1c85e3 | bellard | /* return true if setcc_slow is not needed (WARNING: must be kept in
|
888 | 8e1c85e3 | bellard | sync with gen_jcc1) */
|
889 | 8e1c85e3 | bellard | static int is_fast_jcc_case(DisasContext *s, int b) |
890 | 8e1c85e3 | bellard | { |
891 | 8e1c85e3 | bellard | int jcc_op;
|
892 | 8e1c85e3 | bellard | jcc_op = (b >> 1) & 7; |
893 | 8e1c85e3 | bellard | switch(s->cc_op) {
|
894 | 8e1c85e3 | bellard | /* we optimize the cmp/jcc case */
|
895 | 8e1c85e3 | bellard | case CC_OP_SUBB:
|
896 | 8e1c85e3 | bellard | case CC_OP_SUBW:
|
897 | 8e1c85e3 | bellard | case CC_OP_SUBL:
|
898 | 8e1c85e3 | bellard | case CC_OP_SUBQ:
|
899 | 8e1c85e3 | bellard | if (jcc_op == JCC_O || jcc_op == JCC_P)
|
900 | 8e1c85e3 | bellard | goto slow_jcc;
|
901 | 8e1c85e3 | bellard | break;
|
902 | 8e1c85e3 | bellard | |
903 | 8e1c85e3 | bellard | /* some jumps are easy to compute */
|
904 | 8e1c85e3 | bellard | case CC_OP_ADDB:
|
905 | 8e1c85e3 | bellard | case CC_OP_ADDW:
|
906 | 8e1c85e3 | bellard | case CC_OP_ADDL:
|
907 | 8e1c85e3 | bellard | case CC_OP_ADDQ:
|
908 | 8e1c85e3 | bellard | |
909 | 8e1c85e3 | bellard | case CC_OP_LOGICB:
|
910 | 8e1c85e3 | bellard | case CC_OP_LOGICW:
|
911 | 8e1c85e3 | bellard | case CC_OP_LOGICL:
|
912 | 8e1c85e3 | bellard | case CC_OP_LOGICQ:
|
913 | 8e1c85e3 | bellard | |
914 | 8e1c85e3 | bellard | case CC_OP_INCB:
|
915 | 8e1c85e3 | bellard | case CC_OP_INCW:
|
916 | 8e1c85e3 | bellard | case CC_OP_INCL:
|
917 | 8e1c85e3 | bellard | case CC_OP_INCQ:
|
918 | 8e1c85e3 | bellard | |
919 | 8e1c85e3 | bellard | case CC_OP_DECB:
|
920 | 8e1c85e3 | bellard | case CC_OP_DECW:
|
921 | 8e1c85e3 | bellard | case CC_OP_DECL:
|
922 | 8e1c85e3 | bellard | case CC_OP_DECQ:
|
923 | 8e1c85e3 | bellard | |
924 | 8e1c85e3 | bellard | case CC_OP_SHLB:
|
925 | 8e1c85e3 | bellard | case CC_OP_SHLW:
|
926 | 8e1c85e3 | bellard | case CC_OP_SHLL:
|
927 | 8e1c85e3 | bellard | case CC_OP_SHLQ:
|
928 | 8e1c85e3 | bellard | if (jcc_op != JCC_Z && jcc_op != JCC_S)
|
929 | 8e1c85e3 | bellard | goto slow_jcc;
|
930 | 8e1c85e3 | bellard | break;
|
931 | 8e1c85e3 | bellard | default:
|
932 | 8e1c85e3 | bellard | slow_jcc:
|
933 | 8e1c85e3 | bellard | return 0; |
934 | 8e1c85e3 | bellard | } |
935 | 8e1c85e3 | bellard | return 1; |
936 | 8e1c85e3 | bellard | } |
937 | 8e1c85e3 | bellard | |
938 | 8e1c85e3 | bellard | /* generate a conditional jump to label 'l1' according to jump opcode
|
939 | 8e1c85e3 | bellard | value 'b'. In the fast case, T0 is guaranted not to be used. */
|
940 | 8e1c85e3 | bellard | static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) |
941 | 8e1c85e3 | bellard | { |
942 | 8e1c85e3 | bellard | int inv, jcc_op, size, cond;
|
943 | 8e1c85e3 | bellard | TCGv t0; |
944 | 8e1c85e3 | bellard | |
945 | 8e1c85e3 | bellard | inv = b & 1;
|
946 | 8e1c85e3 | bellard | jcc_op = (b >> 1) & 7; |
947 | 8e1c85e3 | bellard | |
948 | 8e1c85e3 | bellard | switch(cc_op) {
|
949 | 8e1c85e3 | bellard | /* we optimize the cmp/jcc case */
|
950 | 8e1c85e3 | bellard | case CC_OP_SUBB:
|
951 | 8e1c85e3 | bellard | case CC_OP_SUBW:
|
952 | 8e1c85e3 | bellard | case CC_OP_SUBL:
|
953 | 8e1c85e3 | bellard | case CC_OP_SUBQ:
|
954 | 8e1c85e3 | bellard | |
955 | 8e1c85e3 | bellard | size = cc_op - CC_OP_SUBB; |
956 | 8e1c85e3 | bellard | switch(jcc_op) {
|
957 | 8e1c85e3 | bellard | case JCC_Z:
|
958 | 8e1c85e3 | bellard | fast_jcc_z:
|
959 | 8e1c85e3 | bellard | switch(size) {
|
960 | 8e1c85e3 | bellard | case 0: |
961 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
|
962 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
963 | 8e1c85e3 | bellard | break;
|
964 | 8e1c85e3 | bellard | case 1: |
965 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
|
966 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
967 | 8e1c85e3 | bellard | break;
|
968 | 8e1c85e3 | bellard | #ifdef TARGET_X86_64
|
969 | 8e1c85e3 | bellard | case 2: |
970 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
|
971 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
972 | 8e1c85e3 | bellard | break;
|
973 | 8e1c85e3 | bellard | #endif
|
974 | 8e1c85e3 | bellard | default:
|
975 | 8e1c85e3 | bellard | t0 = cpu_cc_dst; |
976 | 8e1c85e3 | bellard | break;
|
977 | 8e1c85e3 | bellard | } |
978 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
|
979 | 8e1c85e3 | bellard | break;
|
980 | 8e1c85e3 | bellard | case JCC_S:
|
981 | 8e1c85e3 | bellard | fast_jcc_s:
|
982 | 8e1c85e3 | bellard | switch(size) {
|
983 | 8e1c85e3 | bellard | case 0: |
984 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
|
985 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
986 | cb63669a | pbrook | 0, l1);
|
987 | 8e1c85e3 | bellard | break;
|
988 | 8e1c85e3 | bellard | case 1: |
989 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
|
990 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
991 | cb63669a | pbrook | 0, l1);
|
992 | 8e1c85e3 | bellard | break;
|
993 | 8e1c85e3 | bellard | #ifdef TARGET_X86_64
|
994 | 8e1c85e3 | bellard | case 2: |
995 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
|
996 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
997 | cb63669a | pbrook | 0, l1);
|
998 | 8e1c85e3 | bellard | break;
|
999 | 8e1c85e3 | bellard | #endif
|
1000 | 8e1c85e3 | bellard | default:
|
1001 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, |
1002 | cb63669a | pbrook | 0, l1);
|
1003 | 8e1c85e3 | bellard | break;
|
1004 | 8e1c85e3 | bellard | } |
1005 | 8e1c85e3 | bellard | break;
|
1006 | 8e1c85e3 | bellard | |
1007 | 8e1c85e3 | bellard | case JCC_B:
|
1008 | 8e1c85e3 | bellard | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; |
1009 | 8e1c85e3 | bellard | goto fast_jcc_b;
|
1010 | 8e1c85e3 | bellard | case JCC_BE:
|
1011 | 8e1c85e3 | bellard | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; |
1012 | 8e1c85e3 | bellard | fast_jcc_b:
|
1013 | 8e1c85e3 | bellard | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); |
1014 | 8e1c85e3 | bellard | switch(size) {
|
1015 | 8e1c85e3 | bellard | case 0: |
1016 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1017 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
|
1018 | 8e1c85e3 | bellard | tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
|
1019 | 8e1c85e3 | bellard | break;
|
1020 | 8e1c85e3 | bellard | case 1: |
1021 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1022 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
|
1023 | 8e1c85e3 | bellard | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
|
1024 | 8e1c85e3 | bellard | break;
|
1025 | 8e1c85e3 | bellard | #ifdef TARGET_X86_64
|
1026 | 8e1c85e3 | bellard | case 2: |
1027 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1028 | 8e1c85e3 | bellard | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
|
1029 | 8e1c85e3 | bellard | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
|
1030 | 8e1c85e3 | bellard | break;
|
1031 | 8e1c85e3 | bellard | #endif
|
1032 | 8e1c85e3 | bellard | default:
|
1033 | 8e1c85e3 | bellard | t0 = cpu_cc_src; |
1034 | 8e1c85e3 | bellard | break;
|
1035 | 8e1c85e3 | bellard | } |
1036 | 8e1c85e3 | bellard | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1037 | 8e1c85e3 | bellard | break;
|
1038 | 8e1c85e3 | bellard | |
1039 | 8e1c85e3 | bellard | case JCC_L:
|
1040 | 8e1c85e3 | bellard | cond = inv ? TCG_COND_GE : TCG_COND_LT; |
1041 | 8e1c85e3 | bellard | goto fast_jcc_l;
|
1042 | 8e1c85e3 | bellard | case JCC_LE:
|
1043 | 8e1c85e3 | bellard | cond = inv ? TCG_COND_GT : TCG_COND_LE; |
1044 | 8e1c85e3 | bellard | fast_jcc_l:
|
1045 | 8e1c85e3 | bellard | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); |
1046 | 8e1c85e3 | bellard | switch(size) {
|
1047 | 8e1c85e3 | bellard | case 0: |
1048 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1049 | 8e1c85e3 | bellard | tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); |
1050 | 8e1c85e3 | bellard | tcg_gen_ext8s_tl(t0, cpu_cc_src); |
1051 | 8e1c85e3 | bellard | break;
|
1052 | 8e1c85e3 | bellard | case 1: |
1053 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1054 | 8e1c85e3 | bellard | tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); |
1055 | 8e1c85e3 | bellard | tcg_gen_ext16s_tl(t0, cpu_cc_src); |
1056 | 8e1c85e3 | bellard | break;
|
1057 | 8e1c85e3 | bellard | #ifdef TARGET_X86_64
|
1058 | 8e1c85e3 | bellard | case 2: |
1059 | 8e1c85e3 | bellard | t0 = cpu_tmp0; |
1060 | 8e1c85e3 | bellard | tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); |
1061 | 8e1c85e3 | bellard | tcg_gen_ext32s_tl(t0, cpu_cc_src); |
1062 | 8e1c85e3 | bellard | break;
|
1063 | 8e1c85e3 | bellard | #endif
|
1064 | 8e1c85e3 | bellard | default:
|
1065 | 8e1c85e3 | bellard | t0 = cpu_cc_src; |
1066 | 8e1c85e3 | bellard | break;
|
1067 | 8e1c85e3 | bellard | } |
1068 | 8e1c85e3 | bellard | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1069 | 8e1c85e3 | bellard | break;
|
1070 | 8e1c85e3 | bellard | |
1071 | 8e1c85e3 | bellard | default:
|
1072 | 8e1c85e3 | bellard | goto slow_jcc;
|
1073 | 8e1c85e3 | bellard | } |
1074 | 8e1c85e3 | bellard | break;
|
1075 | 8e1c85e3 | bellard | |
1076 | 8e1c85e3 | bellard | /* some jumps are easy to compute */
|
1077 | 8e1c85e3 | bellard | case CC_OP_ADDB:
|
1078 | 8e1c85e3 | bellard | case CC_OP_ADDW:
|
1079 | 8e1c85e3 | bellard | case CC_OP_ADDL:
|
1080 | 8e1c85e3 | bellard | case CC_OP_ADDQ:
|
1081 | 8e1c85e3 | bellard | |
1082 | 8e1c85e3 | bellard | case CC_OP_ADCB:
|
1083 | 8e1c85e3 | bellard | case CC_OP_ADCW:
|
1084 | 8e1c85e3 | bellard | case CC_OP_ADCL:
|
1085 | 8e1c85e3 | bellard | case CC_OP_ADCQ:
|
1086 | 8e1c85e3 | bellard | |
1087 | 8e1c85e3 | bellard | case CC_OP_SBBB:
|
1088 | 8e1c85e3 | bellard | case CC_OP_SBBW:
|
1089 | 8e1c85e3 | bellard | case CC_OP_SBBL:
|
1090 | 8e1c85e3 | bellard | case CC_OP_SBBQ:
|
1091 | 8e1c85e3 | bellard | |
1092 | 8e1c85e3 | bellard | case CC_OP_LOGICB:
|
1093 | 8e1c85e3 | bellard | case CC_OP_LOGICW:
|
1094 | 8e1c85e3 | bellard | case CC_OP_LOGICL:
|
1095 | 8e1c85e3 | bellard | case CC_OP_LOGICQ:
|
1096 | 8e1c85e3 | bellard | |
1097 | 8e1c85e3 | bellard | case CC_OP_INCB:
|
1098 | 8e1c85e3 | bellard | case CC_OP_INCW:
|
1099 | 8e1c85e3 | bellard | case CC_OP_INCL:
|
1100 | 8e1c85e3 | bellard | case CC_OP_INCQ:
|
1101 | 8e1c85e3 | bellard | |
1102 | 8e1c85e3 | bellard | case CC_OP_DECB:
|
1103 | 8e1c85e3 | bellard | case CC_OP_DECW:
|
1104 | 8e1c85e3 | bellard | case CC_OP_DECL:
|
1105 | 8e1c85e3 | bellard | case CC_OP_DECQ:
|
1106 | 8e1c85e3 | bellard | |
1107 | 8e1c85e3 | bellard | case CC_OP_SHLB:
|
1108 | 8e1c85e3 | bellard | case CC_OP_SHLW:
|
1109 | 8e1c85e3 | bellard | case CC_OP_SHLL:
|
1110 | 8e1c85e3 | bellard | case CC_OP_SHLQ:
|
1111 | 8e1c85e3 | bellard | |
1112 | 8e1c85e3 | bellard | case CC_OP_SARB:
|
1113 | 8e1c85e3 | bellard | case CC_OP_SARW:
|
1114 | 8e1c85e3 | bellard | case CC_OP_SARL:
|
1115 | 8e1c85e3 | bellard | case CC_OP_SARQ:
|
1116 | 8e1c85e3 | bellard | switch(jcc_op) {
|
1117 | 8e1c85e3 | bellard | case JCC_Z:
|
1118 | 8e1c85e3 | bellard | size = (cc_op - CC_OP_ADDB) & 3;
|
1119 | 8e1c85e3 | bellard | goto fast_jcc_z;
|
1120 | 8e1c85e3 | bellard | case JCC_S:
|
1121 | 8e1c85e3 | bellard | size = (cc_op - CC_OP_ADDB) & 3;
|
1122 | 8e1c85e3 | bellard | goto fast_jcc_s;
|
1123 | 8e1c85e3 | bellard | default:
|
1124 | 8e1c85e3 | bellard | goto slow_jcc;
|
1125 | 8e1c85e3 | bellard | } |
1126 | 8e1c85e3 | bellard | break;
|
1127 | 8e1c85e3 | bellard | default:
|
1128 | 8e1c85e3 | bellard | slow_jcc:
|
1129 | 1e4840bf | bellard | gen_setcc_slow_T0(s, jcc_op); |
1130 | cb63669a | pbrook | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1131 | cb63669a | pbrook | cpu_T[0], 0, l1); |
1132 | 8e1c85e3 | bellard | break;
|
1133 | 8e1c85e3 | bellard | } |
1134 | 8e1c85e3 | bellard | } |
1135 | 8e1c85e3 | bellard | |
1136 | 14ce26e7 | bellard | /* XXX: does not work with gdbstub "ice" single step - not a
|
1137 | 14ce26e7 | bellard | serious problem */
|
1138 | 14ce26e7 | bellard | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) |
1139 | 2c0262af | bellard | { |
1140 | 14ce26e7 | bellard | int l1, l2;
|
1141 | 14ce26e7 | bellard | |
1142 | 14ce26e7 | bellard | l1 = gen_new_label(); |
1143 | 14ce26e7 | bellard | l2 = gen_new_label(); |
1144 | 6e0d8677 | bellard | gen_op_jnz_ecx(s->aflag, l1); |
1145 | 14ce26e7 | bellard | gen_set_label(l2); |
1146 | 14ce26e7 | bellard | gen_jmp_tb(s, next_eip, 1);
|
1147 | 14ce26e7 | bellard | gen_set_label(l1); |
1148 | 14ce26e7 | bellard | return l2;
|
1149 | 2c0262af | bellard | } |
1150 | 2c0262af | bellard | |
1151 | 2c0262af | bellard | static inline void gen_stos(DisasContext *s, int ot) |
1152 | 2c0262af | bellard | { |
1153 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
1154 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
1155 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1156 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1157 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_EDI); |
1158 | 2c0262af | bellard | } |
1159 | 2c0262af | bellard | |
1160 | 2c0262af | bellard | static inline void gen_lods(DisasContext *s, int ot) |
1161 | 2c0262af | bellard | { |
1162 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
1163 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1164 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EAX); |
1165 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1166 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_ESI); |
1167 | 2c0262af | bellard | } |
1168 | 2c0262af | bellard | |
1169 | 2c0262af | bellard | static inline void gen_scas(DisasContext *s, int ot) |
1170 | 2c0262af | bellard | { |
1171 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
1172 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
1173 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
1174 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
1175 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1176 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_EDI); |
1177 | 2c0262af | bellard | } |
1178 | 2c0262af | bellard | |
1179 | 2c0262af | bellard | static inline void gen_cmps(DisasContext *s, int ot) |
1180 | 2c0262af | bellard | { |
1181 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
1182 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1183 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
1184 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
1185 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
1186 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1187 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_ESI); |
1188 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_EDI); |
1189 | 2c0262af | bellard | } |
1190 | 2c0262af | bellard | |
1191 | 2c0262af | bellard | static inline void gen_ins(DisasContext *s, int ot) |
1192 | 2c0262af | bellard | { |
1193 | 2e70f6ef | pbrook | if (use_icount)
|
1194 | 2e70f6ef | pbrook | gen_io_start(); |
1195 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
1196 | 6e0d8677 | bellard | /* Note: we must do this dummy write first to be restartable in
|
1197 | 6e0d8677 | bellard | case of page fault. */
|
1198 | 9772c73b | bellard | gen_op_movl_T0_0(); |
1199 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1200 | b8b6a50b | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
|
1201 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
1202 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
1203 | a7812ae4 | pbrook | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
|
1204 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1205 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1206 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_EDI); |
1207 | 2e70f6ef | pbrook | if (use_icount)
|
1208 | 2e70f6ef | pbrook | gen_io_end(); |
1209 | 2c0262af | bellard | } |
1210 | 2c0262af | bellard | |
1211 | 2c0262af | bellard | static inline void gen_outs(DisasContext *s, int ot) |
1212 | 2c0262af | bellard | { |
1213 | 2e70f6ef | pbrook | if (use_icount)
|
1214 | 2e70f6ef | pbrook | gen_io_start(); |
1215 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
1216 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1217 | b8b6a50b | bellard | |
1218 | b8b6a50b | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
|
1219 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
1220 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
1221 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
|
1222 | a7812ae4 | pbrook | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
1223 | b8b6a50b | bellard | |
1224 | 6e0d8677 | bellard | gen_op_movl_T0_Dshift(ot); |
1225 | 6e0d8677 | bellard | gen_op_add_reg_T0(s->aflag, R_ESI); |
1226 | 2e70f6ef | pbrook | if (use_icount)
|
1227 | 2e70f6ef | pbrook | gen_io_end(); |
1228 | 2c0262af | bellard | } |
1229 | 2c0262af | bellard | |
1230 | 2c0262af | bellard | /* same method as Valgrind : we generate jumps to current or next
|
1231 | 2c0262af | bellard | instruction */
|
1232 | 2c0262af | bellard | #define GEN_REPZ(op) \
|
1233 | 2c0262af | bellard | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ |
1234 | 14ce26e7 | bellard | target_ulong cur_eip, target_ulong next_eip) \ |
1235 | 2c0262af | bellard | { \ |
1236 | 14ce26e7 | bellard | int l2;\
|
1237 | 2c0262af | bellard | gen_update_cc_op(s); \ |
1238 | 14ce26e7 | bellard | l2 = gen_jz_ecx_string(s, next_eip); \ |
1239 | 2c0262af | bellard | gen_ ## op(s, ot); \ |
1240 | 6e0d8677 | bellard | gen_op_add_reg_im(s->aflag, R_ECX, -1); \
|
1241 | 2c0262af | bellard | /* a loop would cause two single step exceptions if ECX = 1 \
|
1242 | 2c0262af | bellard | before rep string_insn */ \
|
1243 | 2c0262af | bellard | if (!s->jmp_opt) \
|
1244 | 6e0d8677 | bellard | gen_op_jz_ecx(s->aflag, l2); \ |
1245 | 2c0262af | bellard | gen_jmp(s, cur_eip); \ |
1246 | 2c0262af | bellard | } |
1247 | 2c0262af | bellard | |
1248 | 2c0262af | bellard | #define GEN_REPZ2(op) \
|
1249 | 2c0262af | bellard | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ |
1250 | 14ce26e7 | bellard | target_ulong cur_eip, \ |
1251 | 14ce26e7 | bellard | target_ulong next_eip, \ |
1252 | 2c0262af | bellard | int nz) \
|
1253 | 2c0262af | bellard | { \ |
1254 | 14ce26e7 | bellard | int l2;\
|
1255 | 2c0262af | bellard | gen_update_cc_op(s); \ |
1256 | 14ce26e7 | bellard | l2 = gen_jz_ecx_string(s, next_eip); \ |
1257 | 2c0262af | bellard | gen_ ## op(s, ot); \ |
1258 | 6e0d8677 | bellard | gen_op_add_reg_im(s->aflag, R_ECX, -1); \
|
1259 | 2c0262af | bellard | gen_op_set_cc_op(CC_OP_SUBB + ot); \ |
1260 | 8e1c85e3 | bellard | gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \ |
1261 | 2c0262af | bellard | if (!s->jmp_opt) \
|
1262 | 6e0d8677 | bellard | gen_op_jz_ecx(s->aflag, l2); \ |
1263 | 2c0262af | bellard | gen_jmp(s, cur_eip); \ |
1264 | 2c0262af | bellard | } |
1265 | 2c0262af | bellard | |
1266 | 2c0262af | bellard | GEN_REPZ(movs) |
1267 | 2c0262af | bellard | GEN_REPZ(stos) |
1268 | 2c0262af | bellard | GEN_REPZ(lods) |
1269 | 2c0262af | bellard | GEN_REPZ(ins) |
1270 | 2c0262af | bellard | GEN_REPZ(outs) |
1271 | 2c0262af | bellard | GEN_REPZ2(scas) |
1272 | 2c0262af | bellard | GEN_REPZ2(cmps) |
1273 | 2c0262af | bellard | |
1274 | a7812ae4 | pbrook | static void gen_helper_fp_arith_ST0_FT0(int op) |
1275 | a7812ae4 | pbrook | { |
1276 | a7812ae4 | pbrook | switch (op) {
|
1277 | a7812ae4 | pbrook | case 0: gen_helper_fadd_ST0_FT0(); break; |
1278 | a7812ae4 | pbrook | case 1: gen_helper_fmul_ST0_FT0(); break; |
1279 | a7812ae4 | pbrook | case 2: gen_helper_fcom_ST0_FT0(); break; |
1280 | a7812ae4 | pbrook | case 3: gen_helper_fcom_ST0_FT0(); break; |
1281 | a7812ae4 | pbrook | case 4: gen_helper_fsub_ST0_FT0(); break; |
1282 | a7812ae4 | pbrook | case 5: gen_helper_fsubr_ST0_FT0(); break; |
1283 | a7812ae4 | pbrook | case 6: gen_helper_fdiv_ST0_FT0(); break; |
1284 | a7812ae4 | pbrook | case 7: gen_helper_fdivr_ST0_FT0(); break; |
1285 | a7812ae4 | pbrook | } |
1286 | a7812ae4 | pbrook | } |
1287 | 2c0262af | bellard | |
1288 | 2c0262af | bellard | /* NOTE the exception in "r" op ordering */
|
1289 | a7812ae4 | pbrook | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1290 | a7812ae4 | pbrook | { |
1291 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_const_i32(opreg); |
1292 | a7812ae4 | pbrook | switch (op) {
|
1293 | a7812ae4 | pbrook | case 0: gen_helper_fadd_STN_ST0(tmp); break; |
1294 | a7812ae4 | pbrook | case 1: gen_helper_fmul_STN_ST0(tmp); break; |
1295 | a7812ae4 | pbrook | case 4: gen_helper_fsubr_STN_ST0(tmp); break; |
1296 | a7812ae4 | pbrook | case 5: gen_helper_fsub_STN_ST0(tmp); break; |
1297 | a7812ae4 | pbrook | case 6: gen_helper_fdivr_STN_ST0(tmp); break; |
1298 | a7812ae4 | pbrook | case 7: gen_helper_fdiv_STN_ST0(tmp); break; |
1299 | a7812ae4 | pbrook | } |
1300 | a7812ae4 | pbrook | } |
1301 | 2c0262af | bellard | |
1302 | 2c0262af | bellard | /* if d == OR_TMP0, it means memory operand (address in A0) */
|
1303 | 2c0262af | bellard | static void gen_op(DisasContext *s1, int op, int ot, int d) |
1304 | 2c0262af | bellard | { |
1305 | 2c0262af | bellard | if (d != OR_TMP0) {
|
1306 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, d);
|
1307 | 2c0262af | bellard | } else {
|
1308 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s1->mem_index); |
1309 | 2c0262af | bellard | } |
1310 | 2c0262af | bellard | switch(op) {
|
1311 | 2c0262af | bellard | case OP_ADCL:
|
1312 | cad3a37d | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1313 | cad3a37d | bellard | gen_op_set_cc_op(s1->cc_op); |
1314 | cad3a37d | bellard | gen_compute_eflags_c(cpu_tmp4); |
1315 | cad3a37d | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1316 | cad3a37d | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
1317 | cad3a37d | bellard | if (d != OR_TMP0)
|
1318 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1319 | cad3a37d | bellard | else
|
1320 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1321 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
1322 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1323 | cad3a37d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); |
1324 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
|
1325 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); |
1326 | cad3a37d | bellard | s1->cc_op = CC_OP_DYNAMIC; |
1327 | cad3a37d | bellard | break;
|
1328 | 2c0262af | bellard | case OP_SBBL:
|
1329 | 2c0262af | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1330 | 2c0262af | bellard | gen_op_set_cc_op(s1->cc_op); |
1331 | cad3a37d | bellard | gen_compute_eflags_c(cpu_tmp4); |
1332 | cad3a37d | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1333 | cad3a37d | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
1334 | cad3a37d | bellard | if (d != OR_TMP0)
|
1335 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, d); |
1336 | cad3a37d | bellard | else
|
1337 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1338 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
1339 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1340 | cad3a37d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); |
1341 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
|
1342 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); |
1343 | 2c0262af | bellard | s1->cc_op = CC_OP_DYNAMIC; |
1344 | cad3a37d | bellard | break;
|
1345 | 2c0262af | bellard | case OP_ADDL:
|
1346 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
1347 | cad3a37d | bellard | if (d != OR_TMP0)
|
1348 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1349 | cad3a37d | bellard | else
|
1350 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1351 | cad3a37d | bellard | gen_op_update2_cc(); |
1352 | 2c0262af | bellard | s1->cc_op = CC_OP_ADDB + ot; |
1353 | 2c0262af | bellard | break;
|
1354 | 2c0262af | bellard | case OP_SUBL:
|
1355 | 57fec1fe | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1356 | cad3a37d | bellard | if (d != OR_TMP0)
|
1357 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1358 | cad3a37d | bellard | else
|
1359 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1360 | cad3a37d | bellard | gen_op_update2_cc(); |
1361 | 2c0262af | bellard | s1->cc_op = CC_OP_SUBB + ot; |
1362 | 2c0262af | bellard | break;
|
1363 | 2c0262af | bellard | default:
|
1364 | 2c0262af | bellard | case OP_ANDL:
|
1365 | 57fec1fe | bellard | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1366 | cad3a37d | bellard | if (d != OR_TMP0)
|
1367 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1368 | cad3a37d | bellard | else
|
1369 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1370 | cad3a37d | bellard | gen_op_update1_cc(); |
1371 | 57fec1fe | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1372 | 57fec1fe | bellard | break;
|
1373 | 2c0262af | bellard | case OP_ORL:
|
1374 | 57fec1fe | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1375 | cad3a37d | bellard | if (d != OR_TMP0)
|
1376 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1377 | cad3a37d | bellard | else
|
1378 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1379 | cad3a37d | bellard | gen_op_update1_cc(); |
1380 | 57fec1fe | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1381 | 57fec1fe | bellard | break;
|
1382 | 2c0262af | bellard | case OP_XORL:
|
1383 | 57fec1fe | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1384 | cad3a37d | bellard | if (d != OR_TMP0)
|
1385 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1386 | cad3a37d | bellard | else
|
1387 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1388 | cad3a37d | bellard | gen_op_update1_cc(); |
1389 | 2c0262af | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1390 | 2c0262af | bellard | break;
|
1391 | 2c0262af | bellard | case OP_CMPL:
|
1392 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
1393 | 2c0262af | bellard | s1->cc_op = CC_OP_SUBB + ot; |
1394 | 2c0262af | bellard | break;
|
1395 | 2c0262af | bellard | } |
1396 | b6abf97d | bellard | } |
1397 | b6abf97d | bellard | |
1398 | 2c0262af | bellard | /* if d == OR_TMP0, it means memory operand (address in A0) */
|
1399 | 2c0262af | bellard | static void gen_inc(DisasContext *s1, int ot, int d, int c) |
1400 | 2c0262af | bellard | { |
1401 | 2c0262af | bellard | if (d != OR_TMP0)
|
1402 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, d);
|
1403 | 2c0262af | bellard | else
|
1404 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s1->mem_index); |
1405 | 2c0262af | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1406 | 2c0262af | bellard | gen_op_set_cc_op(s1->cc_op); |
1407 | 2c0262af | bellard | if (c > 0) { |
1408 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
1409 | 2c0262af | bellard | s1->cc_op = CC_OP_INCB + ot; |
1410 | 2c0262af | bellard | } else {
|
1411 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
1412 | 2c0262af | bellard | s1->cc_op = CC_OP_DECB + ot; |
1413 | 2c0262af | bellard | } |
1414 | 2c0262af | bellard | if (d != OR_TMP0)
|
1415 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, d); |
1416 | 2c0262af | bellard | else
|
1417 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1418 | b6abf97d | bellard | gen_compute_eflags_c(cpu_cc_src); |
1419 | cd31fefa | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1420 | 2c0262af | bellard | } |
1421 | 2c0262af | bellard | |
1422 | b6abf97d | bellard | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1423 | b6abf97d | bellard | int is_right, int is_arith) |
1424 | 2c0262af | bellard | { |
1425 | b6abf97d | bellard | target_ulong mask; |
1426 | b6abf97d | bellard | int shift_label;
|
1427 | 1e4840bf | bellard | TCGv t0, t1; |
1428 | 1e4840bf | bellard | |
1429 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1430 | b6abf97d | bellard | mask = 0x3f;
|
1431 | 2c0262af | bellard | else
|
1432 | b6abf97d | bellard | mask = 0x1f;
|
1433 | 3b46e624 | ths | |
1434 | b6abf97d | bellard | /* load */
|
1435 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1436 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1437 | 2c0262af | bellard | else
|
1438 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1439 | b6abf97d | bellard | |
1440 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
1441 | b6abf97d | bellard | |
1442 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1); |
1443 | b6abf97d | bellard | |
1444 | b6abf97d | bellard | if (is_right) {
|
1445 | b6abf97d | bellard | if (is_arith) {
|
1446 | f484d386 | bellard | gen_exts(ot, cpu_T[0]);
|
1447 | b6abf97d | bellard | tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1448 | b6abf97d | bellard | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1449 | b6abf97d | bellard | } else {
|
1450 | cad3a37d | bellard | gen_extu(ot, cpu_T[0]);
|
1451 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1452 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1453 | b6abf97d | bellard | } |
1454 | b6abf97d | bellard | } else {
|
1455 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1456 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1457 | b6abf97d | bellard | } |
1458 | b6abf97d | bellard | |
1459 | b6abf97d | bellard | /* store */
|
1460 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1461 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1462 | b6abf97d | bellard | else
|
1463 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1464 | b6abf97d | bellard | |
1465 | b6abf97d | bellard | /* update eflags if non zero shift */
|
1466 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1467 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1468 | b6abf97d | bellard | |
1469 | 1e4840bf | bellard | /* XXX: inefficient */
|
1470 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1471 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1472 | 1e4840bf | bellard | |
1473 | 1e4840bf | bellard | tcg_gen_mov_tl(t0, cpu_T[0]);
|
1474 | 1e4840bf | bellard | tcg_gen_mov_tl(t1, cpu_T3); |
1475 | 1e4840bf | bellard | |
1476 | b6abf97d | bellard | shift_label = gen_new_label(); |
1477 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label); |
1478 | b6abf97d | bellard | |
1479 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_src, t1); |
1480 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_dst, t0); |
1481 | b6abf97d | bellard | if (is_right)
|
1482 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
1483 | b6abf97d | bellard | else
|
1484 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
1485 | b6abf97d | bellard | |
1486 | b6abf97d | bellard | gen_set_label(shift_label); |
1487 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1488 | 1e4840bf | bellard | |
1489 | 1e4840bf | bellard | tcg_temp_free(t0); |
1490 | 1e4840bf | bellard | tcg_temp_free(t1); |
1491 | b6abf97d | bellard | } |
1492 | b6abf97d | bellard | |
1493 | c1c37968 | bellard | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1494 | c1c37968 | bellard | int is_right, int is_arith) |
1495 | c1c37968 | bellard | { |
1496 | c1c37968 | bellard | int mask;
|
1497 | c1c37968 | bellard | |
1498 | c1c37968 | bellard | if (ot == OT_QUAD)
|
1499 | c1c37968 | bellard | mask = 0x3f;
|
1500 | c1c37968 | bellard | else
|
1501 | c1c37968 | bellard | mask = 0x1f;
|
1502 | c1c37968 | bellard | |
1503 | c1c37968 | bellard | /* load */
|
1504 | c1c37968 | bellard | if (op1 == OR_TMP0)
|
1505 | c1c37968 | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1506 | c1c37968 | bellard | else
|
1507 | c1c37968 | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1508 | c1c37968 | bellard | |
1509 | c1c37968 | bellard | op2 &= mask; |
1510 | c1c37968 | bellard | if (op2 != 0) { |
1511 | c1c37968 | bellard | if (is_right) {
|
1512 | c1c37968 | bellard | if (is_arith) {
|
1513 | c1c37968 | bellard | gen_exts(ot, cpu_T[0]);
|
1514 | 2a449d14 | bellard | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
1515 | c1c37968 | bellard | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1516 | c1c37968 | bellard | } else {
|
1517 | c1c37968 | bellard | gen_extu(ot, cpu_T[0]);
|
1518 | 2a449d14 | bellard | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
1519 | c1c37968 | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1520 | c1c37968 | bellard | } |
1521 | c1c37968 | bellard | } else {
|
1522 | 2a449d14 | bellard | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
1523 | c1c37968 | bellard | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1524 | c1c37968 | bellard | } |
1525 | c1c37968 | bellard | } |
1526 | c1c37968 | bellard | |
1527 | c1c37968 | bellard | /* store */
|
1528 | c1c37968 | bellard | if (op1 == OR_TMP0)
|
1529 | c1c37968 | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1530 | c1c37968 | bellard | else
|
1531 | c1c37968 | bellard | gen_op_mov_reg_T0(ot, op1); |
1532 | c1c37968 | bellard | |
1533 | c1c37968 | bellard | /* update eflags if non zero shift */
|
1534 | c1c37968 | bellard | if (op2 != 0) { |
1535 | 2a449d14 | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
1536 | c1c37968 | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1537 | c1c37968 | bellard | if (is_right)
|
1538 | c1c37968 | bellard | s->cc_op = CC_OP_SARB + ot; |
1539 | c1c37968 | bellard | else
|
1540 | c1c37968 | bellard | s->cc_op = CC_OP_SHLB + ot; |
1541 | c1c37968 | bellard | } |
1542 | c1c37968 | bellard | } |
1543 | c1c37968 | bellard | |
1544 | b6abf97d | bellard | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1545 | b6abf97d | bellard | { |
1546 | b6abf97d | bellard | if (arg2 >= 0) |
1547 | b6abf97d | bellard | tcg_gen_shli_tl(ret, arg1, arg2); |
1548 | b6abf97d | bellard | else
|
1549 | b6abf97d | bellard | tcg_gen_shri_tl(ret, arg1, -arg2); |
1550 | b6abf97d | bellard | } |
1551 | b6abf97d | bellard | |
1552 | b6abf97d | bellard | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1553 | b6abf97d | bellard | int is_right)
|
1554 | b6abf97d | bellard | { |
1555 | b6abf97d | bellard | target_ulong mask; |
1556 | b6abf97d | bellard | int label1, label2, data_bits;
|
1557 | 1e4840bf | bellard | TCGv t0, t1, t2, a0; |
1558 | 1e4840bf | bellard | |
1559 | 1e4840bf | bellard | /* XXX: inefficient, but we must use local temps */
|
1560 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1561 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1562 | a7812ae4 | pbrook | t2 = tcg_temp_local_new(); |
1563 | a7812ae4 | pbrook | a0 = tcg_temp_local_new(); |
1564 | 1e4840bf | bellard | |
1565 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1566 | b6abf97d | bellard | mask = 0x3f;
|
1567 | b6abf97d | bellard | else
|
1568 | b6abf97d | bellard | mask = 0x1f;
|
1569 | b6abf97d | bellard | |
1570 | b6abf97d | bellard | /* load */
|
1571 | 1e4840bf | bellard | if (op1 == OR_TMP0) {
|
1572 | 1e4840bf | bellard | tcg_gen_mov_tl(a0, cpu_A0); |
1573 | 1e4840bf | bellard | gen_op_ld_v(ot + s->mem_index, t0, a0); |
1574 | 1e4840bf | bellard | } else {
|
1575 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t0, op1); |
1576 | 1e4840bf | bellard | } |
1577 | b6abf97d | bellard | |
1578 | 1e4840bf | bellard | tcg_gen_mov_tl(t1, cpu_T[1]);
|
1579 | 1e4840bf | bellard | |
1580 | 1e4840bf | bellard | tcg_gen_andi_tl(t1, t1, mask); |
1581 | b6abf97d | bellard | |
1582 | b6abf97d | bellard | /* Must test zero case to avoid using undefined behaviour in TCG
|
1583 | b6abf97d | bellard | shifts. */
|
1584 | b6abf97d | bellard | label1 = gen_new_label(); |
1585 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
|
1586 | b6abf97d | bellard | |
1587 | b6abf97d | bellard | if (ot <= OT_WORD)
|
1588 | 1e4840bf | bellard | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
1589 | b6abf97d | bellard | else
|
1590 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_tmp0, t1); |
1591 | b6abf97d | bellard | |
1592 | 1e4840bf | bellard | gen_extu(ot, t0); |
1593 | 1e4840bf | bellard | tcg_gen_mov_tl(t2, t0); |
1594 | b6abf97d | bellard | |
1595 | b6abf97d | bellard | data_bits = 8 << ot;
|
1596 | b6abf97d | bellard | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
|
1597 | b6abf97d | bellard | fix TCG definition) */
|
1598 | b6abf97d | bellard | if (is_right) {
|
1599 | 1e4840bf | bellard | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
1600 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
1601 | 1e4840bf | bellard | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
1602 | b6abf97d | bellard | } else {
|
1603 | 1e4840bf | bellard | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
1604 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
1605 | 1e4840bf | bellard | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
1606 | b6abf97d | bellard | } |
1607 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
1608 | b6abf97d | bellard | |
1609 | b6abf97d | bellard | gen_set_label(label1); |
1610 | b6abf97d | bellard | /* store */
|
1611 | 1e4840bf | bellard | if (op1 == OR_TMP0) {
|
1612 | 1e4840bf | bellard | gen_op_st_v(ot + s->mem_index, t0, a0); |
1613 | 1e4840bf | bellard | } else {
|
1614 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, op1, t0); |
1615 | 1e4840bf | bellard | } |
1616 | b6abf97d | bellard | |
1617 | b6abf97d | bellard | /* update eflags */
|
1618 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1619 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1620 | b6abf97d | bellard | |
1621 | b6abf97d | bellard | label2 = gen_new_label(); |
1622 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
|
1623 | b6abf97d | bellard | |
1624 | b6abf97d | bellard | gen_compute_eflags(cpu_cc_src); |
1625 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1626 | 1e4840bf | bellard | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
1627 | b6abf97d | bellard | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1628 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); |
1629 | b6abf97d | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
1630 | b6abf97d | bellard | if (is_right) {
|
1631 | 1e4840bf | bellard | tcg_gen_shri_tl(t0, t0, data_bits - 1);
|
1632 | b6abf97d | bellard | } |
1633 | 1e4840bf | bellard | tcg_gen_andi_tl(t0, t0, CC_C); |
1634 | 1e4840bf | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); |
1635 | b6abf97d | bellard | |
1636 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_dst); |
1637 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
1638 | b6abf97d | bellard | |
1639 | b6abf97d | bellard | gen_set_label(label2); |
1640 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1641 | 1e4840bf | bellard | |
1642 | 1e4840bf | bellard | tcg_temp_free(t0); |
1643 | 1e4840bf | bellard | tcg_temp_free(t1); |
1644 | 1e4840bf | bellard | tcg_temp_free(t2); |
1645 | 1e4840bf | bellard | tcg_temp_free(a0); |
1646 | b6abf97d | bellard | } |
1647 | b6abf97d | bellard | |
1648 | 8cd6345d | malc | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1649 | 8cd6345d | malc | int is_right)
|
1650 | 8cd6345d | malc | { |
1651 | 8cd6345d | malc | int mask;
|
1652 | 8cd6345d | malc | int data_bits;
|
1653 | 8cd6345d | malc | TCGv t0, t1, a0; |
1654 | 8cd6345d | malc | |
1655 | 8cd6345d | malc | /* XXX: inefficient, but we must use local temps */
|
1656 | 8cd6345d | malc | t0 = tcg_temp_local_new(); |
1657 | 8cd6345d | malc | t1 = tcg_temp_local_new(); |
1658 | 8cd6345d | malc | a0 = tcg_temp_local_new(); |
1659 | 8cd6345d | malc | |
1660 | 8cd6345d | malc | if (ot == OT_QUAD)
|
1661 | 8cd6345d | malc | mask = 0x3f;
|
1662 | 8cd6345d | malc | else
|
1663 | 8cd6345d | malc | mask = 0x1f;
|
1664 | 8cd6345d | malc | |
1665 | 8cd6345d | malc | /* load */
|
1666 | 8cd6345d | malc | if (op1 == OR_TMP0) {
|
1667 | 8cd6345d | malc | tcg_gen_mov_tl(a0, cpu_A0); |
1668 | 8cd6345d | malc | gen_op_ld_v(ot + s->mem_index, t0, a0); |
1669 | 8cd6345d | malc | } else {
|
1670 | 8cd6345d | malc | gen_op_mov_v_reg(ot, t0, op1); |
1671 | 8cd6345d | malc | } |
1672 | 8cd6345d | malc | |
1673 | 8cd6345d | malc | gen_extu(ot, t0); |
1674 | 8cd6345d | malc | tcg_gen_mov_tl(t1, t0); |
1675 | 8cd6345d | malc | |
1676 | 8cd6345d | malc | op2 &= mask; |
1677 | 8cd6345d | malc | data_bits = 8 << ot;
|
1678 | 8cd6345d | malc | if (op2 != 0) { |
1679 | 8cd6345d | malc | int shift = op2 & ((1 << (3 + ot)) - 1); |
1680 | 8cd6345d | malc | if (is_right) {
|
1681 | 8cd6345d | malc | tcg_gen_shri_tl(cpu_tmp4, t0, shift); |
1682 | 8cd6345d | malc | tcg_gen_shli_tl(t0, t0, data_bits - shift); |
1683 | 8cd6345d | malc | } |
1684 | 8cd6345d | malc | else {
|
1685 | 8cd6345d | malc | tcg_gen_shli_tl(cpu_tmp4, t0, shift); |
1686 | 8cd6345d | malc | tcg_gen_shri_tl(t0, t0, data_bits - shift); |
1687 | 8cd6345d | malc | } |
1688 | 8cd6345d | malc | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
1689 | 8cd6345d | malc | } |
1690 | 8cd6345d | malc | |
1691 | 8cd6345d | malc | /* store */
|
1692 | 8cd6345d | malc | if (op1 == OR_TMP0) {
|
1693 | 8cd6345d | malc | gen_op_st_v(ot + s->mem_index, t0, a0); |
1694 | 8cd6345d | malc | } else {
|
1695 | 8cd6345d | malc | gen_op_mov_reg_v(ot, op1, t0); |
1696 | 8cd6345d | malc | } |
1697 | 8cd6345d | malc | |
1698 | 8cd6345d | malc | if (op2 != 0) { |
1699 | 8cd6345d | malc | /* update eflags */
|
1700 | 8cd6345d | malc | if (s->cc_op != CC_OP_DYNAMIC)
|
1701 | 8cd6345d | malc | gen_op_set_cc_op(s->cc_op); |
1702 | 8cd6345d | malc | |
1703 | 8cd6345d | malc | gen_compute_eflags(cpu_cc_src); |
1704 | 8cd6345d | malc | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1705 | 8cd6345d | malc | tcg_gen_xor_tl(cpu_tmp0, t1, t0); |
1706 | 8cd6345d | malc | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1707 | 8cd6345d | malc | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); |
1708 | 8cd6345d | malc | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
1709 | 8cd6345d | malc | if (is_right) {
|
1710 | 8cd6345d | malc | tcg_gen_shri_tl(t0, t0, data_bits - 1);
|
1711 | 8cd6345d | malc | } |
1712 | 8cd6345d | malc | tcg_gen_andi_tl(t0, t0, CC_C); |
1713 | 8cd6345d | malc | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); |
1714 | 8cd6345d | malc | |
1715 | 8cd6345d | malc | tcg_gen_discard_tl(cpu_cc_dst); |
1716 | 8cd6345d | malc | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
1717 | 8cd6345d | malc | s->cc_op = CC_OP_EFLAGS; |
1718 | 8cd6345d | malc | } |
1719 | 8cd6345d | malc | |
1720 | 8cd6345d | malc | tcg_temp_free(t0); |
1721 | 8cd6345d | malc | tcg_temp_free(t1); |
1722 | 8cd6345d | malc | tcg_temp_free(a0); |
1723 | 8cd6345d | malc | } |
1724 | 8cd6345d | malc | |
1725 | b6abf97d | bellard | /* XXX: add faster immediate = 1 case */
|
1726 | b6abf97d | bellard | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, |
1727 | b6abf97d | bellard | int is_right)
|
1728 | b6abf97d | bellard | { |
1729 | b6abf97d | bellard | int label1;
|
1730 | b6abf97d | bellard | |
1731 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1732 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1733 | b6abf97d | bellard | |
1734 | b6abf97d | bellard | /* load */
|
1735 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1736 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1737 | b6abf97d | bellard | else
|
1738 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1739 | b6abf97d | bellard | |
1740 | a7812ae4 | pbrook | if (is_right) {
|
1741 | a7812ae4 | pbrook | switch (ot) {
|
1742 | a7812ae4 | pbrook | case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1743 | a7812ae4 | pbrook | case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1744 | a7812ae4 | pbrook | case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1745 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
1746 | a7812ae4 | pbrook | case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1747 | a7812ae4 | pbrook | #endif
|
1748 | a7812ae4 | pbrook | } |
1749 | a7812ae4 | pbrook | } else {
|
1750 | a7812ae4 | pbrook | switch (ot) {
|
1751 | a7812ae4 | pbrook | case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1752 | a7812ae4 | pbrook | case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1753 | a7812ae4 | pbrook | case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1754 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
1755 | a7812ae4 | pbrook | case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break; |
1756 | a7812ae4 | pbrook | #endif
|
1757 | a7812ae4 | pbrook | } |
1758 | a7812ae4 | pbrook | } |
1759 | b6abf97d | bellard | /* store */
|
1760 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1761 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1762 | b6abf97d | bellard | else
|
1763 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1764 | b6abf97d | bellard | |
1765 | b6abf97d | bellard | /* update eflags */
|
1766 | b6abf97d | bellard | label1 = gen_new_label(); |
1767 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
|
1768 | b6abf97d | bellard | |
1769 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp); |
1770 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_dst); |
1771 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
1772 | b6abf97d | bellard | |
1773 | b6abf97d | bellard | gen_set_label(label1); |
1774 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1775 | b6abf97d | bellard | } |
1776 | b6abf97d | bellard | |
1777 | b6abf97d | bellard | /* XXX: add faster immediate case */
|
1778 | b6abf97d | bellard | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, |
1779 | b6abf97d | bellard | int is_right)
|
1780 | b6abf97d | bellard | { |
1781 | b6abf97d | bellard | int label1, label2, data_bits;
|
1782 | b6abf97d | bellard | target_ulong mask; |
1783 | 1e4840bf | bellard | TCGv t0, t1, t2, a0; |
1784 | 1e4840bf | bellard | |
1785 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1786 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1787 | a7812ae4 | pbrook | t2 = tcg_temp_local_new(); |
1788 | a7812ae4 | pbrook | a0 = tcg_temp_local_new(); |
1789 | b6abf97d | bellard | |
1790 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1791 | b6abf97d | bellard | mask = 0x3f;
|
1792 | b6abf97d | bellard | else
|
1793 | b6abf97d | bellard | mask = 0x1f;
|
1794 | b6abf97d | bellard | |
1795 | b6abf97d | bellard | /* load */
|
1796 | 1e4840bf | bellard | if (op1 == OR_TMP0) {
|
1797 | 1e4840bf | bellard | tcg_gen_mov_tl(a0, cpu_A0); |
1798 | 1e4840bf | bellard | gen_op_ld_v(ot + s->mem_index, t0, a0); |
1799 | 1e4840bf | bellard | } else {
|
1800 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t0, op1); |
1801 | 1e4840bf | bellard | } |
1802 | b6abf97d | bellard | |
1803 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); |
1804 | 1e4840bf | bellard | |
1805 | 1e4840bf | bellard | tcg_gen_mov_tl(t1, cpu_T[1]);
|
1806 | 1e4840bf | bellard | tcg_gen_mov_tl(t2, cpu_T3); |
1807 | 1e4840bf | bellard | |
1808 | b6abf97d | bellard | /* Must test zero case to avoid using undefined behaviour in TCG
|
1809 | b6abf97d | bellard | shifts. */
|
1810 | b6abf97d | bellard | label1 = gen_new_label(); |
1811 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
|
1812 | b6abf97d | bellard | |
1813 | 1e4840bf | bellard | tcg_gen_addi_tl(cpu_tmp5, t2, -1);
|
1814 | b6abf97d | bellard | if (ot == OT_WORD) {
|
1815 | b6abf97d | bellard | /* Note: we implement the Intel behaviour for shift count > 16 */
|
1816 | b6abf97d | bellard | if (is_right) {
|
1817 | 1e4840bf | bellard | tcg_gen_andi_tl(t0, t0, 0xffff);
|
1818 | 1e4840bf | bellard | tcg_gen_shli_tl(cpu_tmp0, t1, 16);
|
1819 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
1820 | 1e4840bf | bellard | tcg_gen_ext32u_tl(t0, t0); |
1821 | b6abf97d | bellard | |
1822 | 1e4840bf | bellard | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
1823 | b6abf97d | bellard | |
1824 | b6abf97d | bellard | /* only needed if count > 16, but a test would complicate */
|
1825 | 1e4840bf | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
|
1826 | 1e4840bf | bellard | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
1827 | b6abf97d | bellard | |
1828 | 1e4840bf | bellard | tcg_gen_shr_tl(t0, t0, t2); |
1829 | b6abf97d | bellard | |
1830 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
1831 | b6abf97d | bellard | } else {
|
1832 | b6abf97d | bellard | /* XXX: not optimal */
|
1833 | 1e4840bf | bellard | tcg_gen_andi_tl(t0, t0, 0xffff);
|
1834 | 1e4840bf | bellard | tcg_gen_shli_tl(t1, t1, 16);
|
1835 | 1e4840bf | bellard | tcg_gen_or_tl(t1, t1, t0); |
1836 | 1e4840bf | bellard | tcg_gen_ext32u_tl(t1, t1); |
1837 | b6abf97d | bellard | |
1838 | 1e4840bf | bellard | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
1839 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
|
1840 | 1e4840bf | bellard | tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0); |
1841 | b6abf97d | bellard | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6); |
1842 | b6abf97d | bellard | |
1843 | 1e4840bf | bellard | tcg_gen_shl_tl(t0, t0, t2); |
1844 | 1e4840bf | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
|
1845 | 1e4840bf | bellard | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1846 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, t1); |
1847 | b6abf97d | bellard | } |
1848 | b6abf97d | bellard | } else {
|
1849 | b6abf97d | bellard | data_bits = 8 << ot;
|
1850 | b6abf97d | bellard | if (is_right) {
|
1851 | b6abf97d | bellard | if (ot == OT_LONG)
|
1852 | 1e4840bf | bellard | tcg_gen_ext32u_tl(t0, t0); |
1853 | b6abf97d | bellard | |
1854 | 1e4840bf | bellard | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
1855 | b6abf97d | bellard | |
1856 | 1e4840bf | bellard | tcg_gen_shr_tl(t0, t0, t2); |
1857 | 1e4840bf | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); |
1858 | 1e4840bf | bellard | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1859 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, t1); |
1860 | b6abf97d | bellard | |
1861 | b6abf97d | bellard | } else {
|
1862 | b6abf97d | bellard | if (ot == OT_LONG)
|
1863 | 1e4840bf | bellard | tcg_gen_ext32u_tl(t1, t1); |
1864 | b6abf97d | bellard | |
1865 | 1e4840bf | bellard | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
1866 | b6abf97d | bellard | |
1867 | 1e4840bf | bellard | tcg_gen_shl_tl(t0, t0, t2); |
1868 | 1e4840bf | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); |
1869 | 1e4840bf | bellard | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1870 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, t1); |
1871 | b6abf97d | bellard | } |
1872 | b6abf97d | bellard | } |
1873 | 1e4840bf | bellard | tcg_gen_mov_tl(t1, cpu_tmp4); |
1874 | b6abf97d | bellard | |
1875 | b6abf97d | bellard | gen_set_label(label1); |
1876 | b6abf97d | bellard | /* store */
|
1877 | 1e4840bf | bellard | if (op1 == OR_TMP0) {
|
1878 | 1e4840bf | bellard | gen_op_st_v(ot + s->mem_index, t0, a0); |
1879 | 1e4840bf | bellard | } else {
|
1880 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, op1, t0); |
1881 | 1e4840bf | bellard | } |
1882 | b6abf97d | bellard | |
1883 | b6abf97d | bellard | /* update eflags */
|
1884 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1885 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1886 | b6abf97d | bellard | |
1887 | b6abf97d | bellard | label2 = gen_new_label(); |
1888 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
|
1889 | b6abf97d | bellard | |
1890 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_src, t1); |
1891 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_dst, t0); |
1892 | b6abf97d | bellard | if (is_right) {
|
1893 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
1894 | b6abf97d | bellard | } else {
|
1895 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
1896 | b6abf97d | bellard | } |
1897 | b6abf97d | bellard | gen_set_label(label2); |
1898 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1899 | 1e4840bf | bellard | |
1900 | 1e4840bf | bellard | tcg_temp_free(t0); |
1901 | 1e4840bf | bellard | tcg_temp_free(t1); |
1902 | 1e4840bf | bellard | tcg_temp_free(t2); |
1903 | 1e4840bf | bellard | tcg_temp_free(a0); |
1904 | b6abf97d | bellard | } |
1905 | b6abf97d | bellard | |
1906 | b6abf97d | bellard | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) |
1907 | b6abf97d | bellard | { |
1908 | b6abf97d | bellard | if (s != OR_TMP1)
|
1909 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 1, s);
|
1910 | b6abf97d | bellard | switch(op) {
|
1911 | b6abf97d | bellard | case OP_ROL:
|
1912 | b6abf97d | bellard | gen_rot_rm_T1(s1, ot, d, 0);
|
1913 | b6abf97d | bellard | break;
|
1914 | b6abf97d | bellard | case OP_ROR:
|
1915 | b6abf97d | bellard | gen_rot_rm_T1(s1, ot, d, 1);
|
1916 | b6abf97d | bellard | break;
|
1917 | b6abf97d | bellard | case OP_SHL:
|
1918 | b6abf97d | bellard | case OP_SHL1:
|
1919 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 0, 0); |
1920 | b6abf97d | bellard | break;
|
1921 | b6abf97d | bellard | case OP_SHR:
|
1922 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 1, 0); |
1923 | b6abf97d | bellard | break;
|
1924 | b6abf97d | bellard | case OP_SAR:
|
1925 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 1, 1); |
1926 | b6abf97d | bellard | break;
|
1927 | b6abf97d | bellard | case OP_RCL:
|
1928 | b6abf97d | bellard | gen_rotc_rm_T1(s1, ot, d, 0);
|
1929 | b6abf97d | bellard | break;
|
1930 | b6abf97d | bellard | case OP_RCR:
|
1931 | b6abf97d | bellard | gen_rotc_rm_T1(s1, ot, d, 1);
|
1932 | b6abf97d | bellard | break;
|
1933 | b6abf97d | bellard | } |
1934 | 2c0262af | bellard | } |
1935 | 2c0262af | bellard | |
1936 | 2c0262af | bellard | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) |
1937 | 2c0262af | bellard | { |
1938 | c1c37968 | bellard | switch(op) {
|
1939 | 8cd6345d | malc | case OP_ROL:
|
1940 | 8cd6345d | malc | gen_rot_rm_im(s1, ot, d, c, 0);
|
1941 | 8cd6345d | malc | break;
|
1942 | 8cd6345d | malc | case OP_ROR:
|
1943 | 8cd6345d | malc | gen_rot_rm_im(s1, ot, d, c, 1);
|
1944 | 8cd6345d | malc | break;
|
1945 | c1c37968 | bellard | case OP_SHL:
|
1946 | c1c37968 | bellard | case OP_SHL1:
|
1947 | c1c37968 | bellard | gen_shift_rm_im(s1, ot, d, c, 0, 0); |
1948 | c1c37968 | bellard | break;
|
1949 | c1c37968 | bellard | case OP_SHR:
|
1950 | c1c37968 | bellard | gen_shift_rm_im(s1, ot, d, c, 1, 0); |
1951 | c1c37968 | bellard | break;
|
1952 | c1c37968 | bellard | case OP_SAR:
|
1953 | c1c37968 | bellard | gen_shift_rm_im(s1, ot, d, c, 1, 1); |
1954 | c1c37968 | bellard | break;
|
1955 | c1c37968 | bellard | default:
|
1956 | c1c37968 | bellard | /* currently not optimized */
|
1957 | c1c37968 | bellard | gen_op_movl_T1_im(c); |
1958 | c1c37968 | bellard | gen_shift(s1, op, ot, d, OR_TMP1); |
1959 | c1c37968 | bellard | break;
|
1960 | c1c37968 | bellard | } |
1961 | 2c0262af | bellard | } |
1962 | 2c0262af | bellard | |
1963 | 2c0262af | bellard | static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) |
1964 | 2c0262af | bellard | { |
1965 | 14ce26e7 | bellard | target_long disp; |
1966 | 2c0262af | bellard | int havesib;
|
1967 | 14ce26e7 | bellard | int base;
|
1968 | 2c0262af | bellard | int index;
|
1969 | 2c0262af | bellard | int scale;
|
1970 | 2c0262af | bellard | int opreg;
|
1971 | 2c0262af | bellard | int mod, rm, code, override, must_add_seg;
|
1972 | 2c0262af | bellard | |
1973 | 2c0262af | bellard | override = s->override; |
1974 | 2c0262af | bellard | must_add_seg = s->addseg; |
1975 | 2c0262af | bellard | if (override >= 0) |
1976 | 2c0262af | bellard | must_add_seg = 1;
|
1977 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
1978 | 2c0262af | bellard | rm = modrm & 7;
|
1979 | 2c0262af | bellard | |
1980 | 2c0262af | bellard | if (s->aflag) {
|
1981 | 2c0262af | bellard | |
1982 | 2c0262af | bellard | havesib = 0;
|
1983 | 2c0262af | bellard | base = rm; |
1984 | 2c0262af | bellard | index = 0;
|
1985 | 2c0262af | bellard | scale = 0;
|
1986 | 3b46e624 | ths | |
1987 | 2c0262af | bellard | if (base == 4) { |
1988 | 2c0262af | bellard | havesib = 1;
|
1989 | 61382a50 | bellard | code = ldub_code(s->pc++); |
1990 | 2c0262af | bellard | scale = (code >> 6) & 3; |
1991 | 14ce26e7 | bellard | index = ((code >> 3) & 7) | REX_X(s); |
1992 | 14ce26e7 | bellard | base = (code & 7);
|
1993 | 2c0262af | bellard | } |
1994 | 14ce26e7 | bellard | base |= REX_B(s); |
1995 | 2c0262af | bellard | |
1996 | 2c0262af | bellard | switch (mod) {
|
1997 | 2c0262af | bellard | case 0: |
1998 | 14ce26e7 | bellard | if ((base & 7) == 5) { |
1999 | 2c0262af | bellard | base = -1;
|
2000 | 14ce26e7 | bellard | disp = (int32_t)ldl_code(s->pc); |
2001 | 2c0262af | bellard | s->pc += 4;
|
2002 | 14ce26e7 | bellard | if (CODE64(s) && !havesib) {
|
2003 | 14ce26e7 | bellard | disp += s->pc + s->rip_offset; |
2004 | 14ce26e7 | bellard | } |
2005 | 2c0262af | bellard | } else {
|
2006 | 2c0262af | bellard | disp = 0;
|
2007 | 2c0262af | bellard | } |
2008 | 2c0262af | bellard | break;
|
2009 | 2c0262af | bellard | case 1: |
2010 | 61382a50 | bellard | disp = (int8_t)ldub_code(s->pc++); |
2011 | 2c0262af | bellard | break;
|
2012 | 2c0262af | bellard | default:
|
2013 | 2c0262af | bellard | case 2: |
2014 | 61382a50 | bellard | disp = ldl_code(s->pc); |
2015 | 2c0262af | bellard | s->pc += 4;
|
2016 | 2c0262af | bellard | break;
|
2017 | 2c0262af | bellard | } |
2018 | 3b46e624 | ths | |
2019 | 2c0262af | bellard | if (base >= 0) { |
2020 | 2c0262af | bellard | /* for correct popl handling with esp */
|
2021 | 2c0262af | bellard | if (base == 4 && s->popl_esp_hack) |
2022 | 2c0262af | bellard | disp += s->popl_esp_hack; |
2023 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2024 | 14ce26e7 | bellard | if (s->aflag == 2) { |
2025 | 57fec1fe | bellard | gen_op_movq_A0_reg(base); |
2026 | 14ce26e7 | bellard | if (disp != 0) { |
2027 | 57fec1fe | bellard | gen_op_addq_A0_im(disp); |
2028 | 14ce26e7 | bellard | } |
2029 | 5fafdf24 | ths | } else
|
2030 | 14ce26e7 | bellard | #endif
|
2031 | 14ce26e7 | bellard | { |
2032 | 57fec1fe | bellard | gen_op_movl_A0_reg(base); |
2033 | 14ce26e7 | bellard | if (disp != 0) |
2034 | 14ce26e7 | bellard | gen_op_addl_A0_im(disp); |
2035 | 14ce26e7 | bellard | } |
2036 | 2c0262af | bellard | } else {
|
2037 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2038 | 14ce26e7 | bellard | if (s->aflag == 2) { |
2039 | 57fec1fe | bellard | gen_op_movq_A0_im(disp); |
2040 | 5fafdf24 | ths | } else
|
2041 | 14ce26e7 | bellard | #endif
|
2042 | 14ce26e7 | bellard | { |
2043 | 14ce26e7 | bellard | gen_op_movl_A0_im(disp); |
2044 | 14ce26e7 | bellard | } |
2045 | 2c0262af | bellard | } |
2046 | 2c0262af | bellard | /* XXX: index == 4 is always invalid */
|
2047 | 2c0262af | bellard | if (havesib && (index != 4 || scale != 0)) { |
2048 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2049 | 14ce26e7 | bellard | if (s->aflag == 2) { |
2050 | 57fec1fe | bellard | gen_op_addq_A0_reg_sN(scale, index); |
2051 | 5fafdf24 | ths | } else
|
2052 | 14ce26e7 | bellard | #endif
|
2053 | 14ce26e7 | bellard | { |
2054 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(scale, index); |
2055 | 14ce26e7 | bellard | } |
2056 | 2c0262af | bellard | } |
2057 | 2c0262af | bellard | if (must_add_seg) {
|
2058 | 2c0262af | bellard | if (override < 0) { |
2059 | 2c0262af | bellard | if (base == R_EBP || base == R_ESP)
|
2060 | 2c0262af | bellard | override = R_SS; |
2061 | 2c0262af | bellard | else
|
2062 | 2c0262af | bellard | override = R_DS; |
2063 | 2c0262af | bellard | } |
2064 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2065 | 14ce26e7 | bellard | if (s->aflag == 2) { |
2066 | 57fec1fe | bellard | gen_op_addq_A0_seg(override); |
2067 | 5fafdf24 | ths | } else
|
2068 | 14ce26e7 | bellard | #endif
|
2069 | 14ce26e7 | bellard | { |
2070 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
2071 | 14ce26e7 | bellard | } |
2072 | 2c0262af | bellard | } |
2073 | 2c0262af | bellard | } else {
|
2074 | 2c0262af | bellard | switch (mod) {
|
2075 | 2c0262af | bellard | case 0: |
2076 | 2c0262af | bellard | if (rm == 6) { |
2077 | 61382a50 | bellard | disp = lduw_code(s->pc); |
2078 | 2c0262af | bellard | s->pc += 2;
|
2079 | 2c0262af | bellard | gen_op_movl_A0_im(disp); |
2080 | 2c0262af | bellard | rm = 0; /* avoid SS override */ |
2081 | 2c0262af | bellard | goto no_rm;
|
2082 | 2c0262af | bellard | } else {
|
2083 | 2c0262af | bellard | disp = 0;
|
2084 | 2c0262af | bellard | } |
2085 | 2c0262af | bellard | break;
|
2086 | 2c0262af | bellard | case 1: |
2087 | 61382a50 | bellard | disp = (int8_t)ldub_code(s->pc++); |
2088 | 2c0262af | bellard | break;
|
2089 | 2c0262af | bellard | default:
|
2090 | 2c0262af | bellard | case 2: |
2091 | 61382a50 | bellard | disp = lduw_code(s->pc); |
2092 | 2c0262af | bellard | s->pc += 2;
|
2093 | 2c0262af | bellard | break;
|
2094 | 2c0262af | bellard | } |
2095 | 2c0262af | bellard | switch(rm) {
|
2096 | 2c0262af | bellard | case 0: |
2097 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
2098 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
2099 | 2c0262af | bellard | break;
|
2100 | 2c0262af | bellard | case 1: |
2101 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
2102 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
2103 | 2c0262af | bellard | break;
|
2104 | 2c0262af | bellard | case 2: |
2105 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
2106 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
2107 | 2c0262af | bellard | break;
|
2108 | 2c0262af | bellard | case 3: |
2109 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
2110 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
2111 | 2c0262af | bellard | break;
|
2112 | 2c0262af | bellard | case 4: |
2113 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
2114 | 2c0262af | bellard | break;
|
2115 | 2c0262af | bellard | case 5: |
2116 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
2117 | 2c0262af | bellard | break;
|
2118 | 2c0262af | bellard | case 6: |
2119 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
2120 | 2c0262af | bellard | break;
|
2121 | 2c0262af | bellard | default:
|
2122 | 2c0262af | bellard | case 7: |
2123 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
2124 | 2c0262af | bellard | break;
|
2125 | 2c0262af | bellard | } |
2126 | 2c0262af | bellard | if (disp != 0) |
2127 | 2c0262af | bellard | gen_op_addl_A0_im(disp); |
2128 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2129 | 2c0262af | bellard | no_rm:
|
2130 | 2c0262af | bellard | if (must_add_seg) {
|
2131 | 2c0262af | bellard | if (override < 0) { |
2132 | 2c0262af | bellard | if (rm == 2 || rm == 3 || rm == 6) |
2133 | 2c0262af | bellard | override = R_SS; |
2134 | 2c0262af | bellard | else
|
2135 | 2c0262af | bellard | override = R_DS; |
2136 | 2c0262af | bellard | } |
2137 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
2138 | 2c0262af | bellard | } |
2139 | 2c0262af | bellard | } |
2140 | 2c0262af | bellard | |
2141 | 2c0262af | bellard | opreg = OR_A0; |
2142 | 2c0262af | bellard | disp = 0;
|
2143 | 2c0262af | bellard | *reg_ptr = opreg; |
2144 | 2c0262af | bellard | *offset_ptr = disp; |
2145 | 2c0262af | bellard | } |
2146 | 2c0262af | bellard | |
2147 | e17a36ce | bellard | static void gen_nop_modrm(DisasContext *s, int modrm) |
2148 | e17a36ce | bellard | { |
2149 | e17a36ce | bellard | int mod, rm, base, code;
|
2150 | e17a36ce | bellard | |
2151 | e17a36ce | bellard | mod = (modrm >> 6) & 3; |
2152 | e17a36ce | bellard | if (mod == 3) |
2153 | e17a36ce | bellard | return;
|
2154 | e17a36ce | bellard | rm = modrm & 7;
|
2155 | e17a36ce | bellard | |
2156 | e17a36ce | bellard | if (s->aflag) {
|
2157 | e17a36ce | bellard | |
2158 | e17a36ce | bellard | base = rm; |
2159 | 3b46e624 | ths | |
2160 | e17a36ce | bellard | if (base == 4) { |
2161 | e17a36ce | bellard | code = ldub_code(s->pc++); |
2162 | e17a36ce | bellard | base = (code & 7);
|
2163 | e17a36ce | bellard | } |
2164 | 3b46e624 | ths | |
2165 | e17a36ce | bellard | switch (mod) {
|
2166 | e17a36ce | bellard | case 0: |
2167 | e17a36ce | bellard | if (base == 5) { |
2168 | e17a36ce | bellard | s->pc += 4;
|
2169 | e17a36ce | bellard | } |
2170 | e17a36ce | bellard | break;
|
2171 | e17a36ce | bellard | case 1: |
2172 | e17a36ce | bellard | s->pc++; |
2173 | e17a36ce | bellard | break;
|
2174 | e17a36ce | bellard | default:
|
2175 | e17a36ce | bellard | case 2: |
2176 | e17a36ce | bellard | s->pc += 4;
|
2177 | e17a36ce | bellard | break;
|
2178 | e17a36ce | bellard | } |
2179 | e17a36ce | bellard | } else {
|
2180 | e17a36ce | bellard | switch (mod) {
|
2181 | e17a36ce | bellard | case 0: |
2182 | e17a36ce | bellard | if (rm == 6) { |
2183 | e17a36ce | bellard | s->pc += 2;
|
2184 | e17a36ce | bellard | } |
2185 | e17a36ce | bellard | break;
|
2186 | e17a36ce | bellard | case 1: |
2187 | e17a36ce | bellard | s->pc++; |
2188 | e17a36ce | bellard | break;
|
2189 | e17a36ce | bellard | default:
|
2190 | e17a36ce | bellard | case 2: |
2191 | e17a36ce | bellard | s->pc += 2;
|
2192 | e17a36ce | bellard | break;
|
2193 | e17a36ce | bellard | } |
2194 | e17a36ce | bellard | } |
2195 | e17a36ce | bellard | } |
2196 | e17a36ce | bellard | |
2197 | 664e0f19 | bellard | /* used for LEA and MOV AX, mem */
|
2198 | 664e0f19 | bellard | static void gen_add_A0_ds_seg(DisasContext *s) |
2199 | 664e0f19 | bellard | { |
2200 | 664e0f19 | bellard | int override, must_add_seg;
|
2201 | 664e0f19 | bellard | must_add_seg = s->addseg; |
2202 | 664e0f19 | bellard | override = R_DS; |
2203 | 664e0f19 | bellard | if (s->override >= 0) { |
2204 | 664e0f19 | bellard | override = s->override; |
2205 | 664e0f19 | bellard | must_add_seg = 1;
|
2206 | 664e0f19 | bellard | } else {
|
2207 | 664e0f19 | bellard | override = R_DS; |
2208 | 664e0f19 | bellard | } |
2209 | 664e0f19 | bellard | if (must_add_seg) {
|
2210 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
2211 | 8f091a59 | bellard | if (CODE64(s)) {
|
2212 | 57fec1fe | bellard | gen_op_addq_A0_seg(override); |
2213 | 5fafdf24 | ths | } else
|
2214 | 8f091a59 | bellard | #endif
|
2215 | 8f091a59 | bellard | { |
2216 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
2217 | 8f091a59 | bellard | } |
2218 | 664e0f19 | bellard | } |
2219 | 664e0f19 | bellard | } |
2220 | 664e0f19 | bellard | |
2221 | 222a3336 | balrog | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
|
2222 | 2c0262af | bellard | OR_TMP0 */
|
2223 | 2c0262af | bellard | static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) |
2224 | 2c0262af | bellard | { |
2225 | 2c0262af | bellard | int mod, rm, opreg, disp;
|
2226 | 2c0262af | bellard | |
2227 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
2228 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
2229 | 2c0262af | bellard | if (mod == 3) { |
2230 | 2c0262af | bellard | if (is_store) {
|
2231 | 2c0262af | bellard | if (reg != OR_TMP0)
|
2232 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
2233 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
2234 | 2c0262af | bellard | } else {
|
2235 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
2236 | 2c0262af | bellard | if (reg != OR_TMP0)
|
2237 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
2238 | 2c0262af | bellard | } |
2239 | 2c0262af | bellard | } else {
|
2240 | 2c0262af | bellard | gen_lea_modrm(s, modrm, &opreg, &disp); |
2241 | 2c0262af | bellard | if (is_store) {
|
2242 | 2c0262af | bellard | if (reg != OR_TMP0)
|
2243 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
2244 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
2245 | 2c0262af | bellard | } else {
|
2246 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
2247 | 2c0262af | bellard | if (reg != OR_TMP0)
|
2248 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
2249 | 2c0262af | bellard | } |
2250 | 2c0262af | bellard | } |
2251 | 2c0262af | bellard | } |
2252 | 2c0262af | bellard | |
2253 | 2c0262af | bellard | static inline uint32_t insn_get(DisasContext *s, int ot) |
2254 | 2c0262af | bellard | { |
2255 | 2c0262af | bellard | uint32_t ret; |
2256 | 2c0262af | bellard | |
2257 | 2c0262af | bellard | switch(ot) {
|
2258 | 2c0262af | bellard | case OT_BYTE:
|
2259 | 61382a50 | bellard | ret = ldub_code(s->pc); |
2260 | 2c0262af | bellard | s->pc++; |
2261 | 2c0262af | bellard | break;
|
2262 | 2c0262af | bellard | case OT_WORD:
|
2263 | 61382a50 | bellard | ret = lduw_code(s->pc); |
2264 | 2c0262af | bellard | s->pc += 2;
|
2265 | 2c0262af | bellard | break;
|
2266 | 2c0262af | bellard | default:
|
2267 | 2c0262af | bellard | case OT_LONG:
|
2268 | 61382a50 | bellard | ret = ldl_code(s->pc); |
2269 | 2c0262af | bellard | s->pc += 4;
|
2270 | 2c0262af | bellard | break;
|
2271 | 2c0262af | bellard | } |
2272 | 2c0262af | bellard | return ret;
|
2273 | 2c0262af | bellard | } |
2274 | 2c0262af | bellard | |
2275 | 14ce26e7 | bellard | static inline int insn_const_size(unsigned int ot) |
2276 | 14ce26e7 | bellard | { |
2277 | 14ce26e7 | bellard | if (ot <= OT_LONG)
|
2278 | 14ce26e7 | bellard | return 1 << ot; |
2279 | 14ce26e7 | bellard | else
|
2280 | 14ce26e7 | bellard | return 4; |
2281 | 14ce26e7 | bellard | } |
2282 | 14ce26e7 | bellard | |
2283 | 6e256c93 | bellard | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2284 | 6e256c93 | bellard | { |
2285 | 6e256c93 | bellard | TranslationBlock *tb; |
2286 | 6e256c93 | bellard | target_ulong pc; |
2287 | 6e256c93 | bellard | |
2288 | 6e256c93 | bellard | pc = s->cs_base + eip; |
2289 | 6e256c93 | bellard | tb = s->tb; |
2290 | 6e256c93 | bellard | /* NOTE: we handle the case where the TB spans two pages here */
|
2291 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
|
2292 | 6e256c93 | bellard | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
|
2293 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
|
2294 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
2295 | 6e256c93 | bellard | gen_jmp_im(eip); |
2296 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
|
2297 | 6e256c93 | bellard | } else {
|
2298 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
|
2299 | 6e256c93 | bellard | gen_jmp_im(eip); |
2300 | 6e256c93 | bellard | gen_eob(s); |
2301 | 6e256c93 | bellard | } |
2302 | 6e256c93 | bellard | } |
2303 | 6e256c93 | bellard | |
2304 | 5fafdf24 | ths | static inline void gen_jcc(DisasContext *s, int b, |
2305 | 14ce26e7 | bellard | target_ulong val, target_ulong next_eip) |
2306 | 2c0262af | bellard | { |
2307 | 8e1c85e3 | bellard | int l1, l2, cc_op;
|
2308 | 3b46e624 | ths | |
2309 | 8e1c85e3 | bellard | cc_op = s->cc_op; |
2310 | 8e1c85e3 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
2311 | 8e1c85e3 | bellard | gen_op_set_cc_op(s->cc_op); |
2312 | 8e1c85e3 | bellard | s->cc_op = CC_OP_DYNAMIC; |
2313 | 8e1c85e3 | bellard | } |
2314 | 2c0262af | bellard | if (s->jmp_opt) {
|
2315 | 14ce26e7 | bellard | l1 = gen_new_label(); |
2316 | 8e1c85e3 | bellard | gen_jcc1(s, cc_op, b, l1); |
2317 | 8e1c85e3 | bellard | |
2318 | 6e256c93 | bellard | gen_goto_tb(s, 0, next_eip);
|
2319 | 14ce26e7 | bellard | |
2320 | 14ce26e7 | bellard | gen_set_label(l1); |
2321 | 6e256c93 | bellard | gen_goto_tb(s, 1, val);
|
2322 | 2c0262af | bellard | s->is_jmp = 3;
|
2323 | 2c0262af | bellard | } else {
|
2324 | 14ce26e7 | bellard | |
2325 | 14ce26e7 | bellard | l1 = gen_new_label(); |
2326 | 14ce26e7 | bellard | l2 = gen_new_label(); |
2327 | 8e1c85e3 | bellard | gen_jcc1(s, cc_op, b, l1); |
2328 | 8e1c85e3 | bellard | |
2329 | 14ce26e7 | bellard | gen_jmp_im(next_eip); |
2330 | 8e1c85e3 | bellard | tcg_gen_br(l2); |
2331 | 8e1c85e3 | bellard | |
2332 | 14ce26e7 | bellard | gen_set_label(l1); |
2333 | 14ce26e7 | bellard | gen_jmp_im(val); |
2334 | 14ce26e7 | bellard | gen_set_label(l2); |
2335 | 2c0262af | bellard | gen_eob(s); |
2336 | 2c0262af | bellard | } |
2337 | 2c0262af | bellard | } |
2338 | 2c0262af | bellard | |
2339 | 2c0262af | bellard | static void gen_setcc(DisasContext *s, int b) |
2340 | 2c0262af | bellard | { |
2341 | 8e1c85e3 | bellard | int inv, jcc_op, l1;
|
2342 | 1e4840bf | bellard | TCGv t0; |
2343 | 14ce26e7 | bellard | |
2344 | 8e1c85e3 | bellard | if (is_fast_jcc_case(s, b)) {
|
2345 | 8e1c85e3 | bellard | /* nominal case: we use a jump */
|
2346 | 1e4840bf | bellard | /* XXX: make it faster by adding new instructions in TCG */
|
2347 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
2348 | 1e4840bf | bellard | tcg_gen_movi_tl(t0, 0);
|
2349 | 8e1c85e3 | bellard | l1 = gen_new_label(); |
2350 | 8e1c85e3 | bellard | gen_jcc1(s, s->cc_op, b ^ 1, l1);
|
2351 | 1e4840bf | bellard | tcg_gen_movi_tl(t0, 1);
|
2352 | 8e1c85e3 | bellard | gen_set_label(l1); |
2353 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_T[0], t0);
|
2354 | 1e4840bf | bellard | tcg_temp_free(t0); |
2355 | 8e1c85e3 | bellard | } else {
|
2356 | 8e1c85e3 | bellard | /* slow case: it is more efficient not to generate a jump,
|
2357 | 8e1c85e3 | bellard | although it is questionnable whether this optimization is
|
2358 | 8e1c85e3 | bellard | worth to */
|
2359 | 8e1c85e3 | bellard | inv = b & 1;
|
2360 | 8e1c85e3 | bellard | jcc_op = (b >> 1) & 7; |
2361 | 1e4840bf | bellard | gen_setcc_slow_T0(s, jcc_op); |
2362 | 8e1c85e3 | bellard | if (inv) {
|
2363 | 8e1c85e3 | bellard | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); |
2364 | 8e1c85e3 | bellard | } |
2365 | 2c0262af | bellard | } |
2366 | 2c0262af | bellard | } |
2367 | 2c0262af | bellard | |
2368 | 3bd7da9e | bellard | static inline void gen_op_movl_T0_seg(int seg_reg) |
2369 | 3bd7da9e | bellard | { |
2370 | 3bd7da9e | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
|
2371 | 3bd7da9e | bellard | offsetof(CPUX86State,segs[seg_reg].selector)); |
2372 | 3bd7da9e | bellard | } |
2373 | 3bd7da9e | bellard | |
2374 | 3bd7da9e | bellard | static inline void gen_op_movl_seg_T0_vm(int seg_reg) |
2375 | 3bd7da9e | bellard | { |
2376 | 3bd7da9e | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
2377 | 3bd7da9e | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env,
|
2378 | 3bd7da9e | bellard | offsetof(CPUX86State,segs[seg_reg].selector)); |
2379 | 3bd7da9e | bellard | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); |
2380 | 3bd7da9e | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env,
|
2381 | 3bd7da9e | bellard | offsetof(CPUX86State,segs[seg_reg].base)); |
2382 | 3bd7da9e | bellard | } |
2383 | 3bd7da9e | bellard | |
2384 | 2c0262af | bellard | /* move T0 to seg_reg and compute if the CPU state may change. Never
|
2385 | 2c0262af | bellard | call this function with seg_reg == R_CS */
|
2386 | 14ce26e7 | bellard | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2387 | 2c0262af | bellard | { |
2388 | 3415a4dd | bellard | if (s->pe && !s->vm86) {
|
2389 | 3415a4dd | bellard | /* XXX: optimize by finding processor state dynamically */
|
2390 | 3415a4dd | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2391 | 3415a4dd | bellard | gen_op_set_cc_op(s->cc_op); |
2392 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2393 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
2394 | a7812ae4 | pbrook | gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32); |
2395 | dc196a57 | bellard | /* abort translation because the addseg value may change or
|
2396 | dc196a57 | bellard | because ss32 may change. For R_SS, translation must always
|
2397 | dc196a57 | bellard | stop as a special handling must be done to disable hardware
|
2398 | dc196a57 | bellard | interrupts for the next instruction */
|
2399 | dc196a57 | bellard | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
|
2400 | dc196a57 | bellard | s->is_jmp = 3;
|
2401 | 3415a4dd | bellard | } else {
|
2402 | 3bd7da9e | bellard | gen_op_movl_seg_T0_vm(seg_reg); |
2403 | dc196a57 | bellard | if (seg_reg == R_SS)
|
2404 | dc196a57 | bellard | s->is_jmp = 3;
|
2405 | 3415a4dd | bellard | } |
2406 | 2c0262af | bellard | } |
2407 | 2c0262af | bellard | |
2408 | 0573fbfc | ths | static inline int svm_is_rep(int prefixes) |
2409 | 0573fbfc | ths | { |
2410 | 0573fbfc | ths | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); |
2411 | 0573fbfc | ths | } |
2412 | 0573fbfc | ths | |
2413 | 872929aa | bellard | static inline void |
2414 | 0573fbfc | ths | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
2415 | b8b6a50b | bellard | uint32_t type, uint64_t param) |
2416 | 0573fbfc | ths | { |
2417 | 872929aa | bellard | /* no SVM activated; fast case */
|
2418 | 872929aa | bellard | if (likely(!(s->flags & HF_SVMI_MASK)))
|
2419 | 872929aa | bellard | return;
|
2420 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2421 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
2422 | 872929aa | bellard | gen_jmp_im(pc_start - s->cs_base); |
2423 | a7812ae4 | pbrook | gen_helper_svm_check_intercept_param(tcg_const_i32(type), |
2424 | a7812ae4 | pbrook | tcg_const_i64(param)); |
2425 | 0573fbfc | ths | } |
2426 | 0573fbfc | ths | |
2427 | 872929aa | bellard | static inline void |
2428 | 0573fbfc | ths | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2429 | 0573fbfc | ths | { |
2430 | 872929aa | bellard | gen_svm_check_intercept_param(s, pc_start, type, 0);
|
2431 | 0573fbfc | ths | } |
2432 | 0573fbfc | ths | |
2433 | 4f31916f | bellard | static inline void gen_stack_update(DisasContext *s, int addend) |
2434 | 4f31916f | bellard | { |
2435 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2436 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2437 | 6e0d8677 | bellard | gen_op_add_reg_im(2, R_ESP, addend);
|
2438 | 14ce26e7 | bellard | } else
|
2439 | 14ce26e7 | bellard | #endif
|
2440 | 4f31916f | bellard | if (s->ss32) {
|
2441 | 6e0d8677 | bellard | gen_op_add_reg_im(1, R_ESP, addend);
|
2442 | 4f31916f | bellard | } else {
|
2443 | 6e0d8677 | bellard | gen_op_add_reg_im(0, R_ESP, addend);
|
2444 | 4f31916f | bellard | } |
2445 | 4f31916f | bellard | } |
2446 | 4f31916f | bellard | |
2447 | 2c0262af | bellard | /* generate a push. It depends on ss32, addseg and dflag */
|
2448 | 2c0262af | bellard | static void gen_push_T0(DisasContext *s) |
2449 | 2c0262af | bellard | { |
2450 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2451 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2452 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2453 | 8f091a59 | bellard | if (s->dflag) {
|
2454 | 57fec1fe | bellard | gen_op_addq_A0_im(-8);
|
2455 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_QUAD + s->mem_index); |
2456 | 8f091a59 | bellard | } else {
|
2457 | 57fec1fe | bellard | gen_op_addq_A0_im(-2);
|
2458 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2459 | 8f091a59 | bellard | } |
2460 | 57fec1fe | bellard | gen_op_mov_reg_A0(2, R_ESP);
|
2461 | 5fafdf24 | ths | } else
|
2462 | 14ce26e7 | bellard | #endif
|
2463 | 14ce26e7 | bellard | { |
2464 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2465 | 14ce26e7 | bellard | if (!s->dflag)
|
2466 | 57fec1fe | bellard | gen_op_addl_A0_im(-2);
|
2467 | 14ce26e7 | bellard | else
|
2468 | 57fec1fe | bellard | gen_op_addl_A0_im(-4);
|
2469 | 14ce26e7 | bellard | if (s->ss32) {
|
2470 | 14ce26e7 | bellard | if (s->addseg) {
|
2471 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2472 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2473 | 14ce26e7 | bellard | } |
2474 | 14ce26e7 | bellard | } else {
|
2475 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2476 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2477 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2478 | 2c0262af | bellard | } |
2479 | 57fec1fe | bellard | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
|
2480 | 14ce26e7 | bellard | if (s->ss32 && !s->addseg)
|
2481 | 57fec1fe | bellard | gen_op_mov_reg_A0(1, R_ESP);
|
2482 | 14ce26e7 | bellard | else
|
2483 | 57fec1fe | bellard | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
|
2484 | 2c0262af | bellard | } |
2485 | 2c0262af | bellard | } |
2486 | 2c0262af | bellard | |
2487 | 4f31916f | bellard | /* generate a push. It depends on ss32, addseg and dflag */
|
2488 | 4f31916f | bellard | /* slower version for T1, only used for call Ev */
|
2489 | 4f31916f | bellard | static void gen_push_T1(DisasContext *s) |
2490 | 2c0262af | bellard | { |
2491 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2492 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2493 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2494 | 8f091a59 | bellard | if (s->dflag) {
|
2495 | 57fec1fe | bellard | gen_op_addq_A0_im(-8);
|
2496 | 57fec1fe | bellard | gen_op_st_T1_A0(OT_QUAD + s->mem_index); |
2497 | 8f091a59 | bellard | } else {
|
2498 | 57fec1fe | bellard | gen_op_addq_A0_im(-2);
|
2499 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2500 | 8f091a59 | bellard | } |
2501 | 57fec1fe | bellard | gen_op_mov_reg_A0(2, R_ESP);
|
2502 | 5fafdf24 | ths | } else
|
2503 | 14ce26e7 | bellard | #endif
|
2504 | 14ce26e7 | bellard | { |
2505 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2506 | 14ce26e7 | bellard | if (!s->dflag)
|
2507 | 57fec1fe | bellard | gen_op_addl_A0_im(-2);
|
2508 | 14ce26e7 | bellard | else
|
2509 | 57fec1fe | bellard | gen_op_addl_A0_im(-4);
|
2510 | 14ce26e7 | bellard | if (s->ss32) {
|
2511 | 14ce26e7 | bellard | if (s->addseg) {
|
2512 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2513 | 14ce26e7 | bellard | } |
2514 | 14ce26e7 | bellard | } else {
|
2515 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2516 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2517 | 2c0262af | bellard | } |
2518 | 57fec1fe | bellard | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
|
2519 | 3b46e624 | ths | |
2520 | 14ce26e7 | bellard | if (s->ss32 && !s->addseg)
|
2521 | 57fec1fe | bellard | gen_op_mov_reg_A0(1, R_ESP);
|
2522 | 14ce26e7 | bellard | else
|
2523 | 14ce26e7 | bellard | gen_stack_update(s, (-2) << s->dflag);
|
2524 | 2c0262af | bellard | } |
2525 | 2c0262af | bellard | } |
2526 | 2c0262af | bellard | |
2527 | 4f31916f | bellard | /* two step pop is necessary for precise exceptions */
|
2528 | 4f31916f | bellard | static void gen_pop_T0(DisasContext *s) |
2529 | 2c0262af | bellard | { |
2530 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2531 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2532 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2533 | 57fec1fe | bellard | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); |
2534 | 5fafdf24 | ths | } else
|
2535 | 14ce26e7 | bellard | #endif
|
2536 | 14ce26e7 | bellard | { |
2537 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2538 | 14ce26e7 | bellard | if (s->ss32) {
|
2539 | 14ce26e7 | bellard | if (s->addseg)
|
2540 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2541 | 14ce26e7 | bellard | } else {
|
2542 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2543 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2544 | 14ce26e7 | bellard | } |
2545 | 57fec1fe | bellard | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
|
2546 | 2c0262af | bellard | } |
2547 | 2c0262af | bellard | } |
2548 | 2c0262af | bellard | |
2549 | 2c0262af | bellard | static void gen_pop_update(DisasContext *s) |
2550 | 2c0262af | bellard | { |
2551 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2552 | 8f091a59 | bellard | if (CODE64(s) && s->dflag) {
|
2553 | 14ce26e7 | bellard | gen_stack_update(s, 8);
|
2554 | 14ce26e7 | bellard | } else
|
2555 | 14ce26e7 | bellard | #endif
|
2556 | 14ce26e7 | bellard | { |
2557 | 14ce26e7 | bellard | gen_stack_update(s, 2 << s->dflag);
|
2558 | 14ce26e7 | bellard | } |
2559 | 2c0262af | bellard | } |
2560 | 2c0262af | bellard | |
2561 | 2c0262af | bellard | static void gen_stack_A0(DisasContext *s) |
2562 | 2c0262af | bellard | { |
2563 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2564 | 2c0262af | bellard | if (!s->ss32)
|
2565 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2566 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2567 | 2c0262af | bellard | if (s->addseg)
|
2568 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2569 | 2c0262af | bellard | } |
2570 | 2c0262af | bellard | |
2571 | 2c0262af | bellard | /* NOTE: wrap around in 16 bit not fully handled */
|
2572 | 2c0262af | bellard | static void gen_pusha(DisasContext *s) |
2573 | 2c0262af | bellard | { |
2574 | 2c0262af | bellard | int i;
|
2575 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2576 | 2c0262af | bellard | gen_op_addl_A0_im(-16 << s->dflag);
|
2577 | 2c0262af | bellard | if (!s->ss32)
|
2578 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2579 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2580 | 2c0262af | bellard | if (s->addseg)
|
2581 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2582 | 2c0262af | bellard | for(i = 0;i < 8; i++) { |
2583 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2584 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2585 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
2586 | 2c0262af | bellard | } |
2587 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2588 | 2c0262af | bellard | } |
2589 | 2c0262af | bellard | |
2590 | 2c0262af | bellard | /* NOTE: wrap around in 16 bit not fully handled */
|
2591 | 2c0262af | bellard | static void gen_popa(DisasContext *s) |
2592 | 2c0262af | bellard | { |
2593 | 2c0262af | bellard | int i;
|
2594 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2595 | 2c0262af | bellard | if (!s->ss32)
|
2596 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2597 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2598 | bbf662ee | bellard | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); |
2599 | 2c0262af | bellard | if (s->addseg)
|
2600 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2601 | 2c0262af | bellard | for(i = 0;i < 8; i++) { |
2602 | 2c0262af | bellard | /* ESP is not reloaded */
|
2603 | 2c0262af | bellard | if (i != 3) { |
2604 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2605 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
|
2606 | 2c0262af | bellard | } |
2607 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
2608 | 2c0262af | bellard | } |
2609 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2610 | 2c0262af | bellard | } |
2611 | 2c0262af | bellard | |
2612 | 2c0262af | bellard | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2613 | 2c0262af | bellard | { |
2614 | 61a8c4ec | bellard | int ot, opsize;
|
2615 | 2c0262af | bellard | |
2616 | 2c0262af | bellard | level &= 0x1f;
|
2617 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
2618 | 8f091a59 | bellard | if (CODE64(s)) {
|
2619 | 8f091a59 | bellard | ot = s->dflag ? OT_QUAD : OT_WORD; |
2620 | 8f091a59 | bellard | opsize = 1 << ot;
|
2621 | 3b46e624 | ths | |
2622 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2623 | 8f091a59 | bellard | gen_op_addq_A0_im(-opsize); |
2624 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2625 | 8f091a59 | bellard | |
2626 | 8f091a59 | bellard | /* push bp */
|
2627 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
2628 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
2629 | 8f091a59 | bellard | if (level) {
|
2630 | b5b38f61 | bellard | /* XXX: must save state */
|
2631 | a7812ae4 | pbrook | gen_helper_enter64_level(tcg_const_i32(level), |
2632 | a7812ae4 | pbrook | tcg_const_i32((ot == OT_QUAD)), |
2633 | a7812ae4 | pbrook | cpu_T[1]);
|
2634 | 8f091a59 | bellard | } |
2635 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EBP); |
2636 | bbf662ee | bellard | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
2637 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
2638 | 5fafdf24 | ths | } else
|
2639 | 8f091a59 | bellard | #endif
|
2640 | 8f091a59 | bellard | { |
2641 | 8f091a59 | bellard | ot = s->dflag + OT_WORD; |
2642 | 8f091a59 | bellard | opsize = 2 << s->dflag;
|
2643 | 3b46e624 | ths | |
2644 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2645 | 8f091a59 | bellard | gen_op_addl_A0_im(-opsize); |
2646 | 8f091a59 | bellard | if (!s->ss32)
|
2647 | 8f091a59 | bellard | gen_op_andl_A0_ffff(); |
2648 | bbf662ee | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_A0);
|
2649 | 8f091a59 | bellard | if (s->addseg)
|
2650 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2651 | 8f091a59 | bellard | /* push bp */
|
2652 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
2653 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
2654 | 8f091a59 | bellard | if (level) {
|
2655 | b5b38f61 | bellard | /* XXX: must save state */
|
2656 | a7812ae4 | pbrook | gen_helper_enter_level(tcg_const_i32(level), |
2657 | a7812ae4 | pbrook | tcg_const_i32(s->dflag), |
2658 | a7812ae4 | pbrook | cpu_T[1]);
|
2659 | 8f091a59 | bellard | } |
2660 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EBP); |
2661 | bbf662ee | bellard | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
2662 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2663 | 2c0262af | bellard | } |
2664 | 2c0262af | bellard | } |
2665 | 2c0262af | bellard | |
2666 | 14ce26e7 | bellard | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2667 | 2c0262af | bellard | { |
2668 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2669 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2670 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2671 | a7812ae4 | pbrook | gen_helper_raise_exception(tcg_const_i32(trapno)); |
2672 | 2c0262af | bellard | s->is_jmp = 3;
|
2673 | 2c0262af | bellard | } |
2674 | 2c0262af | bellard | |
2675 | 2c0262af | bellard | /* an interrupt is different from an exception because of the
|
2676 | 7f75ffd3 | blueswir1 | privilege checks */
|
2677 | 5fafdf24 | ths | static void gen_interrupt(DisasContext *s, int intno, |
2678 | 14ce26e7 | bellard | target_ulong cur_eip, target_ulong next_eip) |
2679 | 2c0262af | bellard | { |
2680 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2681 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2682 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2683 | a7812ae4 | pbrook | gen_helper_raise_interrupt(tcg_const_i32(intno), |
2684 | a7812ae4 | pbrook | tcg_const_i32(next_eip - cur_eip)); |
2685 | 2c0262af | bellard | s->is_jmp = 3;
|
2686 | 2c0262af | bellard | } |
2687 | 2c0262af | bellard | |
2688 | 14ce26e7 | bellard | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2689 | 2c0262af | bellard | { |
2690 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2691 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2692 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2693 | a7812ae4 | pbrook | gen_helper_debug(); |
2694 | 2c0262af | bellard | s->is_jmp = 3;
|
2695 | 2c0262af | bellard | } |
2696 | 2c0262af | bellard | |
2697 | 2c0262af | bellard | /* generate a generic end of block. Trace exception is also generated
|
2698 | 2c0262af | bellard | if needed */
|
2699 | 2c0262af | bellard | static void gen_eob(DisasContext *s) |
2700 | 2c0262af | bellard | { |
2701 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2702 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2703 | a2cc3b24 | bellard | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
|
2704 | a7812ae4 | pbrook | gen_helper_reset_inhibit_irq(); |
2705 | a2cc3b24 | bellard | } |
2706 | a2397807 | Jan Kiszka | if (s->tb->flags & HF_RF_MASK) {
|
2707 | a2397807 | Jan Kiszka | gen_helper_reset_rf(); |
2708 | a2397807 | Jan Kiszka | } |
2709 | 34865134 | bellard | if (s->singlestep_enabled) {
|
2710 | a7812ae4 | pbrook | gen_helper_debug(); |
2711 | 34865134 | bellard | } else if (s->tf) { |
2712 | a7812ae4 | pbrook | gen_helper_single_step(); |
2713 | 2c0262af | bellard | } else {
|
2714 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2715 | 2c0262af | bellard | } |
2716 | 2c0262af | bellard | s->is_jmp = 3;
|
2717 | 2c0262af | bellard | } |
2718 | 2c0262af | bellard | |
2719 | 2c0262af | bellard | /* generate a jump to eip. No segment change must happen before as a
|
2720 | 2c0262af | bellard | direct call to the next block may occur */
|
2721 | 14ce26e7 | bellard | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2722 | 2c0262af | bellard | { |
2723 | 2c0262af | bellard | if (s->jmp_opt) {
|
2724 | 6e256c93 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
2725 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2726 | 6e256c93 | bellard | s->cc_op = CC_OP_DYNAMIC; |
2727 | 6e256c93 | bellard | } |
2728 | 6e256c93 | bellard | gen_goto_tb(s, tb_num, eip); |
2729 | 2c0262af | bellard | s->is_jmp = 3;
|
2730 | 2c0262af | bellard | } else {
|
2731 | 14ce26e7 | bellard | gen_jmp_im(eip); |
2732 | 2c0262af | bellard | gen_eob(s); |
2733 | 2c0262af | bellard | } |
2734 | 2c0262af | bellard | } |
2735 | 2c0262af | bellard | |
2736 | 14ce26e7 | bellard | static void gen_jmp(DisasContext *s, target_ulong eip) |
2737 | 14ce26e7 | bellard | { |
2738 | 14ce26e7 | bellard | gen_jmp_tb(s, eip, 0);
|
2739 | 14ce26e7 | bellard | } |
2740 | 14ce26e7 | bellard | |
2741 | 8686c490 | bellard | static inline void gen_ldq_env_A0(int idx, int offset) |
2742 | 8686c490 | bellard | { |
2743 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2744 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2745 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); |
2746 | 8686c490 | bellard | } |
2747 | 664e0f19 | bellard | |
2748 | 8686c490 | bellard | static inline void gen_stq_env_A0(int idx, int offset) |
2749 | 8686c490 | bellard | { |
2750 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2751 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2752 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); |
2753 | 8686c490 | bellard | } |
2754 | 664e0f19 | bellard | |
2755 | 8686c490 | bellard | static inline void gen_ldo_env_A0(int idx, int offset) |
2756 | 8686c490 | bellard | { |
2757 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2758 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2759 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
2760 | 8686c490 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
|
2761 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2762 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
2763 | 8686c490 | bellard | } |
2764 | 14ce26e7 | bellard | |
2765 | 8686c490 | bellard | static inline void gen_sto_env_A0(int idx, int offset) |
2766 | 8686c490 | bellard | { |
2767 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2768 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
2769 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); |
2770 | 8686c490 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
|
2771 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
2772 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2773 | 8686c490 | bellard | } |
2774 | 14ce26e7 | bellard | |
2775 | 5af45186 | bellard | static inline void gen_op_movo(int d_offset, int s_offset) |
2776 | 5af45186 | bellard | { |
2777 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2778 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2779 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
|
2780 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
|
2781 | 5af45186 | bellard | } |
2782 | 5af45186 | bellard | |
2783 | 5af45186 | bellard | static inline void gen_op_movq(int d_offset, int s_offset) |
2784 | 5af45186 | bellard | { |
2785 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2786 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2787 | 5af45186 | bellard | } |
2788 | 5af45186 | bellard | |
2789 | 5af45186 | bellard | static inline void gen_op_movl(int d_offset, int s_offset) |
2790 | 5af45186 | bellard | { |
2791 | b6abf97d | bellard | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2792 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); |
2793 | 5af45186 | bellard | } |
2794 | 5af45186 | bellard | |
2795 | 5af45186 | bellard | static inline void gen_op_movq_env_0(int d_offset) |
2796 | 5af45186 | bellard | { |
2797 | b6abf97d | bellard | tcg_gen_movi_i64(cpu_tmp1_i64, 0);
|
2798 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2799 | 5af45186 | bellard | } |
2800 | 664e0f19 | bellard | |
2801 | 5af45186 | bellard | #define SSE_SPECIAL ((void *)1) |
2802 | 5af45186 | bellard | #define SSE_DUMMY ((void *)2) |
2803 | 664e0f19 | bellard | |
2804 | a7812ae4 | pbrook | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2805 | a7812ae4 | pbrook | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ |
2806 | a7812ae4 | pbrook | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } |
2807 | 5af45186 | bellard | |
2808 | 5af45186 | bellard | static void *sse_op_table1[256][4] = { |
2809 | a35f3ec7 | aurel32 | /* 3DNow! extensions */
|
2810 | a35f3ec7 | aurel32 | [0x0e] = { SSE_DUMMY }, /* femms */ |
2811 | a35f3ec7 | aurel32 | [0x0f] = { SSE_DUMMY }, /* pf... */ |
2812 | 664e0f19 | bellard | /* pure SSE operations */
|
2813 | 664e0f19 | bellard | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ |
2814 | 664e0f19 | bellard | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ |
2815 | 465e9838 | bellard | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
2816 | 664e0f19 | bellard | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
2817 | a7812ae4 | pbrook | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
|
2818 | a7812ae4 | pbrook | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
|
2819 | 664e0f19 | bellard | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2820 | 664e0f19 | bellard | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ |
2821 | 664e0f19 | bellard | |
2822 | 664e0f19 | bellard | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ |
2823 | 664e0f19 | bellard | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ |
2824 | 664e0f19 | bellard | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ |
2825 | 664e0f19 | bellard | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */ |
2826 | 664e0f19 | bellard | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2827 | 664e0f19 | bellard | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ |
2828 | a7812ae4 | pbrook | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
|
2829 | a7812ae4 | pbrook | [0x2f] = { gen_helper_comiss, gen_helper_comisd },
|
2830 | 664e0f19 | bellard | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2831 | 664e0f19 | bellard | [0x51] = SSE_FOP(sqrt),
|
2832 | a7812ae4 | pbrook | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2833 | a7812ae4 | pbrook | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, |
2834 | a7812ae4 | pbrook | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ |
2835 | a7812ae4 | pbrook | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ |
2836 | a7812ae4 | pbrook | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ |
2837 | a7812ae4 | pbrook | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ |
2838 | 664e0f19 | bellard | [0x58] = SSE_FOP(add),
|
2839 | 664e0f19 | bellard | [0x59] = SSE_FOP(mul),
|
2840 | a7812ae4 | pbrook | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
|
2841 | a7812ae4 | pbrook | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, |
2842 | a7812ae4 | pbrook | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
|
2843 | 664e0f19 | bellard | [0x5c] = SSE_FOP(sub),
|
2844 | 664e0f19 | bellard | [0x5d] = SSE_FOP(min),
|
2845 | 664e0f19 | bellard | [0x5e] = SSE_FOP(div),
|
2846 | 664e0f19 | bellard | [0x5f] = SSE_FOP(max),
|
2847 | 664e0f19 | bellard | |
2848 | 664e0f19 | bellard | [0xc2] = SSE_FOP(cmpeq),
|
2849 | a7812ae4 | pbrook | [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
|
2850 | 664e0f19 | bellard | |
2851 | 222a3336 | balrog | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2852 | 222a3336 | balrog | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2853 | 4242b1bd | balrog | |
2854 | 664e0f19 | bellard | /* MMX ops and their SSE extensions */
|
2855 | 664e0f19 | bellard | [0x60] = MMX_OP2(punpcklbw),
|
2856 | 664e0f19 | bellard | [0x61] = MMX_OP2(punpcklwd),
|
2857 | 664e0f19 | bellard | [0x62] = MMX_OP2(punpckldq),
|
2858 | 664e0f19 | bellard | [0x63] = MMX_OP2(packsswb),
|
2859 | 664e0f19 | bellard | [0x64] = MMX_OP2(pcmpgtb),
|
2860 | 664e0f19 | bellard | [0x65] = MMX_OP2(pcmpgtw),
|
2861 | 664e0f19 | bellard | [0x66] = MMX_OP2(pcmpgtl),
|
2862 | 664e0f19 | bellard | [0x67] = MMX_OP2(packuswb),
|
2863 | 664e0f19 | bellard | [0x68] = MMX_OP2(punpckhbw),
|
2864 | 664e0f19 | bellard | [0x69] = MMX_OP2(punpckhwd),
|
2865 | 664e0f19 | bellard | [0x6a] = MMX_OP2(punpckhdq),
|
2866 | 664e0f19 | bellard | [0x6b] = MMX_OP2(packssdw),
|
2867 | a7812ae4 | pbrook | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2868 | a7812ae4 | pbrook | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, |
2869 | 664e0f19 | bellard | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2870 | 664e0f19 | bellard | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ |
2871 | a7812ae4 | pbrook | [0x70] = { gen_helper_pshufw_mmx,
|
2872 | a7812ae4 | pbrook | gen_helper_pshufd_xmm, |
2873 | a7812ae4 | pbrook | gen_helper_pshufhw_xmm, |
2874 | a7812ae4 | pbrook | gen_helper_pshuflw_xmm }, |
2875 | 664e0f19 | bellard | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2876 | 664e0f19 | bellard | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ |
2877 | 664e0f19 | bellard | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ |
2878 | 664e0f19 | bellard | [0x74] = MMX_OP2(pcmpeqb),
|
2879 | 664e0f19 | bellard | [0x75] = MMX_OP2(pcmpeqw),
|
2880 | 664e0f19 | bellard | [0x76] = MMX_OP2(pcmpeql),
|
2881 | a35f3ec7 | aurel32 | [0x77] = { SSE_DUMMY }, /* emms */ |
2882 | a7812ae4 | pbrook | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2883 | a7812ae4 | pbrook | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, |
2884 | 664e0f19 | bellard | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2885 | 664e0f19 | bellard | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ |
2886 | 664e0f19 | bellard | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ |
2887 | 664e0f19 | bellard | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ |
2888 | a7812ae4 | pbrook | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
2889 | 664e0f19 | bellard | [0xd1] = MMX_OP2(psrlw),
|
2890 | 664e0f19 | bellard | [0xd2] = MMX_OP2(psrld),
|
2891 | 664e0f19 | bellard | [0xd3] = MMX_OP2(psrlq),
|
2892 | 664e0f19 | bellard | [0xd4] = MMX_OP2(paddq),
|
2893 | 664e0f19 | bellard | [0xd5] = MMX_OP2(pmullw),
|
2894 | 664e0f19 | bellard | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, |
2895 | 664e0f19 | bellard | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ |
2896 | 664e0f19 | bellard | [0xd8] = MMX_OP2(psubusb),
|
2897 | 664e0f19 | bellard | [0xd9] = MMX_OP2(psubusw),
|
2898 | 664e0f19 | bellard | [0xda] = MMX_OP2(pminub),
|
2899 | 664e0f19 | bellard | [0xdb] = MMX_OP2(pand),
|
2900 | 664e0f19 | bellard | [0xdc] = MMX_OP2(paddusb),
|
2901 | 664e0f19 | bellard | [0xdd] = MMX_OP2(paddusw),
|
2902 | 664e0f19 | bellard | [0xde] = MMX_OP2(pmaxub),
|
2903 | 664e0f19 | bellard | [0xdf] = MMX_OP2(pandn),
|
2904 | 664e0f19 | bellard | [0xe0] = MMX_OP2(pavgb),
|
2905 | 664e0f19 | bellard | [0xe1] = MMX_OP2(psraw),
|
2906 | 664e0f19 | bellard | [0xe2] = MMX_OP2(psrad),
|
2907 | 664e0f19 | bellard | [0xe3] = MMX_OP2(pavgw),
|
2908 | 664e0f19 | bellard | [0xe4] = MMX_OP2(pmulhuw),
|
2909 | 664e0f19 | bellard | [0xe5] = MMX_OP2(pmulhw),
|
2910 | a7812ae4 | pbrook | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
2911 | 664e0f19 | bellard | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2912 | 664e0f19 | bellard | [0xe8] = MMX_OP2(psubsb),
|
2913 | 664e0f19 | bellard | [0xe9] = MMX_OP2(psubsw),
|
2914 | 664e0f19 | bellard | [0xea] = MMX_OP2(pminsw),
|
2915 | 664e0f19 | bellard | [0xeb] = MMX_OP2(por),
|
2916 | 664e0f19 | bellard | [0xec] = MMX_OP2(paddsb),
|
2917 | 664e0f19 | bellard | [0xed] = MMX_OP2(paddsw),
|
2918 | 664e0f19 | bellard | [0xee] = MMX_OP2(pmaxsw),
|
2919 | 664e0f19 | bellard | [0xef] = MMX_OP2(pxor),
|
2920 | 465e9838 | bellard | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
2921 | 664e0f19 | bellard | [0xf1] = MMX_OP2(psllw),
|
2922 | 664e0f19 | bellard | [0xf2] = MMX_OP2(pslld),
|
2923 | 664e0f19 | bellard | [0xf3] = MMX_OP2(psllq),
|
2924 | 664e0f19 | bellard | [0xf4] = MMX_OP2(pmuludq),
|
2925 | 664e0f19 | bellard | [0xf5] = MMX_OP2(pmaddwd),
|
2926 | 664e0f19 | bellard | [0xf6] = MMX_OP2(psadbw),
|
2927 | 664e0f19 | bellard | [0xf7] = MMX_OP2(maskmov),
|
2928 | 664e0f19 | bellard | [0xf8] = MMX_OP2(psubb),
|
2929 | 664e0f19 | bellard | [0xf9] = MMX_OP2(psubw),
|
2930 | 664e0f19 | bellard | [0xfa] = MMX_OP2(psubl),
|
2931 | 664e0f19 | bellard | [0xfb] = MMX_OP2(psubq),
|
2932 | 664e0f19 | bellard | [0xfc] = MMX_OP2(paddb),
|
2933 | 664e0f19 | bellard | [0xfd] = MMX_OP2(paddw),
|
2934 | 664e0f19 | bellard | [0xfe] = MMX_OP2(paddl),
|
2935 | 664e0f19 | bellard | }; |
2936 | 664e0f19 | bellard | |
2937 | 5af45186 | bellard | static void *sse_op_table2[3 * 8][2] = { |
2938 | 664e0f19 | bellard | [0 + 2] = MMX_OP2(psrlw), |
2939 | 664e0f19 | bellard | [0 + 4] = MMX_OP2(psraw), |
2940 | 664e0f19 | bellard | [0 + 6] = MMX_OP2(psllw), |
2941 | 664e0f19 | bellard | [8 + 2] = MMX_OP2(psrld), |
2942 | 664e0f19 | bellard | [8 + 4] = MMX_OP2(psrad), |
2943 | 664e0f19 | bellard | [8 + 6] = MMX_OP2(pslld), |
2944 | 664e0f19 | bellard | [16 + 2] = MMX_OP2(psrlq), |
2945 | a7812ae4 | pbrook | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
2946 | 664e0f19 | bellard | [16 + 6] = MMX_OP2(psllq), |
2947 | a7812ae4 | pbrook | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
2948 | 664e0f19 | bellard | }; |
2949 | 664e0f19 | bellard | |
2950 | 5af45186 | bellard | static void *sse_op_table3[4 * 3] = { |
2951 | a7812ae4 | pbrook | gen_helper_cvtsi2ss, |
2952 | a7812ae4 | pbrook | gen_helper_cvtsi2sd, |
2953 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvtsq2ss), |
2954 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvtsq2sd), |
2955 | a7812ae4 | pbrook | |
2956 | a7812ae4 | pbrook | gen_helper_cvttss2si, |
2957 | a7812ae4 | pbrook | gen_helper_cvttsd2si, |
2958 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvttss2sq), |
2959 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvttsd2sq), |
2960 | a7812ae4 | pbrook | |
2961 | a7812ae4 | pbrook | gen_helper_cvtss2si, |
2962 | a7812ae4 | pbrook | gen_helper_cvtsd2si, |
2963 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvtss2sq), |
2964 | a7812ae4 | pbrook | X86_64_ONLY(gen_helper_cvtsd2sq), |
2965 | 664e0f19 | bellard | }; |
2966 | 3b46e624 | ths | |
2967 | 5af45186 | bellard | static void *sse_op_table4[8][4] = { |
2968 | 664e0f19 | bellard | SSE_FOP(cmpeq), |
2969 | 664e0f19 | bellard | SSE_FOP(cmplt), |
2970 | 664e0f19 | bellard | SSE_FOP(cmple), |
2971 | 664e0f19 | bellard | SSE_FOP(cmpunord), |
2972 | 664e0f19 | bellard | SSE_FOP(cmpneq), |
2973 | 664e0f19 | bellard | SSE_FOP(cmpnlt), |
2974 | 664e0f19 | bellard | SSE_FOP(cmpnle), |
2975 | 664e0f19 | bellard | SSE_FOP(cmpord), |
2976 | 664e0f19 | bellard | }; |
2977 | 3b46e624 | ths | |
2978 | 5af45186 | bellard | static void *sse_op_table5[256] = { |
2979 | a7812ae4 | pbrook | [0x0c] = gen_helper_pi2fw,
|
2980 | a7812ae4 | pbrook | [0x0d] = gen_helper_pi2fd,
|
2981 | a7812ae4 | pbrook | [0x1c] = gen_helper_pf2iw,
|
2982 | a7812ae4 | pbrook | [0x1d] = gen_helper_pf2id,
|
2983 | a7812ae4 | pbrook | [0x8a] = gen_helper_pfnacc,
|
2984 | a7812ae4 | pbrook | [0x8e] = gen_helper_pfpnacc,
|
2985 | a7812ae4 | pbrook | [0x90] = gen_helper_pfcmpge,
|
2986 | a7812ae4 | pbrook | [0x94] = gen_helper_pfmin,
|
2987 | a7812ae4 | pbrook | [0x96] = gen_helper_pfrcp,
|
2988 | a7812ae4 | pbrook | [0x97] = gen_helper_pfrsqrt,
|
2989 | a7812ae4 | pbrook | [0x9a] = gen_helper_pfsub,
|
2990 | a7812ae4 | pbrook | [0x9e] = gen_helper_pfadd,
|
2991 | a7812ae4 | pbrook | [0xa0] = gen_helper_pfcmpgt,
|
2992 | a7812ae4 | pbrook | [0xa4] = gen_helper_pfmax,
|
2993 | a7812ae4 | pbrook | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ |
2994 | a7812ae4 | pbrook | [0xa7] = gen_helper_movq, /* pfrsqit1 */ |
2995 | a7812ae4 | pbrook | [0xaa] = gen_helper_pfsubr,
|
2996 | a7812ae4 | pbrook | [0xae] = gen_helper_pfacc,
|
2997 | a7812ae4 | pbrook | [0xb0] = gen_helper_pfcmpeq,
|
2998 | a7812ae4 | pbrook | [0xb4] = gen_helper_pfmul,
|
2999 | a7812ae4 | pbrook | [0xb6] = gen_helper_movq, /* pfrcpit2 */ |
3000 | a7812ae4 | pbrook | [0xb7] = gen_helper_pmulhrw_mmx,
|
3001 | a7812ae4 | pbrook | [0xbb] = gen_helper_pswapd,
|
3002 | a7812ae4 | pbrook | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ |
3003 | a35f3ec7 | aurel32 | }; |
3004 | a35f3ec7 | aurel32 | |
3005 | 222a3336 | balrog | struct sse_op_helper_s {
|
3006 | 222a3336 | balrog | void *op[2]; uint32_t ext_mask; |
3007 | 222a3336 | balrog | }; |
3008 | 222a3336 | balrog | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
|
3009 | a7812ae4 | pbrook | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3010 | a7812ae4 | pbrook | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } |
3011 | 222a3336 | balrog | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
3012 | 222a3336 | balrog | static struct sse_op_helper_s sse_op_table6[256] = { |
3013 | 222a3336 | balrog | [0x00] = SSSE3_OP(pshufb),
|
3014 | 222a3336 | balrog | [0x01] = SSSE3_OP(phaddw),
|
3015 | 222a3336 | balrog | [0x02] = SSSE3_OP(phaddd),
|
3016 | 222a3336 | balrog | [0x03] = SSSE3_OP(phaddsw),
|
3017 | 222a3336 | balrog | [0x04] = SSSE3_OP(pmaddubsw),
|
3018 | 222a3336 | balrog | [0x05] = SSSE3_OP(phsubw),
|
3019 | 222a3336 | balrog | [0x06] = SSSE3_OP(phsubd),
|
3020 | 222a3336 | balrog | [0x07] = SSSE3_OP(phsubsw),
|
3021 | 222a3336 | balrog | [0x08] = SSSE3_OP(psignb),
|
3022 | 222a3336 | balrog | [0x09] = SSSE3_OP(psignw),
|
3023 | 222a3336 | balrog | [0x0a] = SSSE3_OP(psignd),
|
3024 | 222a3336 | balrog | [0x0b] = SSSE3_OP(pmulhrsw),
|
3025 | 222a3336 | balrog | [0x10] = SSE41_OP(pblendvb),
|
3026 | 222a3336 | balrog | [0x14] = SSE41_OP(blendvps),
|
3027 | 222a3336 | balrog | [0x15] = SSE41_OP(blendvpd),
|
3028 | 222a3336 | balrog | [0x17] = SSE41_OP(ptest),
|
3029 | 222a3336 | balrog | [0x1c] = SSSE3_OP(pabsb),
|
3030 | 222a3336 | balrog | [0x1d] = SSSE3_OP(pabsw),
|
3031 | 222a3336 | balrog | [0x1e] = SSSE3_OP(pabsd),
|
3032 | 222a3336 | balrog | [0x20] = SSE41_OP(pmovsxbw),
|
3033 | 222a3336 | balrog | [0x21] = SSE41_OP(pmovsxbd),
|
3034 | 222a3336 | balrog | [0x22] = SSE41_OP(pmovsxbq),
|
3035 | 222a3336 | balrog | [0x23] = SSE41_OP(pmovsxwd),
|
3036 | 222a3336 | balrog | [0x24] = SSE41_OP(pmovsxwq),
|
3037 | 222a3336 | balrog | [0x25] = SSE41_OP(pmovsxdq),
|
3038 | 222a3336 | balrog | [0x28] = SSE41_OP(pmuldq),
|
3039 | 222a3336 | balrog | [0x29] = SSE41_OP(pcmpeqq),
|
3040 | 222a3336 | balrog | [0x2a] = SSE41_SPECIAL, /* movntqda */ |
3041 | 222a3336 | balrog | [0x2b] = SSE41_OP(packusdw),
|
3042 | 222a3336 | balrog | [0x30] = SSE41_OP(pmovzxbw),
|
3043 | 222a3336 | balrog | [0x31] = SSE41_OP(pmovzxbd),
|
3044 | 222a3336 | balrog | [0x32] = SSE41_OP(pmovzxbq),
|
3045 | 222a3336 | balrog | [0x33] = SSE41_OP(pmovzxwd),
|
3046 | 222a3336 | balrog | [0x34] = SSE41_OP(pmovzxwq),
|
3047 | 222a3336 | balrog | [0x35] = SSE41_OP(pmovzxdq),
|
3048 | 222a3336 | balrog | [0x37] = SSE42_OP(pcmpgtq),
|
3049 | 222a3336 | balrog | [0x38] = SSE41_OP(pminsb),
|
3050 | 222a3336 | balrog | [0x39] = SSE41_OP(pminsd),
|
3051 | 222a3336 | balrog | [0x3a] = SSE41_OP(pminuw),
|
3052 | 222a3336 | balrog | [0x3b] = SSE41_OP(pminud),
|
3053 | 222a3336 | balrog | [0x3c] = SSE41_OP(pmaxsb),
|
3054 | 222a3336 | balrog | [0x3d] = SSE41_OP(pmaxsd),
|
3055 | 222a3336 | balrog | [0x3e] = SSE41_OP(pmaxuw),
|
3056 | 222a3336 | balrog | [0x3f] = SSE41_OP(pmaxud),
|
3057 | 222a3336 | balrog | [0x40] = SSE41_OP(pmulld),
|
3058 | 222a3336 | balrog | [0x41] = SSE41_OP(phminposuw),
|
3059 | 4242b1bd | balrog | }; |
3060 | 4242b1bd | balrog | |
3061 | 222a3336 | balrog | static struct sse_op_helper_s sse_op_table7[256] = { |
3062 | 222a3336 | balrog | [0x08] = SSE41_OP(roundps),
|
3063 | 222a3336 | balrog | [0x09] = SSE41_OP(roundpd),
|
3064 | 222a3336 | balrog | [0x0a] = SSE41_OP(roundss),
|
3065 | 222a3336 | balrog | [0x0b] = SSE41_OP(roundsd),
|
3066 | 222a3336 | balrog | [0x0c] = SSE41_OP(blendps),
|
3067 | 222a3336 | balrog | [0x0d] = SSE41_OP(blendpd),
|
3068 | 222a3336 | balrog | [0x0e] = SSE41_OP(pblendw),
|
3069 | 222a3336 | balrog | [0x0f] = SSSE3_OP(palignr),
|
3070 | 222a3336 | balrog | [0x14] = SSE41_SPECIAL, /* pextrb */ |
3071 | 222a3336 | balrog | [0x15] = SSE41_SPECIAL, /* pextrw */ |
3072 | 222a3336 | balrog | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ |
3073 | 222a3336 | balrog | [0x17] = SSE41_SPECIAL, /* extractps */ |
3074 | 222a3336 | balrog | [0x20] = SSE41_SPECIAL, /* pinsrb */ |
3075 | 222a3336 | balrog | [0x21] = SSE41_SPECIAL, /* insertps */ |
3076 | 222a3336 | balrog | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ |
3077 | 222a3336 | balrog | [0x40] = SSE41_OP(dpps),
|
3078 | 222a3336 | balrog | [0x41] = SSE41_OP(dppd),
|
3079 | 222a3336 | balrog | [0x42] = SSE41_OP(mpsadbw),
|
3080 | 222a3336 | balrog | [0x60] = SSE42_OP(pcmpestrm),
|
3081 | 222a3336 | balrog | [0x61] = SSE42_OP(pcmpestri),
|
3082 | 222a3336 | balrog | [0x62] = SSE42_OP(pcmpistrm),
|
3083 | 222a3336 | balrog | [0x63] = SSE42_OP(pcmpistri),
|
3084 | 4242b1bd | balrog | }; |
3085 | 4242b1bd | balrog | |
3086 | 664e0f19 | bellard | static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) |
3087 | 664e0f19 | bellard | { |
3088 | 664e0f19 | bellard | int b1, op1_offset, op2_offset, is_xmm, val, ot;
|
3089 | 664e0f19 | bellard | int modrm, mod, rm, reg, reg_addr, offset_addr;
|
3090 | 5af45186 | bellard | void *sse_op2;
|
3091 | 664e0f19 | bellard | |
3092 | 664e0f19 | bellard | b &= 0xff;
|
3093 | 5fafdf24 | ths | if (s->prefix & PREFIX_DATA)
|
3094 | 664e0f19 | bellard | b1 = 1;
|
3095 | 5fafdf24 | ths | else if (s->prefix & PREFIX_REPZ) |
3096 | 664e0f19 | bellard | b1 = 2;
|
3097 | 5fafdf24 | ths | else if (s->prefix & PREFIX_REPNZ) |
3098 | 664e0f19 | bellard | b1 = 3;
|
3099 | 664e0f19 | bellard | else
|
3100 | 664e0f19 | bellard | b1 = 0;
|
3101 | 664e0f19 | bellard | sse_op2 = sse_op_table1[b][b1]; |
3102 | 5fafdf24 | ths | if (!sse_op2)
|
3103 | 664e0f19 | bellard | goto illegal_op;
|
3104 | a35f3ec7 | aurel32 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
3105 | 664e0f19 | bellard | is_xmm = 1;
|
3106 | 664e0f19 | bellard | } else {
|
3107 | 664e0f19 | bellard | if (b1 == 0) { |
3108 | 664e0f19 | bellard | /* MMX case */
|
3109 | 664e0f19 | bellard | is_xmm = 0;
|
3110 | 664e0f19 | bellard | } else {
|
3111 | 664e0f19 | bellard | is_xmm = 1;
|
3112 | 664e0f19 | bellard | } |
3113 | 664e0f19 | bellard | } |
3114 | 664e0f19 | bellard | /* simple MMX/SSE operation */
|
3115 | 664e0f19 | bellard | if (s->flags & HF_TS_MASK) {
|
3116 | 664e0f19 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
3117 | 664e0f19 | bellard | return;
|
3118 | 664e0f19 | bellard | } |
3119 | 664e0f19 | bellard | if (s->flags & HF_EM_MASK) {
|
3120 | 664e0f19 | bellard | illegal_op:
|
3121 | 664e0f19 | bellard | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); |
3122 | 664e0f19 | bellard | return;
|
3123 | 664e0f19 | bellard | } |
3124 | 664e0f19 | bellard | if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
|
3125 | 4242b1bd | balrog | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3126 | 4242b1bd | balrog | goto illegal_op;
|
3127 | e771edab | aurel32 | if (b == 0x0e) { |
3128 | e771edab | aurel32 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
|
3129 | e771edab | aurel32 | goto illegal_op;
|
3130 | e771edab | aurel32 | /* femms */
|
3131 | a7812ae4 | pbrook | gen_helper_emms(); |
3132 | e771edab | aurel32 | return;
|
3133 | e771edab | aurel32 | } |
3134 | e771edab | aurel32 | if (b == 0x77) { |
3135 | e771edab | aurel32 | /* emms */
|
3136 | a7812ae4 | pbrook | gen_helper_emms(); |
3137 | 664e0f19 | bellard | return;
|
3138 | 664e0f19 | bellard | } |
3139 | 664e0f19 | bellard | /* prepare MMX state (XXX: optimize by storing fptt and fptags in
|
3140 | 664e0f19 | bellard | the static cpu state) */
|
3141 | 664e0f19 | bellard | if (!is_xmm) {
|
3142 | a7812ae4 | pbrook | gen_helper_enter_mmx(); |
3143 | 664e0f19 | bellard | } |
3144 | 664e0f19 | bellard | |
3145 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
3146 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7); |
3147 | 664e0f19 | bellard | if (is_xmm)
|
3148 | 664e0f19 | bellard | reg |= rex_r; |
3149 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
3150 | 664e0f19 | bellard | if (sse_op2 == SSE_SPECIAL) {
|
3151 | 664e0f19 | bellard | b |= (b1 << 8);
|
3152 | 664e0f19 | bellard | switch(b) {
|
3153 | 664e0f19 | bellard | case 0x0e7: /* movntq */ |
3154 | 5fafdf24 | ths | if (mod == 3) |
3155 | 664e0f19 | bellard | goto illegal_op;
|
3156 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3157 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
3158 | 664e0f19 | bellard | break;
|
3159 | 664e0f19 | bellard | case 0x1e7: /* movntdq */ |
3160 | 664e0f19 | bellard | case 0x02b: /* movntps */ |
3161 | 664e0f19 | bellard | case 0x12b: /* movntps */ |
3162 | 465e9838 | bellard | case 0x3f0: /* lddqu */ |
3163 | 465e9838 | bellard | if (mod == 3) |
3164 | 664e0f19 | bellard | goto illegal_op;
|
3165 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3166 | 8686c490 | bellard | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3167 | 664e0f19 | bellard | break;
|
3168 | 664e0f19 | bellard | case 0x6e: /* movd mm, ea */ |
3169 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3170 | dabd98dd | bellard | if (s->dflag == 2) { |
3171 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
|
3172 | 5af45186 | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
|
3173 | 5fafdf24 | ths | } else
|
3174 | dabd98dd | bellard | #endif
|
3175 | dabd98dd | bellard | { |
3176 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
|
3177 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3178 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3179 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3180 | a7812ae4 | pbrook | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); |
3181 | dabd98dd | bellard | } |
3182 | 664e0f19 | bellard | break;
|
3183 | 664e0f19 | bellard | case 0x16e: /* movd xmm, ea */ |
3184 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3185 | dabd98dd | bellard | if (s->dflag == 2) { |
3186 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
|
3187 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3188 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3189 | a7812ae4 | pbrook | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
|
3190 | 5fafdf24 | ths | } else
|
3191 | dabd98dd | bellard | #endif
|
3192 | dabd98dd | bellard | { |
3193 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
|
3194 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3195 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3196 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3197 | a7812ae4 | pbrook | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
3198 | dabd98dd | bellard | } |
3199 | 664e0f19 | bellard | break;
|
3200 | 664e0f19 | bellard | case 0x6f: /* movq mm, ea */ |
3201 | 664e0f19 | bellard | if (mod != 3) { |
3202 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3203 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
3204 | 664e0f19 | bellard | } else {
|
3205 | 664e0f19 | bellard | rm = (modrm & 7);
|
3206 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3207 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[rm].mmx)); |
3208 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
3209 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3210 | 664e0f19 | bellard | } |
3211 | 664e0f19 | bellard | break;
|
3212 | 664e0f19 | bellard | case 0x010: /* movups */ |
3213 | 664e0f19 | bellard | case 0x110: /* movupd */ |
3214 | 664e0f19 | bellard | case 0x028: /* movaps */ |
3215 | 664e0f19 | bellard | case 0x128: /* movapd */ |
3216 | 664e0f19 | bellard | case 0x16f: /* movdqa xmm, ea */ |
3217 | 664e0f19 | bellard | case 0x26f: /* movdqu xmm, ea */ |
3218 | 664e0f19 | bellard | if (mod != 3) { |
3219 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3220 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3221 | 664e0f19 | bellard | } else {
|
3222 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3223 | 664e0f19 | bellard | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), |
3224 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3225 | 664e0f19 | bellard | } |
3226 | 664e0f19 | bellard | break;
|
3227 | 664e0f19 | bellard | case 0x210: /* movss xmm, ea */ |
3228 | 664e0f19 | bellard | if (mod != 3) { |
3229 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3230 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3231 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
3232 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3233 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3234 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3235 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); |
3236 | 664e0f19 | bellard | } else {
|
3237 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3238 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3239 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
3240 | 664e0f19 | bellard | } |
3241 | 664e0f19 | bellard | break;
|
3242 | 664e0f19 | bellard | case 0x310: /* movsd xmm, ea */ |
3243 | 664e0f19 | bellard | if (mod != 3) { |
3244 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3245 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3246 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3247 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3248 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); |
3249 | 664e0f19 | bellard | } else {
|
3250 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3251 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3252 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3253 | 664e0f19 | bellard | } |
3254 | 664e0f19 | bellard | break;
|
3255 | 664e0f19 | bellard | case 0x012: /* movlps */ |
3256 | 664e0f19 | bellard | case 0x112: /* movlpd */ |
3257 | 664e0f19 | bellard | if (mod != 3) { |
3258 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3259 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3260 | 664e0f19 | bellard | } else {
|
3261 | 664e0f19 | bellard | /* movhlps */
|
3262 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3263 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3264 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
3265 | 664e0f19 | bellard | } |
3266 | 664e0f19 | bellard | break;
|
3267 | 465e9838 | bellard | case 0x212: /* movsldup */ |
3268 | 465e9838 | bellard | if (mod != 3) { |
3269 | 465e9838 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3270 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3271 | 465e9838 | bellard | } else {
|
3272 | 465e9838 | bellard | rm = (modrm & 7) | REX_B(s);
|
3273 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3274 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
3275 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
3276 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
|
3277 | 465e9838 | bellard | } |
3278 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
3279 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3280 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
3281 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
3282 | 465e9838 | bellard | break;
|
3283 | 465e9838 | bellard | case 0x312: /* movddup */ |
3284 | 465e9838 | bellard | if (mod != 3) { |
3285 | 465e9838 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3286 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3287 | 465e9838 | bellard | } else {
|
3288 | 465e9838 | bellard | rm = (modrm & 7) | REX_B(s);
|
3289 | 465e9838 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3290 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3291 | 465e9838 | bellard | } |
3292 | 465e9838 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
3293 | ba6526df | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3294 | 465e9838 | bellard | break;
|
3295 | 664e0f19 | bellard | case 0x016: /* movhps */ |
3296 | 664e0f19 | bellard | case 0x116: /* movhpd */ |
3297 | 664e0f19 | bellard | if (mod != 3) { |
3298 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3299 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3300 | 664e0f19 | bellard | } else {
|
3301 | 664e0f19 | bellard | /* movlhps */
|
3302 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3303 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
3304 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3305 | 664e0f19 | bellard | } |
3306 | 664e0f19 | bellard | break;
|
3307 | 664e0f19 | bellard | case 0x216: /* movshdup */ |
3308 | 664e0f19 | bellard | if (mod != 3) { |
3309 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3310 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3311 | 664e0f19 | bellard | } else {
|
3312 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3313 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
3314 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
|
3315 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
3316 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
|
3317 | 664e0f19 | bellard | } |
3318 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3319 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
|
3320 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
3321 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
3322 | 664e0f19 | bellard | break;
|
3323 | 664e0f19 | bellard | case 0x7e: /* movd ea, mm */ |
3324 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3325 | dabd98dd | bellard | if (s->dflag == 2) { |
3326 | 5af45186 | bellard | tcg_gen_ld_i64(cpu_T[0], cpu_env,
|
3327 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3328 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
|
3329 | 5fafdf24 | ths | } else
|
3330 | dabd98dd | bellard | #endif
|
3331 | dabd98dd | bellard | { |
3332 | 5af45186 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
|
3333 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
|
3334 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
|
3335 | dabd98dd | bellard | } |
3336 | 664e0f19 | bellard | break;
|
3337 | 664e0f19 | bellard | case 0x17e: /* movd ea, xmm */ |
3338 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3339 | dabd98dd | bellard | if (s->dflag == 2) { |
3340 | 5af45186 | bellard | tcg_gen_ld_i64(cpu_T[0], cpu_env,
|
3341 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3342 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
|
3343 | 5fafdf24 | ths | } else
|
3344 | dabd98dd | bellard | #endif
|
3345 | dabd98dd | bellard | { |
3346 | 5af45186 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
|
3347 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3348 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
|
3349 | dabd98dd | bellard | } |
3350 | 664e0f19 | bellard | break;
|
3351 | 664e0f19 | bellard | case 0x27e: /* movq xmm, ea */ |
3352 | 664e0f19 | bellard | if (mod != 3) { |
3353 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3354 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3355 | 664e0f19 | bellard | } else {
|
3356 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3357 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3358 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3359 | 664e0f19 | bellard | } |
3360 | 664e0f19 | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3361 | 664e0f19 | bellard | break;
|
3362 | 664e0f19 | bellard | case 0x7f: /* movq ea, mm */ |
3363 | 664e0f19 | bellard | if (mod != 3) { |
3364 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3365 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
3366 | 664e0f19 | bellard | } else {
|
3367 | 664e0f19 | bellard | rm = (modrm & 7);
|
3368 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), |
3369 | 664e0f19 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3370 | 664e0f19 | bellard | } |
3371 | 664e0f19 | bellard | break;
|
3372 | 664e0f19 | bellard | case 0x011: /* movups */ |
3373 | 664e0f19 | bellard | case 0x111: /* movupd */ |
3374 | 664e0f19 | bellard | case 0x029: /* movaps */ |
3375 | 664e0f19 | bellard | case 0x129: /* movapd */ |
3376 | 664e0f19 | bellard | case 0x17f: /* movdqa ea, xmm */ |
3377 | 664e0f19 | bellard | case 0x27f: /* movdqu ea, xmm */ |
3378 | 664e0f19 | bellard | if (mod != 3) { |
3379 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3380 | 8686c490 | bellard | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3381 | 664e0f19 | bellard | } else {
|
3382 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3383 | 664e0f19 | bellard | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), |
3384 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3385 | 664e0f19 | bellard | } |
3386 | 664e0f19 | bellard | break;
|
3387 | 664e0f19 | bellard | case 0x211: /* movss ea, xmm */ |
3388 | 664e0f19 | bellard | if (mod != 3) { |
3389 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3390 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
3391 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
3392 | 664e0f19 | bellard | } else {
|
3393 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3394 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
|
3395 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3396 | 664e0f19 | bellard | } |
3397 | 664e0f19 | bellard | break;
|
3398 | 664e0f19 | bellard | case 0x311: /* movsd ea, xmm */ |
3399 | 664e0f19 | bellard | if (mod != 3) { |
3400 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3401 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3402 | 664e0f19 | bellard | } else {
|
3403 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3404 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
3405 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3406 | 664e0f19 | bellard | } |
3407 | 664e0f19 | bellard | break;
|
3408 | 664e0f19 | bellard | case 0x013: /* movlps */ |
3409 | 664e0f19 | bellard | case 0x113: /* movlpd */ |
3410 | 664e0f19 | bellard | if (mod != 3) { |
3411 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3412 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3413 | 664e0f19 | bellard | } else {
|
3414 | 664e0f19 | bellard | goto illegal_op;
|
3415 | 664e0f19 | bellard | } |
3416 | 664e0f19 | bellard | break;
|
3417 | 664e0f19 | bellard | case 0x017: /* movhps */ |
3418 | 664e0f19 | bellard | case 0x117: /* movhpd */ |
3419 | 664e0f19 | bellard | if (mod != 3) { |
3420 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3421 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3422 | 664e0f19 | bellard | } else {
|
3423 | 664e0f19 | bellard | goto illegal_op;
|
3424 | 664e0f19 | bellard | } |
3425 | 664e0f19 | bellard | break;
|
3426 | 664e0f19 | bellard | case 0x71: /* shift mm, im */ |
3427 | 664e0f19 | bellard | case 0x72: |
3428 | 664e0f19 | bellard | case 0x73: |
3429 | 664e0f19 | bellard | case 0x171: /* shift xmm, im */ |
3430 | 664e0f19 | bellard | case 0x172: |
3431 | 664e0f19 | bellard | case 0x173: |
3432 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3433 | 664e0f19 | bellard | if (is_xmm) {
|
3434 | 664e0f19 | bellard | gen_op_movl_T0_im(val); |
3435 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
3436 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3437 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
3438 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_t0); |
3439 | 664e0f19 | bellard | } else {
|
3440 | 664e0f19 | bellard | gen_op_movl_T0_im(val); |
3441 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
3442 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3443 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
3444 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,mmx_t0); |
3445 | 664e0f19 | bellard | } |
3446 | 664e0f19 | bellard | sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; |
3447 | 664e0f19 | bellard | if (!sse_op2)
|
3448 | 664e0f19 | bellard | goto illegal_op;
|
3449 | 664e0f19 | bellard | if (is_xmm) {
|
3450 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3451 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3452 | 664e0f19 | bellard | } else {
|
3453 | 664e0f19 | bellard | rm = (modrm & 7);
|
3454 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3455 | 664e0f19 | bellard | } |
3456 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3457 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); |
3458 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
|
3459 | 664e0f19 | bellard | break;
|
3460 | 664e0f19 | bellard | case 0x050: /* movmskps */ |
3461 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3462 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3463 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3464 | a7812ae4 | pbrook | gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0); |
3465 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3466 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3467 | 664e0f19 | bellard | break;
|
3468 | 664e0f19 | bellard | case 0x150: /* movmskpd */ |
3469 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3470 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3471 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3472 | a7812ae4 | pbrook | gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0); |
3473 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3474 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3475 | 664e0f19 | bellard | break;
|
3476 | 664e0f19 | bellard | case 0x02a: /* cvtpi2ps */ |
3477 | 664e0f19 | bellard | case 0x12a: /* cvtpi2pd */ |
3478 | a7812ae4 | pbrook | gen_helper_enter_mmx(); |
3479 | 664e0f19 | bellard | if (mod != 3) { |
3480 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3481 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,mmx_t0); |
3482 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, op2_offset); |
3483 | 664e0f19 | bellard | } else {
|
3484 | 664e0f19 | bellard | rm = (modrm & 7);
|
3485 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3486 | 664e0f19 | bellard | } |
3487 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3488 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3489 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3490 | 664e0f19 | bellard | switch(b >> 8) { |
3491 | 664e0f19 | bellard | case 0x0: |
3492 | a7812ae4 | pbrook | gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1); |
3493 | 664e0f19 | bellard | break;
|
3494 | 664e0f19 | bellard | default:
|
3495 | 664e0f19 | bellard | case 0x1: |
3496 | a7812ae4 | pbrook | gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1); |
3497 | 664e0f19 | bellard | break;
|
3498 | 664e0f19 | bellard | } |
3499 | 664e0f19 | bellard | break;
|
3500 | 664e0f19 | bellard | case 0x22a: /* cvtsi2ss */ |
3501 | 664e0f19 | bellard | case 0x32a: /* cvtsi2sd */ |
3502 | 664e0f19 | bellard | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3503 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
3504 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3505 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3506 | 5af45186 | bellard | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; |
3507 | 28e10711 | bellard | if (ot == OT_LONG) {
|
3508 | 28e10711 | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3509 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
|
3510 | 28e10711 | bellard | } else {
|
3511 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]); |
3512 | 28e10711 | bellard | } |
3513 | 664e0f19 | bellard | break;
|
3514 | 664e0f19 | bellard | case 0x02c: /* cvttps2pi */ |
3515 | 664e0f19 | bellard | case 0x12c: /* cvttpd2pi */ |
3516 | 664e0f19 | bellard | case 0x02d: /* cvtps2pi */ |
3517 | 664e0f19 | bellard | case 0x12d: /* cvtpd2pi */ |
3518 | a7812ae4 | pbrook | gen_helper_enter_mmx(); |
3519 | 664e0f19 | bellard | if (mod != 3) { |
3520 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3521 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3522 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, op2_offset); |
3523 | 664e0f19 | bellard | } else {
|
3524 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3525 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3526 | 664e0f19 | bellard | } |
3527 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
|
3528 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3529 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3530 | 664e0f19 | bellard | switch(b) {
|
3531 | 664e0f19 | bellard | case 0x02c: |
3532 | a7812ae4 | pbrook | gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1); |
3533 | 664e0f19 | bellard | break;
|
3534 | 664e0f19 | bellard | case 0x12c: |
3535 | a7812ae4 | pbrook | gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1); |
3536 | 664e0f19 | bellard | break;
|
3537 | 664e0f19 | bellard | case 0x02d: |
3538 | a7812ae4 | pbrook | gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1); |
3539 | 664e0f19 | bellard | break;
|
3540 | 664e0f19 | bellard | case 0x12d: |
3541 | a7812ae4 | pbrook | gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1); |
3542 | 664e0f19 | bellard | break;
|
3543 | 664e0f19 | bellard | } |
3544 | 664e0f19 | bellard | break;
|
3545 | 664e0f19 | bellard | case 0x22c: /* cvttss2si */ |
3546 | 664e0f19 | bellard | case 0x32c: /* cvttsd2si */ |
3547 | 664e0f19 | bellard | case 0x22d: /* cvtss2si */ |
3548 | 664e0f19 | bellard | case 0x32d: /* cvtsd2si */ |
3549 | 664e0f19 | bellard | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3550 | 31313213 | bellard | if (mod != 3) { |
3551 | 31313213 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3552 | 31313213 | bellard | if ((b >> 8) & 1) { |
3553 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
|
3554 | 31313213 | bellard | } else {
|
3555 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3556 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
3557 | 31313213 | bellard | } |
3558 | 31313213 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3559 | 31313213 | bellard | } else {
|
3560 | 31313213 | bellard | rm = (modrm & 7) | REX_B(s);
|
3561 | 31313213 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3562 | 31313213 | bellard | } |
3563 | 5af45186 | bellard | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + |
3564 | 5af45186 | bellard | (b & 1) * 4]; |
3565 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3566 | 5af45186 | bellard | if (ot == OT_LONG) {
|
3567 | a7812ae4 | pbrook | ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
|
3568 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3569 | 5af45186 | bellard | } else {
|
3570 | a7812ae4 | pbrook | ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0); |
3571 | 5af45186 | bellard | } |
3572 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
3573 | 664e0f19 | bellard | break;
|
3574 | 664e0f19 | bellard | case 0xc4: /* pinsrw */ |
3575 | 5fafdf24 | ths | case 0x1c4: |
3576 | d1e42c5c | bellard | s->rip_offset = 1;
|
3577 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
3578 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3579 | 664e0f19 | bellard | if (b1) {
|
3580 | 664e0f19 | bellard | val &= 7;
|
3581 | 5af45186 | bellard | tcg_gen_st16_tl(cpu_T[0], cpu_env,
|
3582 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); |
3583 | 664e0f19 | bellard | } else {
|
3584 | 664e0f19 | bellard | val &= 3;
|
3585 | 5af45186 | bellard | tcg_gen_st16_tl(cpu_T[0], cpu_env,
|
3586 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); |
3587 | 664e0f19 | bellard | } |
3588 | 664e0f19 | bellard | break;
|
3589 | 664e0f19 | bellard | case 0xc5: /* pextrw */ |
3590 | 5fafdf24 | ths | case 0x1c5: |
3591 | 664e0f19 | bellard | if (mod != 3) |
3592 | 664e0f19 | bellard | goto illegal_op;
|
3593 | 6dc2d0da | balrog | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3594 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3595 | 664e0f19 | bellard | if (b1) {
|
3596 | 664e0f19 | bellard | val &= 7;
|
3597 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3598 | 5af45186 | bellard | tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
|
3599 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); |
3600 | 664e0f19 | bellard | } else {
|
3601 | 664e0f19 | bellard | val &= 3;
|
3602 | 664e0f19 | bellard | rm = (modrm & 7);
|
3603 | 5af45186 | bellard | tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
|
3604 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); |
3605 | 664e0f19 | bellard | } |
3606 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3607 | 6dc2d0da | balrog | gen_op_mov_reg_T0(ot, reg); |
3608 | 664e0f19 | bellard | break;
|
3609 | 664e0f19 | bellard | case 0x1d6: /* movq ea, xmm */ |
3610 | 664e0f19 | bellard | if (mod != 3) { |
3611 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3612 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3613 | 664e0f19 | bellard | } else {
|
3614 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3615 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
3616 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3617 | 664e0f19 | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
3618 | 664e0f19 | bellard | } |
3619 | 664e0f19 | bellard | break;
|
3620 | 664e0f19 | bellard | case 0x2d6: /* movq2dq */ |
3621 | a7812ae4 | pbrook | gen_helper_enter_mmx(); |
3622 | 480c1cdb | bellard | rm = (modrm & 7);
|
3623 | 480c1cdb | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3624 | 480c1cdb | bellard | offsetof(CPUX86State,fpregs[rm].mmx)); |
3625 | 480c1cdb | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3626 | 664e0f19 | bellard | break;
|
3627 | 664e0f19 | bellard | case 0x3d6: /* movdq2q */ |
3628 | a7812ae4 | pbrook | gen_helper_enter_mmx(); |
3629 | 480c1cdb | bellard | rm = (modrm & 7) | REX_B(s);
|
3630 | 480c1cdb | bellard | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
|
3631 | 480c1cdb | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3632 | 664e0f19 | bellard | break;
|
3633 | 664e0f19 | bellard | case 0xd7: /* pmovmskb */ |
3634 | 664e0f19 | bellard | case 0x1d7: |
3635 | 664e0f19 | bellard | if (mod != 3) |
3636 | 664e0f19 | bellard | goto illegal_op;
|
3637 | 664e0f19 | bellard | if (b1) {
|
3638 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3639 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
3640 | a7812ae4 | pbrook | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0); |
3641 | 664e0f19 | bellard | } else {
|
3642 | 664e0f19 | bellard | rm = (modrm & 7);
|
3643 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
3644 | a7812ae4 | pbrook | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0); |
3645 | 664e0f19 | bellard | } |
3646 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3647 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3648 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3649 | 664e0f19 | bellard | break;
|
3650 | 4242b1bd | balrog | case 0x138: |
3651 | 000cacf6 | balrog | if (s->prefix & PREFIX_REPNZ)
|
3652 | 000cacf6 | balrog | goto crc32;
|
3653 | 000cacf6 | balrog | case 0x038: |
3654 | 4242b1bd | balrog | b = modrm; |
3655 | 4242b1bd | balrog | modrm = ldub_code(s->pc++); |
3656 | 4242b1bd | balrog | rm = modrm & 7;
|
3657 | 4242b1bd | balrog | reg = ((modrm >> 3) & 7) | rex_r; |
3658 | 4242b1bd | balrog | mod = (modrm >> 6) & 3; |
3659 | 4242b1bd | balrog | |
3660 | 222a3336 | balrog | sse_op2 = sse_op_table6[b].op[b1]; |
3661 | 4242b1bd | balrog | if (!sse_op2)
|
3662 | 4242b1bd | balrog | goto illegal_op;
|
3663 | 222a3336 | balrog | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
|
3664 | 222a3336 | balrog | goto illegal_op;
|
3665 | 4242b1bd | balrog | |
3666 | 4242b1bd | balrog | if (b1) {
|
3667 | 4242b1bd | balrog | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3668 | 4242b1bd | balrog | if (mod == 3) { |
3669 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); |
3670 | 4242b1bd | balrog | } else {
|
3671 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,xmm_t0); |
3672 | 4242b1bd | balrog | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3673 | 222a3336 | balrog | switch (b) {
|
3674 | 222a3336 | balrog | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ |
3675 | 222a3336 | balrog | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ |
3676 | 222a3336 | balrog | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ |
3677 | 222a3336 | balrog | gen_ldq_env_A0(s->mem_index, op2_offset + |
3678 | 222a3336 | balrog | offsetof(XMMReg, XMM_Q(0)));
|
3679 | 222a3336 | balrog | break;
|
3680 | 222a3336 | balrog | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ |
3681 | 222a3336 | balrog | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ |
3682 | a7812ae4 | pbrook | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
3683 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3684 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3685 | 222a3336 | balrog | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3686 | 222a3336 | balrog | offsetof(XMMReg, XMM_L(0)));
|
3687 | 222a3336 | balrog | break;
|
3688 | 222a3336 | balrog | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ |
3689 | 222a3336 | balrog | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, |
3690 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3691 | 222a3336 | balrog | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + |
3692 | 222a3336 | balrog | offsetof(XMMReg, XMM_W(0)));
|
3693 | 222a3336 | balrog | break;
|
3694 | 222a3336 | balrog | case 0x2a: /* movntqda */ |
3695 | 222a3336 | balrog | gen_ldo_env_A0(s->mem_index, op1_offset); |
3696 | 222a3336 | balrog | return;
|
3697 | 222a3336 | balrog | default:
|
3698 | 222a3336 | balrog | gen_ldo_env_A0(s->mem_index, op2_offset); |
3699 | 222a3336 | balrog | } |
3700 | 4242b1bd | balrog | } |
3701 | 4242b1bd | balrog | } else {
|
3702 | 4242b1bd | balrog | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); |
3703 | 4242b1bd | balrog | if (mod == 3) { |
3704 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3705 | 4242b1bd | balrog | } else {
|
3706 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,mmx_t0); |
3707 | 4242b1bd | balrog | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3708 | 4242b1bd | balrog | gen_ldq_env_A0(s->mem_index, op2_offset); |
3709 | 4242b1bd | balrog | } |
3710 | 4242b1bd | balrog | } |
3711 | 222a3336 | balrog | if (sse_op2 == SSE_SPECIAL)
|
3712 | 222a3336 | balrog | goto illegal_op;
|
3713 | 222a3336 | balrog | |
3714 | 4242b1bd | balrog | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3715 | 4242b1bd | balrog | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3716 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
|
3717 | 222a3336 | balrog | |
3718 | 222a3336 | balrog | if (b == 0x17) |
3719 | 222a3336 | balrog | s->cc_op = CC_OP_EFLAGS; |
3720 | 4242b1bd | balrog | break;
|
3721 | 222a3336 | balrog | case 0x338: /* crc32 */ |
3722 | 222a3336 | balrog | crc32:
|
3723 | 222a3336 | balrog | b = modrm; |
3724 | 222a3336 | balrog | modrm = ldub_code(s->pc++); |
3725 | 222a3336 | balrog | reg = ((modrm >> 3) & 7) | rex_r; |
3726 | 222a3336 | balrog | |
3727 | 222a3336 | balrog | if (b != 0xf0 && b != 0xf1) |
3728 | 222a3336 | balrog | goto illegal_op;
|
3729 | 222a3336 | balrog | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
|
3730 | 4242b1bd | balrog | goto illegal_op;
|
3731 | 4242b1bd | balrog | |
3732 | 222a3336 | balrog | if (b == 0xf0) |
3733 | 222a3336 | balrog | ot = OT_BYTE; |
3734 | 222a3336 | balrog | else if (b == 0xf1 && s->dflag != 2) |
3735 | 222a3336 | balrog | if (s->prefix & PREFIX_DATA)
|
3736 | 222a3336 | balrog | ot = OT_WORD; |
3737 | 222a3336 | balrog | else
|
3738 | 222a3336 | balrog | ot = OT_LONG; |
3739 | 222a3336 | balrog | else
|
3740 | 222a3336 | balrog | ot = OT_QUAD; |
3741 | 222a3336 | balrog | |
3742 | 222a3336 | balrog | gen_op_mov_TN_reg(OT_LONG, 0, reg);
|
3743 | 222a3336 | balrog | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3744 | 222a3336 | balrog | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
3745 | a7812ae4 | pbrook | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
|
3746 | a7812ae4 | pbrook | cpu_T[0], tcg_const_i32(8 << ot)); |
3747 | 222a3336 | balrog | |
3748 | 222a3336 | balrog | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3749 | 222a3336 | balrog | gen_op_mov_reg_T0(ot, reg); |
3750 | 222a3336 | balrog | break;
|
3751 | 222a3336 | balrog | case 0x03a: |
3752 | 222a3336 | balrog | case 0x13a: |
3753 | 4242b1bd | balrog | b = modrm; |
3754 | 4242b1bd | balrog | modrm = ldub_code(s->pc++); |
3755 | 4242b1bd | balrog | rm = modrm & 7;
|
3756 | 4242b1bd | balrog | reg = ((modrm >> 3) & 7) | rex_r; |
3757 | 4242b1bd | balrog | mod = (modrm >> 6) & 3; |
3758 | 4242b1bd | balrog | |
3759 | 222a3336 | balrog | sse_op2 = sse_op_table7[b].op[b1]; |
3760 | 4242b1bd | balrog | if (!sse_op2)
|
3761 | 4242b1bd | balrog | goto illegal_op;
|
3762 | 222a3336 | balrog | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
|
3763 | 222a3336 | balrog | goto illegal_op;
|
3764 | 222a3336 | balrog | |
3765 | 222a3336 | balrog | if (sse_op2 == SSE_SPECIAL) {
|
3766 | 222a3336 | balrog | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3767 | 222a3336 | balrog | rm = (modrm & 7) | REX_B(s);
|
3768 | 222a3336 | balrog | if (mod != 3) |
3769 | 222a3336 | balrog | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3770 | 222a3336 | balrog | reg = ((modrm >> 3) & 7) | rex_r; |
3771 | 222a3336 | balrog | val = ldub_code(s->pc++); |
3772 | 222a3336 | balrog | switch (b) {
|
3773 | 222a3336 | balrog | case 0x14: /* pextrb */ |
3774 | 222a3336 | balrog | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
|
3775 | 222a3336 | balrog | xmm_regs[reg].XMM_B(val & 15)));
|
3776 | 222a3336 | balrog | if (mod == 3) |
3777 | 222a3336 | balrog | gen_op_mov_reg_T0(ot, rm); |
3778 | 222a3336 | balrog | else
|
3779 | 222a3336 | balrog | tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
|
3780 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3781 | 222a3336 | balrog | break;
|
3782 | 222a3336 | balrog | case 0x15: /* pextrw */ |
3783 | 222a3336 | balrog | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
|
3784 | 222a3336 | balrog | xmm_regs[reg].XMM_W(val & 7)));
|
3785 | 222a3336 | balrog | if (mod == 3) |
3786 | 222a3336 | balrog | gen_op_mov_reg_T0(ot, rm); |
3787 | 222a3336 | balrog | else
|
3788 | 222a3336 | balrog | tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
|
3789 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3790 | 222a3336 | balrog | break;
|
3791 | 222a3336 | balrog | case 0x16: |
3792 | 222a3336 | balrog | if (ot == OT_LONG) { /* pextrd */ |
3793 | 222a3336 | balrog | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3794 | 222a3336 | balrog | offsetof(CPUX86State, |
3795 | 222a3336 | balrog | xmm_regs[reg].XMM_L(val & 3)));
|
3796 | a7812ae4 | pbrook | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3797 | 222a3336 | balrog | if (mod == 3) |
3798 | a7812ae4 | pbrook | gen_op_mov_reg_v(ot, rm, cpu_T[0]);
|
3799 | 222a3336 | balrog | else
|
3800 | a7812ae4 | pbrook | tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
|
3801 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3802 | 222a3336 | balrog | } else { /* pextrq */ |
3803 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
3804 | 222a3336 | balrog | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3805 | 222a3336 | balrog | offsetof(CPUX86State, |
3806 | 222a3336 | balrog | xmm_regs[reg].XMM_Q(val & 1)));
|
3807 | 222a3336 | balrog | if (mod == 3) |
3808 | 222a3336 | balrog | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); |
3809 | 222a3336 | balrog | else
|
3810 | 222a3336 | balrog | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
3811 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3812 | a7812ae4 | pbrook | #else
|
3813 | a7812ae4 | pbrook | goto illegal_op;
|
3814 | a7812ae4 | pbrook | #endif
|
3815 | 222a3336 | balrog | } |
3816 | 222a3336 | balrog | break;
|
3817 | 222a3336 | balrog | case 0x17: /* extractps */ |
3818 | 222a3336 | balrog | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
|
3819 | 222a3336 | balrog | xmm_regs[reg].XMM_L(val & 3)));
|
3820 | 222a3336 | balrog | if (mod == 3) |
3821 | 222a3336 | balrog | gen_op_mov_reg_T0(ot, rm); |
3822 | 222a3336 | balrog | else
|
3823 | 222a3336 | balrog | tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
|
3824 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3825 | 222a3336 | balrog | break;
|
3826 | 222a3336 | balrog | case 0x20: /* pinsrb */ |
3827 | 222a3336 | balrog | if (mod == 3) |
3828 | 222a3336 | balrog | gen_op_mov_TN_reg(OT_LONG, 0, rm);
|
3829 | 222a3336 | balrog | else
|
3830 | a7812ae4 | pbrook | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
3831 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3832 | a7812ae4 | pbrook | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
3833 | 222a3336 | balrog | xmm_regs[reg].XMM_B(val & 15)));
|
3834 | 222a3336 | balrog | break;
|
3835 | 222a3336 | balrog | case 0x21: /* insertps */ |
3836 | a7812ae4 | pbrook | if (mod == 3) { |
3837 | 222a3336 | balrog | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3838 | 222a3336 | balrog | offsetof(CPUX86State,xmm_regs[rm] |
3839 | 222a3336 | balrog | .XMM_L((val >> 6) & 3))); |
3840 | a7812ae4 | pbrook | } else {
|
3841 | a7812ae4 | pbrook | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
3842 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3843 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3844 | a7812ae4 | pbrook | } |
3845 | 222a3336 | balrog | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3846 | 222a3336 | balrog | offsetof(CPUX86State,xmm_regs[reg] |
3847 | 222a3336 | balrog | .XMM_L((val >> 4) & 3))); |
3848 | 222a3336 | balrog | if ((val >> 0) & 1) |
3849 | 222a3336 | balrog | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), |
3850 | 222a3336 | balrog | cpu_env, offsetof(CPUX86State, |
3851 | 222a3336 | balrog | xmm_regs[reg].XMM_L(0)));
|
3852 | 222a3336 | balrog | if ((val >> 1) & 1) |
3853 | 222a3336 | balrog | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), |
3854 | 222a3336 | balrog | cpu_env, offsetof(CPUX86State, |
3855 | 222a3336 | balrog | xmm_regs[reg].XMM_L(1)));
|
3856 | 222a3336 | balrog | if ((val >> 2) & 1) |
3857 | 222a3336 | balrog | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), |
3858 | 222a3336 | balrog | cpu_env, offsetof(CPUX86State, |
3859 | 222a3336 | balrog | xmm_regs[reg].XMM_L(2)));
|
3860 | 222a3336 | balrog | if ((val >> 3) & 1) |
3861 | 222a3336 | balrog | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), |
3862 | 222a3336 | balrog | cpu_env, offsetof(CPUX86State, |
3863 | 222a3336 | balrog | xmm_regs[reg].XMM_L(3)));
|
3864 | 222a3336 | balrog | break;
|
3865 | 222a3336 | balrog | case 0x22: |
3866 | 222a3336 | balrog | if (ot == OT_LONG) { /* pinsrd */ |
3867 | 222a3336 | balrog | if (mod == 3) |
3868 | a7812ae4 | pbrook | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
3869 | 222a3336 | balrog | else
|
3870 | a7812ae4 | pbrook | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
3871 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3872 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3873 | 222a3336 | balrog | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3874 | 222a3336 | balrog | offsetof(CPUX86State, |
3875 | 222a3336 | balrog | xmm_regs[reg].XMM_L(val & 3)));
|
3876 | 222a3336 | balrog | } else { /* pinsrq */ |
3877 | a7812ae4 | pbrook | #ifdef TARGET_X86_64
|
3878 | 222a3336 | balrog | if (mod == 3) |
3879 | 222a3336 | balrog | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); |
3880 | 222a3336 | balrog | else
|
3881 | 222a3336 | balrog | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
3882 | 222a3336 | balrog | (s->mem_index >> 2) - 1); |
3883 | 222a3336 | balrog | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
3884 | 222a3336 | balrog | offsetof(CPUX86State, |
3885 | 222a3336 | balrog | xmm_regs[reg].XMM_Q(val & 1)));
|
3886 | a7812ae4 | pbrook | #else
|
3887 | a7812ae4 | pbrook | goto illegal_op;
|
3888 | a7812ae4 | pbrook | #endif
|
3889 | 222a3336 | balrog | } |
3890 | 222a3336 | balrog | break;
|
3891 | 222a3336 | balrog | } |
3892 | 222a3336 | balrog | return;
|
3893 | 222a3336 | balrog | } |
3894 | 4242b1bd | balrog | |
3895 | 4242b1bd | balrog | if (b1) {
|
3896 | 4242b1bd | balrog | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3897 | 4242b1bd | balrog | if (mod == 3) { |
3898 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); |
3899 | 4242b1bd | balrog | } else {
|
3900 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,xmm_t0); |
3901 | 4242b1bd | balrog | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3902 | 4242b1bd | balrog | gen_ldo_env_A0(s->mem_index, op2_offset); |
3903 | 4242b1bd | balrog | } |
3904 | 4242b1bd | balrog | } else {
|
3905 | 4242b1bd | balrog | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); |
3906 | 4242b1bd | balrog | if (mod == 3) { |
3907 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3908 | 4242b1bd | balrog | } else {
|
3909 | 4242b1bd | balrog | op2_offset = offsetof(CPUX86State,mmx_t0); |
3910 | 4242b1bd | balrog | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3911 | 4242b1bd | balrog | gen_ldq_env_A0(s->mem_index, op2_offset); |
3912 | 4242b1bd | balrog | } |
3913 | 4242b1bd | balrog | } |
3914 | 4242b1bd | balrog | val = ldub_code(s->pc++); |
3915 | 4242b1bd | balrog | |
3916 | 222a3336 | balrog | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3917 | 222a3336 | balrog | s->cc_op = CC_OP_EFLAGS; |
3918 | 222a3336 | balrog | |
3919 | 222a3336 | balrog | if (s->dflag == 2) |
3920 | 222a3336 | balrog | /* The helper must use entire 64-bit gp registers */
|
3921 | 222a3336 | balrog | val |= 1 << 8; |
3922 | 222a3336 | balrog | } |
3923 | 222a3336 | balrog | |
3924 | 4242b1bd | balrog | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3925 | 4242b1bd | balrog | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3926 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
|
3927 | 4242b1bd | balrog | break;
|
3928 | 664e0f19 | bellard | default:
|
3929 | 664e0f19 | bellard | goto illegal_op;
|
3930 | 664e0f19 | bellard | } |
3931 | 664e0f19 | bellard | } else {
|
3932 | 664e0f19 | bellard | /* generic MMX or SSE operation */
|
3933 | d1e42c5c | bellard | switch(b) {
|
3934 | d1e42c5c | bellard | case 0x70: /* pshufx insn */ |
3935 | d1e42c5c | bellard | case 0xc6: /* pshufx insn */ |
3936 | d1e42c5c | bellard | case 0xc2: /* compare insns */ |
3937 | d1e42c5c | bellard | s->rip_offset = 1;
|
3938 | d1e42c5c | bellard | break;
|
3939 | d1e42c5c | bellard | default:
|
3940 | d1e42c5c | bellard | break;
|
3941 | 664e0f19 | bellard | } |
3942 | 664e0f19 | bellard | if (is_xmm) {
|
3943 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3944 | 664e0f19 | bellard | if (mod != 3) { |
3945 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3946 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3947 | 480c1cdb | bellard | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
3948 | 664e0f19 | bellard | b == 0xc2)) {
|
3949 | 664e0f19 | bellard | /* specific case for SSE single instructions */
|
3950 | 664e0f19 | bellard | if (b1 == 2) { |
3951 | 664e0f19 | bellard | /* 32 bit access */
|
3952 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3953 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
3954 | 664e0f19 | bellard | } else {
|
3955 | 664e0f19 | bellard | /* 64 bit access */
|
3956 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
|
3957 | 664e0f19 | bellard | } |
3958 | 664e0f19 | bellard | } else {
|
3959 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, op2_offset); |
3960 | 664e0f19 | bellard | } |
3961 | 664e0f19 | bellard | } else {
|
3962 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3963 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3964 | 664e0f19 | bellard | } |
3965 | 664e0f19 | bellard | } else {
|
3966 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); |
3967 | 664e0f19 | bellard | if (mod != 3) { |
3968 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3969 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,mmx_t0); |
3970 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, op2_offset); |
3971 | 664e0f19 | bellard | } else {
|
3972 | 664e0f19 | bellard | rm = (modrm & 7);
|
3973 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3974 | 664e0f19 | bellard | } |
3975 | 664e0f19 | bellard | } |
3976 | 664e0f19 | bellard | switch(b) {
|
3977 | a35f3ec7 | aurel32 | case 0x0f: /* 3DNow! data insns */ |
3978 | e771edab | aurel32 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
|
3979 | e771edab | aurel32 | goto illegal_op;
|
3980 | a35f3ec7 | aurel32 | val = ldub_code(s->pc++); |
3981 | a35f3ec7 | aurel32 | sse_op2 = sse_op_table5[val]; |
3982 | a35f3ec7 | aurel32 | if (!sse_op2)
|
3983 | a35f3ec7 | aurel32 | goto illegal_op;
|
3984 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3985 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3986 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
|
3987 | a35f3ec7 | aurel32 | break;
|
3988 | 664e0f19 | bellard | case 0x70: /* pshufx insn */ |
3989 | 664e0f19 | bellard | case 0xc6: /* pshufx insn */ |
3990 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3991 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3992 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3993 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
|
3994 | 664e0f19 | bellard | break;
|
3995 | 664e0f19 | bellard | case 0xc2: |
3996 | 664e0f19 | bellard | /* compare insns */
|
3997 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3998 | 664e0f19 | bellard | if (val >= 8) |
3999 | 664e0f19 | bellard | goto illegal_op;
|
4000 | 664e0f19 | bellard | sse_op2 = sse_op_table4[val][b1]; |
4001 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4002 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
4003 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
|
4004 | 664e0f19 | bellard | break;
|
4005 | b8b6a50b | bellard | case 0xf7: |
4006 | b8b6a50b | bellard | /* maskmov : we must prepare A0 */
|
4007 | b8b6a50b | bellard | if (mod != 3) |
4008 | b8b6a50b | bellard | goto illegal_op;
|
4009 | b8b6a50b | bellard | #ifdef TARGET_X86_64
|
4010 | b8b6a50b | bellard | if (s->aflag == 2) { |
4011 | b8b6a50b | bellard | gen_op_movq_A0_reg(R_EDI); |
4012 | b8b6a50b | bellard | } else
|
4013 | b8b6a50b | bellard | #endif
|
4014 | b8b6a50b | bellard | { |
4015 | b8b6a50b | bellard | gen_op_movl_A0_reg(R_EDI); |
4016 | b8b6a50b | bellard | if (s->aflag == 0) |
4017 | b8b6a50b | bellard | gen_op_andl_A0_ffff(); |
4018 | b8b6a50b | bellard | } |
4019 | b8b6a50b | bellard | gen_add_A0_ds_seg(s); |
4020 | b8b6a50b | bellard | |
4021 | b8b6a50b | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4022 | b8b6a50b | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
4023 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
|
4024 | b8b6a50b | bellard | break;
|
4025 | 664e0f19 | bellard | default:
|
4026 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4027 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
4028 | a7812ae4 | pbrook | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
|
4029 | 664e0f19 | bellard | break;
|
4030 | 664e0f19 | bellard | } |
4031 | 664e0f19 | bellard | if (b == 0x2e || b == 0x2f) { |
4032 | 664e0f19 | bellard | s->cc_op = CC_OP_EFLAGS; |
4033 | 664e0f19 | bellard | } |
4034 | 664e0f19 | bellard | } |
4035 | 664e0f19 | bellard | } |
4036 | 664e0f19 | bellard | |
4037 | 2c0262af | bellard | /* convert one instruction. s->is_jmp is set if the translation must
|
4038 | 2c0262af | bellard | be stopped. Return the next pc value */
|
4039 | 14ce26e7 | bellard | static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
|
4040 | 2c0262af | bellard | { |
4041 | 2c0262af | bellard | int b, prefixes, aflag, dflag;
|
4042 | 2c0262af | bellard | int shift, ot;
|
4043 | 2c0262af | bellard | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
|
4044 | 14ce26e7 | bellard | target_ulong next_eip, tval; |
4045 | 14ce26e7 | bellard | int rex_w, rex_r;
|
4046 | 2c0262af | bellard | |
4047 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
4048 | 70cff25e | bellard | tcg_gen_debug_insn_start(pc_start); |
4049 | 2c0262af | bellard | s->pc = pc_start; |
4050 | 2c0262af | bellard | prefixes = 0;
|
4051 | 2c0262af | bellard | aflag = s->code32; |
4052 | 2c0262af | bellard | dflag = s->code32; |
4053 | 2c0262af | bellard | s->override = -1;
|
4054 | 14ce26e7 | bellard | rex_w = -1;
|
4055 | 14ce26e7 | bellard | rex_r = 0;
|
4056 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4057 | 14ce26e7 | bellard | s->rex_x = 0;
|
4058 | 14ce26e7 | bellard | s->rex_b = 0;
|
4059 | 5fafdf24 | ths | x86_64_hregs = 0;
|
4060 | 14ce26e7 | bellard | #endif
|
4061 | 14ce26e7 | bellard | s->rip_offset = 0; /* for relative ip address */ |
4062 | 2c0262af | bellard | next_byte:
|
4063 | 61382a50 | bellard | b = ldub_code(s->pc); |
4064 | 2c0262af | bellard | s->pc++; |
4065 | 2c0262af | bellard | /* check prefixes */
|
4066 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4067 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4068 | 14ce26e7 | bellard | switch (b) {
|
4069 | 14ce26e7 | bellard | case 0xf3: |
4070 | 14ce26e7 | bellard | prefixes |= PREFIX_REPZ; |
4071 | 14ce26e7 | bellard | goto next_byte;
|
4072 | 14ce26e7 | bellard | case 0xf2: |
4073 | 14ce26e7 | bellard | prefixes |= PREFIX_REPNZ; |
4074 | 14ce26e7 | bellard | goto next_byte;
|
4075 | 14ce26e7 | bellard | case 0xf0: |
4076 | 14ce26e7 | bellard | prefixes |= PREFIX_LOCK; |
4077 | 14ce26e7 | bellard | goto next_byte;
|
4078 | 14ce26e7 | bellard | case 0x2e: |
4079 | 14ce26e7 | bellard | s->override = R_CS; |
4080 | 14ce26e7 | bellard | goto next_byte;
|
4081 | 14ce26e7 | bellard | case 0x36: |
4082 | 14ce26e7 | bellard | s->override = R_SS; |
4083 | 14ce26e7 | bellard | goto next_byte;
|
4084 | 14ce26e7 | bellard | case 0x3e: |
4085 | 14ce26e7 | bellard | s->override = R_DS; |
4086 | 14ce26e7 | bellard | goto next_byte;
|
4087 | 14ce26e7 | bellard | case 0x26: |
4088 | 14ce26e7 | bellard | s->override = R_ES; |
4089 | 14ce26e7 | bellard | goto next_byte;
|
4090 | 14ce26e7 | bellard | case 0x64: |
4091 | 14ce26e7 | bellard | s->override = R_FS; |
4092 | 14ce26e7 | bellard | goto next_byte;
|
4093 | 14ce26e7 | bellard | case 0x65: |
4094 | 14ce26e7 | bellard | s->override = R_GS; |
4095 | 14ce26e7 | bellard | goto next_byte;
|
4096 | 14ce26e7 | bellard | case 0x66: |
4097 | 14ce26e7 | bellard | prefixes |= PREFIX_DATA; |
4098 | 14ce26e7 | bellard | goto next_byte;
|
4099 | 14ce26e7 | bellard | case 0x67: |
4100 | 14ce26e7 | bellard | prefixes |= PREFIX_ADR; |
4101 | 14ce26e7 | bellard | goto next_byte;
|
4102 | 14ce26e7 | bellard | case 0x40 ... 0x4f: |
4103 | 14ce26e7 | bellard | /* REX prefix */
|
4104 | 14ce26e7 | bellard | rex_w = (b >> 3) & 1; |
4105 | 14ce26e7 | bellard | rex_r = (b & 0x4) << 1; |
4106 | 14ce26e7 | bellard | s->rex_x = (b & 0x2) << 2; |
4107 | 14ce26e7 | bellard | REX_B(s) = (b & 0x1) << 3; |
4108 | 14ce26e7 | bellard | x86_64_hregs = 1; /* select uniform byte register addressing */ |
4109 | 14ce26e7 | bellard | goto next_byte;
|
4110 | 14ce26e7 | bellard | } |
4111 | 14ce26e7 | bellard | if (rex_w == 1) { |
4112 | 14ce26e7 | bellard | /* 0x66 is ignored if rex.w is set */
|
4113 | 14ce26e7 | bellard | dflag = 2;
|
4114 | 14ce26e7 | bellard | } else {
|
4115 | 14ce26e7 | bellard | if (prefixes & PREFIX_DATA)
|
4116 | 14ce26e7 | bellard | dflag ^= 1;
|
4117 | 14ce26e7 | bellard | } |
4118 | 14ce26e7 | bellard | if (!(prefixes & PREFIX_ADR))
|
4119 | 14ce26e7 | bellard | aflag = 2;
|
4120 | 5fafdf24 | ths | } else
|
4121 | 14ce26e7 | bellard | #endif
|
4122 | 14ce26e7 | bellard | { |
4123 | 14ce26e7 | bellard | switch (b) {
|
4124 | 14ce26e7 | bellard | case 0xf3: |
4125 | 14ce26e7 | bellard | prefixes |= PREFIX_REPZ; |
4126 | 14ce26e7 | bellard | goto next_byte;
|
4127 | 14ce26e7 | bellard | case 0xf2: |
4128 | 14ce26e7 | bellard | prefixes |= PREFIX_REPNZ; |
4129 | 14ce26e7 | bellard | goto next_byte;
|
4130 | 14ce26e7 | bellard | case 0xf0: |
4131 | 14ce26e7 | bellard | prefixes |= PREFIX_LOCK; |
4132 | 14ce26e7 | bellard | goto next_byte;
|
4133 | 14ce26e7 | bellard | case 0x2e: |
4134 | 14ce26e7 | bellard | s->override = R_CS; |
4135 | 14ce26e7 | bellard | goto next_byte;
|
4136 | 14ce26e7 | bellard | case 0x36: |
4137 | 14ce26e7 | bellard | s->override = R_SS; |
4138 | 14ce26e7 | bellard | goto next_byte;
|
4139 | 14ce26e7 | bellard | case 0x3e: |
4140 | 14ce26e7 | bellard | s->override = R_DS; |
4141 | 14ce26e7 | bellard | goto next_byte;
|
4142 | 14ce26e7 | bellard | case 0x26: |
4143 | 14ce26e7 | bellard | s->override = R_ES; |
4144 | 14ce26e7 | bellard | goto next_byte;
|
4145 | 14ce26e7 | bellard | case 0x64: |
4146 | 14ce26e7 | bellard | s->override = R_FS; |
4147 | 14ce26e7 | bellard | goto next_byte;
|
4148 | 14ce26e7 | bellard | case 0x65: |
4149 | 14ce26e7 | bellard | s->override = R_GS; |
4150 | 14ce26e7 | bellard | goto next_byte;
|
4151 | 14ce26e7 | bellard | case 0x66: |
4152 | 14ce26e7 | bellard | prefixes |= PREFIX_DATA; |
4153 | 14ce26e7 | bellard | goto next_byte;
|
4154 | 14ce26e7 | bellard | case 0x67: |
4155 | 14ce26e7 | bellard | prefixes |= PREFIX_ADR; |
4156 | 14ce26e7 | bellard | goto next_byte;
|
4157 | 14ce26e7 | bellard | } |
4158 | 14ce26e7 | bellard | if (prefixes & PREFIX_DATA)
|
4159 | 14ce26e7 | bellard | dflag ^= 1;
|
4160 | 14ce26e7 | bellard | if (prefixes & PREFIX_ADR)
|
4161 | 14ce26e7 | bellard | aflag ^= 1;
|
4162 | 2c0262af | bellard | } |
4163 | 2c0262af | bellard | |
4164 | 2c0262af | bellard | s->prefix = prefixes; |
4165 | 2c0262af | bellard | s->aflag = aflag; |
4166 | 2c0262af | bellard | s->dflag = dflag; |
4167 | 2c0262af | bellard | |
4168 | 2c0262af | bellard | /* lock generation */
|
4169 | 2c0262af | bellard | if (prefixes & PREFIX_LOCK)
|
4170 | a7812ae4 | pbrook | gen_helper_lock(); |
4171 | 2c0262af | bellard | |
4172 | 2c0262af | bellard | /* now check op code */
|
4173 | 2c0262af | bellard | reswitch:
|
4174 | 2c0262af | bellard | switch(b) {
|
4175 | 2c0262af | bellard | case 0x0f: |
4176 | 2c0262af | bellard | /**************************/
|
4177 | 2c0262af | bellard | /* extended op code */
|
4178 | 61382a50 | bellard | b = ldub_code(s->pc++) | 0x100;
|
4179 | 2c0262af | bellard | goto reswitch;
|
4180 | 3b46e624 | ths | |
4181 | 2c0262af | bellard | /**************************/
|
4182 | 2c0262af | bellard | /* arith & logic */
|
4183 | 2c0262af | bellard | case 0x00 ... 0x05: |
4184 | 2c0262af | bellard | case 0x08 ... 0x0d: |
4185 | 2c0262af | bellard | case 0x10 ... 0x15: |
4186 | 2c0262af | bellard | case 0x18 ... 0x1d: |
4187 | 2c0262af | bellard | case 0x20 ... 0x25: |
4188 | 2c0262af | bellard | case 0x28 ... 0x2d: |
4189 | 2c0262af | bellard | case 0x30 ... 0x35: |
4190 | 2c0262af | bellard | case 0x38 ... 0x3d: |
4191 | 2c0262af | bellard | { |
4192 | 2c0262af | bellard | int op, f, val;
|
4193 | 2c0262af | bellard | op = (b >> 3) & 7; |
4194 | 2c0262af | bellard | f = (b >> 1) & 3; |
4195 | 2c0262af | bellard | |
4196 | 2c0262af | bellard | if ((b & 1) == 0) |
4197 | 2c0262af | bellard | ot = OT_BYTE; |
4198 | 2c0262af | bellard | else
|
4199 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4200 | 3b46e624 | ths | |
4201 | 2c0262af | bellard | switch(f) {
|
4202 | 2c0262af | bellard | case 0: /* OP Ev, Gv */ |
4203 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4204 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4205 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4206 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4207 | 2c0262af | bellard | if (mod != 3) { |
4208 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4209 | 2c0262af | bellard | opreg = OR_TMP0; |
4210 | 2c0262af | bellard | } else if (op == OP_XORL && rm == reg) { |
4211 | 2c0262af | bellard | xor_zero:
|
4212 | 2c0262af | bellard | /* xor reg, reg optimisation */
|
4213 | 2c0262af | bellard | gen_op_movl_T0_0(); |
4214 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4215 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
4216 | 2c0262af | bellard | gen_op_update1_cc(); |
4217 | 2c0262af | bellard | break;
|
4218 | 2c0262af | bellard | } else {
|
4219 | 2c0262af | bellard | opreg = rm; |
4220 | 2c0262af | bellard | } |
4221 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4222 | 2c0262af | bellard | gen_op(s, op, ot, opreg); |
4223 | 2c0262af | bellard | break;
|
4224 | 2c0262af | bellard | case 1: /* OP Gv, Ev */ |
4225 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4226 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4227 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4228 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4229 | 2c0262af | bellard | if (mod != 3) { |
4230 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4231 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4232 | 2c0262af | bellard | } else if (op == OP_XORL && rm == reg) { |
4233 | 2c0262af | bellard | goto xor_zero;
|
4234 | 2c0262af | bellard | } else {
|
4235 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
4236 | 2c0262af | bellard | } |
4237 | 2c0262af | bellard | gen_op(s, op, ot, reg); |
4238 | 2c0262af | bellard | break;
|
4239 | 2c0262af | bellard | case 2: /* OP A, Iv */ |
4240 | 2c0262af | bellard | val = insn_get(s, ot); |
4241 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4242 | 2c0262af | bellard | gen_op(s, op, ot, OR_EAX); |
4243 | 2c0262af | bellard | break;
|
4244 | 2c0262af | bellard | } |
4245 | 2c0262af | bellard | } |
4246 | 2c0262af | bellard | break;
|
4247 | 2c0262af | bellard | |
4248 | ec9d6075 | bellard | case 0x82: |
4249 | ec9d6075 | bellard | if (CODE64(s))
|
4250 | ec9d6075 | bellard | goto illegal_op;
|
4251 | 2c0262af | bellard | case 0x80: /* GRP1 */ |
4252 | 2c0262af | bellard | case 0x81: |
4253 | 2c0262af | bellard | case 0x83: |
4254 | 2c0262af | bellard | { |
4255 | 2c0262af | bellard | int val;
|
4256 | 2c0262af | bellard | |
4257 | 2c0262af | bellard | if ((b & 1) == 0) |
4258 | 2c0262af | bellard | ot = OT_BYTE; |
4259 | 2c0262af | bellard | else
|
4260 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4261 | 3b46e624 | ths | |
4262 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4263 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4264 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4265 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
4266 | 3b46e624 | ths | |
4267 | 2c0262af | bellard | if (mod != 3) { |
4268 | 14ce26e7 | bellard | if (b == 0x83) |
4269 | 14ce26e7 | bellard | s->rip_offset = 1;
|
4270 | 14ce26e7 | bellard | else
|
4271 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
4272 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4273 | 2c0262af | bellard | opreg = OR_TMP0; |
4274 | 2c0262af | bellard | } else {
|
4275 | 14ce26e7 | bellard | opreg = rm; |
4276 | 2c0262af | bellard | } |
4277 | 2c0262af | bellard | |
4278 | 2c0262af | bellard | switch(b) {
|
4279 | 2c0262af | bellard | default:
|
4280 | 2c0262af | bellard | case 0x80: |
4281 | 2c0262af | bellard | case 0x81: |
4282 | d64477af | bellard | case 0x82: |
4283 | 2c0262af | bellard | val = insn_get(s, ot); |
4284 | 2c0262af | bellard | break;
|
4285 | 2c0262af | bellard | case 0x83: |
4286 | 2c0262af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
4287 | 2c0262af | bellard | break;
|
4288 | 2c0262af | bellard | } |
4289 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4290 | 2c0262af | bellard | gen_op(s, op, ot, opreg); |
4291 | 2c0262af | bellard | } |
4292 | 2c0262af | bellard | break;
|
4293 | 2c0262af | bellard | |
4294 | 2c0262af | bellard | /**************************/
|
4295 | 2c0262af | bellard | /* inc, dec, and other misc arith */
|
4296 | 2c0262af | bellard | case 0x40 ... 0x47: /* inc Gv */ |
4297 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
4298 | 2c0262af | bellard | gen_inc(s, ot, OR_EAX + (b & 7), 1); |
4299 | 2c0262af | bellard | break;
|
4300 | 2c0262af | bellard | case 0x48 ... 0x4f: /* dec Gv */ |
4301 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
4302 | 2c0262af | bellard | gen_inc(s, ot, OR_EAX + (b & 7), -1); |
4303 | 2c0262af | bellard | break;
|
4304 | 2c0262af | bellard | case 0xf6: /* GRP3 */ |
4305 | 2c0262af | bellard | case 0xf7: |
4306 | 2c0262af | bellard | if ((b & 1) == 0) |
4307 | 2c0262af | bellard | ot = OT_BYTE; |
4308 | 2c0262af | bellard | else
|
4309 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4310 | 2c0262af | bellard | |
4311 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4312 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4313 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4314 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
4315 | 2c0262af | bellard | if (mod != 3) { |
4316 | 14ce26e7 | bellard | if (op == 0) |
4317 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
4318 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4319 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
4320 | 2c0262af | bellard | } else {
|
4321 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
4322 | 2c0262af | bellard | } |
4323 | 2c0262af | bellard | |
4324 | 2c0262af | bellard | switch(op) {
|
4325 | 2c0262af | bellard | case 0: /* test */ |
4326 | 2c0262af | bellard | val = insn_get(s, ot); |
4327 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4328 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
4329 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4330 | 2c0262af | bellard | break;
|
4331 | 2c0262af | bellard | case 2: /* not */ |
4332 | b6abf97d | bellard | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
4333 | 2c0262af | bellard | if (mod != 3) { |
4334 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4335 | 2c0262af | bellard | } else {
|
4336 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4337 | 2c0262af | bellard | } |
4338 | 2c0262af | bellard | break;
|
4339 | 2c0262af | bellard | case 3: /* neg */ |
4340 | b6abf97d | bellard | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
4341 | 2c0262af | bellard | if (mod != 3) { |
4342 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4343 | 2c0262af | bellard | } else {
|
4344 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4345 | 2c0262af | bellard | } |
4346 | 2c0262af | bellard | gen_op_update_neg_cc(); |
4347 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
4348 | 2c0262af | bellard | break;
|
4349 | 2c0262af | bellard | case 4: /* mul */ |
4350 | 2c0262af | bellard | switch(ot) {
|
4351 | 2c0262af | bellard | case OT_BYTE:
|
4352 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
|
4353 | 0211e5af | bellard | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
4354 | 0211e5af | bellard | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); |
4355 | 0211e5af | bellard | /* XXX: use 32 bit mul which could be faster */
|
4356 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4357 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
4358 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4359 | 0211e5af | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); |
4360 | d36cd60e | bellard | s->cc_op = CC_OP_MULB; |
4361 | 2c0262af | bellard | break;
|
4362 | 2c0262af | bellard | case OT_WORD:
|
4363 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
|
4364 | 0211e5af | bellard | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
4365 | 0211e5af | bellard | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); |
4366 | 0211e5af | bellard | /* XXX: use 32 bit mul which could be faster */
|
4367 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4368 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
4369 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4370 | 0211e5af | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); |
4371 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EDX); |
4372 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
4373 | d36cd60e | bellard | s->cc_op = CC_OP_MULW; |
4374 | 2c0262af | bellard | break;
|
4375 | 2c0262af | bellard | default:
|
4376 | 2c0262af | bellard | case OT_LONG:
|
4377 | 0211e5af | bellard | #ifdef TARGET_X86_64
|
4378 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
|
4379 | 0211e5af | bellard | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
4380 | 0211e5af | bellard | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); |
4381 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4382 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EAX); |
4383 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4384 | 0211e5af | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); |
4385 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EDX); |
4386 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
4387 | 0211e5af | bellard | #else
|
4388 | 0211e5af | bellard | { |
4389 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
4390 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
4391 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
4392 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
|
4393 | 0211e5af | bellard | tcg_gen_extu_i32_i64(t0, cpu_T[0]);
|
4394 | 0211e5af | bellard | tcg_gen_extu_i32_i64(t1, cpu_T[1]);
|
4395 | 0211e5af | bellard | tcg_gen_mul_i64(t0, t0, t1); |
4396 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[0], t0);
|
4397 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EAX); |
4398 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4399 | 0211e5af | bellard | tcg_gen_shri_i64(t0, t0, 32);
|
4400 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[0], t0);
|
4401 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EDX); |
4402 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
4403 | 0211e5af | bellard | } |
4404 | 0211e5af | bellard | #endif
|
4405 | d36cd60e | bellard | s->cc_op = CC_OP_MULL; |
4406 | 2c0262af | bellard | break;
|
4407 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4408 | 14ce26e7 | bellard | case OT_QUAD:
|
4409 | a7812ae4 | pbrook | gen_helper_mulq_EAX_T0(cpu_T[0]);
|
4410 | 14ce26e7 | bellard | s->cc_op = CC_OP_MULQ; |
4411 | 14ce26e7 | bellard | break;
|
4412 | 14ce26e7 | bellard | #endif
|
4413 | 2c0262af | bellard | } |
4414 | 2c0262af | bellard | break;
|
4415 | 2c0262af | bellard | case 5: /* imul */ |
4416 | 2c0262af | bellard | switch(ot) {
|
4417 | 2c0262af | bellard | case OT_BYTE:
|
4418 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
|
4419 | 0211e5af | bellard | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4420 | 0211e5af | bellard | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); |
4421 | 0211e5af | bellard | /* XXX: use 32 bit mul which could be faster */
|
4422 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4423 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
4424 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4425 | 0211e5af | bellard | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
|
4426 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4427 | d36cd60e | bellard | s->cc_op = CC_OP_MULB; |
4428 | 2c0262af | bellard | break;
|
4429 | 2c0262af | bellard | case OT_WORD:
|
4430 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
|
4431 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4432 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); |
4433 | 0211e5af | bellard | /* XXX: use 32 bit mul which could be faster */
|
4434 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4435 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
4436 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4437 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
|
4438 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4439 | 0211e5af | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); |
4440 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_WORD, R_EDX); |
4441 | d36cd60e | bellard | s->cc_op = CC_OP_MULW; |
4442 | 2c0262af | bellard | break;
|
4443 | 2c0262af | bellard | default:
|
4444 | 2c0262af | bellard | case OT_LONG:
|
4445 | 0211e5af | bellard | #ifdef TARGET_X86_64
|
4446 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
|
4447 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4448 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); |
4449 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4450 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EAX); |
4451 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4452 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
|
4453 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4454 | 0211e5af | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); |
4455 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EDX); |
4456 | 0211e5af | bellard | #else
|
4457 | 0211e5af | bellard | { |
4458 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
4459 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
4460 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
4461 | 0211e5af | bellard | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
|
4462 | 0211e5af | bellard | tcg_gen_ext_i32_i64(t0, cpu_T[0]);
|
4463 | 0211e5af | bellard | tcg_gen_ext_i32_i64(t1, cpu_T[1]);
|
4464 | 0211e5af | bellard | tcg_gen_mul_i64(t0, t0, t1); |
4465 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[0], t0);
|
4466 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EAX); |
4467 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4468 | 0211e5af | bellard | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); |
4469 | 0211e5af | bellard | tcg_gen_shri_i64(t0, t0, 32);
|
4470 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[0], t0);
|
4471 | 0211e5af | bellard | gen_op_mov_reg_T0(OT_LONG, R_EDX); |
4472 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4473 | 0211e5af | bellard | } |
4474 | 0211e5af | bellard | #endif
|
4475 | d36cd60e | bellard | s->cc_op = CC_OP_MULL; |
4476 | 2c0262af | bellard | break;
|
4477 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4478 | 14ce26e7 | bellard | case OT_QUAD:
|
4479 | a7812ae4 | pbrook | gen_helper_imulq_EAX_T0(cpu_T[0]);
|
4480 | 14ce26e7 | bellard | s->cc_op = CC_OP_MULQ; |
4481 | 14ce26e7 | bellard | break;
|
4482 | 14ce26e7 | bellard | #endif
|
4483 | 2c0262af | bellard | } |
4484 | 2c0262af | bellard | break;
|
4485 | 2c0262af | bellard | case 6: /* div */ |
4486 | 2c0262af | bellard | switch(ot) {
|
4487 | 2c0262af | bellard | case OT_BYTE:
|
4488 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4489 | a7812ae4 | pbrook | gen_helper_divb_AL(cpu_T[0]);
|
4490 | 2c0262af | bellard | break;
|
4491 | 2c0262af | bellard | case OT_WORD:
|
4492 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4493 | a7812ae4 | pbrook | gen_helper_divw_AX(cpu_T[0]);
|
4494 | 2c0262af | bellard | break;
|
4495 | 2c0262af | bellard | default:
|
4496 | 2c0262af | bellard | case OT_LONG:
|
4497 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4498 | a7812ae4 | pbrook | gen_helper_divl_EAX(cpu_T[0]);
|
4499 | 14ce26e7 | bellard | break;
|
4500 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4501 | 14ce26e7 | bellard | case OT_QUAD:
|
4502 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4503 | a7812ae4 | pbrook | gen_helper_divq_EAX(cpu_T[0]);
|
4504 | 2c0262af | bellard | break;
|
4505 | 14ce26e7 | bellard | #endif
|
4506 | 2c0262af | bellard | } |
4507 | 2c0262af | bellard | break;
|
4508 | 2c0262af | bellard | case 7: /* idiv */ |
4509 | 2c0262af | bellard | switch(ot) {
|
4510 | 2c0262af | bellard | case OT_BYTE:
|
4511 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4512 | a7812ae4 | pbrook | gen_helper_idivb_AL(cpu_T[0]);
|
4513 | 2c0262af | bellard | break;
|
4514 | 2c0262af | bellard | case OT_WORD:
|
4515 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4516 | a7812ae4 | pbrook | gen_helper_idivw_AX(cpu_T[0]);
|
4517 | 2c0262af | bellard | break;
|
4518 | 2c0262af | bellard | default:
|
4519 | 2c0262af | bellard | case OT_LONG:
|
4520 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4521 | a7812ae4 | pbrook | gen_helper_idivl_EAX(cpu_T[0]);
|
4522 | 14ce26e7 | bellard | break;
|
4523 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4524 | 14ce26e7 | bellard | case OT_QUAD:
|
4525 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4526 | a7812ae4 | pbrook | gen_helper_idivq_EAX(cpu_T[0]);
|
4527 | 2c0262af | bellard | break;
|
4528 | 14ce26e7 | bellard | #endif
|
4529 | 2c0262af | bellard | } |
4530 | 2c0262af | bellard | break;
|
4531 | 2c0262af | bellard | default:
|
4532 | 2c0262af | bellard | goto illegal_op;
|
4533 | 2c0262af | bellard | } |
4534 | 2c0262af | bellard | break;
|
4535 | 2c0262af | bellard | |
4536 | 2c0262af | bellard | case 0xfe: /* GRP4 */ |
4537 | 2c0262af | bellard | case 0xff: /* GRP5 */ |
4538 | 2c0262af | bellard | if ((b & 1) == 0) |
4539 | 2c0262af | bellard | ot = OT_BYTE; |
4540 | 2c0262af | bellard | else
|
4541 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4542 | 2c0262af | bellard | |
4543 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4544 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4545 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4546 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
4547 | 2c0262af | bellard | if (op >= 2 && b == 0xfe) { |
4548 | 2c0262af | bellard | goto illegal_op;
|
4549 | 2c0262af | bellard | } |
4550 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4551 | aba9d61e | bellard | if (op == 2 || op == 4) { |
4552 | 14ce26e7 | bellard | /* operand size for jumps is 64 bit */
|
4553 | 14ce26e7 | bellard | ot = OT_QUAD; |
4554 | aba9d61e | bellard | } else if (op == 3 || op == 5) { |
4555 | aba9d61e | bellard | /* for call calls, the operand is 16 or 32 bit, even
|
4556 | aba9d61e | bellard | in long mode */
|
4557 | aba9d61e | bellard | ot = dflag ? OT_LONG : OT_WORD; |
4558 | 14ce26e7 | bellard | } else if (op == 6) { |
4559 | 14ce26e7 | bellard | /* default push size is 64 bit */
|
4560 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4561 | 14ce26e7 | bellard | } |
4562 | 14ce26e7 | bellard | } |
4563 | 2c0262af | bellard | if (mod != 3) { |
4564 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4565 | 2c0262af | bellard | if (op >= 2 && op != 3 && op != 5) |
4566 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
4567 | 2c0262af | bellard | } else {
|
4568 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
4569 | 2c0262af | bellard | } |
4570 | 2c0262af | bellard | |
4571 | 2c0262af | bellard | switch(op) {
|
4572 | 2c0262af | bellard | case 0: /* inc Ev */ |
4573 | 2c0262af | bellard | if (mod != 3) |
4574 | 2c0262af | bellard | opreg = OR_TMP0; |
4575 | 2c0262af | bellard | else
|
4576 | 2c0262af | bellard | opreg = rm; |
4577 | 2c0262af | bellard | gen_inc(s, ot, opreg, 1);
|
4578 | 2c0262af | bellard | break;
|
4579 | 2c0262af | bellard | case 1: /* dec Ev */ |
4580 | 2c0262af | bellard | if (mod != 3) |
4581 | 2c0262af | bellard | opreg = OR_TMP0; |
4582 | 2c0262af | bellard | else
|
4583 | 2c0262af | bellard | opreg = rm; |
4584 | 2c0262af | bellard | gen_inc(s, ot, opreg, -1);
|
4585 | 2c0262af | bellard | break;
|
4586 | 2c0262af | bellard | case 2: /* call Ev */ |
4587 | 4f31916f | bellard | /* XXX: optimize if memory (no 'and' is necessary) */
|
4588 | 2c0262af | bellard | if (s->dflag == 0) |
4589 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
4590 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
4591 | 1ef38687 | bellard | gen_movtl_T1_im(next_eip); |
4592 | 4f31916f | bellard | gen_push_T1(s); |
4593 | 4f31916f | bellard | gen_op_jmp_T0(); |
4594 | 2c0262af | bellard | gen_eob(s); |
4595 | 2c0262af | bellard | break;
|
4596 | 61382a50 | bellard | case 3: /* lcall Ev */ |
4597 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4598 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
4599 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
4600 | 2c0262af | bellard | do_lcall:
|
4601 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
4602 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4603 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
4604 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4605 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4606 | a7812ae4 | pbrook | gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
|
4607 | a7812ae4 | pbrook | tcg_const_i32(dflag), |
4608 | a7812ae4 | pbrook | tcg_const_i32(s->pc - pc_start)); |
4609 | 2c0262af | bellard | } else {
|
4610 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4611 | a7812ae4 | pbrook | gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
|
4612 | a7812ae4 | pbrook | tcg_const_i32(dflag), |
4613 | a7812ae4 | pbrook | tcg_const_i32(s->pc - s->cs_base)); |
4614 | 2c0262af | bellard | } |
4615 | 2c0262af | bellard | gen_eob(s); |
4616 | 2c0262af | bellard | break;
|
4617 | 2c0262af | bellard | case 4: /* jmp Ev */ |
4618 | 2c0262af | bellard | if (s->dflag == 0) |
4619 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
4620 | 2c0262af | bellard | gen_op_jmp_T0(); |
4621 | 2c0262af | bellard | gen_eob(s); |
4622 | 2c0262af | bellard | break;
|
4623 | 2c0262af | bellard | case 5: /* ljmp Ev */ |
4624 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4625 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
4626 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
4627 | 2c0262af | bellard | do_ljmp:
|
4628 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
4629 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4630 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
4631 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4632 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4633 | a7812ae4 | pbrook | gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
|
4634 | a7812ae4 | pbrook | tcg_const_i32(s->pc - pc_start)); |
4635 | 2c0262af | bellard | } else {
|
4636 | 3bd7da9e | bellard | gen_op_movl_seg_T0_vm(R_CS); |
4637 | 2c0262af | bellard | gen_op_movl_T0_T1(); |
4638 | 2c0262af | bellard | gen_op_jmp_T0(); |
4639 | 2c0262af | bellard | } |
4640 | 2c0262af | bellard | gen_eob(s); |
4641 | 2c0262af | bellard | break;
|
4642 | 2c0262af | bellard | case 6: /* push Ev */ |
4643 | 2c0262af | bellard | gen_push_T0(s); |
4644 | 2c0262af | bellard | break;
|
4645 | 2c0262af | bellard | default:
|
4646 | 2c0262af | bellard | goto illegal_op;
|
4647 | 2c0262af | bellard | } |
4648 | 2c0262af | bellard | break;
|
4649 | 2c0262af | bellard | |
4650 | 2c0262af | bellard | case 0x84: /* test Ev, Gv */ |
4651 | 5fafdf24 | ths | case 0x85: |
4652 | 2c0262af | bellard | if ((b & 1) == 0) |
4653 | 2c0262af | bellard | ot = OT_BYTE; |
4654 | 2c0262af | bellard | else
|
4655 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4656 | 2c0262af | bellard | |
4657 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4658 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4659 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4660 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4661 | 3b46e624 | ths | |
4662 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
4663 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4664 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
4665 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4666 | 2c0262af | bellard | break;
|
4667 | 3b46e624 | ths | |
4668 | 2c0262af | bellard | case 0xa8: /* test eAX, Iv */ |
4669 | 2c0262af | bellard | case 0xa9: |
4670 | 2c0262af | bellard | if ((b & 1) == 0) |
4671 | 2c0262af | bellard | ot = OT_BYTE; |
4672 | 2c0262af | bellard | else
|
4673 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4674 | 2c0262af | bellard | val = insn_get(s, ot); |
4675 | 2c0262af | bellard | |
4676 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, OR_EAX);
|
4677 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4678 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
4679 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4680 | 2c0262af | bellard | break;
|
4681 | 3b46e624 | ths | |
4682 | 2c0262af | bellard | case 0x98: /* CWDE/CBW */ |
4683 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4684 | 14ce26e7 | bellard | if (dflag == 2) { |
4685 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
4686 | e108dd01 | bellard | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4687 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_QUAD, R_EAX); |
4688 | 14ce26e7 | bellard | } else
|
4689 | 14ce26e7 | bellard | #endif
|
4690 | e108dd01 | bellard | if (dflag == 1) { |
4691 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
|
4692 | e108dd01 | bellard | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4693 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_LONG, R_EAX); |
4694 | e108dd01 | bellard | } else {
|
4695 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
|
4696 | e108dd01 | bellard | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
4697 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
4698 | e108dd01 | bellard | } |
4699 | 2c0262af | bellard | break;
|
4700 | 2c0262af | bellard | case 0x99: /* CDQ/CWD */ |
4701 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4702 | 14ce26e7 | bellard | if (dflag == 2) { |
4703 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
|
4704 | e108dd01 | bellard | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); |
4705 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_QUAD, R_EDX); |
4706 | 14ce26e7 | bellard | } else
|
4707 | 14ce26e7 | bellard | #endif
|
4708 | e108dd01 | bellard | if (dflag == 1) { |
4709 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
4710 | e108dd01 | bellard | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4711 | e108dd01 | bellard | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); |
4712 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_LONG, R_EDX); |
4713 | e108dd01 | bellard | } else {
|
4714 | e108dd01 | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
|
4715 | e108dd01 | bellard | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4716 | e108dd01 | bellard | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); |
4717 | e108dd01 | bellard | gen_op_mov_reg_T0(OT_WORD, R_EDX); |
4718 | e108dd01 | bellard | } |
4719 | 2c0262af | bellard | break;
|
4720 | 2c0262af | bellard | case 0x1af: /* imul Gv, Ev */ |
4721 | 2c0262af | bellard | case 0x69: /* imul Gv, Ev, I */ |
4722 | 2c0262af | bellard | case 0x6b: |
4723 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4724 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4725 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4726 | 14ce26e7 | bellard | if (b == 0x69) |
4727 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
4728 | 14ce26e7 | bellard | else if (b == 0x6b) |
4729 | 14ce26e7 | bellard | s->rip_offset = 1;
|
4730 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
4731 | 2c0262af | bellard | if (b == 0x69) { |
4732 | 2c0262af | bellard | val = insn_get(s, ot); |
4733 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4734 | 2c0262af | bellard | } else if (b == 0x6b) { |
4735 | d64477af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
4736 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4737 | 2c0262af | bellard | } else {
|
4738 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4739 | 2c0262af | bellard | } |
4740 | 2c0262af | bellard | |
4741 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4742 | 14ce26e7 | bellard | if (ot == OT_QUAD) {
|
4743 | a7812ae4 | pbrook | gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]); |
4744 | 14ce26e7 | bellard | } else
|
4745 | 14ce26e7 | bellard | #endif
|
4746 | 2c0262af | bellard | if (ot == OT_LONG) {
|
4747 | 0211e5af | bellard | #ifdef TARGET_X86_64
|
4748 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
4749 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); |
4750 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4751 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4752 | 0211e5af | bellard | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
|
4753 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4754 | 0211e5af | bellard | #else
|
4755 | 0211e5af | bellard | { |
4756 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
4757 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
4758 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
4759 | 0211e5af | bellard | tcg_gen_ext_i32_i64(t0, cpu_T[0]);
|
4760 | 0211e5af | bellard | tcg_gen_ext_i32_i64(t1, cpu_T[1]);
|
4761 | 0211e5af | bellard | tcg_gen_mul_i64(t0, t0, t1); |
4762 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[0], t0);
|
4763 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4764 | 0211e5af | bellard | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); |
4765 | 0211e5af | bellard | tcg_gen_shri_i64(t0, t0, 32);
|
4766 | 0211e5af | bellard | tcg_gen_trunc_i64_i32(cpu_T[1], t0);
|
4767 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
|
4768 | 0211e5af | bellard | } |
4769 | 0211e5af | bellard | #endif
|
4770 | 2c0262af | bellard | } else {
|
4771 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4772 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); |
4773 | 0211e5af | bellard | /* XXX: use 32 bit mul which could be faster */
|
4774 | 0211e5af | bellard | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
4775 | 0211e5af | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
4776 | 0211e5af | bellard | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
|
4777 | 0211e5af | bellard | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
|
4778 | 2c0262af | bellard | } |
4779 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
4780 | d36cd60e | bellard | s->cc_op = CC_OP_MULB + ot; |
4781 | 2c0262af | bellard | break;
|
4782 | 2c0262af | bellard | case 0x1c0: |
4783 | 2c0262af | bellard | case 0x1c1: /* xadd Ev, Gv */ |
4784 | 2c0262af | bellard | if ((b & 1) == 0) |
4785 | 2c0262af | bellard | ot = OT_BYTE; |
4786 | 2c0262af | bellard | else
|
4787 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4788 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4789 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4790 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4791 | 2c0262af | bellard | if (mod == 3) { |
4792 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4793 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4794 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
4795 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
4796 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4797 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4798 | 2c0262af | bellard | } else {
|
4799 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4800 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4801 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4802 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
4803 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4804 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4805 | 2c0262af | bellard | } |
4806 | 2c0262af | bellard | gen_op_update2_cc(); |
4807 | 2c0262af | bellard | s->cc_op = CC_OP_ADDB + ot; |
4808 | 2c0262af | bellard | break;
|
4809 | 2c0262af | bellard | case 0x1b0: |
4810 | 2c0262af | bellard | case 0x1b1: /* cmpxchg Ev, Gv */ |
4811 | cad3a37d | bellard | { |
4812 | 1130328e | bellard | int label1, label2;
|
4813 | 1e4840bf | bellard | TCGv t0, t1, t2, a0; |
4814 | cad3a37d | bellard | |
4815 | cad3a37d | bellard | if ((b & 1) == 0) |
4816 | cad3a37d | bellard | ot = OT_BYTE; |
4817 | cad3a37d | bellard | else
|
4818 | cad3a37d | bellard | ot = dflag + OT_WORD; |
4819 | cad3a37d | bellard | modrm = ldub_code(s->pc++); |
4820 | cad3a37d | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4821 | cad3a37d | bellard | mod = (modrm >> 6) & 3; |
4822 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
4823 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
4824 | a7812ae4 | pbrook | t2 = tcg_temp_local_new(); |
4825 | a7812ae4 | pbrook | a0 = tcg_temp_local_new(); |
4826 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t1, reg); |
4827 | cad3a37d | bellard | if (mod == 3) { |
4828 | cad3a37d | bellard | rm = (modrm & 7) | REX_B(s);
|
4829 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t0, rm); |
4830 | cad3a37d | bellard | } else {
|
4831 | cad3a37d | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4832 | 1e4840bf | bellard | tcg_gen_mov_tl(a0, cpu_A0); |
4833 | 1e4840bf | bellard | gen_op_ld_v(ot + s->mem_index, t0, a0); |
4834 | cad3a37d | bellard | rm = 0; /* avoid warning */ |
4835 | cad3a37d | bellard | } |
4836 | cad3a37d | bellard | label1 = gen_new_label(); |
4837 | 1e4840bf | bellard | tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX])); |
4838 | 1e4840bf | bellard | tcg_gen_sub_tl(t2, t2, t0); |
4839 | 1e4840bf | bellard | gen_extu(ot, t2); |
4840 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
|
4841 | cad3a37d | bellard | if (mod == 3) { |
4842 | 1130328e | bellard | label2 = gen_new_label(); |
4843 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, R_EAX, t0); |
4844 | 1130328e | bellard | tcg_gen_br(label2); |
4845 | 1130328e | bellard | gen_set_label(label1); |
4846 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, rm, t1); |
4847 | 1130328e | bellard | gen_set_label(label2); |
4848 | cad3a37d | bellard | } else {
|
4849 | 1e4840bf | bellard | tcg_gen_mov_tl(t1, t0); |
4850 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, R_EAX, t0); |
4851 | 1130328e | bellard | gen_set_label(label1); |
4852 | 1130328e | bellard | /* always store */
|
4853 | 1e4840bf | bellard | gen_op_st_v(ot + s->mem_index, t1, a0); |
4854 | cad3a37d | bellard | } |
4855 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_src, t0); |
4856 | 1e4840bf | bellard | tcg_gen_mov_tl(cpu_cc_dst, t2); |
4857 | cad3a37d | bellard | s->cc_op = CC_OP_SUBB + ot; |
4858 | 1e4840bf | bellard | tcg_temp_free(t0); |
4859 | 1e4840bf | bellard | tcg_temp_free(t1); |
4860 | 1e4840bf | bellard | tcg_temp_free(t2); |
4861 | 1e4840bf | bellard | tcg_temp_free(a0); |
4862 | 2c0262af | bellard | } |
4863 | 2c0262af | bellard | break;
|
4864 | 2c0262af | bellard | case 0x1c7: /* cmpxchg8b */ |
4865 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4866 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4867 | 71c3558e | balrog | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
4868 | 2c0262af | bellard | goto illegal_op;
|
4869 | 1b9d9ebb | bellard | #ifdef TARGET_X86_64
|
4870 | 1b9d9ebb | bellard | if (dflag == 2) { |
4871 | 1b9d9ebb | bellard | if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
|
4872 | 1b9d9ebb | bellard | goto illegal_op;
|
4873 | 1b9d9ebb | bellard | gen_jmp_im(pc_start - s->cs_base); |
4874 | 1b9d9ebb | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4875 | 1b9d9ebb | bellard | gen_op_set_cc_op(s->cc_op); |
4876 | 1b9d9ebb | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4877 | a7812ae4 | pbrook | gen_helper_cmpxchg16b(cpu_A0); |
4878 | 1b9d9ebb | bellard | } else
|
4879 | 1b9d9ebb | bellard | #endif
|
4880 | 1b9d9ebb | bellard | { |
4881 | 1b9d9ebb | bellard | if (!(s->cpuid_features & CPUID_CX8))
|
4882 | 1b9d9ebb | bellard | goto illegal_op;
|
4883 | 1b9d9ebb | bellard | gen_jmp_im(pc_start - s->cs_base); |
4884 | 1b9d9ebb | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4885 | 1b9d9ebb | bellard | gen_op_set_cc_op(s->cc_op); |
4886 | 1b9d9ebb | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4887 | a7812ae4 | pbrook | gen_helper_cmpxchg8b(cpu_A0); |
4888 | 1b9d9ebb | bellard | } |
4889 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
4890 | 2c0262af | bellard | break;
|
4891 | 3b46e624 | ths | |
4892 | 2c0262af | bellard | /**************************/
|
4893 | 2c0262af | bellard | /* push/pop */
|
4894 | 2c0262af | bellard | case 0x50 ... 0x57: /* push */ |
4895 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
4896 | 2c0262af | bellard | gen_push_T0(s); |
4897 | 2c0262af | bellard | break;
|
4898 | 2c0262af | bellard | case 0x58 ... 0x5f: /* pop */ |
4899 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4900 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4901 | 14ce26e7 | bellard | } else {
|
4902 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4903 | 14ce26e7 | bellard | } |
4904 | 2c0262af | bellard | gen_pop_T0(s); |
4905 | 77729c24 | bellard | /* NOTE: order is important for pop %sp */
|
4906 | 2c0262af | bellard | gen_pop_update(s); |
4907 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
|
4908 | 2c0262af | bellard | break;
|
4909 | 2c0262af | bellard | case 0x60: /* pusha */ |
4910 | 14ce26e7 | bellard | if (CODE64(s))
|
4911 | 14ce26e7 | bellard | goto illegal_op;
|
4912 | 2c0262af | bellard | gen_pusha(s); |
4913 | 2c0262af | bellard | break;
|
4914 | 2c0262af | bellard | case 0x61: /* popa */ |
4915 | 14ce26e7 | bellard | if (CODE64(s))
|
4916 | 14ce26e7 | bellard | goto illegal_op;
|
4917 | 2c0262af | bellard | gen_popa(s); |
4918 | 2c0262af | bellard | break;
|
4919 | 2c0262af | bellard | case 0x68: /* push Iv */ |
4920 | 2c0262af | bellard | case 0x6a: |
4921 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4922 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4923 | 14ce26e7 | bellard | } else {
|
4924 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4925 | 14ce26e7 | bellard | } |
4926 | 2c0262af | bellard | if (b == 0x68) |
4927 | 2c0262af | bellard | val = insn_get(s, ot); |
4928 | 2c0262af | bellard | else
|
4929 | 2c0262af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
4930 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
4931 | 2c0262af | bellard | gen_push_T0(s); |
4932 | 2c0262af | bellard | break;
|
4933 | 2c0262af | bellard | case 0x8f: /* pop Ev */ |
4934 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4935 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4936 | 14ce26e7 | bellard | } else {
|
4937 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4938 | 14ce26e7 | bellard | } |
4939 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4940 | 77729c24 | bellard | mod = (modrm >> 6) & 3; |
4941 | 2c0262af | bellard | gen_pop_T0(s); |
4942 | 77729c24 | bellard | if (mod == 3) { |
4943 | 77729c24 | bellard | /* NOTE: order is important for pop %sp */
|
4944 | 77729c24 | bellard | gen_pop_update(s); |
4945 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4946 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4947 | 77729c24 | bellard | } else {
|
4948 | 77729c24 | bellard | /* NOTE: order is important too for MMU exceptions */
|
4949 | 14ce26e7 | bellard | s->popl_esp_hack = 1 << ot;
|
4950 | 77729c24 | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
4951 | 77729c24 | bellard | s->popl_esp_hack = 0;
|
4952 | 77729c24 | bellard | gen_pop_update(s); |
4953 | 77729c24 | bellard | } |
4954 | 2c0262af | bellard | break;
|
4955 | 2c0262af | bellard | case 0xc8: /* enter */ |
4956 | 2c0262af | bellard | { |
4957 | 2c0262af | bellard | int level;
|
4958 | 61382a50 | bellard | val = lduw_code(s->pc); |
4959 | 2c0262af | bellard | s->pc += 2;
|
4960 | 61382a50 | bellard | level = ldub_code(s->pc++); |
4961 | 2c0262af | bellard | gen_enter(s, val, level); |
4962 | 2c0262af | bellard | } |
4963 | 2c0262af | bellard | break;
|
4964 | 2c0262af | bellard | case 0xc9: /* leave */ |
4965 | 2c0262af | bellard | /* XXX: exception not precise (ESP is updated before potential exception) */
|
4966 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4967 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
|
4968 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, R_ESP); |
4969 | 14ce26e7 | bellard | } else if (s->ss32) { |
4970 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
4971 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, R_ESP); |
4972 | 2c0262af | bellard | } else {
|
4973 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
|
4974 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_WORD, R_ESP); |
4975 | 2c0262af | bellard | } |
4976 | 2c0262af | bellard | gen_pop_T0(s); |
4977 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4978 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4979 | 14ce26e7 | bellard | } else {
|
4980 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4981 | 14ce26e7 | bellard | } |
4982 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EBP); |
4983 | 2c0262af | bellard | gen_pop_update(s); |
4984 | 2c0262af | bellard | break;
|
4985 | 2c0262af | bellard | case 0x06: /* push es */ |
4986 | 2c0262af | bellard | case 0x0e: /* push cs */ |
4987 | 2c0262af | bellard | case 0x16: /* push ss */ |
4988 | 2c0262af | bellard | case 0x1e: /* push ds */ |
4989 | 14ce26e7 | bellard | if (CODE64(s))
|
4990 | 14ce26e7 | bellard | goto illegal_op;
|
4991 | 2c0262af | bellard | gen_op_movl_T0_seg(b >> 3);
|
4992 | 2c0262af | bellard | gen_push_T0(s); |
4993 | 2c0262af | bellard | break;
|
4994 | 2c0262af | bellard | case 0x1a0: /* push fs */ |
4995 | 2c0262af | bellard | case 0x1a8: /* push gs */ |
4996 | 2c0262af | bellard | gen_op_movl_T0_seg((b >> 3) & 7); |
4997 | 2c0262af | bellard | gen_push_T0(s); |
4998 | 2c0262af | bellard | break;
|
4999 | 2c0262af | bellard | case 0x07: /* pop es */ |
5000 | 2c0262af | bellard | case 0x17: /* pop ss */ |
5001 | 2c0262af | bellard | case 0x1f: /* pop ds */ |
5002 | 14ce26e7 | bellard | if (CODE64(s))
|
5003 | 14ce26e7 | bellard | goto illegal_op;
|
5004 | 2c0262af | bellard | reg = b >> 3;
|
5005 | 2c0262af | bellard | gen_pop_T0(s); |
5006 | 2c0262af | bellard | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5007 | 2c0262af | bellard | gen_pop_update(s); |
5008 | 2c0262af | bellard | if (reg == R_SS) {
|
5009 | a2cc3b24 | bellard | /* if reg == SS, inhibit interrupts/trace. */
|
5010 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
5011 | a2cc3b24 | bellard | _first_ does it */
|
5012 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
5013 | a7812ae4 | pbrook | gen_helper_set_inhibit_irq(); |
5014 | 2c0262af | bellard | s->tf = 0;
|
5015 | 2c0262af | bellard | } |
5016 | 2c0262af | bellard | if (s->is_jmp) {
|
5017 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5018 | 2c0262af | bellard | gen_eob(s); |
5019 | 2c0262af | bellard | } |
5020 | 2c0262af | bellard | break;
|
5021 | 2c0262af | bellard | case 0x1a1: /* pop fs */ |
5022 | 2c0262af | bellard | case 0x1a9: /* pop gs */ |
5023 | 2c0262af | bellard | gen_pop_T0(s); |
5024 | 2c0262af | bellard | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); |
5025 | 2c0262af | bellard | gen_pop_update(s); |
5026 | 2c0262af | bellard | if (s->is_jmp) {
|
5027 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5028 | 2c0262af | bellard | gen_eob(s); |
5029 | 2c0262af | bellard | } |
5030 | 2c0262af | bellard | break;
|
5031 | 2c0262af | bellard | |
5032 | 2c0262af | bellard | /**************************/
|
5033 | 2c0262af | bellard | /* mov */
|
5034 | 2c0262af | bellard | case 0x88: |
5035 | 2c0262af | bellard | case 0x89: /* mov Gv, Ev */ |
5036 | 2c0262af | bellard | if ((b & 1) == 0) |
5037 | 2c0262af | bellard | ot = OT_BYTE; |
5038 | 2c0262af | bellard | else
|
5039 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5040 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5041 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5042 | 3b46e624 | ths | |
5043 | 2c0262af | bellard | /* generate a generic store */
|
5044 | 14ce26e7 | bellard | gen_ldst_modrm(s, modrm, ot, reg, 1);
|
5045 | 2c0262af | bellard | break;
|
5046 | 2c0262af | bellard | case 0xc6: |
5047 | 2c0262af | bellard | case 0xc7: /* mov Ev, Iv */ |
5048 | 2c0262af | bellard | if ((b & 1) == 0) |
5049 | 2c0262af | bellard | ot = OT_BYTE; |
5050 | 2c0262af | bellard | else
|
5051 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5052 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5053 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5054 | 14ce26e7 | bellard | if (mod != 3) { |
5055 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
5056 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5057 | 14ce26e7 | bellard | } |
5058 | 2c0262af | bellard | val = insn_get(s, ot); |
5059 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
5060 | 2c0262af | bellard | if (mod != 3) |
5061 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
5062 | 2c0262af | bellard | else
|
5063 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
|
5064 | 2c0262af | bellard | break;
|
5065 | 2c0262af | bellard | case 0x8a: |
5066 | 2c0262af | bellard | case 0x8b: /* mov Ev, Gv */ |
5067 | 2c0262af | bellard | if ((b & 1) == 0) |
5068 | 2c0262af | bellard | ot = OT_BYTE; |
5069 | 2c0262af | bellard | else
|
5070 | 14ce26e7 | bellard | ot = OT_WORD + dflag; |
5071 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5072 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5073 | 3b46e624 | ths | |
5074 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
5075 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
5076 | 2c0262af | bellard | break;
|
5077 | 2c0262af | bellard | case 0x8e: /* mov seg, Gv */ |
5078 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5079 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
5080 | 2c0262af | bellard | if (reg >= 6 || reg == R_CS) |
5081 | 2c0262af | bellard | goto illegal_op;
|
5082 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
5083 | 2c0262af | bellard | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5084 | 2c0262af | bellard | if (reg == R_SS) {
|
5085 | 2c0262af | bellard | /* if reg == SS, inhibit interrupts/trace */
|
5086 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
5087 | a2cc3b24 | bellard | _first_ does it */
|
5088 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
5089 | a7812ae4 | pbrook | gen_helper_set_inhibit_irq(); |
5090 | 2c0262af | bellard | s->tf = 0;
|
5091 | 2c0262af | bellard | } |
5092 | 2c0262af | bellard | if (s->is_jmp) {
|
5093 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5094 | 2c0262af | bellard | gen_eob(s); |
5095 | 2c0262af | bellard | } |
5096 | 2c0262af | bellard | break;
|
5097 | 2c0262af | bellard | case 0x8c: /* mov Gv, seg */ |
5098 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5099 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
5100 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5101 | 2c0262af | bellard | if (reg >= 6) |
5102 | 2c0262af | bellard | goto illegal_op;
|
5103 | 2c0262af | bellard | gen_op_movl_T0_seg(reg); |
5104 | 14ce26e7 | bellard | if (mod == 3) |
5105 | 14ce26e7 | bellard | ot = OT_WORD + dflag; |
5106 | 14ce26e7 | bellard | else
|
5107 | 14ce26e7 | bellard | ot = OT_WORD; |
5108 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
5109 | 2c0262af | bellard | break;
|
5110 | 2c0262af | bellard | |
5111 | 2c0262af | bellard | case 0x1b6: /* movzbS Gv, Eb */ |
5112 | 2c0262af | bellard | case 0x1b7: /* movzwS Gv, Eb */ |
5113 | 2c0262af | bellard | case 0x1be: /* movsbS Gv, Eb */ |
5114 | 2c0262af | bellard | case 0x1bf: /* movswS Gv, Eb */ |
5115 | 2c0262af | bellard | { |
5116 | 2c0262af | bellard | int d_ot;
|
5117 | 2c0262af | bellard | /* d_ot is the size of destination */
|
5118 | 2c0262af | bellard | d_ot = dflag + OT_WORD; |
5119 | 2c0262af | bellard | /* ot is the size of source */
|
5120 | 2c0262af | bellard | ot = (b & 1) + OT_BYTE;
|
5121 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5122 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5123 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5124 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5125 | 3b46e624 | ths | |
5126 | 2c0262af | bellard | if (mod == 3) { |
5127 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
5128 | 2c0262af | bellard | switch(ot | (b & 8)) { |
5129 | 2c0262af | bellard | case OT_BYTE:
|
5130 | e108dd01 | bellard | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
5131 | 2c0262af | bellard | break;
|
5132 | 2c0262af | bellard | case OT_BYTE | 8: |
5133 | e108dd01 | bellard | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
5134 | 2c0262af | bellard | break;
|
5135 | 2c0262af | bellard | case OT_WORD:
|
5136 | e108dd01 | bellard | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
5137 | 2c0262af | bellard | break;
|
5138 | 2c0262af | bellard | default:
|
5139 | 2c0262af | bellard | case OT_WORD | 8: |
5140 | e108dd01 | bellard | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
5141 | 2c0262af | bellard | break;
|
5142 | 2c0262af | bellard | } |
5143 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
5144 | 2c0262af | bellard | } else {
|
5145 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5146 | 2c0262af | bellard | if (b & 8) { |
5147 | 57fec1fe | bellard | gen_op_lds_T0_A0(ot + s->mem_index); |
5148 | 2c0262af | bellard | } else {
|
5149 | 57fec1fe | bellard | gen_op_ldu_T0_A0(ot + s->mem_index); |
5150 | 2c0262af | bellard | } |
5151 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
5152 | 2c0262af | bellard | } |
5153 | 2c0262af | bellard | } |
5154 | 2c0262af | bellard | break;
|
5155 | 2c0262af | bellard | |
5156 | 2c0262af | bellard | case 0x8d: /* lea */ |
5157 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5158 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5159 | 3a1d9b8b | bellard | mod = (modrm >> 6) & 3; |
5160 | 3a1d9b8b | bellard | if (mod == 3) |
5161 | 3a1d9b8b | bellard | goto illegal_op;
|
5162 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5163 | 2c0262af | bellard | /* we must ensure that no segment is added */
|
5164 | 2c0262af | bellard | s->override = -1;
|
5165 | 2c0262af | bellard | val = s->addseg; |
5166 | 2c0262af | bellard | s->addseg = 0;
|
5167 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5168 | 2c0262af | bellard | s->addseg = val; |
5169 | 57fec1fe | bellard | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
5170 | 2c0262af | bellard | break;
|
5171 | 3b46e624 | ths | |
5172 | 2c0262af | bellard | case 0xa0: /* mov EAX, Ov */ |
5173 | 2c0262af | bellard | case 0xa1: |
5174 | 2c0262af | bellard | case 0xa2: /* mov Ov, EAX */ |
5175 | 2c0262af | bellard | case 0xa3: |
5176 | 2c0262af | bellard | { |
5177 | 14ce26e7 | bellard | target_ulong offset_addr; |
5178 | 14ce26e7 | bellard | |
5179 | 14ce26e7 | bellard | if ((b & 1) == 0) |
5180 | 14ce26e7 | bellard | ot = OT_BYTE; |
5181 | 14ce26e7 | bellard | else
|
5182 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5183 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
5184 | 8f091a59 | bellard | if (s->aflag == 2) { |
5185 | 14ce26e7 | bellard | offset_addr = ldq_code(s->pc); |
5186 | 14ce26e7 | bellard | s->pc += 8;
|
5187 | 57fec1fe | bellard | gen_op_movq_A0_im(offset_addr); |
5188 | 5fafdf24 | ths | } else
|
5189 | 14ce26e7 | bellard | #endif
|
5190 | 14ce26e7 | bellard | { |
5191 | 14ce26e7 | bellard | if (s->aflag) {
|
5192 | 14ce26e7 | bellard | offset_addr = insn_get(s, OT_LONG); |
5193 | 14ce26e7 | bellard | } else {
|
5194 | 14ce26e7 | bellard | offset_addr = insn_get(s, OT_WORD); |
5195 | 14ce26e7 | bellard | } |
5196 | 14ce26e7 | bellard | gen_op_movl_A0_im(offset_addr); |
5197 | 14ce26e7 | bellard | } |
5198 | 664e0f19 | bellard | gen_add_A0_ds_seg(s); |
5199 | 14ce26e7 | bellard | if ((b & 2) == 0) { |
5200 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
5201 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EAX); |
5202 | 14ce26e7 | bellard | } else {
|
5203 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, R_EAX);
|
5204 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
5205 | 2c0262af | bellard | } |
5206 | 2c0262af | bellard | } |
5207 | 2c0262af | bellard | break;
|
5208 | 2c0262af | bellard | case 0xd7: /* xlat */ |
5209 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
5210 | 8f091a59 | bellard | if (s->aflag == 2) { |
5211 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_EBX); |
5212 | bbf662ee | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
|
5213 | bbf662ee | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); |
5214 | bbf662ee | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
|
5215 | 5fafdf24 | ths | } else
|
5216 | 14ce26e7 | bellard | #endif
|
5217 | 14ce26e7 | bellard | { |
5218 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
5219 | bbf662ee | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
5220 | bbf662ee | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); |
5221 | bbf662ee | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
|
5222 | 14ce26e7 | bellard | if (s->aflag == 0) |
5223 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
5224 | bbf662ee | bellard | else
|
5225 | bbf662ee | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
5226 | 14ce26e7 | bellard | } |
5227 | 664e0f19 | bellard | gen_add_A0_ds_seg(s); |
5228 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5229 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, R_EAX); |
5230 | 2c0262af | bellard | break;
|
5231 | 2c0262af | bellard | case 0xb0 ... 0xb7: /* mov R, Ib */ |
5232 | 2c0262af | bellard | val = insn_get(s, OT_BYTE); |
5233 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
5234 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
|
5235 | 2c0262af | bellard | break;
|
5236 | 2c0262af | bellard | case 0xb8 ... 0xbf: /* mov R, Iv */ |
5237 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
5238 | 14ce26e7 | bellard | if (dflag == 2) { |
5239 | 14ce26e7 | bellard | uint64_t tmp; |
5240 | 14ce26e7 | bellard | /* 64 bit case */
|
5241 | 14ce26e7 | bellard | tmp = ldq_code(s->pc); |
5242 | 14ce26e7 | bellard | s->pc += 8;
|
5243 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
5244 | 14ce26e7 | bellard | gen_movtl_T0_im(tmp); |
5245 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, reg); |
5246 | 5fafdf24 | ths | } else
|
5247 | 14ce26e7 | bellard | #endif
|
5248 | 14ce26e7 | bellard | { |
5249 | 14ce26e7 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5250 | 14ce26e7 | bellard | val = insn_get(s, ot); |
5251 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
5252 | 14ce26e7 | bellard | gen_op_movl_T0_im(val); |
5253 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
5254 | 14ce26e7 | bellard | } |
5255 | 2c0262af | bellard | break;
|
5256 | 2c0262af | bellard | |
5257 | 2c0262af | bellard | case 0x91 ... 0x97: /* xchg R, EAX */ |
5258 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5259 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
5260 | 2c0262af | bellard | rm = R_EAX; |
5261 | 2c0262af | bellard | goto do_xchg_reg;
|
5262 | 2c0262af | bellard | case 0x86: |
5263 | 2c0262af | bellard | case 0x87: /* xchg Ev, Gv */ |
5264 | 2c0262af | bellard | if ((b & 1) == 0) |
5265 | 2c0262af | bellard | ot = OT_BYTE; |
5266 | 2c0262af | bellard | else
|
5267 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5268 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5269 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5270 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5271 | 2c0262af | bellard | if (mod == 3) { |
5272 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5273 | 2c0262af | bellard | do_xchg_reg:
|
5274 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
5275 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
5276 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
5277 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
5278 | 2c0262af | bellard | } else {
|
5279 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5280 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
5281 | 2c0262af | bellard | /* for xchg, lock is implicit */
|
5282 | 2c0262af | bellard | if (!(prefixes & PREFIX_LOCK))
|
5283 | a7812ae4 | pbrook | gen_helper_lock(); |
5284 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
5285 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
5286 | 2c0262af | bellard | if (!(prefixes & PREFIX_LOCK))
|
5287 | a7812ae4 | pbrook | gen_helper_unlock(); |
5288 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
5289 | 2c0262af | bellard | } |
5290 | 2c0262af | bellard | break;
|
5291 | 2c0262af | bellard | case 0xc4: /* les Gv */ |
5292 | 14ce26e7 | bellard | if (CODE64(s))
|
5293 | 14ce26e7 | bellard | goto illegal_op;
|
5294 | 2c0262af | bellard | op = R_ES; |
5295 | 2c0262af | bellard | goto do_lxx;
|
5296 | 2c0262af | bellard | case 0xc5: /* lds Gv */ |
5297 | 14ce26e7 | bellard | if (CODE64(s))
|
5298 | 14ce26e7 | bellard | goto illegal_op;
|
5299 | 2c0262af | bellard | op = R_DS; |
5300 | 2c0262af | bellard | goto do_lxx;
|
5301 | 2c0262af | bellard | case 0x1b2: /* lss Gv */ |
5302 | 2c0262af | bellard | op = R_SS; |
5303 | 2c0262af | bellard | goto do_lxx;
|
5304 | 2c0262af | bellard | case 0x1b4: /* lfs Gv */ |
5305 | 2c0262af | bellard | op = R_FS; |
5306 | 2c0262af | bellard | goto do_lxx;
|
5307 | 2c0262af | bellard | case 0x1b5: /* lgs Gv */ |
5308 | 2c0262af | bellard | op = R_GS; |
5309 | 2c0262af | bellard | do_lxx:
|
5310 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5311 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5312 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5313 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5314 | 2c0262af | bellard | if (mod == 3) |
5315 | 2c0262af | bellard | goto illegal_op;
|
5316 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5317 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
5318 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
5319 | 2c0262af | bellard | /* load the segment first to handle exceptions properly */
|
5320 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
5321 | 2c0262af | bellard | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5322 | 2c0262af | bellard | /* then put the data */
|
5323 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
5324 | 2c0262af | bellard | if (s->is_jmp) {
|
5325 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5326 | 2c0262af | bellard | gen_eob(s); |
5327 | 2c0262af | bellard | } |
5328 | 2c0262af | bellard | break;
|
5329 | 3b46e624 | ths | |
5330 | 2c0262af | bellard | /************************/
|
5331 | 2c0262af | bellard | /* shifts */
|
5332 | 2c0262af | bellard | case 0xc0: |
5333 | 2c0262af | bellard | case 0xc1: |
5334 | 2c0262af | bellard | /* shift Ev,Ib */
|
5335 | 2c0262af | bellard | shift = 2;
|
5336 | 2c0262af | bellard | grp2:
|
5337 | 2c0262af | bellard | { |
5338 | 2c0262af | bellard | if ((b & 1) == 0) |
5339 | 2c0262af | bellard | ot = OT_BYTE; |
5340 | 2c0262af | bellard | else
|
5341 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5342 | 3b46e624 | ths | |
5343 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5344 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5345 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
5346 | 3b46e624 | ths | |
5347 | 2c0262af | bellard | if (mod != 3) { |
5348 | 14ce26e7 | bellard | if (shift == 2) { |
5349 | 14ce26e7 | bellard | s->rip_offset = 1;
|
5350 | 14ce26e7 | bellard | } |
5351 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5352 | 2c0262af | bellard | opreg = OR_TMP0; |
5353 | 2c0262af | bellard | } else {
|
5354 | 14ce26e7 | bellard | opreg = (modrm & 7) | REX_B(s);
|
5355 | 2c0262af | bellard | } |
5356 | 2c0262af | bellard | |
5357 | 2c0262af | bellard | /* simpler op */
|
5358 | 2c0262af | bellard | if (shift == 0) { |
5359 | 2c0262af | bellard | gen_shift(s, op, ot, opreg, OR_ECX); |
5360 | 2c0262af | bellard | } else {
|
5361 | 2c0262af | bellard | if (shift == 2) { |
5362 | 61382a50 | bellard | shift = ldub_code(s->pc++); |
5363 | 2c0262af | bellard | } |
5364 | 2c0262af | bellard | gen_shifti(s, op, ot, opreg, shift); |
5365 | 2c0262af | bellard | } |
5366 | 2c0262af | bellard | } |
5367 | 2c0262af | bellard | break;
|
5368 | 2c0262af | bellard | case 0xd0: |
5369 | 2c0262af | bellard | case 0xd1: |
5370 | 2c0262af | bellard | /* shift Ev,1 */
|
5371 | 2c0262af | bellard | shift = 1;
|
5372 | 2c0262af | bellard | goto grp2;
|
5373 | 2c0262af | bellard | case 0xd2: |
5374 | 2c0262af | bellard | case 0xd3: |
5375 | 2c0262af | bellard | /* shift Ev,cl */
|
5376 | 2c0262af | bellard | shift = 0;
|
5377 | 2c0262af | bellard | goto grp2;
|
5378 | 2c0262af | bellard | |
5379 | 2c0262af | bellard | case 0x1a4: /* shld imm */ |
5380 | 2c0262af | bellard | op = 0;
|
5381 | 2c0262af | bellard | shift = 1;
|
5382 | 2c0262af | bellard | goto do_shiftd;
|
5383 | 2c0262af | bellard | case 0x1a5: /* shld cl */ |
5384 | 2c0262af | bellard | op = 0;
|
5385 | 2c0262af | bellard | shift = 0;
|
5386 | 2c0262af | bellard | goto do_shiftd;
|
5387 | 2c0262af | bellard | case 0x1ac: /* shrd imm */ |
5388 | 2c0262af | bellard | op = 1;
|
5389 | 2c0262af | bellard | shift = 1;
|
5390 | 2c0262af | bellard | goto do_shiftd;
|
5391 | 2c0262af | bellard | case 0x1ad: /* shrd cl */ |
5392 | 2c0262af | bellard | op = 1;
|
5393 | 2c0262af | bellard | shift = 0;
|
5394 | 2c0262af | bellard | do_shiftd:
|
5395 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5396 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5397 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5398 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5399 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5400 | 2c0262af | bellard | if (mod != 3) { |
5401 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5402 | b6abf97d | bellard | opreg = OR_TMP0; |
5403 | 2c0262af | bellard | } else {
|
5404 | b6abf97d | bellard | opreg = rm; |
5405 | 2c0262af | bellard | } |
5406 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
5407 | 3b46e624 | ths | |
5408 | 2c0262af | bellard | if (shift) {
|
5409 | 61382a50 | bellard | val = ldub_code(s->pc++); |
5410 | b6abf97d | bellard | tcg_gen_movi_tl(cpu_T3, val); |
5411 | 2c0262af | bellard | } else {
|
5412 | b6abf97d | bellard | tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX])); |
5413 | 2c0262af | bellard | } |
5414 | b6abf97d | bellard | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
5415 | 2c0262af | bellard | break;
|
5416 | 2c0262af | bellard | |
5417 | 2c0262af | bellard | /************************/
|
5418 | 2c0262af | bellard | /* floats */
|
5419 | 5fafdf24 | ths | case 0xd8 ... 0xdf: |
5420 | 7eee2a50 | bellard | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
|
5421 | 7eee2a50 | bellard | /* if CR0.EM or CR0.TS are set, generate an FPU exception */
|
5422 | 7eee2a50 | bellard | /* XXX: what to do if illegal op ? */
|
5423 | 7eee2a50 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
5424 | 7eee2a50 | bellard | break;
|
5425 | 7eee2a50 | bellard | } |
5426 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5427 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5428 | 2c0262af | bellard | rm = modrm & 7;
|
5429 | 2c0262af | bellard | op = ((b & 7) << 3) | ((modrm >> 3) & 7); |
5430 | 2c0262af | bellard | if (mod != 3) { |
5431 | 2c0262af | bellard | /* memory op */
|
5432 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5433 | 2c0262af | bellard | switch(op) {
|
5434 | 2c0262af | bellard | case 0x00 ... 0x07: /* fxxxs */ |
5435 | 2c0262af | bellard | case 0x10 ... 0x17: /* fixxxl */ |
5436 | 2c0262af | bellard | case 0x20 ... 0x27: /* fxxxl */ |
5437 | 2c0262af | bellard | case 0x30 ... 0x37: /* fixxx */ |
5438 | 2c0262af | bellard | { |
5439 | 2c0262af | bellard | int op1;
|
5440 | 2c0262af | bellard | op1 = op & 7;
|
5441 | 2c0262af | bellard | |
5442 | 2c0262af | bellard | switch(op >> 4) { |
5443 | 2c0262af | bellard | case 0: |
5444 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
5445 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5446 | a7812ae4 | pbrook | gen_helper_flds_FT0(cpu_tmp2_i32); |
5447 | 2c0262af | bellard | break;
|
5448 | 2c0262af | bellard | case 1: |
5449 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
5450 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5451 | a7812ae4 | pbrook | gen_helper_fildl_FT0(cpu_tmp2_i32); |
5452 | 2c0262af | bellard | break;
|
5453 | 2c0262af | bellard | case 2: |
5454 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
5455 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5456 | a7812ae4 | pbrook | gen_helper_fldl_FT0(cpu_tmp1_i64); |
5457 | 2c0262af | bellard | break;
|
5458 | 2c0262af | bellard | case 3: |
5459 | 2c0262af | bellard | default:
|
5460 | ba7cd150 | bellard | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
5461 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5462 | a7812ae4 | pbrook | gen_helper_fildl_FT0(cpu_tmp2_i32); |
5463 | 2c0262af | bellard | break;
|
5464 | 2c0262af | bellard | } |
5465 | 3b46e624 | ths | |
5466 | a7812ae4 | pbrook | gen_helper_fp_arith_ST0_FT0(op1); |
5467 | 2c0262af | bellard | if (op1 == 3) { |
5468 | 2c0262af | bellard | /* fcomp needs pop */
|
5469 | a7812ae4 | pbrook | gen_helper_fpop(); |
5470 | 2c0262af | bellard | } |
5471 | 2c0262af | bellard | } |
5472 | 2c0262af | bellard | break;
|
5473 | 2c0262af | bellard | case 0x08: /* flds */ |
5474 | 2c0262af | bellard | case 0x0a: /* fsts */ |
5475 | 2c0262af | bellard | case 0x0b: /* fstps */ |
5476 | 465e9838 | bellard | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5477 | 465e9838 | bellard | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ |
5478 | 465e9838 | bellard | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ |
5479 | 2c0262af | bellard | switch(op & 7) { |
5480 | 2c0262af | bellard | case 0: |
5481 | 2c0262af | bellard | switch(op >> 4) { |
5482 | 2c0262af | bellard | case 0: |
5483 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
5484 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5485 | a7812ae4 | pbrook | gen_helper_flds_ST0(cpu_tmp2_i32); |
5486 | 2c0262af | bellard | break;
|
5487 | 2c0262af | bellard | case 1: |
5488 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
5489 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5490 | a7812ae4 | pbrook | gen_helper_fildl_ST0(cpu_tmp2_i32); |
5491 | 2c0262af | bellard | break;
|
5492 | 2c0262af | bellard | case 2: |
5493 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
5494 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5495 | a7812ae4 | pbrook | gen_helper_fldl_ST0(cpu_tmp1_i64); |
5496 | 2c0262af | bellard | break;
|
5497 | 2c0262af | bellard | case 3: |
5498 | 2c0262af | bellard | default:
|
5499 | ba7cd150 | bellard | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
5500 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5501 | a7812ae4 | pbrook | gen_helper_fildl_ST0(cpu_tmp2_i32); |
5502 | 2c0262af | bellard | break;
|
5503 | 2c0262af | bellard | } |
5504 | 2c0262af | bellard | break;
|
5505 | 465e9838 | bellard | case 1: |
5506 | 19e6c4b8 | bellard | /* XXX: the corresponding CPUID bit must be tested ! */
|
5507 | 465e9838 | bellard | switch(op >> 4) { |
5508 | 465e9838 | bellard | case 1: |
5509 | a7812ae4 | pbrook | gen_helper_fisttl_ST0(cpu_tmp2_i32); |
5510 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5511 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
5512 | 465e9838 | bellard | break;
|
5513 | 465e9838 | bellard | case 2: |
5514 | a7812ae4 | pbrook | gen_helper_fisttll_ST0(cpu_tmp1_i64); |
5515 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
5516 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5517 | 465e9838 | bellard | break;
|
5518 | 465e9838 | bellard | case 3: |
5519 | 465e9838 | bellard | default:
|
5520 | a7812ae4 | pbrook | gen_helper_fistt_ST0(cpu_tmp2_i32); |
5521 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5522 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
5523 | 19e6c4b8 | bellard | break;
|
5524 | 465e9838 | bellard | } |
5525 | a7812ae4 | pbrook | gen_helper_fpop(); |
5526 | 465e9838 | bellard | break;
|
5527 | 2c0262af | bellard | default:
|
5528 | 2c0262af | bellard | switch(op >> 4) { |
5529 | 2c0262af | bellard | case 0: |
5530 | a7812ae4 | pbrook | gen_helper_fsts_ST0(cpu_tmp2_i32); |
5531 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5532 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
5533 | 2c0262af | bellard | break;
|
5534 | 2c0262af | bellard | case 1: |
5535 | a7812ae4 | pbrook | gen_helper_fistl_ST0(cpu_tmp2_i32); |
5536 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5537 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
5538 | 2c0262af | bellard | break;
|
5539 | 2c0262af | bellard | case 2: |
5540 | a7812ae4 | pbrook | gen_helper_fstl_ST0(cpu_tmp1_i64); |
5541 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
5542 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5543 | 2c0262af | bellard | break;
|
5544 | 2c0262af | bellard | case 3: |
5545 | 2c0262af | bellard | default:
|
5546 | a7812ae4 | pbrook | gen_helper_fist_ST0(cpu_tmp2_i32); |
5547 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5548 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
5549 | 2c0262af | bellard | break;
|
5550 | 2c0262af | bellard | } |
5551 | 2c0262af | bellard | if ((op & 7) == 3) |
5552 | a7812ae4 | pbrook | gen_helper_fpop(); |
5553 | 2c0262af | bellard | break;
|
5554 | 2c0262af | bellard | } |
5555 | 2c0262af | bellard | break;
|
5556 | 2c0262af | bellard | case 0x0c: /* fldenv mem */ |
5557 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5558 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5559 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5560 | a7812ae4 | pbrook | gen_helper_fldenv( |
5561 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32(s->dflag)); |
5562 | 2c0262af | bellard | break;
|
5563 | 2c0262af | bellard | case 0x0d: /* fldcw mem */ |
5564 | 19e6c4b8 | bellard | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
5565 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5566 | a7812ae4 | pbrook | gen_helper_fldcw(cpu_tmp2_i32); |
5567 | 2c0262af | bellard | break;
|
5568 | 2c0262af | bellard | case 0x0e: /* fnstenv mem */ |
5569 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5570 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5571 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5572 | a7812ae4 | pbrook | gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag)); |
5573 | 2c0262af | bellard | break;
|
5574 | 2c0262af | bellard | case 0x0f: /* fnstcw mem */ |
5575 | a7812ae4 | pbrook | gen_helper_fnstcw(cpu_tmp2_i32); |
5576 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5577 | 19e6c4b8 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
5578 | 2c0262af | bellard | break;
|
5579 | 2c0262af | bellard | case 0x1d: /* fldt mem */ |
5580 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5581 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5582 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5583 | a7812ae4 | pbrook | gen_helper_fldt_ST0(cpu_A0); |
5584 | 2c0262af | bellard | break;
|
5585 | 2c0262af | bellard | case 0x1f: /* fstpt mem */ |
5586 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5587 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5588 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5589 | a7812ae4 | pbrook | gen_helper_fstt_ST0(cpu_A0); |
5590 | a7812ae4 | pbrook | gen_helper_fpop(); |
5591 | 2c0262af | bellard | break;
|
5592 | 2c0262af | bellard | case 0x2c: /* frstor mem */ |
5593 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5594 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5595 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5596 | a7812ae4 | pbrook | gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag)); |
5597 | 2c0262af | bellard | break;
|
5598 | 2c0262af | bellard | case 0x2e: /* fnsave mem */ |
5599 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5600 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5601 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5602 | a7812ae4 | pbrook | gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag)); |
5603 | 2c0262af | bellard | break;
|
5604 | 2c0262af | bellard | case 0x2f: /* fnstsw mem */ |
5605 | a7812ae4 | pbrook | gen_helper_fnstsw(cpu_tmp2_i32); |
5606 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5607 | 19e6c4b8 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
5608 | 2c0262af | bellard | break;
|
5609 | 2c0262af | bellard | case 0x3c: /* fbld */ |
5610 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5611 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5612 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5613 | a7812ae4 | pbrook | gen_helper_fbld_ST0(cpu_A0); |
5614 | 2c0262af | bellard | break;
|
5615 | 2c0262af | bellard | case 0x3e: /* fbstp */ |
5616 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5617 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
5618 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5619 | a7812ae4 | pbrook | gen_helper_fbst_ST0(cpu_A0); |
5620 | a7812ae4 | pbrook | gen_helper_fpop(); |
5621 | 2c0262af | bellard | break;
|
5622 | 2c0262af | bellard | case 0x3d: /* fildll */ |
5623 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
5624 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5625 | a7812ae4 | pbrook | gen_helper_fildll_ST0(cpu_tmp1_i64); |
5626 | 2c0262af | bellard | break;
|
5627 | 2c0262af | bellard | case 0x3f: /* fistpll */ |
5628 | a7812ae4 | pbrook | gen_helper_fistll_ST0(cpu_tmp1_i64); |
5629 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
5630 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
5631 | a7812ae4 | pbrook | gen_helper_fpop(); |
5632 | 2c0262af | bellard | break;
|
5633 | 2c0262af | bellard | default:
|
5634 | 2c0262af | bellard | goto illegal_op;
|
5635 | 2c0262af | bellard | } |
5636 | 2c0262af | bellard | } else {
|
5637 | 2c0262af | bellard | /* register float ops */
|
5638 | 2c0262af | bellard | opreg = rm; |
5639 | 2c0262af | bellard | |
5640 | 2c0262af | bellard | switch(op) {
|
5641 | 2c0262af | bellard | case 0x08: /* fld sti */ |
5642 | a7812ae4 | pbrook | gen_helper_fpush(); |
5643 | a7812ae4 | pbrook | gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7)); |
5644 | 2c0262af | bellard | break;
|
5645 | 2c0262af | bellard | case 0x09: /* fxchg sti */ |
5646 | c169c906 | bellard | case 0x29: /* fxchg4 sti, undocumented op */ |
5647 | c169c906 | bellard | case 0x39: /* fxchg7 sti, undocumented op */ |
5648 | a7812ae4 | pbrook | gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg)); |
5649 | 2c0262af | bellard | break;
|
5650 | 2c0262af | bellard | case 0x0a: /* grp d9/2 */ |
5651 | 2c0262af | bellard | switch(rm) {
|
5652 | 2c0262af | bellard | case 0: /* fnop */ |
5653 | 023fe10d | bellard | /* check exceptions (FreeBSD FPU probe) */
|
5654 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5655 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
5656 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5657 | a7812ae4 | pbrook | gen_helper_fwait(); |
5658 | 2c0262af | bellard | break;
|
5659 | 2c0262af | bellard | default:
|
5660 | 2c0262af | bellard | goto illegal_op;
|
5661 | 2c0262af | bellard | } |
5662 | 2c0262af | bellard | break;
|
5663 | 2c0262af | bellard | case 0x0c: /* grp d9/4 */ |
5664 | 2c0262af | bellard | switch(rm) {
|
5665 | 2c0262af | bellard | case 0: /* fchs */ |
5666 | a7812ae4 | pbrook | gen_helper_fchs_ST0(); |
5667 | 2c0262af | bellard | break;
|
5668 | 2c0262af | bellard | case 1: /* fabs */ |
5669 | a7812ae4 | pbrook | gen_helper_fabs_ST0(); |
5670 | 2c0262af | bellard | break;
|
5671 | 2c0262af | bellard | case 4: /* ftst */ |
5672 | a7812ae4 | pbrook | gen_helper_fldz_FT0(); |
5673 | a7812ae4 | pbrook | gen_helper_fcom_ST0_FT0(); |
5674 | 2c0262af | bellard | break;
|
5675 | 2c0262af | bellard | case 5: /* fxam */ |
5676 | a7812ae4 | pbrook | gen_helper_fxam_ST0(); |
5677 | 2c0262af | bellard | break;
|
5678 | 2c0262af | bellard | default:
|
5679 | 2c0262af | bellard | goto illegal_op;
|
5680 | 2c0262af | bellard | } |
5681 | 2c0262af | bellard | break;
|
5682 | 2c0262af | bellard | case 0x0d: /* grp d9/5 */ |
5683 | 2c0262af | bellard | { |
5684 | 2c0262af | bellard | switch(rm) {
|
5685 | 2c0262af | bellard | case 0: |
5686 | a7812ae4 | pbrook | gen_helper_fpush(); |
5687 | a7812ae4 | pbrook | gen_helper_fld1_ST0(); |
5688 | 2c0262af | bellard | break;
|
5689 | 2c0262af | bellard | case 1: |
5690 | a7812ae4 | pbrook | gen_helper_fpush(); |
5691 | a7812ae4 | pbrook | gen_helper_fldl2t_ST0(); |
5692 | 2c0262af | bellard | break;
|
5693 | 2c0262af | bellard | case 2: |
5694 | a7812ae4 | pbrook | gen_helper_fpush(); |
5695 | a7812ae4 | pbrook | gen_helper_fldl2e_ST0(); |
5696 | 2c0262af | bellard | break;
|
5697 | 2c0262af | bellard | case 3: |
5698 | a7812ae4 | pbrook | gen_helper_fpush(); |
5699 | a7812ae4 | pbrook | gen_helper_fldpi_ST0(); |
5700 | 2c0262af | bellard | break;
|
5701 | 2c0262af | bellard | case 4: |
5702 | a7812ae4 | pbrook | gen_helper_fpush(); |
5703 | a7812ae4 | pbrook | gen_helper_fldlg2_ST0(); |
5704 | 2c0262af | bellard | break;
|
5705 | 2c0262af | bellard | case 5: |
5706 | a7812ae4 | pbrook | gen_helper_fpush(); |
5707 | a7812ae4 | pbrook | gen_helper_fldln2_ST0(); |
5708 | 2c0262af | bellard | break;
|
5709 | 2c0262af | bellard | case 6: |
5710 | a7812ae4 | pbrook | gen_helper_fpush(); |
5711 | a7812ae4 | pbrook | gen_helper_fldz_ST0(); |
5712 | 2c0262af | bellard | break;
|
5713 | 2c0262af | bellard | default:
|
5714 | 2c0262af | bellard | goto illegal_op;
|
5715 | 2c0262af | bellard | } |
5716 | 2c0262af | bellard | } |
5717 | 2c0262af | bellard | break;
|
5718 | 2c0262af | bellard | case 0x0e: /* grp d9/6 */ |
5719 | 2c0262af | bellard | switch(rm) {
|
5720 | 2c0262af | bellard | case 0: /* f2xm1 */ |
5721 | a7812ae4 | pbrook | gen_helper_f2xm1(); |
5722 | 2c0262af | bellard | break;
|
5723 | 2c0262af | bellard | case 1: /* fyl2x */ |
5724 | a7812ae4 | pbrook | gen_helper_fyl2x(); |
5725 | 2c0262af | bellard | break;
|
5726 | 2c0262af | bellard | case 2: /* fptan */ |
5727 | a7812ae4 | pbrook | gen_helper_fptan(); |
5728 | 2c0262af | bellard | break;
|
5729 | 2c0262af | bellard | case 3: /* fpatan */ |
5730 | a7812ae4 | pbrook | gen_helper_fpatan(); |
5731 | 2c0262af | bellard | break;
|
5732 | 2c0262af | bellard | case 4: /* fxtract */ |
5733 | a7812ae4 | pbrook | gen_helper_fxtract(); |
5734 | 2c0262af | bellard | break;
|
5735 | 2c0262af | bellard | case 5: /* fprem1 */ |
5736 | a7812ae4 | pbrook | gen_helper_fprem1(); |
5737 | 2c0262af | bellard | break;
|
5738 | 2c0262af | bellard | case 6: /* fdecstp */ |
5739 | a7812ae4 | pbrook | gen_helper_fdecstp(); |
5740 | 2c0262af | bellard | break;
|
5741 | 2c0262af | bellard | default:
|
5742 | 2c0262af | bellard | case 7: /* fincstp */ |
5743 | a7812ae4 | pbrook | gen_helper_fincstp(); |
5744 | 2c0262af | bellard | break;
|
5745 | 2c0262af | bellard | } |
5746 | 2c0262af | bellard | break;
|
5747 | 2c0262af | bellard | case 0x0f: /* grp d9/7 */ |
5748 | 2c0262af | bellard | switch(rm) {
|
5749 | 2c0262af | bellard | case 0: /* fprem */ |
5750 | a7812ae4 | pbrook | gen_helper_fprem(); |
5751 | 2c0262af | bellard | break;
|
5752 | 2c0262af | bellard | case 1: /* fyl2xp1 */ |
5753 | a7812ae4 | pbrook | gen_helper_fyl2xp1(); |
5754 | 2c0262af | bellard | break;
|
5755 | 2c0262af | bellard | case 2: /* fsqrt */ |
5756 | a7812ae4 | pbrook | gen_helper_fsqrt(); |
5757 | 2c0262af | bellard | break;
|
5758 | 2c0262af | bellard | case 3: /* fsincos */ |
5759 | a7812ae4 | pbrook | gen_helper_fsincos(); |
5760 | 2c0262af | bellard | break;
|
5761 | 2c0262af | bellard | case 5: /* fscale */ |
5762 | a7812ae4 | pbrook | gen_helper_fscale(); |
5763 | 2c0262af | bellard | break;
|
5764 | 2c0262af | bellard | case 4: /* frndint */ |
5765 | a7812ae4 | pbrook | gen_helper_frndint(); |
5766 | 2c0262af | bellard | break;
|
5767 | 2c0262af | bellard | case 6: /* fsin */ |
5768 | a7812ae4 | pbrook | gen_helper_fsin(); |
5769 | 2c0262af | bellard | break;
|
5770 | 2c0262af | bellard | default:
|
5771 | 2c0262af | bellard | case 7: /* fcos */ |
5772 | a7812ae4 | pbrook | gen_helper_fcos(); |
5773 | 2c0262af | bellard | break;
|
5774 | 2c0262af | bellard | } |
5775 | 2c0262af | bellard | break;
|
5776 | 2c0262af | bellard | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ |
5777 | 2c0262af | bellard | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ |
5778 | 2c0262af | bellard | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ |
5779 | 2c0262af | bellard | { |
5780 | 2c0262af | bellard | int op1;
|
5781 | 3b46e624 | ths | |
5782 | 2c0262af | bellard | op1 = op & 7;
|
5783 | 2c0262af | bellard | if (op >= 0x20) { |
5784 | a7812ae4 | pbrook | gen_helper_fp_arith_STN_ST0(op1, opreg); |
5785 | 2c0262af | bellard | if (op >= 0x30) |
5786 | a7812ae4 | pbrook | gen_helper_fpop(); |
5787 | 2c0262af | bellard | } else {
|
5788 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5789 | a7812ae4 | pbrook | gen_helper_fp_arith_ST0_FT0(op1); |
5790 | 2c0262af | bellard | } |
5791 | 2c0262af | bellard | } |
5792 | 2c0262af | bellard | break;
|
5793 | 2c0262af | bellard | case 0x02: /* fcom */ |
5794 | c169c906 | bellard | case 0x22: /* fcom2, undocumented op */ |
5795 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5796 | a7812ae4 | pbrook | gen_helper_fcom_ST0_FT0(); |
5797 | 2c0262af | bellard | break;
|
5798 | 2c0262af | bellard | case 0x03: /* fcomp */ |
5799 | c169c906 | bellard | case 0x23: /* fcomp3, undocumented op */ |
5800 | c169c906 | bellard | case 0x32: /* fcomp5, undocumented op */ |
5801 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5802 | a7812ae4 | pbrook | gen_helper_fcom_ST0_FT0(); |
5803 | a7812ae4 | pbrook | gen_helper_fpop(); |
5804 | 2c0262af | bellard | break;
|
5805 | 2c0262af | bellard | case 0x15: /* da/5 */ |
5806 | 2c0262af | bellard | switch(rm) {
|
5807 | 2c0262af | bellard | case 1: /* fucompp */ |
5808 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(1));
|
5809 | a7812ae4 | pbrook | gen_helper_fucom_ST0_FT0(); |
5810 | a7812ae4 | pbrook | gen_helper_fpop(); |
5811 | a7812ae4 | pbrook | gen_helper_fpop(); |
5812 | 2c0262af | bellard | break;
|
5813 | 2c0262af | bellard | default:
|
5814 | 2c0262af | bellard | goto illegal_op;
|
5815 | 2c0262af | bellard | } |
5816 | 2c0262af | bellard | break;
|
5817 | 2c0262af | bellard | case 0x1c: |
5818 | 2c0262af | bellard | switch(rm) {
|
5819 | 2c0262af | bellard | case 0: /* feni (287 only, just do nop here) */ |
5820 | 2c0262af | bellard | break;
|
5821 | 2c0262af | bellard | case 1: /* fdisi (287 only, just do nop here) */ |
5822 | 2c0262af | bellard | break;
|
5823 | 2c0262af | bellard | case 2: /* fclex */ |
5824 | a7812ae4 | pbrook | gen_helper_fclex(); |
5825 | 2c0262af | bellard | break;
|
5826 | 2c0262af | bellard | case 3: /* fninit */ |
5827 | a7812ae4 | pbrook | gen_helper_fninit(); |
5828 | 2c0262af | bellard | break;
|
5829 | 2c0262af | bellard | case 4: /* fsetpm (287 only, just do nop here) */ |
5830 | 2c0262af | bellard | break;
|
5831 | 2c0262af | bellard | default:
|
5832 | 2c0262af | bellard | goto illegal_op;
|
5833 | 2c0262af | bellard | } |
5834 | 2c0262af | bellard | break;
|
5835 | 2c0262af | bellard | case 0x1d: /* fucomi */ |
5836 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5837 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5838 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5839 | a7812ae4 | pbrook | gen_helper_fucomi_ST0_FT0(); |
5840 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5841 | 2c0262af | bellard | break;
|
5842 | 2c0262af | bellard | case 0x1e: /* fcomi */ |
5843 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5844 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5845 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5846 | a7812ae4 | pbrook | gen_helper_fcomi_ST0_FT0(); |
5847 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5848 | 2c0262af | bellard | break;
|
5849 | 658c8bda | bellard | case 0x28: /* ffree sti */ |
5850 | a7812ae4 | pbrook | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5851 | 5fafdf24 | ths | break;
|
5852 | 2c0262af | bellard | case 0x2a: /* fst sti */ |
5853 | a7812ae4 | pbrook | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
5854 | 2c0262af | bellard | break;
|
5855 | 2c0262af | bellard | case 0x2b: /* fstp sti */ |
5856 | c169c906 | bellard | case 0x0b: /* fstp1 sti, undocumented op */ |
5857 | c169c906 | bellard | case 0x3a: /* fstp8 sti, undocumented op */ |
5858 | c169c906 | bellard | case 0x3b: /* fstp9 sti, undocumented op */ |
5859 | a7812ae4 | pbrook | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
5860 | a7812ae4 | pbrook | gen_helper_fpop(); |
5861 | 2c0262af | bellard | break;
|
5862 | 2c0262af | bellard | case 0x2c: /* fucom st(i) */ |
5863 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5864 | a7812ae4 | pbrook | gen_helper_fucom_ST0_FT0(); |
5865 | 2c0262af | bellard | break;
|
5866 | 2c0262af | bellard | case 0x2d: /* fucomp st(i) */ |
5867 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5868 | a7812ae4 | pbrook | gen_helper_fucom_ST0_FT0(); |
5869 | a7812ae4 | pbrook | gen_helper_fpop(); |
5870 | 2c0262af | bellard | break;
|
5871 | 2c0262af | bellard | case 0x33: /* de/3 */ |
5872 | 2c0262af | bellard | switch(rm) {
|
5873 | 2c0262af | bellard | case 1: /* fcompp */ |
5874 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(1));
|
5875 | a7812ae4 | pbrook | gen_helper_fcom_ST0_FT0(); |
5876 | a7812ae4 | pbrook | gen_helper_fpop(); |
5877 | a7812ae4 | pbrook | gen_helper_fpop(); |
5878 | 2c0262af | bellard | break;
|
5879 | 2c0262af | bellard | default:
|
5880 | 2c0262af | bellard | goto illegal_op;
|
5881 | 2c0262af | bellard | } |
5882 | 2c0262af | bellard | break;
|
5883 | c169c906 | bellard | case 0x38: /* ffreep sti, undocumented op */ |
5884 | a7812ae4 | pbrook | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5885 | a7812ae4 | pbrook | gen_helper_fpop(); |
5886 | c169c906 | bellard | break;
|
5887 | 2c0262af | bellard | case 0x3c: /* df/4 */ |
5888 | 2c0262af | bellard | switch(rm) {
|
5889 | 2c0262af | bellard | case 0: |
5890 | a7812ae4 | pbrook | gen_helper_fnstsw(cpu_tmp2_i32); |
5891 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5892 | 19e6c4b8 | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
5893 | 2c0262af | bellard | break;
|
5894 | 2c0262af | bellard | default:
|
5895 | 2c0262af | bellard | goto illegal_op;
|
5896 | 2c0262af | bellard | } |
5897 | 2c0262af | bellard | break;
|
5898 | 2c0262af | bellard | case 0x3d: /* fucomip */ |
5899 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5900 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5901 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5902 | a7812ae4 | pbrook | gen_helper_fucomi_ST0_FT0(); |
5903 | a7812ae4 | pbrook | gen_helper_fpop(); |
5904 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5905 | 2c0262af | bellard | break;
|
5906 | 2c0262af | bellard | case 0x3e: /* fcomip */ |
5907 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5908 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5909 | a7812ae4 | pbrook | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5910 | a7812ae4 | pbrook | gen_helper_fcomi_ST0_FT0(); |
5911 | a7812ae4 | pbrook | gen_helper_fpop(); |
5912 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5913 | 2c0262af | bellard | break;
|
5914 | a2cc3b24 | bellard | case 0x10 ... 0x13: /* fcmovxx */ |
5915 | a2cc3b24 | bellard | case 0x18 ... 0x1b: |
5916 | a2cc3b24 | bellard | { |
5917 | 19e6c4b8 | bellard | int op1, l1;
|
5918 | d70040bc | pbrook | static const uint8_t fcmov_cc[8] = { |
5919 | a2cc3b24 | bellard | (JCC_B << 1),
|
5920 | a2cc3b24 | bellard | (JCC_Z << 1),
|
5921 | a2cc3b24 | bellard | (JCC_BE << 1),
|
5922 | a2cc3b24 | bellard | (JCC_P << 1),
|
5923 | a2cc3b24 | bellard | }; |
5924 | 1e4840bf | bellard | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
5925 | 19e6c4b8 | bellard | l1 = gen_new_label(); |
5926 | 1e4840bf | bellard | gen_jcc1(s, s->cc_op, op1, l1); |
5927 | a7812ae4 | pbrook | gen_helper_fmov_ST0_STN(tcg_const_i32(opreg)); |
5928 | 19e6c4b8 | bellard | gen_set_label(l1); |
5929 | a2cc3b24 | bellard | } |
5930 | a2cc3b24 | bellard | break;
|
5931 | 2c0262af | bellard | default:
|
5932 | 2c0262af | bellard | goto illegal_op;
|
5933 | 2c0262af | bellard | } |
5934 | 2c0262af | bellard | } |
5935 | 2c0262af | bellard | break;
|
5936 | 2c0262af | bellard | /************************/
|
5937 | 2c0262af | bellard | /* string ops */
|
5938 | 2c0262af | bellard | |
5939 | 2c0262af | bellard | case 0xa4: /* movsS */ |
5940 | 2c0262af | bellard | case 0xa5: |
5941 | 2c0262af | bellard | if ((b & 1) == 0) |
5942 | 2c0262af | bellard | ot = OT_BYTE; |
5943 | 2c0262af | bellard | else
|
5944 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5945 | 2c0262af | bellard | |
5946 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5947 | 2c0262af | bellard | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5948 | 2c0262af | bellard | } else {
|
5949 | 2c0262af | bellard | gen_movs(s, ot); |
5950 | 2c0262af | bellard | } |
5951 | 2c0262af | bellard | break;
|
5952 | 3b46e624 | ths | |
5953 | 2c0262af | bellard | case 0xaa: /* stosS */ |
5954 | 2c0262af | bellard | case 0xab: |
5955 | 2c0262af | bellard | if ((b & 1) == 0) |
5956 | 2c0262af | bellard | ot = OT_BYTE; |
5957 | 2c0262af | bellard | else
|
5958 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5959 | 2c0262af | bellard | |
5960 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5961 | 2c0262af | bellard | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5962 | 2c0262af | bellard | } else {
|
5963 | 2c0262af | bellard | gen_stos(s, ot); |
5964 | 2c0262af | bellard | } |
5965 | 2c0262af | bellard | break;
|
5966 | 2c0262af | bellard | case 0xac: /* lodsS */ |
5967 | 2c0262af | bellard | case 0xad: |
5968 | 2c0262af | bellard | if ((b & 1) == 0) |
5969 | 2c0262af | bellard | ot = OT_BYTE; |
5970 | 2c0262af | bellard | else
|
5971 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5972 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5973 | 2c0262af | bellard | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5974 | 2c0262af | bellard | } else {
|
5975 | 2c0262af | bellard | gen_lods(s, ot); |
5976 | 2c0262af | bellard | } |
5977 | 2c0262af | bellard | break;
|
5978 | 2c0262af | bellard | case 0xae: /* scasS */ |
5979 | 2c0262af | bellard | case 0xaf: |
5980 | 2c0262af | bellard | if ((b & 1) == 0) |
5981 | 2c0262af | bellard | ot = OT_BYTE; |
5982 | 2c0262af | bellard | else
|
5983 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5984 | 2c0262af | bellard | if (prefixes & PREFIX_REPNZ) {
|
5985 | 2c0262af | bellard | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
|
5986 | 2c0262af | bellard | } else if (prefixes & PREFIX_REPZ) { |
5987 | 2c0262af | bellard | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
|
5988 | 2c0262af | bellard | } else {
|
5989 | 2c0262af | bellard | gen_scas(s, ot); |
5990 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
5991 | 2c0262af | bellard | } |
5992 | 2c0262af | bellard | break;
|
5993 | 2c0262af | bellard | |
5994 | 2c0262af | bellard | case 0xa6: /* cmpsS */ |
5995 | 2c0262af | bellard | case 0xa7: |
5996 | 2c0262af | bellard | if ((b & 1) == 0) |
5997 | 2c0262af | bellard | ot = OT_BYTE; |
5998 | 2c0262af | bellard | else
|
5999 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
6000 | 2c0262af | bellard | if (prefixes & PREFIX_REPNZ) {
|
6001 | 2c0262af | bellard | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
|
6002 | 2c0262af | bellard | } else if (prefixes & PREFIX_REPZ) { |
6003 | 2c0262af | bellard | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
|
6004 | 2c0262af | bellard | } else {
|
6005 | 2c0262af | bellard | gen_cmps(s, ot); |
6006 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
6007 | 2c0262af | bellard | } |
6008 | 2c0262af | bellard | break;
|
6009 | 2c0262af | bellard | case 0x6c: /* insS */ |
6010 | 2c0262af | bellard | case 0x6d: |
6011 | f115e911 | bellard | if ((b & 1) == 0) |
6012 | f115e911 | bellard | ot = OT_BYTE; |
6013 | f115e911 | bellard | else
|
6014 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6015 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
6016 | 0573fbfc | ths | gen_op_andl_T0_ffff(); |
6017 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6018 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
|
6019 | f115e911 | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
6020 | f115e911 | bellard | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
6021 | 2c0262af | bellard | } else {
|
6022 | f115e911 | bellard | gen_ins(s, ot); |
6023 | 2e70f6ef | pbrook | if (use_icount) {
|
6024 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6025 | 2e70f6ef | pbrook | } |
6026 | 2c0262af | bellard | } |
6027 | 2c0262af | bellard | break;
|
6028 | 2c0262af | bellard | case 0x6e: /* outsS */ |
6029 | 2c0262af | bellard | case 0x6f: |
6030 | f115e911 | bellard | if ((b & 1) == 0) |
6031 | f115e911 | bellard | ot = OT_BYTE; |
6032 | f115e911 | bellard | else
|
6033 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6034 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
6035 | 0573fbfc | ths | gen_op_andl_T0_ffff(); |
6036 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6037 | b8b6a50b | bellard | svm_is_rep(prefixes) | 4);
|
6038 | f115e911 | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
6039 | f115e911 | bellard | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
6040 | 2c0262af | bellard | } else {
|
6041 | f115e911 | bellard | gen_outs(s, ot); |
6042 | 2e70f6ef | pbrook | if (use_icount) {
|
6043 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6044 | 2e70f6ef | pbrook | } |
6045 | 2c0262af | bellard | } |
6046 | 2c0262af | bellard | break;
|
6047 | 2c0262af | bellard | |
6048 | 2c0262af | bellard | /************************/
|
6049 | 2c0262af | bellard | /* port I/O */
|
6050 | 0573fbfc | ths | |
6051 | 2c0262af | bellard | case 0xe4: |
6052 | 2c0262af | bellard | case 0xe5: |
6053 | f115e911 | bellard | if ((b & 1) == 0) |
6054 | f115e911 | bellard | ot = OT_BYTE; |
6055 | f115e911 | bellard | else
|
6056 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6057 | f115e911 | bellard | val = ldub_code(s->pc++); |
6058 | f115e911 | bellard | gen_op_movl_T0_im(val); |
6059 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6060 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
6061 | 2e70f6ef | pbrook | if (use_icount)
|
6062 | 2e70f6ef | pbrook | gen_io_start(); |
6063 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6064 | a7812ae4 | pbrook | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
|
6065 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EAX); |
6066 | 2e70f6ef | pbrook | if (use_icount) {
|
6067 | 2e70f6ef | pbrook | gen_io_end(); |
6068 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6069 | 2e70f6ef | pbrook | } |
6070 | 2c0262af | bellard | break;
|
6071 | 2c0262af | bellard | case 0xe6: |
6072 | 2c0262af | bellard | case 0xe7: |
6073 | f115e911 | bellard | if ((b & 1) == 0) |
6074 | f115e911 | bellard | ot = OT_BYTE; |
6075 | f115e911 | bellard | else
|
6076 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6077 | f115e911 | bellard | val = ldub_code(s->pc++); |
6078 | f115e911 | bellard | gen_op_movl_T0_im(val); |
6079 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6080 | b8b6a50b | bellard | svm_is_rep(prefixes)); |
6081 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, R_EAX);
|
6082 | b8b6a50b | bellard | |
6083 | 2e70f6ef | pbrook | if (use_icount)
|
6084 | 2e70f6ef | pbrook | gen_io_start(); |
6085 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6086 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
6087 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
6088 | a7812ae4 | pbrook | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
6089 | 2e70f6ef | pbrook | if (use_icount) {
|
6090 | 2e70f6ef | pbrook | gen_io_end(); |
6091 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6092 | 2e70f6ef | pbrook | } |
6093 | 2c0262af | bellard | break;
|
6094 | 2c0262af | bellard | case 0xec: |
6095 | 2c0262af | bellard | case 0xed: |
6096 | f115e911 | bellard | if ((b & 1) == 0) |
6097 | f115e911 | bellard | ot = OT_BYTE; |
6098 | f115e911 | bellard | else
|
6099 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6100 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
6101 | 4f31916f | bellard | gen_op_andl_T0_ffff(); |
6102 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6103 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
6104 | 2e70f6ef | pbrook | if (use_icount)
|
6105 | 2e70f6ef | pbrook | gen_io_start(); |
6106 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6107 | a7812ae4 | pbrook | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
|
6108 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EAX); |
6109 | 2e70f6ef | pbrook | if (use_icount) {
|
6110 | 2e70f6ef | pbrook | gen_io_end(); |
6111 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6112 | 2e70f6ef | pbrook | } |
6113 | 2c0262af | bellard | break;
|
6114 | 2c0262af | bellard | case 0xee: |
6115 | 2c0262af | bellard | case 0xef: |
6116 | f115e911 | bellard | if ((b & 1) == 0) |
6117 | f115e911 | bellard | ot = OT_BYTE; |
6118 | f115e911 | bellard | else
|
6119 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6120 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
6121 | 4f31916f | bellard | gen_op_andl_T0_ffff(); |
6122 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
6123 | b8b6a50b | bellard | svm_is_rep(prefixes)); |
6124 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, R_EAX);
|
6125 | b8b6a50b | bellard | |
6126 | 2e70f6ef | pbrook | if (use_icount)
|
6127 | 2e70f6ef | pbrook | gen_io_start(); |
6128 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6129 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
6130 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
6131 | a7812ae4 | pbrook | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
6132 | 2e70f6ef | pbrook | if (use_icount) {
|
6133 | 2e70f6ef | pbrook | gen_io_end(); |
6134 | 2e70f6ef | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6135 | 2e70f6ef | pbrook | } |
6136 | 2c0262af | bellard | break;
|
6137 | 2c0262af | bellard | |
6138 | 2c0262af | bellard | /************************/
|
6139 | 2c0262af | bellard | /* control */
|
6140 | 2c0262af | bellard | case 0xc2: /* ret im */ |
6141 | 61382a50 | bellard | val = ldsw_code(s->pc); |
6142 | 2c0262af | bellard | s->pc += 2;
|
6143 | 2c0262af | bellard | gen_pop_T0(s); |
6144 | 8f091a59 | bellard | if (CODE64(s) && s->dflag)
|
6145 | 8f091a59 | bellard | s->dflag = 2;
|
6146 | 2c0262af | bellard | gen_stack_update(s, val + (2 << s->dflag));
|
6147 | 2c0262af | bellard | if (s->dflag == 0) |
6148 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
6149 | 2c0262af | bellard | gen_op_jmp_T0(); |
6150 | 2c0262af | bellard | gen_eob(s); |
6151 | 2c0262af | bellard | break;
|
6152 | 2c0262af | bellard | case 0xc3: /* ret */ |
6153 | 2c0262af | bellard | gen_pop_T0(s); |
6154 | 2c0262af | bellard | gen_pop_update(s); |
6155 | 2c0262af | bellard | if (s->dflag == 0) |
6156 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
6157 | 2c0262af | bellard | gen_op_jmp_T0(); |
6158 | 2c0262af | bellard | gen_eob(s); |
6159 | 2c0262af | bellard | break;
|
6160 | 2c0262af | bellard | case 0xca: /* lret im */ |
6161 | 61382a50 | bellard | val = ldsw_code(s->pc); |
6162 | 2c0262af | bellard | s->pc += 2;
|
6163 | 2c0262af | bellard | do_lret:
|
6164 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
6165 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6166 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6167 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6168 | a7812ae4 | pbrook | gen_helper_lret_protected(tcg_const_i32(s->dflag), |
6169 | a7812ae4 | pbrook | tcg_const_i32(val)); |
6170 | 2c0262af | bellard | } else {
|
6171 | 2c0262af | bellard | gen_stack_A0(s); |
6172 | 2c0262af | bellard | /* pop offset */
|
6173 | 57fec1fe | bellard | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
|
6174 | 2c0262af | bellard | if (s->dflag == 0) |
6175 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
6176 | 2c0262af | bellard | /* NOTE: keeping EIP updated is not a problem in case of
|
6177 | 2c0262af | bellard | exception */
|
6178 | 2c0262af | bellard | gen_op_jmp_T0(); |
6179 | 2c0262af | bellard | /* pop selector */
|
6180 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
6181 | 57fec1fe | bellard | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
|
6182 | 3bd7da9e | bellard | gen_op_movl_seg_T0_vm(R_CS); |
6183 | 2c0262af | bellard | /* add stack offset */
|
6184 | 2c0262af | bellard | gen_stack_update(s, val + (4 << s->dflag));
|
6185 | 2c0262af | bellard | } |
6186 | 2c0262af | bellard | gen_eob(s); |
6187 | 2c0262af | bellard | break;
|
6188 | 2c0262af | bellard | case 0xcb: /* lret */ |
6189 | 2c0262af | bellard | val = 0;
|
6190 | 2c0262af | bellard | goto do_lret;
|
6191 | 2c0262af | bellard | case 0xcf: /* iret */ |
6192 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
6193 | 2c0262af | bellard | if (!s->pe) {
|
6194 | 2c0262af | bellard | /* real mode */
|
6195 | a7812ae4 | pbrook | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
6196 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6197 | f115e911 | bellard | } else if (s->vm86) { |
6198 | f115e911 | bellard | if (s->iopl != 3) { |
6199 | f115e911 | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6200 | f115e911 | bellard | } else {
|
6201 | a7812ae4 | pbrook | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
6202 | f115e911 | bellard | s->cc_op = CC_OP_EFLAGS; |
6203 | f115e911 | bellard | } |
6204 | 2c0262af | bellard | } else {
|
6205 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6206 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6207 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6208 | a7812ae4 | pbrook | gen_helper_iret_protected(tcg_const_i32(s->dflag), |
6209 | a7812ae4 | pbrook | tcg_const_i32(s->pc - s->cs_base)); |
6210 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6211 | 2c0262af | bellard | } |
6212 | 2c0262af | bellard | gen_eob(s); |
6213 | 2c0262af | bellard | break;
|
6214 | 2c0262af | bellard | case 0xe8: /* call im */ |
6215 | 2c0262af | bellard | { |
6216 | 14ce26e7 | bellard | if (dflag)
|
6217 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
6218 | 14ce26e7 | bellard | else
|
6219 | 14ce26e7 | bellard | tval = (int16_t)insn_get(s, OT_WORD); |
6220 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
6221 | 14ce26e7 | bellard | tval += next_eip; |
6222 | 2c0262af | bellard | if (s->dflag == 0) |
6223 | 14ce26e7 | bellard | tval &= 0xffff;
|
6224 | 14ce26e7 | bellard | gen_movtl_T0_im(next_eip); |
6225 | 2c0262af | bellard | gen_push_T0(s); |
6226 | 14ce26e7 | bellard | gen_jmp(s, tval); |
6227 | 2c0262af | bellard | } |
6228 | 2c0262af | bellard | break;
|
6229 | 2c0262af | bellard | case 0x9a: /* lcall im */ |
6230 | 2c0262af | bellard | { |
6231 | 2c0262af | bellard | unsigned int selector, offset; |
6232 | 3b46e624 | ths | |
6233 | 14ce26e7 | bellard | if (CODE64(s))
|
6234 | 14ce26e7 | bellard | goto illegal_op;
|
6235 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6236 | 2c0262af | bellard | offset = insn_get(s, ot); |
6237 | 2c0262af | bellard | selector = insn_get(s, OT_WORD); |
6238 | 3b46e624 | ths | |
6239 | 2c0262af | bellard | gen_op_movl_T0_im(selector); |
6240 | 14ce26e7 | bellard | gen_op_movl_T1_imu(offset); |
6241 | 2c0262af | bellard | } |
6242 | 2c0262af | bellard | goto do_lcall;
|
6243 | ecada8a2 | bellard | case 0xe9: /* jmp im */ |
6244 | 14ce26e7 | bellard | if (dflag)
|
6245 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
6246 | 14ce26e7 | bellard | else
|
6247 | 14ce26e7 | bellard | tval = (int16_t)insn_get(s, OT_WORD); |
6248 | 14ce26e7 | bellard | tval += s->pc - s->cs_base; |
6249 | 2c0262af | bellard | if (s->dflag == 0) |
6250 | 14ce26e7 | bellard | tval &= 0xffff;
|
6251 | 32938e12 | aurel32 | else if(!CODE64(s)) |
6252 | 32938e12 | aurel32 | tval &= 0xffffffff;
|
6253 | 14ce26e7 | bellard | gen_jmp(s, tval); |
6254 | 2c0262af | bellard | break;
|
6255 | 2c0262af | bellard | case 0xea: /* ljmp im */ |
6256 | 2c0262af | bellard | { |
6257 | 2c0262af | bellard | unsigned int selector, offset; |
6258 | 2c0262af | bellard | |
6259 | 14ce26e7 | bellard | if (CODE64(s))
|
6260 | 14ce26e7 | bellard | goto illegal_op;
|
6261 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6262 | 2c0262af | bellard | offset = insn_get(s, ot); |
6263 | 2c0262af | bellard | selector = insn_get(s, OT_WORD); |
6264 | 3b46e624 | ths | |
6265 | 2c0262af | bellard | gen_op_movl_T0_im(selector); |
6266 | 14ce26e7 | bellard | gen_op_movl_T1_imu(offset); |
6267 | 2c0262af | bellard | } |
6268 | 2c0262af | bellard | goto do_ljmp;
|
6269 | 2c0262af | bellard | case 0xeb: /* jmp Jb */ |
6270 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
6271 | 14ce26e7 | bellard | tval += s->pc - s->cs_base; |
6272 | 2c0262af | bellard | if (s->dflag == 0) |
6273 | 14ce26e7 | bellard | tval &= 0xffff;
|
6274 | 14ce26e7 | bellard | gen_jmp(s, tval); |
6275 | 2c0262af | bellard | break;
|
6276 | 2c0262af | bellard | case 0x70 ... 0x7f: /* jcc Jb */ |
6277 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
6278 | 2c0262af | bellard | goto do_jcc;
|
6279 | 2c0262af | bellard | case 0x180 ... 0x18f: /* jcc Jv */ |
6280 | 2c0262af | bellard | if (dflag) {
|
6281 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
6282 | 2c0262af | bellard | } else {
|
6283 | 5fafdf24 | ths | tval = (int16_t)insn_get(s, OT_WORD); |
6284 | 2c0262af | bellard | } |
6285 | 2c0262af | bellard | do_jcc:
|
6286 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
6287 | 14ce26e7 | bellard | tval += next_eip; |
6288 | 2c0262af | bellard | if (s->dflag == 0) |
6289 | 14ce26e7 | bellard | tval &= 0xffff;
|
6290 | 14ce26e7 | bellard | gen_jcc(s, b, tval, next_eip); |
6291 | 2c0262af | bellard | break;
|
6292 | 2c0262af | bellard | |
6293 | 2c0262af | bellard | case 0x190 ... 0x19f: /* setcc Gv */ |
6294 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6295 | 2c0262af | bellard | gen_setcc(s, b); |
6296 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
|
6297 | 2c0262af | bellard | break;
|
6298 | 2c0262af | bellard | case 0x140 ... 0x14f: /* cmov Gv, Ev */ |
6299 | 8e1c85e3 | bellard | { |
6300 | 8e1c85e3 | bellard | int l1;
|
6301 | 1e4840bf | bellard | TCGv t0; |
6302 | 1e4840bf | bellard | |
6303 | 8e1c85e3 | bellard | ot = dflag + OT_WORD; |
6304 | 8e1c85e3 | bellard | modrm = ldub_code(s->pc++); |
6305 | 8e1c85e3 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6306 | 8e1c85e3 | bellard | mod = (modrm >> 6) & 3; |
6307 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
6308 | 8e1c85e3 | bellard | if (mod != 3) { |
6309 | 8e1c85e3 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6310 | 1e4840bf | bellard | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
6311 | 8e1c85e3 | bellard | } else {
|
6312 | 8e1c85e3 | bellard | rm = (modrm & 7) | REX_B(s);
|
6313 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t0, rm); |
6314 | 8e1c85e3 | bellard | } |
6315 | 8e1c85e3 | bellard | #ifdef TARGET_X86_64
|
6316 | 8e1c85e3 | bellard | if (ot == OT_LONG) {
|
6317 | 8e1c85e3 | bellard | /* XXX: specific Intel behaviour ? */
|
6318 | 8e1c85e3 | bellard | l1 = gen_new_label(); |
6319 | 8e1c85e3 | bellard | gen_jcc1(s, s->cc_op, b ^ 1, l1);
|
6320 | 1e4840bf | bellard | tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
6321 | 8e1c85e3 | bellard | gen_set_label(l1); |
6322 | 8e1c85e3 | bellard | tcg_gen_movi_tl(cpu_tmp0, 0);
|
6323 | 8e1c85e3 | bellard | tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); |
6324 | 8e1c85e3 | bellard | } else
|
6325 | 8e1c85e3 | bellard | #endif
|
6326 | 8e1c85e3 | bellard | { |
6327 | 8e1c85e3 | bellard | l1 = gen_new_label(); |
6328 | 8e1c85e3 | bellard | gen_jcc1(s, s->cc_op, b ^ 1, l1);
|
6329 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, reg, t0); |
6330 | 8e1c85e3 | bellard | gen_set_label(l1); |
6331 | 8e1c85e3 | bellard | } |
6332 | 1e4840bf | bellard | tcg_temp_free(t0); |
6333 | 2c0262af | bellard | } |
6334 | 2c0262af | bellard | break;
|
6335 | 3b46e624 | ths | |
6336 | 2c0262af | bellard | /************************/
|
6337 | 2c0262af | bellard | /* flags */
|
6338 | 2c0262af | bellard | case 0x9c: /* pushf */ |
6339 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
6340 | 2c0262af | bellard | if (s->vm86 && s->iopl != 3) { |
6341 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6342 | 2c0262af | bellard | } else {
|
6343 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6344 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6345 | a7812ae4 | pbrook | gen_helper_read_eflags(cpu_T[0]);
|
6346 | 2c0262af | bellard | gen_push_T0(s); |
6347 | 2c0262af | bellard | } |
6348 | 2c0262af | bellard | break;
|
6349 | 2c0262af | bellard | case 0x9d: /* popf */ |
6350 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
6351 | 2c0262af | bellard | if (s->vm86 && s->iopl != 3) { |
6352 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6353 | 2c0262af | bellard | } else {
|
6354 | 2c0262af | bellard | gen_pop_T0(s); |
6355 | 2c0262af | bellard | if (s->cpl == 0) { |
6356 | 2c0262af | bellard | if (s->dflag) {
|
6357 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6358 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK))); |
6359 | 2c0262af | bellard | } else {
|
6360 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6361 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
|
6362 | 2c0262af | bellard | } |
6363 | 2c0262af | bellard | } else {
|
6364 | 4136f33c | bellard | if (s->cpl <= s->iopl) {
|
6365 | 4136f33c | bellard | if (s->dflag) {
|
6366 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6367 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK))); |
6368 | 4136f33c | bellard | } else {
|
6369 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6370 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
|
6371 | 4136f33c | bellard | } |
6372 | 2c0262af | bellard | } else {
|
6373 | 4136f33c | bellard | if (s->dflag) {
|
6374 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6375 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK))); |
6376 | 4136f33c | bellard | } else {
|
6377 | a7812ae4 | pbrook | gen_helper_write_eflags(cpu_T[0],
|
6378 | bd7a7b33 | bellard | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
|
6379 | 4136f33c | bellard | } |
6380 | 2c0262af | bellard | } |
6381 | 2c0262af | bellard | } |
6382 | 2c0262af | bellard | gen_pop_update(s); |
6383 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6384 | 2c0262af | bellard | /* abort translation because TF flag may change */
|
6385 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6386 | 2c0262af | bellard | gen_eob(s); |
6387 | 2c0262af | bellard | } |
6388 | 2c0262af | bellard | break;
|
6389 | 2c0262af | bellard | case 0x9e: /* sahf */ |
6390 | 12e26b75 | bellard | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
|
6391 | 14ce26e7 | bellard | goto illegal_op;
|
6392 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
|
6393 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6394 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6395 | bd7a7b33 | bellard | gen_compute_eflags(cpu_cc_src); |
6396 | bd7a7b33 | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6397 | bd7a7b33 | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); |
6398 | bd7a7b33 | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
|
6399 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6400 | 2c0262af | bellard | break;
|
6401 | 2c0262af | bellard | case 0x9f: /* lahf */ |
6402 | 12e26b75 | bellard | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
|
6403 | 14ce26e7 | bellard | goto illegal_op;
|
6404 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6405 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6406 | bd7a7b33 | bellard | gen_compute_eflags(cpu_T[0]);
|
6407 | bd7a7b33 | bellard | /* Note: gen_compute_eflags() only gives the condition codes */
|
6408 | bd7a7b33 | bellard | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); |
6409 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
6410 | 2c0262af | bellard | break;
|
6411 | 2c0262af | bellard | case 0xf5: /* cmc */ |
6412 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6413 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6414 | bd7a7b33 | bellard | gen_compute_eflags(cpu_cc_src); |
6415 | bd7a7b33 | bellard | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
6416 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6417 | 2c0262af | bellard | break;
|
6418 | 2c0262af | bellard | case 0xf8: /* clc */ |
6419 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6420 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6421 | bd7a7b33 | bellard | gen_compute_eflags(cpu_cc_src); |
6422 | bd7a7b33 | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
6423 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6424 | 2c0262af | bellard | break;
|
6425 | 2c0262af | bellard | case 0xf9: /* stc */ |
6426 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6427 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6428 | bd7a7b33 | bellard | gen_compute_eflags(cpu_cc_src); |
6429 | bd7a7b33 | bellard | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
6430 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6431 | 2c0262af | bellard | break;
|
6432 | 2c0262af | bellard | case 0xfc: /* cld */ |
6433 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_tmp2_i32, 1);
|
6434 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); |
6435 | 2c0262af | bellard | break;
|
6436 | 2c0262af | bellard | case 0xfd: /* std */ |
6437 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_tmp2_i32, -1);
|
6438 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); |
6439 | 2c0262af | bellard | break;
|
6440 | 2c0262af | bellard | |
6441 | 2c0262af | bellard | /************************/
|
6442 | 2c0262af | bellard | /* bit operations */
|
6443 | 2c0262af | bellard | case 0x1ba: /* bt/bts/btr/btc Gv, im */ |
6444 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
6445 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6446 | 33698e5f | bellard | op = (modrm >> 3) & 7; |
6447 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6448 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
6449 | 2c0262af | bellard | if (mod != 3) { |
6450 | 14ce26e7 | bellard | s->rip_offset = 1;
|
6451 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6452 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
6453 | 2c0262af | bellard | } else {
|
6454 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
6455 | 2c0262af | bellard | } |
6456 | 2c0262af | bellard | /* load shift */
|
6457 | 61382a50 | bellard | val = ldub_code(s->pc++); |
6458 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
6459 | 2c0262af | bellard | if (op < 4) |
6460 | 2c0262af | bellard | goto illegal_op;
|
6461 | 2c0262af | bellard | op -= 4;
|
6462 | f484d386 | bellard | goto bt_op;
|
6463 | 2c0262af | bellard | case 0x1a3: /* bt Gv, Ev */ |
6464 | 2c0262af | bellard | op = 0;
|
6465 | 2c0262af | bellard | goto do_btx;
|
6466 | 2c0262af | bellard | case 0x1ab: /* bts */ |
6467 | 2c0262af | bellard | op = 1;
|
6468 | 2c0262af | bellard | goto do_btx;
|
6469 | 2c0262af | bellard | case 0x1b3: /* btr */ |
6470 | 2c0262af | bellard | op = 2;
|
6471 | 2c0262af | bellard | goto do_btx;
|
6472 | 2c0262af | bellard | case 0x1bb: /* btc */ |
6473 | 2c0262af | bellard | op = 3;
|
6474 | 2c0262af | bellard | do_btx:
|
6475 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
6476 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6477 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6478 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6479 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
6480 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 1, reg);
|
6481 | 2c0262af | bellard | if (mod != 3) { |
6482 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6483 | 2c0262af | bellard | /* specific case: we need to add a displacement */
|
6484 | f484d386 | bellard | gen_exts(ot, cpu_T[1]);
|
6485 | f484d386 | bellard | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); |
6486 | f484d386 | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); |
6487 | f484d386 | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
6488 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
6489 | 2c0262af | bellard | } else {
|
6490 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
6491 | 2c0262af | bellard | } |
6492 | f484d386 | bellard | bt_op:
|
6493 | f484d386 | bellard | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); |
6494 | f484d386 | bellard | switch(op) {
|
6495 | f484d386 | bellard | case 0: |
6496 | f484d386 | bellard | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); |
6497 | f484d386 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 0);
|
6498 | f484d386 | bellard | break;
|
6499 | f484d386 | bellard | case 1: |
6500 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
6501 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
6502 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
6503 | f484d386 | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
6504 | f484d386 | bellard | break;
|
6505 | f484d386 | bellard | case 2: |
6506 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
6507 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
6508 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
6509 | f484d386 | bellard | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); |
6510 | f484d386 | bellard | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
6511 | f484d386 | bellard | break;
|
6512 | f484d386 | bellard | default:
|
6513 | f484d386 | bellard | case 3: |
6514 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
6515 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
6516 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
6517 | f484d386 | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
6518 | f484d386 | bellard | break;
|
6519 | f484d386 | bellard | } |
6520 | 2c0262af | bellard | s->cc_op = CC_OP_SARB + ot; |
6521 | 2c0262af | bellard | if (op != 0) { |
6522 | 2c0262af | bellard | if (mod != 3) |
6523 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
6524 | 2c0262af | bellard | else
|
6525 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
6526 | f484d386 | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6527 | f484d386 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 0);
|
6528 | 2c0262af | bellard | } |
6529 | 2c0262af | bellard | break;
|
6530 | 2c0262af | bellard | case 0x1bc: /* bsf */ |
6531 | 2c0262af | bellard | case 0x1bd: /* bsr */ |
6532 | 6191b059 | bellard | { |
6533 | 6191b059 | bellard | int label1;
|
6534 | 1e4840bf | bellard | TCGv t0; |
6535 | 1e4840bf | bellard | |
6536 | 6191b059 | bellard | ot = dflag + OT_WORD; |
6537 | 6191b059 | bellard | modrm = ldub_code(s->pc++); |
6538 | 6191b059 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6539 | 6191b059 | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
6540 | 6191b059 | bellard | gen_extu(ot, cpu_T[0]);
|
6541 | 6191b059 | bellard | label1 = gen_new_label(); |
6542 | 6191b059 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 0);
|
6543 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
6544 | 1e4840bf | bellard | tcg_gen_mov_tl(t0, cpu_T[0]);
|
6545 | 1e4840bf | bellard | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
|
6546 | 6191b059 | bellard | if (b & 1) { |
6547 | a7812ae4 | pbrook | gen_helper_bsr(cpu_T[0], t0);
|
6548 | 6191b059 | bellard | } else {
|
6549 | a7812ae4 | pbrook | gen_helper_bsf(cpu_T[0], t0);
|
6550 | 6191b059 | bellard | } |
6551 | 6191b059 | bellard | gen_op_mov_reg_T0(ot, reg); |
6552 | 6191b059 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 1);
|
6553 | 6191b059 | bellard | gen_set_label(label1); |
6554 | 6191b059 | bellard | tcg_gen_discard_tl(cpu_cc_src); |
6555 | 6191b059 | bellard | s->cc_op = CC_OP_LOGICB + ot; |
6556 | 1e4840bf | bellard | tcg_temp_free(t0); |
6557 | 6191b059 | bellard | } |
6558 | 2c0262af | bellard | break;
|
6559 | 2c0262af | bellard | /************************/
|
6560 | 2c0262af | bellard | /* bcd */
|
6561 | 2c0262af | bellard | case 0x27: /* daa */ |
6562 | 14ce26e7 | bellard | if (CODE64(s))
|
6563 | 14ce26e7 | bellard | goto illegal_op;
|
6564 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6565 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6566 | a7812ae4 | pbrook | gen_helper_daa(); |
6567 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6568 | 2c0262af | bellard | break;
|
6569 | 2c0262af | bellard | case 0x2f: /* das */ |
6570 | 14ce26e7 | bellard | if (CODE64(s))
|
6571 | 14ce26e7 | bellard | goto illegal_op;
|
6572 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6573 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6574 | a7812ae4 | pbrook | gen_helper_das(); |
6575 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6576 | 2c0262af | bellard | break;
|
6577 | 2c0262af | bellard | case 0x37: /* aaa */ |
6578 | 14ce26e7 | bellard | if (CODE64(s))
|
6579 | 14ce26e7 | bellard | goto illegal_op;
|
6580 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6581 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6582 | a7812ae4 | pbrook | gen_helper_aaa(); |
6583 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6584 | 2c0262af | bellard | break;
|
6585 | 2c0262af | bellard | case 0x3f: /* aas */ |
6586 | 14ce26e7 | bellard | if (CODE64(s))
|
6587 | 14ce26e7 | bellard | goto illegal_op;
|
6588 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6589 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6590 | a7812ae4 | pbrook | gen_helper_aas(); |
6591 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6592 | 2c0262af | bellard | break;
|
6593 | 2c0262af | bellard | case 0xd4: /* aam */ |
6594 | 14ce26e7 | bellard | if (CODE64(s))
|
6595 | 14ce26e7 | bellard | goto illegal_op;
|
6596 | 61382a50 | bellard | val = ldub_code(s->pc++); |
6597 | b6d7c3db | ths | if (val == 0) { |
6598 | b6d7c3db | ths | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); |
6599 | b6d7c3db | ths | } else {
|
6600 | a7812ae4 | pbrook | gen_helper_aam(tcg_const_i32(val)); |
6601 | b6d7c3db | ths | s->cc_op = CC_OP_LOGICB; |
6602 | b6d7c3db | ths | } |
6603 | 2c0262af | bellard | break;
|
6604 | 2c0262af | bellard | case 0xd5: /* aad */ |
6605 | 14ce26e7 | bellard | if (CODE64(s))
|
6606 | 14ce26e7 | bellard | goto illegal_op;
|
6607 | 61382a50 | bellard | val = ldub_code(s->pc++); |
6608 | a7812ae4 | pbrook | gen_helper_aad(tcg_const_i32(val)); |
6609 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB; |
6610 | 2c0262af | bellard | break;
|
6611 | 2c0262af | bellard | /************************/
|
6612 | 2c0262af | bellard | /* misc */
|
6613 | 2c0262af | bellard | case 0x90: /* nop */ |
6614 | 14ce26e7 | bellard | /* XXX: xchg + rex handling */
|
6615 | ab1f142b | bellard | /* XXX: correct lock test for all insn */
|
6616 | ab1f142b | bellard | if (prefixes & PREFIX_LOCK)
|
6617 | ab1f142b | bellard | goto illegal_op;
|
6618 | 0573fbfc | ths | if (prefixes & PREFIX_REPZ) {
|
6619 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); |
6620 | 0573fbfc | ths | } |
6621 | 2c0262af | bellard | break;
|
6622 | 2c0262af | bellard | case 0x9b: /* fwait */ |
6623 | 5fafdf24 | ths | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
|
6624 | 7eee2a50 | bellard | (HF_MP_MASK | HF_TS_MASK)) { |
6625 | 7eee2a50 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
6626 | 2ee73ac3 | bellard | } else {
|
6627 | 2ee73ac3 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6628 | 2ee73ac3 | bellard | gen_op_set_cc_op(s->cc_op); |
6629 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6630 | a7812ae4 | pbrook | gen_helper_fwait(); |
6631 | 7eee2a50 | bellard | } |
6632 | 2c0262af | bellard | break;
|
6633 | 2c0262af | bellard | case 0xcc: /* int3 */ |
6634 | 2c0262af | bellard | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); |
6635 | 2c0262af | bellard | break;
|
6636 | 2c0262af | bellard | case 0xcd: /* int N */ |
6637 | 61382a50 | bellard | val = ldub_code(s->pc++); |
6638 | f115e911 | bellard | if (s->vm86 && s->iopl != 3) { |
6639 | 5fafdf24 | ths | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6640 | f115e911 | bellard | } else {
|
6641 | f115e911 | bellard | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); |
6642 | f115e911 | bellard | } |
6643 | 2c0262af | bellard | break;
|
6644 | 2c0262af | bellard | case 0xce: /* into */ |
6645 | 14ce26e7 | bellard | if (CODE64(s))
|
6646 | 14ce26e7 | bellard | goto illegal_op;
|
6647 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6648 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6649 | a8ede8ba | bellard | gen_jmp_im(pc_start - s->cs_base); |
6650 | a7812ae4 | pbrook | gen_helper_into(tcg_const_i32(s->pc - pc_start)); |
6651 | 2c0262af | bellard | break;
|
6652 | 0b97134b | aurel32 | #ifdef WANT_ICEBP
|
6653 | 2c0262af | bellard | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
6654 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
6655 | aba9d61e | bellard | #if 1 |
6656 | 2c0262af | bellard | gen_debug(s, pc_start - s->cs_base); |
6657 | aba9d61e | bellard | #else
|
6658 | aba9d61e | bellard | /* start debug */
|
6659 | aba9d61e | bellard | tb_flush(cpu_single_env); |
6660 | aba9d61e | bellard | cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
6661 | aba9d61e | bellard | #endif
|
6662 | 2c0262af | bellard | break;
|
6663 | 0b97134b | aurel32 | #endif
|
6664 | 2c0262af | bellard | case 0xfa: /* cli */ |
6665 | 2c0262af | bellard | if (!s->vm86) {
|
6666 | 2c0262af | bellard | if (s->cpl <= s->iopl) {
|
6667 | a7812ae4 | pbrook | gen_helper_cli(); |
6668 | 2c0262af | bellard | } else {
|
6669 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6670 | 2c0262af | bellard | } |
6671 | 2c0262af | bellard | } else {
|
6672 | 2c0262af | bellard | if (s->iopl == 3) { |
6673 | a7812ae4 | pbrook | gen_helper_cli(); |
6674 | 2c0262af | bellard | } else {
|
6675 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6676 | 2c0262af | bellard | } |
6677 | 2c0262af | bellard | } |
6678 | 2c0262af | bellard | break;
|
6679 | 2c0262af | bellard | case 0xfb: /* sti */ |
6680 | 2c0262af | bellard | if (!s->vm86) {
|
6681 | 2c0262af | bellard | if (s->cpl <= s->iopl) {
|
6682 | 2c0262af | bellard | gen_sti:
|
6683 | a7812ae4 | pbrook | gen_helper_sti(); |
6684 | 2c0262af | bellard | /* interruptions are enabled only the first insn after sti */
|
6685 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
6686 | a2cc3b24 | bellard | _first_ does it */
|
6687 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
6688 | a7812ae4 | pbrook | gen_helper_set_inhibit_irq(); |
6689 | 2c0262af | bellard | /* give a chance to handle pending irqs */
|
6690 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6691 | 2c0262af | bellard | gen_eob(s); |
6692 | 2c0262af | bellard | } else {
|
6693 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6694 | 2c0262af | bellard | } |
6695 | 2c0262af | bellard | } else {
|
6696 | 2c0262af | bellard | if (s->iopl == 3) { |
6697 | 2c0262af | bellard | goto gen_sti;
|
6698 | 2c0262af | bellard | } else {
|
6699 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6700 | 2c0262af | bellard | } |
6701 | 2c0262af | bellard | } |
6702 | 2c0262af | bellard | break;
|
6703 | 2c0262af | bellard | case 0x62: /* bound */ |
6704 | 14ce26e7 | bellard | if (CODE64(s))
|
6705 | 14ce26e7 | bellard | goto illegal_op;
|
6706 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6707 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6708 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
6709 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6710 | 2c0262af | bellard | if (mod == 3) |
6711 | 2c0262af | bellard | goto illegal_op;
|
6712 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
6713 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6714 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6715 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6716 | 2c0262af | bellard | if (ot == OT_WORD)
|
6717 | a7812ae4 | pbrook | gen_helper_boundw(cpu_A0, cpu_tmp2_i32); |
6718 | 2c0262af | bellard | else
|
6719 | a7812ae4 | pbrook | gen_helper_boundl(cpu_A0, cpu_tmp2_i32); |
6720 | 2c0262af | bellard | break;
|
6721 | 2c0262af | bellard | case 0x1c8 ... 0x1cf: /* bswap reg */ |
6722 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
6723 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6724 | 14ce26e7 | bellard | if (dflag == 2) { |
6725 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, reg);
|
6726 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
6727 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, reg); |
6728 | 5fafdf24 | ths | } else
|
6729 | 8777643e | aurel32 | #endif
|
6730 | 57fec1fe | bellard | { |
6731 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, reg);
|
6732 | 8777643e | aurel32 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6733 | 8777643e | aurel32 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); |
6734 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
6735 | 14ce26e7 | bellard | } |
6736 | 2c0262af | bellard | break;
|
6737 | 2c0262af | bellard | case 0xd6: /* salc */ |
6738 | 14ce26e7 | bellard | if (CODE64(s))
|
6739 | 14ce26e7 | bellard | goto illegal_op;
|
6740 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6741 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6742 | bd7a7b33 | bellard | gen_compute_eflags_c(cpu_T[0]);
|
6743 | bd7a7b33 | bellard | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
6744 | bd7a7b33 | bellard | gen_op_mov_reg_T0(OT_BYTE, R_EAX); |
6745 | 2c0262af | bellard | break;
|
6746 | 2c0262af | bellard | case 0xe0: /* loopnz */ |
6747 | 2c0262af | bellard | case 0xe1: /* loopz */ |
6748 | 2c0262af | bellard | case 0xe2: /* loop */ |
6749 | 2c0262af | bellard | case 0xe3: /* jecxz */ |
6750 | 14ce26e7 | bellard | { |
6751 | 6e0d8677 | bellard | int l1, l2, l3;
|
6752 | 14ce26e7 | bellard | |
6753 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
6754 | 14ce26e7 | bellard | next_eip = s->pc - s->cs_base; |
6755 | 14ce26e7 | bellard | tval += next_eip; |
6756 | 14ce26e7 | bellard | if (s->dflag == 0) |
6757 | 14ce26e7 | bellard | tval &= 0xffff;
|
6758 | 3b46e624 | ths | |
6759 | 14ce26e7 | bellard | l1 = gen_new_label(); |
6760 | 14ce26e7 | bellard | l2 = gen_new_label(); |
6761 | 6e0d8677 | bellard | l3 = gen_new_label(); |
6762 | 14ce26e7 | bellard | b &= 3;
|
6763 | 6e0d8677 | bellard | switch(b) {
|
6764 | 6e0d8677 | bellard | case 0: /* loopnz */ |
6765 | 6e0d8677 | bellard | case 1: /* loopz */ |
6766 | 6e0d8677 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6767 | 6e0d8677 | bellard | gen_op_set_cc_op(s->cc_op); |
6768 | 6e0d8677 | bellard | gen_op_add_reg_im(s->aflag, R_ECX, -1);
|
6769 | 6e0d8677 | bellard | gen_op_jz_ecx(s->aflag, l3); |
6770 | 6e0d8677 | bellard | gen_compute_eflags(cpu_tmp0); |
6771 | 6e0d8677 | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z); |
6772 | 6e0d8677 | bellard | if (b == 0) { |
6773 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
6774 | 6e0d8677 | bellard | } else {
|
6775 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
|
6776 | 6e0d8677 | bellard | } |
6777 | 6e0d8677 | bellard | break;
|
6778 | 6e0d8677 | bellard | case 2: /* loop */ |
6779 | 6e0d8677 | bellard | gen_op_add_reg_im(s->aflag, R_ECX, -1);
|
6780 | 6e0d8677 | bellard | gen_op_jnz_ecx(s->aflag, l1); |
6781 | 6e0d8677 | bellard | break;
|
6782 | 6e0d8677 | bellard | default:
|
6783 | 6e0d8677 | bellard | case 3: /* jcxz */ |
6784 | 6e0d8677 | bellard | gen_op_jz_ecx(s->aflag, l1); |
6785 | 6e0d8677 | bellard | break;
|
6786 | 14ce26e7 | bellard | } |
6787 | 14ce26e7 | bellard | |
6788 | 6e0d8677 | bellard | gen_set_label(l3); |
6789 | 14ce26e7 | bellard | gen_jmp_im(next_eip); |
6790 | 8e1c85e3 | bellard | tcg_gen_br(l2); |
6791 | 6e0d8677 | bellard | |
6792 | 14ce26e7 | bellard | gen_set_label(l1); |
6793 | 14ce26e7 | bellard | gen_jmp_im(tval); |
6794 | 14ce26e7 | bellard | gen_set_label(l2); |
6795 | 14ce26e7 | bellard | gen_eob(s); |
6796 | 14ce26e7 | bellard | } |
6797 | 2c0262af | bellard | break;
|
6798 | 2c0262af | bellard | case 0x130: /* wrmsr */ |
6799 | 2c0262af | bellard | case 0x132: /* rdmsr */ |
6800 | 2c0262af | bellard | if (s->cpl != 0) { |
6801 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6802 | 2c0262af | bellard | } else {
|
6803 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6804 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
6805 | 872929aa | bellard | gen_jmp_im(pc_start - s->cs_base); |
6806 | 0573fbfc | ths | if (b & 2) { |
6807 | a7812ae4 | pbrook | gen_helper_rdmsr(); |
6808 | 0573fbfc | ths | } else {
|
6809 | a7812ae4 | pbrook | gen_helper_wrmsr(); |
6810 | 0573fbfc | ths | } |
6811 | 2c0262af | bellard | } |
6812 | 2c0262af | bellard | break;
|
6813 | 2c0262af | bellard | case 0x131: /* rdtsc */ |
6814 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6815 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
6816 | ecada8a2 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6817 | efade670 | pbrook | if (use_icount)
|
6818 | efade670 | pbrook | gen_io_start(); |
6819 | a7812ae4 | pbrook | gen_helper_rdtsc(); |
6820 | efade670 | pbrook | if (use_icount) {
|
6821 | efade670 | pbrook | gen_io_end(); |
6822 | efade670 | pbrook | gen_jmp(s, s->pc - s->cs_base); |
6823 | efade670 | pbrook | } |
6824 | 2c0262af | bellard | break;
|
6825 | df01e0fc | balrog | case 0x133: /* rdpmc */ |
6826 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6827 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
6828 | df01e0fc | balrog | gen_jmp_im(pc_start - s->cs_base); |
6829 | a7812ae4 | pbrook | gen_helper_rdpmc(); |
6830 | df01e0fc | balrog | break;
|
6831 | 023fe10d | bellard | case 0x134: /* sysenter */ |
6832 | 2436b61a | balrog | /* For Intel SYSENTER is valid on 64-bit */
|
6833 | 2436b61a | balrog | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
|
6834 | 14ce26e7 | bellard | goto illegal_op;
|
6835 | 023fe10d | bellard | if (!s->pe) {
|
6836 | 023fe10d | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6837 | 023fe10d | bellard | } else {
|
6838 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6839 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
6840 | 023fe10d | bellard | s->cc_op = CC_OP_DYNAMIC; |
6841 | 023fe10d | bellard | } |
6842 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6843 | a7812ae4 | pbrook | gen_helper_sysenter(); |
6844 | 023fe10d | bellard | gen_eob(s); |
6845 | 023fe10d | bellard | } |
6846 | 023fe10d | bellard | break;
|
6847 | 023fe10d | bellard | case 0x135: /* sysexit */ |
6848 | 2436b61a | balrog | /* For Intel SYSEXIT is valid on 64-bit */
|
6849 | 2436b61a | balrog | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
|
6850 | 14ce26e7 | bellard | goto illegal_op;
|
6851 | 023fe10d | bellard | if (!s->pe) {
|
6852 | 023fe10d | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6853 | 023fe10d | bellard | } else {
|
6854 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6855 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
6856 | 023fe10d | bellard | s->cc_op = CC_OP_DYNAMIC; |
6857 | 023fe10d | bellard | } |
6858 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6859 | a7812ae4 | pbrook | gen_helper_sysexit(tcg_const_i32(dflag)); |
6860 | 023fe10d | bellard | gen_eob(s); |
6861 | 023fe10d | bellard | } |
6862 | 023fe10d | bellard | break;
|
6863 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6864 | 14ce26e7 | bellard | case 0x105: /* syscall */ |
6865 | 14ce26e7 | bellard | /* XXX: is it usable in real mode ? */
|
6866 | 14ce26e7 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6867 | 14ce26e7 | bellard | gen_op_set_cc_op(s->cc_op); |
6868 | 14ce26e7 | bellard | s->cc_op = CC_OP_DYNAMIC; |
6869 | 14ce26e7 | bellard | } |
6870 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6871 | a7812ae4 | pbrook | gen_helper_syscall(tcg_const_i32(s->pc - pc_start)); |
6872 | 14ce26e7 | bellard | gen_eob(s); |
6873 | 14ce26e7 | bellard | break;
|
6874 | 14ce26e7 | bellard | case 0x107: /* sysret */ |
6875 | 14ce26e7 | bellard | if (!s->pe) {
|
6876 | 14ce26e7 | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6877 | 14ce26e7 | bellard | } else {
|
6878 | 14ce26e7 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6879 | 14ce26e7 | bellard | gen_op_set_cc_op(s->cc_op); |
6880 | 14ce26e7 | bellard | s->cc_op = CC_OP_DYNAMIC; |
6881 | 14ce26e7 | bellard | } |
6882 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6883 | a7812ae4 | pbrook | gen_helper_sysret(tcg_const_i32(s->dflag)); |
6884 | aba9d61e | bellard | /* condition codes are modified only in long mode */
|
6885 | aba9d61e | bellard | if (s->lma)
|
6886 | aba9d61e | bellard | s->cc_op = CC_OP_EFLAGS; |
6887 | 14ce26e7 | bellard | gen_eob(s); |
6888 | 14ce26e7 | bellard | } |
6889 | 14ce26e7 | bellard | break;
|
6890 | 14ce26e7 | bellard | #endif
|
6891 | 2c0262af | bellard | case 0x1a2: /* cpuid */ |
6892 | 9575cb94 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6893 | 9575cb94 | bellard | gen_op_set_cc_op(s->cc_op); |
6894 | 9575cb94 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6895 | a7812ae4 | pbrook | gen_helper_cpuid(); |
6896 | 2c0262af | bellard | break;
|
6897 | 2c0262af | bellard | case 0xf4: /* hlt */ |
6898 | 2c0262af | bellard | if (s->cpl != 0) { |
6899 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6900 | 2c0262af | bellard | } else {
|
6901 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6902 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6903 | 94451178 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6904 | a7812ae4 | pbrook | gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); |
6905 | 2c0262af | bellard | s->is_jmp = 3;
|
6906 | 2c0262af | bellard | } |
6907 | 2c0262af | bellard | break;
|
6908 | 2c0262af | bellard | case 0x100: |
6909 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6910 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6911 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
6912 | 2c0262af | bellard | switch(op) {
|
6913 | 2c0262af | bellard | case 0: /* sldt */ |
6914 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6915 | f115e911 | bellard | goto illegal_op;
|
6916 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
6917 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
|
6918 | 2c0262af | bellard | ot = OT_WORD; |
6919 | 2c0262af | bellard | if (mod == 3) |
6920 | 2c0262af | bellard | ot += s->dflag; |
6921 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
6922 | 2c0262af | bellard | break;
|
6923 | 2c0262af | bellard | case 2: /* lldt */ |
6924 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6925 | f115e911 | bellard | goto illegal_op;
|
6926 | 2c0262af | bellard | if (s->cpl != 0) { |
6927 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6928 | 2c0262af | bellard | } else {
|
6929 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
6930 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6931 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6932 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6933 | a7812ae4 | pbrook | gen_helper_lldt(cpu_tmp2_i32); |
6934 | 2c0262af | bellard | } |
6935 | 2c0262af | bellard | break;
|
6936 | 2c0262af | bellard | case 1: /* str */ |
6937 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6938 | f115e911 | bellard | goto illegal_op;
|
6939 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
6940 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
|
6941 | 2c0262af | bellard | ot = OT_WORD; |
6942 | 2c0262af | bellard | if (mod == 3) |
6943 | 2c0262af | bellard | ot += s->dflag; |
6944 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
6945 | 2c0262af | bellard | break;
|
6946 | 2c0262af | bellard | case 3: /* ltr */ |
6947 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6948 | f115e911 | bellard | goto illegal_op;
|
6949 | 2c0262af | bellard | if (s->cpl != 0) { |
6950 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6951 | 2c0262af | bellard | } else {
|
6952 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
6953 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6954 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6955 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6956 | a7812ae4 | pbrook | gen_helper_ltr(cpu_tmp2_i32); |
6957 | 2c0262af | bellard | } |
6958 | 2c0262af | bellard | break;
|
6959 | 2c0262af | bellard | case 4: /* verr */ |
6960 | 2c0262af | bellard | case 5: /* verw */ |
6961 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6962 | f115e911 | bellard | goto illegal_op;
|
6963 | f115e911 | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6964 | f115e911 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6965 | f115e911 | bellard | gen_op_set_cc_op(s->cc_op); |
6966 | f115e911 | bellard | if (op == 4) |
6967 | a7812ae4 | pbrook | gen_helper_verr(cpu_T[0]);
|
6968 | f115e911 | bellard | else
|
6969 | a7812ae4 | pbrook | gen_helper_verw(cpu_T[0]);
|
6970 | f115e911 | bellard | s->cc_op = CC_OP_EFLAGS; |
6971 | f115e911 | bellard | break;
|
6972 | 2c0262af | bellard | default:
|
6973 | 2c0262af | bellard | goto illegal_op;
|
6974 | 2c0262af | bellard | } |
6975 | 2c0262af | bellard | break;
|
6976 | 2c0262af | bellard | case 0x101: |
6977 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6978 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6979 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
6980 | 3d7374c5 | bellard | rm = modrm & 7;
|
6981 | 2c0262af | bellard | switch(op) {
|
6982 | 2c0262af | bellard | case 0: /* sgdt */ |
6983 | 2c0262af | bellard | if (mod == 3) |
6984 | 2c0262af | bellard | goto illegal_op;
|
6985 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
6986 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6987 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
|
6988 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
6989 | aba9d61e | bellard | gen_add_A0_im(s, 2);
|
6990 | 651ba608 | bellard | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
|
6991 | 2c0262af | bellard | if (!s->dflag)
|
6992 | 2c0262af | bellard | gen_op_andl_T0_im(0xffffff);
|
6993 | 57fec1fe | bellard | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
6994 | 2c0262af | bellard | break;
|
6995 | 3d7374c5 | bellard | case 1: |
6996 | 3d7374c5 | bellard | if (mod == 3) { |
6997 | 3d7374c5 | bellard | switch (rm) {
|
6998 | 3d7374c5 | bellard | case 0: /* monitor */ |
6999 | 3d7374c5 | bellard | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
|
7000 | 3d7374c5 | bellard | s->cpl != 0)
|
7001 | 3d7374c5 | bellard | goto illegal_op;
|
7002 | 94451178 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7003 | 94451178 | bellard | gen_op_set_cc_op(s->cc_op); |
7004 | 3d7374c5 | bellard | gen_jmp_im(pc_start - s->cs_base); |
7005 | 3d7374c5 | bellard | #ifdef TARGET_X86_64
|
7006 | 3d7374c5 | bellard | if (s->aflag == 2) { |
7007 | bbf662ee | bellard | gen_op_movq_A0_reg(R_EAX); |
7008 | 5fafdf24 | ths | } else
|
7009 | 3d7374c5 | bellard | #endif
|
7010 | 3d7374c5 | bellard | { |
7011 | bbf662ee | bellard | gen_op_movl_A0_reg(R_EAX); |
7012 | 3d7374c5 | bellard | if (s->aflag == 0) |
7013 | 3d7374c5 | bellard | gen_op_andl_A0_ffff(); |
7014 | 3d7374c5 | bellard | } |
7015 | 3d7374c5 | bellard | gen_add_A0_ds_seg(s); |
7016 | a7812ae4 | pbrook | gen_helper_monitor(cpu_A0); |
7017 | 3d7374c5 | bellard | break;
|
7018 | 3d7374c5 | bellard | case 1: /* mwait */ |
7019 | 3d7374c5 | bellard | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
|
7020 | 3d7374c5 | bellard | s->cpl != 0)
|
7021 | 3d7374c5 | bellard | goto illegal_op;
|
7022 | 3d7374c5 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
7023 | 3d7374c5 | bellard | gen_op_set_cc_op(s->cc_op); |
7024 | 3d7374c5 | bellard | s->cc_op = CC_OP_DYNAMIC; |
7025 | 3d7374c5 | bellard | } |
7026 | 94451178 | bellard | gen_jmp_im(pc_start - s->cs_base); |
7027 | a7812ae4 | pbrook | gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); |
7028 | 3d7374c5 | bellard | gen_eob(s); |
7029 | 3d7374c5 | bellard | break;
|
7030 | 3d7374c5 | bellard | default:
|
7031 | 3d7374c5 | bellard | goto illegal_op;
|
7032 | 3d7374c5 | bellard | } |
7033 | 3d7374c5 | bellard | } else { /* sidt */ |
7034 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
7035 | 3d7374c5 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7036 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
|
7037 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
7038 | 3d7374c5 | bellard | gen_add_A0_im(s, 2);
|
7039 | 651ba608 | bellard | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
|
7040 | 3d7374c5 | bellard | if (!s->dflag)
|
7041 | 3d7374c5 | bellard | gen_op_andl_T0_im(0xffffff);
|
7042 | 57fec1fe | bellard | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
7043 | 3d7374c5 | bellard | } |
7044 | 3d7374c5 | bellard | break;
|
7045 | 2c0262af | bellard | case 2: /* lgdt */ |
7046 | 2c0262af | bellard | case 3: /* lidt */ |
7047 | 0573fbfc | ths | if (mod == 3) { |
7048 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7049 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
7050 | 872929aa | bellard | gen_jmp_im(pc_start - s->cs_base); |
7051 | 0573fbfc | ths | switch(rm) {
|
7052 | 0573fbfc | ths | case 0: /* VMRUN */ |
7053 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK) || !s->pe)
|
7054 | 872929aa | bellard | goto illegal_op;
|
7055 | 872929aa | bellard | if (s->cpl != 0) { |
7056 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7057 | 0573fbfc | ths | break;
|
7058 | 872929aa | bellard | } else {
|
7059 | a7812ae4 | pbrook | gen_helper_vmrun(tcg_const_i32(s->aflag), |
7060 | a7812ae4 | pbrook | tcg_const_i32(s->pc - pc_start)); |
7061 | db620f46 | bellard | tcg_gen_exit_tb(0);
|
7062 | db620f46 | bellard | s->is_jmp = 3;
|
7063 | 872929aa | bellard | } |
7064 | 0573fbfc | ths | break;
|
7065 | 0573fbfc | ths | case 1: /* VMMCALL */ |
7066 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK))
|
7067 | 872929aa | bellard | goto illegal_op;
|
7068 | a7812ae4 | pbrook | gen_helper_vmmcall(); |
7069 | 0573fbfc | ths | break;
|
7070 | 0573fbfc | ths | case 2: /* VMLOAD */ |
7071 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK) || !s->pe)
|
7072 | 872929aa | bellard | goto illegal_op;
|
7073 | 872929aa | bellard | if (s->cpl != 0) { |
7074 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7075 | 872929aa | bellard | break;
|
7076 | 872929aa | bellard | } else {
|
7077 | a7812ae4 | pbrook | gen_helper_vmload(tcg_const_i32(s->aflag)); |
7078 | 872929aa | bellard | } |
7079 | 0573fbfc | ths | break;
|
7080 | 0573fbfc | ths | case 3: /* VMSAVE */ |
7081 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK) || !s->pe)
|
7082 | 872929aa | bellard | goto illegal_op;
|
7083 | 872929aa | bellard | if (s->cpl != 0) { |
7084 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7085 | 872929aa | bellard | break;
|
7086 | 872929aa | bellard | } else {
|
7087 | a7812ae4 | pbrook | gen_helper_vmsave(tcg_const_i32(s->aflag)); |
7088 | 872929aa | bellard | } |
7089 | 0573fbfc | ths | break;
|
7090 | 0573fbfc | ths | case 4: /* STGI */ |
7091 | 872929aa | bellard | if ((!(s->flags & HF_SVME_MASK) &&
|
7092 | 872929aa | bellard | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || |
7093 | 872929aa | bellard | !s->pe) |
7094 | 872929aa | bellard | goto illegal_op;
|
7095 | 872929aa | bellard | if (s->cpl != 0) { |
7096 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7097 | 872929aa | bellard | break;
|
7098 | 872929aa | bellard | } else {
|
7099 | a7812ae4 | pbrook | gen_helper_stgi(); |
7100 | 872929aa | bellard | } |
7101 | 0573fbfc | ths | break;
|
7102 | 0573fbfc | ths | case 5: /* CLGI */ |
7103 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK) || !s->pe)
|
7104 | 872929aa | bellard | goto illegal_op;
|
7105 | 872929aa | bellard | if (s->cpl != 0) { |
7106 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7107 | 872929aa | bellard | break;
|
7108 | 872929aa | bellard | } else {
|
7109 | a7812ae4 | pbrook | gen_helper_clgi(); |
7110 | 872929aa | bellard | } |
7111 | 0573fbfc | ths | break;
|
7112 | 0573fbfc | ths | case 6: /* SKINIT */ |
7113 | 872929aa | bellard | if ((!(s->flags & HF_SVME_MASK) &&
|
7114 | 872929aa | bellard | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || |
7115 | 872929aa | bellard | !s->pe) |
7116 | 872929aa | bellard | goto illegal_op;
|
7117 | a7812ae4 | pbrook | gen_helper_skinit(); |
7118 | 0573fbfc | ths | break;
|
7119 | 0573fbfc | ths | case 7: /* INVLPGA */ |
7120 | 872929aa | bellard | if (!(s->flags & HF_SVME_MASK) || !s->pe)
|
7121 | 872929aa | bellard | goto illegal_op;
|
7122 | 872929aa | bellard | if (s->cpl != 0) { |
7123 | 872929aa | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7124 | 872929aa | bellard | break;
|
7125 | 872929aa | bellard | } else {
|
7126 | a7812ae4 | pbrook | gen_helper_invlpga(tcg_const_i32(s->aflag)); |
7127 | 872929aa | bellard | } |
7128 | 0573fbfc | ths | break;
|
7129 | 0573fbfc | ths | default:
|
7130 | 0573fbfc | ths | goto illegal_op;
|
7131 | 0573fbfc | ths | } |
7132 | 0573fbfc | ths | } else if (s->cpl != 0) { |
7133 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7134 | 2c0262af | bellard | } else {
|
7135 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, |
7136 | 872929aa | bellard | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
|
7137 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7138 | 57fec1fe | bellard | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
7139 | aba9d61e | bellard | gen_add_A0_im(s, 2);
|
7140 | 57fec1fe | bellard | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
7141 | 2c0262af | bellard | if (!s->dflag)
|
7142 | 2c0262af | bellard | gen_op_andl_T0_im(0xffffff);
|
7143 | 2c0262af | bellard | if (op == 2) { |
7144 | 651ba608 | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
|
7145 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
|
7146 | 2c0262af | bellard | } else {
|
7147 | 651ba608 | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
|
7148 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
|
7149 | 2c0262af | bellard | } |
7150 | 2c0262af | bellard | } |
7151 | 2c0262af | bellard | break;
|
7152 | 2c0262af | bellard | case 4: /* smsw */ |
7153 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
7154 | e2542fe2 | Juan Quintela | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
|
7155 | f60d2728 | malc | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7156 | f60d2728 | malc | #else
|
7157 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
7158 | f60d2728 | malc | #endif
|
7159 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
|
7160 | 2c0262af | bellard | break;
|
7161 | 2c0262af | bellard | case 6: /* lmsw */ |
7162 | 2c0262af | bellard | if (s->cpl != 0) { |
7163 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7164 | 2c0262af | bellard | } else {
|
7165 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
7166 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
7167 | a7812ae4 | pbrook | gen_helper_lmsw(cpu_T[0]);
|
7168 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
7169 | d71b9a8b | bellard | gen_eob(s); |
7170 | 2c0262af | bellard | } |
7171 | 2c0262af | bellard | break;
|
7172 | 2c0262af | bellard | case 7: /* invlpg */ |
7173 | 2c0262af | bellard | if (s->cpl != 0) { |
7174 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7175 | 2c0262af | bellard | } else {
|
7176 | 14ce26e7 | bellard | if (mod == 3) { |
7177 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
7178 | 3d7374c5 | bellard | if (CODE64(s) && rm == 0) { |
7179 | 14ce26e7 | bellard | /* swapgs */
|
7180 | 651ba608 | bellard | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
|
7181 | 651ba608 | bellard | tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
|
7182 | 651ba608 | bellard | tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
|
7183 | 651ba608 | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
|
7184 | 5fafdf24 | ths | } else
|
7185 | 14ce26e7 | bellard | #endif
|
7186 | 14ce26e7 | bellard | { |
7187 | 14ce26e7 | bellard | goto illegal_op;
|
7188 | 14ce26e7 | bellard | } |
7189 | 14ce26e7 | bellard | } else {
|
7190 | 9575cb94 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7191 | 9575cb94 | bellard | gen_op_set_cc_op(s->cc_op); |
7192 | 9575cb94 | bellard | gen_jmp_im(pc_start - s->cs_base); |
7193 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7194 | a7812ae4 | pbrook | gen_helper_invlpg(cpu_A0); |
7195 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
7196 | 14ce26e7 | bellard | gen_eob(s); |
7197 | 14ce26e7 | bellard | } |
7198 | 2c0262af | bellard | } |
7199 | 2c0262af | bellard | break;
|
7200 | 2c0262af | bellard | default:
|
7201 | 2c0262af | bellard | goto illegal_op;
|
7202 | 2c0262af | bellard | } |
7203 | 2c0262af | bellard | break;
|
7204 | 3415a4dd | bellard | case 0x108: /* invd */ |
7205 | 3415a4dd | bellard | case 0x109: /* wbinvd */ |
7206 | 3415a4dd | bellard | if (s->cpl != 0) { |
7207 | 3415a4dd | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7208 | 3415a4dd | bellard | } else {
|
7209 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
|
7210 | 3415a4dd | bellard | /* nothing to do */
|
7211 | 3415a4dd | bellard | } |
7212 | 3415a4dd | bellard | break;
|
7213 | 14ce26e7 | bellard | case 0x63: /* arpl or movslS (x86_64) */ |
7214 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
7215 | 14ce26e7 | bellard | if (CODE64(s)) {
|
7216 | 14ce26e7 | bellard | int d_ot;
|
7217 | 14ce26e7 | bellard | /* d_ot is the size of destination */
|
7218 | 14ce26e7 | bellard | d_ot = dflag + OT_WORD; |
7219 | 14ce26e7 | bellard | |
7220 | 14ce26e7 | bellard | modrm = ldub_code(s->pc++); |
7221 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
7222 | 14ce26e7 | bellard | mod = (modrm >> 6) & 3; |
7223 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
7224 | 3b46e624 | ths | |
7225 | 14ce26e7 | bellard | if (mod == 3) { |
7226 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, rm);
|
7227 | 14ce26e7 | bellard | /* sign extend */
|
7228 | 14ce26e7 | bellard | if (d_ot == OT_QUAD)
|
7229 | e108dd01 | bellard | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
7230 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
7231 | 14ce26e7 | bellard | } else {
|
7232 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7233 | 14ce26e7 | bellard | if (d_ot == OT_QUAD) {
|
7234 | 57fec1fe | bellard | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
7235 | 14ce26e7 | bellard | } else {
|
7236 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
7237 | 14ce26e7 | bellard | } |
7238 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
7239 | 14ce26e7 | bellard | } |
7240 | 5fafdf24 | ths | } else
|
7241 | 14ce26e7 | bellard | #endif
|
7242 | 14ce26e7 | bellard | { |
7243 | 3bd7da9e | bellard | int label1;
|
7244 | 1e4840bf | bellard | TCGv t0, t1, t2; |
7245 | 1e4840bf | bellard | |
7246 | 14ce26e7 | bellard | if (!s->pe || s->vm86)
|
7247 | 14ce26e7 | bellard | goto illegal_op;
|
7248 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
7249 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
7250 | a7812ae4 | pbrook | t2 = tcg_temp_local_new(); |
7251 | 3bd7da9e | bellard | ot = OT_WORD; |
7252 | 14ce26e7 | bellard | modrm = ldub_code(s->pc++); |
7253 | 14ce26e7 | bellard | reg = (modrm >> 3) & 7; |
7254 | 14ce26e7 | bellard | mod = (modrm >> 6) & 3; |
7255 | 14ce26e7 | bellard | rm = modrm & 7;
|
7256 | 14ce26e7 | bellard | if (mod != 3) { |
7257 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7258 | 1e4840bf | bellard | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
7259 | 14ce26e7 | bellard | } else {
|
7260 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t0, rm); |
7261 | 14ce26e7 | bellard | } |
7262 | 1e4840bf | bellard | gen_op_mov_v_reg(ot, t1, reg); |
7263 | 1e4840bf | bellard | tcg_gen_andi_tl(cpu_tmp0, t0, 3);
|
7264 | 1e4840bf | bellard | tcg_gen_andi_tl(t1, t1, 3);
|
7265 | 1e4840bf | bellard | tcg_gen_movi_tl(t2, 0);
|
7266 | 3bd7da9e | bellard | label1 = gen_new_label(); |
7267 | 1e4840bf | bellard | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7268 | 1e4840bf | bellard | tcg_gen_andi_tl(t0, t0, ~3);
|
7269 | 1e4840bf | bellard | tcg_gen_or_tl(t0, t0, t1); |
7270 | 1e4840bf | bellard | tcg_gen_movi_tl(t2, CC_Z); |
7271 | 3bd7da9e | bellard | gen_set_label(label1); |
7272 | 14ce26e7 | bellard | if (mod != 3) { |
7273 | 1e4840bf | bellard | gen_op_st_v(ot + s->mem_index, t0, cpu_A0); |
7274 | 14ce26e7 | bellard | } else {
|
7275 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, rm, t0); |
7276 | 14ce26e7 | bellard | } |
7277 | 3bd7da9e | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7278 | 3bd7da9e | bellard | gen_op_set_cc_op(s->cc_op); |
7279 | 3bd7da9e | bellard | gen_compute_eflags(cpu_cc_src); |
7280 | 3bd7da9e | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
7281 | 1e4840bf | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
7282 | 3bd7da9e | bellard | s->cc_op = CC_OP_EFLAGS; |
7283 | 1e4840bf | bellard | tcg_temp_free(t0); |
7284 | 1e4840bf | bellard | tcg_temp_free(t1); |
7285 | 1e4840bf | bellard | tcg_temp_free(t2); |
7286 | f115e911 | bellard | } |
7287 | f115e911 | bellard | break;
|
7288 | 2c0262af | bellard | case 0x102: /* lar */ |
7289 | 2c0262af | bellard | case 0x103: /* lsl */ |
7290 | cec6843e | bellard | { |
7291 | cec6843e | bellard | int label1;
|
7292 | 1e4840bf | bellard | TCGv t0; |
7293 | cec6843e | bellard | if (!s->pe || s->vm86)
|
7294 | cec6843e | bellard | goto illegal_op;
|
7295 | cec6843e | bellard | ot = dflag ? OT_LONG : OT_WORD; |
7296 | cec6843e | bellard | modrm = ldub_code(s->pc++); |
7297 | cec6843e | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
7298 | cec6843e | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
7299 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
7300 | cec6843e | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7301 | cec6843e | bellard | gen_op_set_cc_op(s->cc_op); |
7302 | cec6843e | bellard | if (b == 0x102) |
7303 | a7812ae4 | pbrook | gen_helper_lar(t0, cpu_T[0]);
|
7304 | cec6843e | bellard | else
|
7305 | a7812ae4 | pbrook | gen_helper_lsl(t0, cpu_T[0]);
|
7306 | cec6843e | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7307 | cec6843e | bellard | label1 = gen_new_label(); |
7308 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
|
7309 | 1e4840bf | bellard | gen_op_mov_reg_v(ot, reg, t0); |
7310 | cec6843e | bellard | gen_set_label(label1); |
7311 | cec6843e | bellard | s->cc_op = CC_OP_EFLAGS; |
7312 | 1e4840bf | bellard | tcg_temp_free(t0); |
7313 | cec6843e | bellard | } |
7314 | 2c0262af | bellard | break;
|
7315 | 2c0262af | bellard | case 0x118: |
7316 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
7317 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
7318 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
7319 | 2c0262af | bellard | switch(op) {
|
7320 | 2c0262af | bellard | case 0: /* prefetchnta */ |
7321 | 2c0262af | bellard | case 1: /* prefetchnt0 */ |
7322 | 2c0262af | bellard | case 2: /* prefetchnt0 */ |
7323 | 2c0262af | bellard | case 3: /* prefetchnt0 */ |
7324 | 2c0262af | bellard | if (mod == 3) |
7325 | 2c0262af | bellard | goto illegal_op;
|
7326 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7327 | 2c0262af | bellard | /* nothing more to do */
|
7328 | 2c0262af | bellard | break;
|
7329 | e17a36ce | bellard | default: /* nop (multi byte) */ |
7330 | e17a36ce | bellard | gen_nop_modrm(s, modrm); |
7331 | e17a36ce | bellard | break;
|
7332 | 2c0262af | bellard | } |
7333 | 2c0262af | bellard | break;
|
7334 | e17a36ce | bellard | case 0x119 ... 0x11f: /* nop (multi byte) */ |
7335 | e17a36ce | bellard | modrm = ldub_code(s->pc++); |
7336 | e17a36ce | bellard | gen_nop_modrm(s, modrm); |
7337 | e17a36ce | bellard | break;
|
7338 | 2c0262af | bellard | case 0x120: /* mov reg, crN */ |
7339 | 2c0262af | bellard | case 0x122: /* mov crN, reg */ |
7340 | 2c0262af | bellard | if (s->cpl != 0) { |
7341 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7342 | 2c0262af | bellard | } else {
|
7343 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
7344 | 2c0262af | bellard | if ((modrm & 0xc0) != 0xc0) |
7345 | 2c0262af | bellard | goto illegal_op;
|
7346 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
7347 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
7348 | 14ce26e7 | bellard | if (CODE64(s))
|
7349 | 14ce26e7 | bellard | ot = OT_QUAD; |
7350 | 14ce26e7 | bellard | else
|
7351 | 14ce26e7 | bellard | ot = OT_LONG; |
7352 | 2c0262af | bellard | switch(reg) {
|
7353 | 2c0262af | bellard | case 0: |
7354 | 2c0262af | bellard | case 2: |
7355 | 2c0262af | bellard | case 3: |
7356 | 2c0262af | bellard | case 4: |
7357 | 9230e66e | bellard | case 8: |
7358 | 872929aa | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7359 | 872929aa | bellard | gen_op_set_cc_op(s->cc_op); |
7360 | 872929aa | bellard | gen_jmp_im(pc_start - s->cs_base); |
7361 | 2c0262af | bellard | if (b & 2) { |
7362 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
7363 | a7812ae4 | pbrook | gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
|
7364 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
7365 | 2c0262af | bellard | gen_eob(s); |
7366 | 2c0262af | bellard | } else {
|
7367 | a7812ae4 | pbrook | gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
|
7368 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
7369 | 2c0262af | bellard | } |
7370 | 2c0262af | bellard | break;
|
7371 | 2c0262af | bellard | default:
|
7372 | 2c0262af | bellard | goto illegal_op;
|
7373 | 2c0262af | bellard | } |
7374 | 2c0262af | bellard | } |
7375 | 2c0262af | bellard | break;
|
7376 | 2c0262af | bellard | case 0x121: /* mov reg, drN */ |
7377 | 2c0262af | bellard | case 0x123: /* mov drN, reg */ |
7378 | 2c0262af | bellard | if (s->cpl != 0) { |
7379 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7380 | 2c0262af | bellard | } else {
|
7381 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
7382 | 2c0262af | bellard | if ((modrm & 0xc0) != 0xc0) |
7383 | 2c0262af | bellard | goto illegal_op;
|
7384 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
7385 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
7386 | 14ce26e7 | bellard | if (CODE64(s))
|
7387 | 14ce26e7 | bellard | ot = OT_QUAD; |
7388 | 14ce26e7 | bellard | else
|
7389 | 14ce26e7 | bellard | ot = OT_LONG; |
7390 | 2c0262af | bellard | /* XXX: do it dynamically with CR4.DE bit */
|
7391 | 14ce26e7 | bellard | if (reg == 4 || reg == 5 || reg >= 8) |
7392 | 2c0262af | bellard | goto illegal_op;
|
7393 | 2c0262af | bellard | if (b & 2) { |
7394 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
7395 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
7396 | a7812ae4 | pbrook | gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
|
7397 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
7398 | 2c0262af | bellard | gen_eob(s); |
7399 | 2c0262af | bellard | } else {
|
7400 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
7401 | 651ba608 | bellard | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
|
7402 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
7403 | 2c0262af | bellard | } |
7404 | 2c0262af | bellard | } |
7405 | 2c0262af | bellard | break;
|
7406 | 2c0262af | bellard | case 0x106: /* clts */ |
7407 | 2c0262af | bellard | if (s->cpl != 0) { |
7408 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7409 | 2c0262af | bellard | } else {
|
7410 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
7411 | a7812ae4 | pbrook | gen_helper_clts(); |
7412 | 7eee2a50 | bellard | /* abort block because static cpu state changed */
|
7413 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
7414 | 7eee2a50 | bellard | gen_eob(s); |
7415 | 2c0262af | bellard | } |
7416 | 2c0262af | bellard | break;
|
7417 | 222a3336 | balrog | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
|
7418 | 664e0f19 | bellard | case 0x1c3: /* MOVNTI reg, mem */ |
7419 | 664e0f19 | bellard | if (!(s->cpuid_features & CPUID_SSE2))
|
7420 | 14ce26e7 | bellard | goto illegal_op;
|
7421 | 664e0f19 | bellard | ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
|
7422 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
7423 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
7424 | 664e0f19 | bellard | if (mod == 3) |
7425 | 664e0f19 | bellard | goto illegal_op;
|
7426 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
7427 | 664e0f19 | bellard | /* generate a generic store */
|
7428 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, ot, reg, 1);
|
7429 | 14ce26e7 | bellard | break;
|
7430 | 664e0f19 | bellard | case 0x1ae: |
7431 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
7432 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
7433 | 664e0f19 | bellard | op = (modrm >> 3) & 7; |
7434 | 664e0f19 | bellard | switch(op) {
|
7435 | 664e0f19 | bellard | case 0: /* fxsave */ |
7436 | 5fafdf24 | ths | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
7437 | 0fd14b72 | bellard | (s->flags & HF_EM_MASK)) |
7438 | 14ce26e7 | bellard | goto illegal_op;
|
7439 | 0fd14b72 | bellard | if (s->flags & HF_TS_MASK) {
|
7440 | 0fd14b72 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7441 | 0fd14b72 | bellard | break;
|
7442 | 0fd14b72 | bellard | } |
7443 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7444 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7445 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
7446 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
7447 | a7812ae4 | pbrook | gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
|
7448 | 664e0f19 | bellard | break;
|
7449 | 664e0f19 | bellard | case 1: /* fxrstor */ |
7450 | 5fafdf24 | ths | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
7451 | 0fd14b72 | bellard | (s->flags & HF_EM_MASK)) |
7452 | 14ce26e7 | bellard | goto illegal_op;
|
7453 | 0fd14b72 | bellard | if (s->flags & HF_TS_MASK) {
|
7454 | 0fd14b72 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7455 | 0fd14b72 | bellard | break;
|
7456 | 0fd14b72 | bellard | } |
7457 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7458 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
7459 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
7460 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
7461 | a7812ae4 | pbrook | gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
|
7462 | 664e0f19 | bellard | break;
|
7463 | 664e0f19 | bellard | case 2: /* ldmxcsr */ |
7464 | 664e0f19 | bellard | case 3: /* stmxcsr */ |
7465 | 664e0f19 | bellard | if (s->flags & HF_TS_MASK) {
|
7466 | 664e0f19 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7467 | 664e0f19 | bellard | break;
|
7468 | 14ce26e7 | bellard | } |
7469 | 664e0f19 | bellard | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
|
7470 | 664e0f19 | bellard | mod == 3)
|
7471 | 14ce26e7 | bellard | goto illegal_op;
|
7472 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7473 | 664e0f19 | bellard | if (op == 2) { |
7474 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
7475 | 651ba608 | bellard | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
|
7476 | 14ce26e7 | bellard | } else {
|
7477 | 651ba608 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
|
7478 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
7479 | 14ce26e7 | bellard | } |
7480 | 664e0f19 | bellard | break;
|
7481 | 664e0f19 | bellard | case 5: /* lfence */ |
7482 | 664e0f19 | bellard | case 6: /* mfence */ |
7483 | 664e0f19 | bellard | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE)) |
7484 | 664e0f19 | bellard | goto illegal_op;
|
7485 | 664e0f19 | bellard | break;
|
7486 | 8f091a59 | bellard | case 7: /* sfence / clflush */ |
7487 | 8f091a59 | bellard | if ((modrm & 0xc7) == 0xc0) { |
7488 | 8f091a59 | bellard | /* sfence */
|
7489 | a35f3ec7 | aurel32 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
|
7490 | 8f091a59 | bellard | if (!(s->cpuid_features & CPUID_SSE))
|
7491 | 8f091a59 | bellard | goto illegal_op;
|
7492 | 8f091a59 | bellard | } else {
|
7493 | 8f091a59 | bellard | /* clflush */
|
7494 | 8f091a59 | bellard | if (!(s->cpuid_features & CPUID_CLFLUSH))
|
7495 | 8f091a59 | bellard | goto illegal_op;
|
7496 | 8f091a59 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7497 | 8f091a59 | bellard | } |
7498 | 8f091a59 | bellard | break;
|
7499 | 664e0f19 | bellard | default:
|
7500 | 14ce26e7 | bellard | goto illegal_op;
|
7501 | 14ce26e7 | bellard | } |
7502 | 14ce26e7 | bellard | break;
|
7503 | a35f3ec7 | aurel32 | case 0x10d: /* 3DNow! prefetch(w) */ |
7504 | 8f091a59 | bellard | modrm = ldub_code(s->pc++); |
7505 | a35f3ec7 | aurel32 | mod = (modrm >> 6) & 3; |
7506 | a35f3ec7 | aurel32 | if (mod == 3) |
7507 | a35f3ec7 | aurel32 | goto illegal_op;
|
7508 | 8f091a59 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7509 | 8f091a59 | bellard | /* ignore for now */
|
7510 | 8f091a59 | bellard | break;
|
7511 | 3b21e03e | bellard | case 0x1aa: /* rsm */ |
7512 | 872929aa | bellard | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
7513 | 3b21e03e | bellard | if (!(s->flags & HF_SMM_MASK))
|
7514 | 3b21e03e | bellard | goto illegal_op;
|
7515 | 3b21e03e | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
7516 | 3b21e03e | bellard | gen_op_set_cc_op(s->cc_op); |
7517 | 3b21e03e | bellard | s->cc_op = CC_OP_DYNAMIC; |
7518 | 3b21e03e | bellard | } |
7519 | 3b21e03e | bellard | gen_jmp_im(s->pc - s->cs_base); |
7520 | a7812ae4 | pbrook | gen_helper_rsm(); |
7521 | 3b21e03e | bellard | gen_eob(s); |
7522 | 3b21e03e | bellard | break;
|
7523 | 222a3336 | balrog | case 0x1b8: /* SSE4.2 popcnt */ |
7524 | 222a3336 | balrog | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
|
7525 | 222a3336 | balrog | PREFIX_REPZ) |
7526 | 222a3336 | balrog | goto illegal_op;
|
7527 | 222a3336 | balrog | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
|
7528 | 222a3336 | balrog | goto illegal_op;
|
7529 | 222a3336 | balrog | |
7530 | 222a3336 | balrog | modrm = ldub_code(s->pc++); |
7531 | 222a3336 | balrog | reg = ((modrm >> 3) & 7); |
7532 | 222a3336 | balrog | |
7533 | 222a3336 | balrog | if (s->prefix & PREFIX_DATA)
|
7534 | 222a3336 | balrog | ot = OT_WORD; |
7535 | 222a3336 | balrog | else if (s->dflag != 2) |
7536 | 222a3336 | balrog | ot = OT_LONG; |
7537 | 222a3336 | balrog | else
|
7538 | 222a3336 | balrog | ot = OT_QUAD; |
7539 | 222a3336 | balrog | |
7540 | 222a3336 | balrog | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
7541 | a7812ae4 | pbrook | gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot)); |
7542 | 222a3336 | balrog | gen_op_mov_reg_T0(ot, reg); |
7543 | fdb0d09d | balrog | |
7544 | fdb0d09d | balrog | s->cc_op = CC_OP_EFLAGS; |
7545 | 222a3336 | balrog | break;
|
7546 | a35f3ec7 | aurel32 | case 0x10e ... 0x10f: |
7547 | a35f3ec7 | aurel32 | /* 3DNow! instructions, ignore prefixes */
|
7548 | a35f3ec7 | aurel32 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); |
7549 | 664e0f19 | bellard | case 0x110 ... 0x117: |
7550 | 664e0f19 | bellard | case 0x128 ... 0x12f: |
7551 | 4242b1bd | balrog | case 0x138 ... 0x13a: |
7552 | 664e0f19 | bellard | case 0x150 ... 0x177: |
7553 | 664e0f19 | bellard | case 0x17c ... 0x17f: |
7554 | 664e0f19 | bellard | case 0x1c2: |
7555 | 664e0f19 | bellard | case 0x1c4 ... 0x1c6: |
7556 | 664e0f19 | bellard | case 0x1d0 ... 0x1fe: |
7557 | 664e0f19 | bellard | gen_sse(s, b, pc_start, rex_r); |
7558 | 664e0f19 | bellard | break;
|
7559 | 2c0262af | bellard | default:
|
7560 | 2c0262af | bellard | goto illegal_op;
|
7561 | 2c0262af | bellard | } |
7562 | 2c0262af | bellard | /* lock generation */
|
7563 | 2c0262af | bellard | if (s->prefix & PREFIX_LOCK)
|
7564 | a7812ae4 | pbrook | gen_helper_unlock(); |
7565 | 2c0262af | bellard | return s->pc;
|
7566 | 2c0262af | bellard | illegal_op:
|
7567 | ab1f142b | bellard | if (s->prefix & PREFIX_LOCK)
|
7568 | a7812ae4 | pbrook | gen_helper_unlock(); |
7569 | 2c0262af | bellard | /* XXX: ensure that no lock was generated */
|
7570 | 2c0262af | bellard | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); |
7571 | 2c0262af | bellard | return s->pc;
|
7572 | 2c0262af | bellard | } |
7573 | 2c0262af | bellard | |
7574 | 2c0262af | bellard | void optimize_flags_init(void) |
7575 | 2c0262af | bellard | { |
7576 | b6abf97d | bellard | #if TCG_TARGET_REG_BITS == 32 |
7577 | b6abf97d | bellard | assert(sizeof(CCTable) == (1 << 3)); |
7578 | b6abf97d | bellard | #else
|
7579 | b6abf97d | bellard | assert(sizeof(CCTable) == (1 << 4)); |
7580 | b6abf97d | bellard | #endif
|
7581 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
7582 | a7812ae4 | pbrook | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, |
7583 | a7812ae4 | pbrook | offsetof(CPUState, cc_op), "cc_op");
|
7584 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
7585 | a7812ae4 | pbrook | "cc_src");
|
7586 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
7587 | a7812ae4 | pbrook | "cc_dst");
|
7588 | a7812ae4 | pbrook | cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp), |
7589 | a7812ae4 | pbrook | "cc_tmp");
|
7590 | 437a88a5 | bellard | |
7591 | 437a88a5 | bellard | /* register helpers */
|
7592 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
7593 | 437a88a5 | bellard | #include "helper.h" |
7594 | 2c0262af | bellard | } |
7595 | 2c0262af | bellard | |
7596 | 2c0262af | bellard | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
7597 | 2c0262af | bellard | basic block 'tb'. If search_pc is TRUE, also generate PC
|
7598 | 2c0262af | bellard | information for each intermediate instruction. */
|
7599 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(CPUState *env, |
7600 | 2cfc5f17 | ths | TranslationBlock *tb, |
7601 | 2cfc5f17 | ths | int search_pc)
|
7602 | 2c0262af | bellard | { |
7603 | 2c0262af | bellard | DisasContext dc1, *dc = &dc1; |
7604 | 14ce26e7 | bellard | target_ulong pc_ptr; |
7605 | 2c0262af | bellard | uint16_t *gen_opc_end; |
7606 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
7607 | c068688b | j_mayer | int j, lj, cflags;
|
7608 | c068688b | j_mayer | uint64_t flags; |
7609 | 14ce26e7 | bellard | target_ulong pc_start; |
7610 | 14ce26e7 | bellard | target_ulong cs_base; |
7611 | 2e70f6ef | pbrook | int num_insns;
|
7612 | 2e70f6ef | pbrook | int max_insns;
|
7613 | 3b46e624 | ths | |
7614 | 2c0262af | bellard | /* generate intermediate code */
|
7615 | 14ce26e7 | bellard | pc_start = tb->pc; |
7616 | 14ce26e7 | bellard | cs_base = tb->cs_base; |
7617 | 2c0262af | bellard | flags = tb->flags; |
7618 | d720b93d | bellard | cflags = tb->cflags; |
7619 | 3a1d9b8b | bellard | |
7620 | 4f31916f | bellard | dc->pe = (flags >> HF_PE_SHIFT) & 1;
|
7621 | 2c0262af | bellard | dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
|
7622 | 2c0262af | bellard | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
|
7623 | 2c0262af | bellard | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
|
7624 | 2c0262af | bellard | dc->f_st = 0;
|
7625 | 2c0262af | bellard | dc->vm86 = (flags >> VM_SHIFT) & 1;
|
7626 | 2c0262af | bellard | dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
|
7627 | 2c0262af | bellard | dc->iopl = (flags >> IOPL_SHIFT) & 3;
|
7628 | 2c0262af | bellard | dc->tf = (flags >> TF_SHIFT) & 1;
|
7629 | 34865134 | bellard | dc->singlestep_enabled = env->singlestep_enabled; |
7630 | 2c0262af | bellard | dc->cc_op = CC_OP_DYNAMIC; |
7631 | 2c0262af | bellard | dc->cs_base = cs_base; |
7632 | 2c0262af | bellard | dc->tb = tb; |
7633 | 2c0262af | bellard | dc->popl_esp_hack = 0;
|
7634 | 2c0262af | bellard | /* select memory access functions */
|
7635 | 2c0262af | bellard | dc->mem_index = 0;
|
7636 | 2c0262af | bellard | if (flags & HF_SOFTMMU_MASK) {
|
7637 | 2c0262af | bellard | if (dc->cpl == 3) |
7638 | 14ce26e7 | bellard | dc->mem_index = 2 * 4; |
7639 | 2c0262af | bellard | else
|
7640 | 14ce26e7 | bellard | dc->mem_index = 1 * 4; |
7641 | 2c0262af | bellard | } |
7642 | 14ce26e7 | bellard | dc->cpuid_features = env->cpuid_features; |
7643 | 3d7374c5 | bellard | dc->cpuid_ext_features = env->cpuid_ext_features; |
7644 | e771edab | aurel32 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
7645 | 12e26b75 | bellard | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
7646 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
7647 | 14ce26e7 | bellard | dc->lma = (flags >> HF_LMA_SHIFT) & 1;
|
7648 | 14ce26e7 | bellard | dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
|
7649 | 14ce26e7 | bellard | #endif
|
7650 | 7eee2a50 | bellard | dc->flags = flags; |
7651 | a2cc3b24 | bellard | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7652 | a2cc3b24 | bellard | (flags & HF_INHIBIT_IRQ_MASK) |
7653 | 415fa2ea | bellard | #ifndef CONFIG_SOFTMMU
|
7654 | 2c0262af | bellard | || (flags & HF_SOFTMMU_MASK) |
7655 | 2c0262af | bellard | #endif
|
7656 | 2c0262af | bellard | ); |
7657 | 4f31916f | bellard | #if 0
|
7658 | 4f31916f | bellard | /* check addseg logic */
|
7659 | dc196a57 | bellard | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
|
7660 | 4f31916f | bellard | printf("ERROR addseg\n");
|
7661 | 4f31916f | bellard | #endif
|
7662 | 4f31916f | bellard | |
7663 | a7812ae4 | pbrook | cpu_T[0] = tcg_temp_new();
|
7664 | a7812ae4 | pbrook | cpu_T[1] = tcg_temp_new();
|
7665 | a7812ae4 | pbrook | cpu_A0 = tcg_temp_new(); |
7666 | a7812ae4 | pbrook | cpu_T3 = tcg_temp_new(); |
7667 | a7812ae4 | pbrook | |
7668 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
7669 | a7812ae4 | pbrook | cpu_tmp1_i64 = tcg_temp_new_i64(); |
7670 | a7812ae4 | pbrook | cpu_tmp2_i32 = tcg_temp_new_i32(); |
7671 | a7812ae4 | pbrook | cpu_tmp3_i32 = tcg_temp_new_i32(); |
7672 | a7812ae4 | pbrook | cpu_tmp4 = tcg_temp_new(); |
7673 | a7812ae4 | pbrook | cpu_tmp5 = tcg_temp_new(); |
7674 | a7812ae4 | pbrook | cpu_tmp6 = tcg_temp_new(); |
7675 | a7812ae4 | pbrook | cpu_ptr0 = tcg_temp_new_ptr(); |
7676 | a7812ae4 | pbrook | cpu_ptr1 = tcg_temp_new_ptr(); |
7677 | 57fec1fe | bellard | |
7678 | 2c0262af | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
7679 | 2c0262af | bellard | |
7680 | 2c0262af | bellard | dc->is_jmp = DISAS_NEXT; |
7681 | 2c0262af | bellard | pc_ptr = pc_start; |
7682 | 2c0262af | bellard | lj = -1;
|
7683 | 2e70f6ef | pbrook | num_insns = 0;
|
7684 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
7685 | 2e70f6ef | pbrook | if (max_insns == 0) |
7686 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
7687 | 2c0262af | bellard | |
7688 | 2e70f6ef | pbrook | gen_icount_start(); |
7689 | 2c0262af | bellard | for(;;) {
|
7690 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
7691 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
7692 | a2397807 | Jan Kiszka | if (bp->pc == pc_ptr &&
|
7693 | a2397807 | Jan Kiszka | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { |
7694 | 2c0262af | bellard | gen_debug(dc, pc_ptr - dc->cs_base); |
7695 | 2c0262af | bellard | break;
|
7696 | 2c0262af | bellard | } |
7697 | 2c0262af | bellard | } |
7698 | 2c0262af | bellard | } |
7699 | 2c0262af | bellard | if (search_pc) {
|
7700 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
7701 | 2c0262af | bellard | if (lj < j) {
|
7702 | 2c0262af | bellard | lj++; |
7703 | 2c0262af | bellard | while (lj < j)
|
7704 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
7705 | 2c0262af | bellard | } |
7706 | 14ce26e7 | bellard | gen_opc_pc[lj] = pc_ptr; |
7707 | 2c0262af | bellard | gen_opc_cc_op[lj] = dc->cc_op; |
7708 | 2c0262af | bellard | gen_opc_instr_start[lj] = 1;
|
7709 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
7710 | 2c0262af | bellard | } |
7711 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7712 | 2e70f6ef | pbrook | gen_io_start(); |
7713 | 2e70f6ef | pbrook | |
7714 | 2c0262af | bellard | pc_ptr = disas_insn(dc, pc_ptr); |
7715 | 2e70f6ef | pbrook | num_insns++; |
7716 | 2c0262af | bellard | /* stop translation if indicated */
|
7717 | 2c0262af | bellard | if (dc->is_jmp)
|
7718 | 2c0262af | bellard | break;
|
7719 | 2c0262af | bellard | /* if single step mode, we generate only one instruction and
|
7720 | 2c0262af | bellard | generate an exception */
|
7721 | a2cc3b24 | bellard | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
|
7722 | a2cc3b24 | bellard | the flag and abort the translation to give the irqs a
|
7723 | a2cc3b24 | bellard | change to be happen */
|
7724 | 5fafdf24 | ths | if (dc->tf || dc->singlestep_enabled ||
|
7725 | 2e70f6ef | pbrook | (flags & HF_INHIBIT_IRQ_MASK)) { |
7726 | 14ce26e7 | bellard | gen_jmp_im(pc_ptr - dc->cs_base); |
7727 | 2c0262af | bellard | gen_eob(dc); |
7728 | 2c0262af | bellard | break;
|
7729 | 2c0262af | bellard | } |
7730 | 2c0262af | bellard | /* if too long translation, stop generation too */
|
7731 | 2c0262af | bellard | if (gen_opc_ptr >= gen_opc_end ||
|
7732 | 2e70f6ef | pbrook | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
|
7733 | 2e70f6ef | pbrook | num_insns >= max_insns) { |
7734 | 14ce26e7 | bellard | gen_jmp_im(pc_ptr - dc->cs_base); |
7735 | 2c0262af | bellard | gen_eob(dc); |
7736 | 2c0262af | bellard | break;
|
7737 | 2c0262af | bellard | } |
7738 | 1b530a6d | aurel32 | if (singlestep) {
|
7739 | 1b530a6d | aurel32 | gen_jmp_im(pc_ptr - dc->cs_base); |
7740 | 1b530a6d | aurel32 | gen_eob(dc); |
7741 | 1b530a6d | aurel32 | break;
|
7742 | 1b530a6d | aurel32 | } |
7743 | 2c0262af | bellard | } |
7744 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
7745 | 2e70f6ef | pbrook | gen_io_end(); |
7746 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
7747 | 2c0262af | bellard | *gen_opc_ptr = INDEX_op_end; |
7748 | 2c0262af | bellard | /* we don't forget to fill the last values */
|
7749 | 2c0262af | bellard | if (search_pc) {
|
7750 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
7751 | 2c0262af | bellard | lj++; |
7752 | 2c0262af | bellard | while (lj <= j)
|
7753 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
7754 | 2c0262af | bellard | } |
7755 | 3b46e624 | ths | |
7756 | 2c0262af | bellard | #ifdef DEBUG_DISAS
|
7757 | 93fcfe39 | aliguori | log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP); |
7758 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
7759 | 14ce26e7 | bellard | int disas_flags;
|
7760 | 93fcfe39 | aliguori | qemu_log("----------------\n");
|
7761 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
7762 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
7763 | 14ce26e7 | bellard | if (dc->code64)
|
7764 | 14ce26e7 | bellard | disas_flags = 2;
|
7765 | 14ce26e7 | bellard | else
|
7766 | 14ce26e7 | bellard | #endif
|
7767 | 14ce26e7 | bellard | disas_flags = !dc->code32; |
7768 | 93fcfe39 | aliguori | log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); |
7769 | 93fcfe39 | aliguori | qemu_log("\n");
|
7770 | 2c0262af | bellard | } |
7771 | 2c0262af | bellard | #endif
|
7772 | 2c0262af | bellard | |
7773 | 2e70f6ef | pbrook | if (!search_pc) {
|
7774 | 2c0262af | bellard | tb->size = pc_ptr - pc_start; |
7775 | 2e70f6ef | pbrook | tb->icount = num_insns; |
7776 | 2e70f6ef | pbrook | } |
7777 | 2c0262af | bellard | } |
7778 | 2c0262af | bellard | |
7779 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
7780 | 2c0262af | bellard | { |
7781 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
7782 | 2c0262af | bellard | } |
7783 | 2c0262af | bellard | |
7784 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
7785 | 2c0262af | bellard | { |
7786 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
7787 | 2c0262af | bellard | } |
7788 | 2c0262af | bellard | |
7789 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
7790 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
7791 | d2856f1a | aurel32 | { |
7792 | d2856f1a | aurel32 | int cc_op;
|
7793 | d2856f1a | aurel32 | #ifdef DEBUG_DISAS
|
7794 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
|
7795 | d2856f1a | aurel32 | int i;
|
7796 | 93fcfe39 | aliguori | qemu_log("RESTORE:\n");
|
7797 | d2856f1a | aurel32 | for(i = 0;i <= pc_pos; i++) { |
7798 | d2856f1a | aurel32 | if (gen_opc_instr_start[i]) {
|
7799 | 93fcfe39 | aliguori | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); |
7800 | d2856f1a | aurel32 | } |
7801 | d2856f1a | aurel32 | } |
7802 | 93fcfe39 | aliguori | qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
7803 | d2856f1a | aurel32 | searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, |
7804 | d2856f1a | aurel32 | (uint32_t)tb->cs_base); |
7805 | d2856f1a | aurel32 | } |
7806 | d2856f1a | aurel32 | #endif
|
7807 | d2856f1a | aurel32 | env->eip = gen_opc_pc[pc_pos] - tb->cs_base; |
7808 | d2856f1a | aurel32 | cc_op = gen_opc_cc_op[pc_pos]; |
7809 | d2856f1a | aurel32 | if (cc_op != CC_OP_DYNAMIC)
|
7810 | d2856f1a | aurel32 | env->cc_op = cc_op; |
7811 | d2856f1a | aurel32 | } |