root / hw / ppc405_uc.c @ 067d01de
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/*
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* QEMU PowerPC 405 embedded processors emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc405.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "qemu-log.h" |
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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#define DEBUG_GPIO
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#define DEBUG_SERIAL
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#define DEBUG_OCM
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//#define DEBUG_I2C
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#define DEBUG_GPT
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#define DEBUG_MAL
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#define DEBUG_CLOCKS
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//#define DEBUG_CLOCKS_LL
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
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uint32_t flags) |
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{ |
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ram_addr_t bdloc; |
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int i, n;
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/* We put the bd structure at the top of memory */
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if (bd->bi_memsize >= 0x01000000UL) |
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bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
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else
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bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
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stl_phys(bdloc + 0x00, bd->bi_memstart);
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stl_phys(bdloc + 0x04, bd->bi_memsize);
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stl_phys(bdloc + 0x08, bd->bi_flashstart);
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stl_phys(bdloc + 0x0C, bd->bi_flashsize);
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stl_phys(bdloc + 0x10, bd->bi_flashoffset);
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stl_phys(bdloc + 0x14, bd->bi_sramstart);
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stl_phys(bdloc + 0x18, bd->bi_sramsize);
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stl_phys(bdloc + 0x1C, bd->bi_bootflags);
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stl_phys(bdloc + 0x20, bd->bi_ipaddr);
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for (i = 0; i < 6; i++) |
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stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
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stl_phys(bdloc + 0x2C, bd->bi_intfreq);
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stl_phys(bdloc + 0x30, bd->bi_busfreq);
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stl_phys(bdloc + 0x34, bd->bi_baudrate);
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for (i = 0; i < 4; i++) |
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stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
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for (i = 0; i < 32; i++) |
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stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
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stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
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stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
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for (i = 0; i < 6; i++) |
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stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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n = 0x6A;
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if (flags & 0x00000001) { |
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for (i = 0; i < 6; i++) |
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stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]); |
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} |
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stl_phys(bdloc + n, bd->bi_opbfreq); |
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n += 4;
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for (i = 0; i < 2; i++) { |
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stl_phys(bdloc + n, bd->bi_iic_fast[i]); |
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n += 4;
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} |
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return bdloc;
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} |
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/*****************************************************************************/
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/* Shared peripherals */
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/*****************************************************************************/
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/* Peripheral local bus arbitrer */
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enum {
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PLB0_BESR = 0x084,
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PLB0_BEAR = 0x086,
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PLB0_ACR = 0x087,
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}; |
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typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
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struct ppc4xx_plb_t {
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uint32_t acr; |
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uint32_t bear; |
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uint32_t besr; |
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}; |
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static target_ulong dcr_read_plb (void *opaque, int dcrn) |
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{ |
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ppc4xx_plb_t *plb; |
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target_ulong ret; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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ret = plb->acr; |
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break;
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case PLB0_BEAR:
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ret = plb->bear; |
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break;
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case PLB0_BESR:
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ret = plb->besr; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
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{ |
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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switch (dcrn) {
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case PLB0_ACR:
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/* We don't care about the actual parameters written as
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* we don't manage any priorities on the bus
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*/
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plb->acr = val & 0xF8000000;
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break;
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case PLB0_BEAR:
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/* Read only */
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break;
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case PLB0_BESR:
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/* Write-clear */
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plb->besr &= ~val; |
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break;
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} |
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} |
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static void ppc4xx_plb_reset (void *opaque) |
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{ |
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ppc4xx_plb_t *plb; |
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plb = opaque; |
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plb->acr = 0x00000000;
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plb->bear = 0x00000000;
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plb->besr = 0x00000000;
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} |
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static void ppc4xx_plb_init(CPUState *env) |
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{ |
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ppc4xx_plb_t *plb; |
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plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
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ppc4xx_plb_reset(plb); |
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qemu_register_reset(ppc4xx_plb_reset, plb); |
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} |
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/*****************************************************************************/
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/* PLB to OPB bridge */
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enum {
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POB0_BESR0 = 0x0A0,
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POB0_BESR1 = 0x0A2,
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POB0_BEAR = 0x0A4,
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}; |
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typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
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struct ppc4xx_pob_t {
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uint32_t bear; |
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uint32_t besr[2];
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}; |
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static target_ulong dcr_read_pob (void *opaque, int dcrn) |
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{ |
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ppc4xx_pob_t *pob; |
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target_ulong ret; |
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pob = opaque; |
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switch (dcrn) {
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case POB0_BEAR:
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ret = pob->bear; |
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break;
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case POB0_BESR0:
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case POB0_BESR1:
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ret = pob->besr[dcrn - POB0_BESR0]; |
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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} |
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return ret;
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} |
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static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
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{ |
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ppc4xx_pob_t *pob; |
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pob = opaque; |
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switch (dcrn) {
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case POB0_BEAR:
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/* Read only */
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break;
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case POB0_BESR0:
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case POB0_BESR1:
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/* Write-clear */
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pob->besr[dcrn - POB0_BESR0] &= ~val; |
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break;
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} |
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} |
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static void ppc4xx_pob_reset (void *opaque) |
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{ |
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ppc4xx_pob_t *pob; |
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pob = opaque; |
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/* No error */
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pob->bear = 0x00000000;
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pob->besr[0] = 0x0000000; |
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pob->besr[1] = 0x0000000; |
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} |
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static void ppc4xx_pob_init(CPUState *env) |
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{ |
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ppc4xx_pob_t *pob; |
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pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
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ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
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qemu_register_reset(ppc4xx_pob_reset, pob); |
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ppc4xx_pob_reset(pob); |
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} |
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/*****************************************************************************/
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/* OPB arbitrer */
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typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
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struct ppc4xx_opba_t {
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uint8_t cr; |
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uint8_t pr; |
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}; |
263 |
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static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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ppc4xx_opba_t *opba; |
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uint32_t ret; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
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#endif
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opba = opaque; |
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switch (addr) {
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case 0x00: |
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ret = opba->cr; |
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break;
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case 0x01: |
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ret = opba->pr; |
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break;
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default:
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ret = 0x00;
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break;
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} |
284 |
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return ret;
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} |
287 |
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static void opba_writeb (void *opaque, |
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target_phys_addr_t addr, uint32_t value) |
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{ |
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ppc4xx_opba_t *opba; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
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value); |
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#endif
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opba = opaque; |
298 |
switch (addr) {
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case 0x00: |
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opba->cr = value & 0xF8;
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break;
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case 0x01: |
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opba->pr = value & 0xFF;
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break;
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default:
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break;
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} |
308 |
} |
309 |
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static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t ret; |
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
316 |
#endif
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ret = opba_readb(opaque, addr) << 8;
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ret |= opba_readb(opaque, addr + 1);
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return ret;
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} |
322 |
|
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static void opba_writew (void *opaque, |
324 |
target_phys_addr_t addr, uint32_t value) |
325 |
{ |
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
328 |
value); |
329 |
#endif
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opba_writeb(opaque, addr, value >> 8);
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opba_writeb(opaque, addr + 1, value);
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332 |
} |
333 |
|
334 |
static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
335 |
{ |
336 |
uint32_t ret; |
337 |
|
338 |
#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
340 |
#endif
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ret = opba_readb(opaque, addr) << 24;
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ret |= opba_readb(opaque, addr + 1) << 16; |
343 |
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return ret;
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} |
346 |
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347 |
static void opba_writel (void *opaque, |
348 |
target_phys_addr_t addr, uint32_t value) |
349 |
{ |
350 |
#ifdef DEBUG_OPBA
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351 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
352 |
value); |
353 |
#endif
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354 |
opba_writeb(opaque, addr, value >> 24);
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355 |
opba_writeb(opaque, addr + 1, value >> 16); |
356 |
} |
357 |
|
358 |
static CPUReadMemoryFunc * const opba_read[] = { |
359 |
&opba_readb, |
360 |
&opba_readw, |
361 |
&opba_readl, |
362 |
}; |
363 |
|
364 |
static CPUWriteMemoryFunc * const opba_write[] = { |
365 |
&opba_writeb, |
366 |
&opba_writew, |
367 |
&opba_writel, |
368 |
}; |
369 |
|
370 |
static void ppc4xx_opba_reset (void *opaque) |
371 |
{ |
372 |
ppc4xx_opba_t *opba; |
373 |
|
374 |
opba = opaque; |
375 |
opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
376 |
opba->pr = 0x11;
|
377 |
} |
378 |
|
379 |
static void ppc4xx_opba_init(target_phys_addr_t base) |
380 |
{ |
381 |
ppc4xx_opba_t *opba; |
382 |
int io;
|
383 |
|
384 |
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
385 |
#ifdef DEBUG_OPBA
|
386 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
387 |
#endif
|
388 |
io = cpu_register_io_memory(opba_read, opba_write, opba); |
389 |
cpu_register_physical_memory(base, 0x002, io);
|
390 |
ppc4xx_opba_reset(opba); |
391 |
qemu_register_reset(ppc4xx_opba_reset, opba); |
392 |
} |
393 |
|
394 |
/*****************************************************************************/
|
395 |
/* Code decompression controller */
|
396 |
/* XXX: TODO */
|
397 |
|
398 |
/*****************************************************************************/
|
399 |
/* Peripheral controller */
|
400 |
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
401 |
struct ppc4xx_ebc_t {
|
402 |
uint32_t addr; |
403 |
uint32_t bcr[8];
|
404 |
uint32_t bap[8];
|
405 |
uint32_t bear; |
406 |
uint32_t besr0; |
407 |
uint32_t besr1; |
408 |
uint32_t cfg; |
409 |
}; |
410 |
|
411 |
enum {
|
412 |
EBC0_CFGADDR = 0x012,
|
413 |
EBC0_CFGDATA = 0x013,
|
414 |
}; |
415 |
|
416 |
static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
417 |
{ |
418 |
ppc4xx_ebc_t *ebc; |
419 |
target_ulong ret; |
420 |
|
421 |
ebc = opaque; |
422 |
switch (dcrn) {
|
423 |
case EBC0_CFGADDR:
|
424 |
ret = ebc->addr; |
425 |
break;
|
426 |
case EBC0_CFGDATA:
|
427 |
switch (ebc->addr) {
|
428 |
case 0x00: /* B0CR */ |
429 |
ret = ebc->bcr[0];
|
430 |
break;
|
431 |
case 0x01: /* B1CR */ |
432 |
ret = ebc->bcr[1];
|
433 |
break;
|
434 |
case 0x02: /* B2CR */ |
435 |
ret = ebc->bcr[2];
|
436 |
break;
|
437 |
case 0x03: /* B3CR */ |
438 |
ret = ebc->bcr[3];
|
439 |
break;
|
440 |
case 0x04: /* B4CR */ |
441 |
ret = ebc->bcr[4];
|
442 |
break;
|
443 |
case 0x05: /* B5CR */ |
444 |
ret = ebc->bcr[5];
|
445 |
break;
|
446 |
case 0x06: /* B6CR */ |
447 |
ret = ebc->bcr[6];
|
448 |
break;
|
449 |
case 0x07: /* B7CR */ |
450 |
ret = ebc->bcr[7];
|
451 |
break;
|
452 |
case 0x10: /* B0AP */ |
453 |
ret = ebc->bap[0];
|
454 |
break;
|
455 |
case 0x11: /* B1AP */ |
456 |
ret = ebc->bap[1];
|
457 |
break;
|
458 |
case 0x12: /* B2AP */ |
459 |
ret = ebc->bap[2];
|
460 |
break;
|
461 |
case 0x13: /* B3AP */ |
462 |
ret = ebc->bap[3];
|
463 |
break;
|
464 |
case 0x14: /* B4AP */ |
465 |
ret = ebc->bap[4];
|
466 |
break;
|
467 |
case 0x15: /* B5AP */ |
468 |
ret = ebc->bap[5];
|
469 |
break;
|
470 |
case 0x16: /* B6AP */ |
471 |
ret = ebc->bap[6];
|
472 |
break;
|
473 |
case 0x17: /* B7AP */ |
474 |
ret = ebc->bap[7];
|
475 |
break;
|
476 |
case 0x20: /* BEAR */ |
477 |
ret = ebc->bear; |
478 |
break;
|
479 |
case 0x21: /* BESR0 */ |
480 |
ret = ebc->besr0; |
481 |
break;
|
482 |
case 0x22: /* BESR1 */ |
483 |
ret = ebc->besr1; |
484 |
break;
|
485 |
case 0x23: /* CFG */ |
486 |
ret = ebc->cfg; |
487 |
break;
|
488 |
default:
|
489 |
ret = 0x00000000;
|
490 |
break;
|
491 |
} |
492 |
default:
|
493 |
ret = 0x00000000;
|
494 |
break;
|
495 |
} |
496 |
|
497 |
return ret;
|
498 |
} |
499 |
|
500 |
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
501 |
{ |
502 |
ppc4xx_ebc_t *ebc; |
503 |
|
504 |
ebc = opaque; |
505 |
switch (dcrn) {
|
506 |
case EBC0_CFGADDR:
|
507 |
ebc->addr = val; |
508 |
break;
|
509 |
case EBC0_CFGDATA:
|
510 |
switch (ebc->addr) {
|
511 |
case 0x00: /* B0CR */ |
512 |
break;
|
513 |
case 0x01: /* B1CR */ |
514 |
break;
|
515 |
case 0x02: /* B2CR */ |
516 |
break;
|
517 |
case 0x03: /* B3CR */ |
518 |
break;
|
519 |
case 0x04: /* B4CR */ |
520 |
break;
|
521 |
case 0x05: /* B5CR */ |
522 |
break;
|
523 |
case 0x06: /* B6CR */ |
524 |
break;
|
525 |
case 0x07: /* B7CR */ |
526 |
break;
|
527 |
case 0x10: /* B0AP */ |
528 |
break;
|
529 |
case 0x11: /* B1AP */ |
530 |
break;
|
531 |
case 0x12: /* B2AP */ |
532 |
break;
|
533 |
case 0x13: /* B3AP */ |
534 |
break;
|
535 |
case 0x14: /* B4AP */ |
536 |
break;
|
537 |
case 0x15: /* B5AP */ |
538 |
break;
|
539 |
case 0x16: /* B6AP */ |
540 |
break;
|
541 |
case 0x17: /* B7AP */ |
542 |
break;
|
543 |
case 0x20: /* BEAR */ |
544 |
break;
|
545 |
case 0x21: /* BESR0 */ |
546 |
break;
|
547 |
case 0x22: /* BESR1 */ |
548 |
break;
|
549 |
case 0x23: /* CFG */ |
550 |
break;
|
551 |
default:
|
552 |
break;
|
553 |
} |
554 |
break;
|
555 |
default:
|
556 |
break;
|
557 |
} |
558 |
} |
559 |
|
560 |
static void ebc_reset (void *opaque) |
561 |
{ |
562 |
ppc4xx_ebc_t *ebc; |
563 |
int i;
|
564 |
|
565 |
ebc = opaque; |
566 |
ebc->addr = 0x00000000;
|
567 |
ebc->bap[0] = 0x7F8FFE80; |
568 |
ebc->bcr[0] = 0xFFE28000; |
569 |
for (i = 0; i < 8; i++) { |
570 |
ebc->bap[i] = 0x00000000;
|
571 |
ebc->bcr[i] = 0x00000000;
|
572 |
} |
573 |
ebc->besr0 = 0x00000000;
|
574 |
ebc->besr1 = 0x00000000;
|
575 |
ebc->cfg = 0x80400000;
|
576 |
} |
577 |
|
578 |
static void ppc405_ebc_init(CPUState *env) |
579 |
{ |
580 |
ppc4xx_ebc_t *ebc; |
581 |
|
582 |
ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
583 |
ebc_reset(ebc); |
584 |
qemu_register_reset(&ebc_reset, ebc); |
585 |
ppc_dcr_register(env, EBC0_CFGADDR, |
586 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
587 |
ppc_dcr_register(env, EBC0_CFGDATA, |
588 |
ebc, &dcr_read_ebc, &dcr_write_ebc); |
589 |
} |
590 |
|
591 |
/*****************************************************************************/
|
592 |
/* DMA controller */
|
593 |
enum {
|
594 |
DMA0_CR0 = 0x100,
|
595 |
DMA0_CT0 = 0x101,
|
596 |
DMA0_DA0 = 0x102,
|
597 |
DMA0_SA0 = 0x103,
|
598 |
DMA0_SG0 = 0x104,
|
599 |
DMA0_CR1 = 0x108,
|
600 |
DMA0_CT1 = 0x109,
|
601 |
DMA0_DA1 = 0x10A,
|
602 |
DMA0_SA1 = 0x10B,
|
603 |
DMA0_SG1 = 0x10C,
|
604 |
DMA0_CR2 = 0x110,
|
605 |
DMA0_CT2 = 0x111,
|
606 |
DMA0_DA2 = 0x112,
|
607 |
DMA0_SA2 = 0x113,
|
608 |
DMA0_SG2 = 0x114,
|
609 |
DMA0_CR3 = 0x118,
|
610 |
DMA0_CT3 = 0x119,
|
611 |
DMA0_DA3 = 0x11A,
|
612 |
DMA0_SA3 = 0x11B,
|
613 |
DMA0_SG3 = 0x11C,
|
614 |
DMA0_SR = 0x120,
|
615 |
DMA0_SGC = 0x123,
|
616 |
DMA0_SLP = 0x125,
|
617 |
DMA0_POL = 0x126,
|
618 |
}; |
619 |
|
620 |
typedef struct ppc405_dma_t ppc405_dma_t; |
621 |
struct ppc405_dma_t {
|
622 |
qemu_irq irqs[4];
|
623 |
uint32_t cr[4];
|
624 |
uint32_t ct[4];
|
625 |
uint32_t da[4];
|
626 |
uint32_t sa[4];
|
627 |
uint32_t sg[4];
|
628 |
uint32_t sr; |
629 |
uint32_t sgc; |
630 |
uint32_t slp; |
631 |
uint32_t pol; |
632 |
}; |
633 |
|
634 |
static target_ulong dcr_read_dma (void *opaque, int dcrn) |
635 |
{ |
636 |
ppc405_dma_t *dma; |
637 |
|
638 |
dma = opaque; |
639 |
|
640 |
return 0; |
641 |
} |
642 |
|
643 |
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
644 |
{ |
645 |
ppc405_dma_t *dma; |
646 |
|
647 |
dma = opaque; |
648 |
} |
649 |
|
650 |
static void ppc405_dma_reset (void *opaque) |
651 |
{ |
652 |
ppc405_dma_t *dma; |
653 |
int i;
|
654 |
|
655 |
dma = opaque; |
656 |
for (i = 0; i < 4; i++) { |
657 |
dma->cr[i] = 0x00000000;
|
658 |
dma->ct[i] = 0x00000000;
|
659 |
dma->da[i] = 0x00000000;
|
660 |
dma->sa[i] = 0x00000000;
|
661 |
dma->sg[i] = 0x00000000;
|
662 |
} |
663 |
dma->sr = 0x00000000;
|
664 |
dma->sgc = 0x00000000;
|
665 |
dma->slp = 0x7C000000;
|
666 |
dma->pol = 0x00000000;
|
667 |
} |
668 |
|
669 |
static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) |
670 |
{ |
671 |
ppc405_dma_t *dma; |
672 |
|
673 |
dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
674 |
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
675 |
ppc405_dma_reset(dma); |
676 |
qemu_register_reset(&ppc405_dma_reset, dma); |
677 |
ppc_dcr_register(env, DMA0_CR0, |
678 |
dma, &dcr_read_dma, &dcr_write_dma); |
679 |
ppc_dcr_register(env, DMA0_CT0, |
680 |
dma, &dcr_read_dma, &dcr_write_dma); |
681 |
ppc_dcr_register(env, DMA0_DA0, |
682 |
dma, &dcr_read_dma, &dcr_write_dma); |
683 |
ppc_dcr_register(env, DMA0_SA0, |
684 |
dma, &dcr_read_dma, &dcr_write_dma); |
685 |
ppc_dcr_register(env, DMA0_SG0, |
686 |
dma, &dcr_read_dma, &dcr_write_dma); |
687 |
ppc_dcr_register(env, DMA0_CR1, |
688 |
dma, &dcr_read_dma, &dcr_write_dma); |
689 |
ppc_dcr_register(env, DMA0_CT1, |
690 |
dma, &dcr_read_dma, &dcr_write_dma); |
691 |
ppc_dcr_register(env, DMA0_DA1, |
692 |
dma, &dcr_read_dma, &dcr_write_dma); |
693 |
ppc_dcr_register(env, DMA0_SA1, |
694 |
dma, &dcr_read_dma, &dcr_write_dma); |
695 |
ppc_dcr_register(env, DMA0_SG1, |
696 |
dma, &dcr_read_dma, &dcr_write_dma); |
697 |
ppc_dcr_register(env, DMA0_CR2, |
698 |
dma, &dcr_read_dma, &dcr_write_dma); |
699 |
ppc_dcr_register(env, DMA0_CT2, |
700 |
dma, &dcr_read_dma, &dcr_write_dma); |
701 |
ppc_dcr_register(env, DMA0_DA2, |
702 |
dma, &dcr_read_dma, &dcr_write_dma); |
703 |
ppc_dcr_register(env, DMA0_SA2, |
704 |
dma, &dcr_read_dma, &dcr_write_dma); |
705 |
ppc_dcr_register(env, DMA0_SG2, |
706 |
dma, &dcr_read_dma, &dcr_write_dma); |
707 |
ppc_dcr_register(env, DMA0_CR3, |
708 |
dma, &dcr_read_dma, &dcr_write_dma); |
709 |
ppc_dcr_register(env, DMA0_CT3, |
710 |
dma, &dcr_read_dma, &dcr_write_dma); |
711 |
ppc_dcr_register(env, DMA0_DA3, |
712 |
dma, &dcr_read_dma, &dcr_write_dma); |
713 |
ppc_dcr_register(env, DMA0_SA3, |
714 |
dma, &dcr_read_dma, &dcr_write_dma); |
715 |
ppc_dcr_register(env, DMA0_SG3, |
716 |
dma, &dcr_read_dma, &dcr_write_dma); |
717 |
ppc_dcr_register(env, DMA0_SR, |
718 |
dma, &dcr_read_dma, &dcr_write_dma); |
719 |
ppc_dcr_register(env, DMA0_SGC, |
720 |
dma, &dcr_read_dma, &dcr_write_dma); |
721 |
ppc_dcr_register(env, DMA0_SLP, |
722 |
dma, &dcr_read_dma, &dcr_write_dma); |
723 |
ppc_dcr_register(env, DMA0_POL, |
724 |
dma, &dcr_read_dma, &dcr_write_dma); |
725 |
} |
726 |
|
727 |
/*****************************************************************************/
|
728 |
/* GPIO */
|
729 |
typedef struct ppc405_gpio_t ppc405_gpio_t; |
730 |
struct ppc405_gpio_t {
|
731 |
uint32_t or; |
732 |
uint32_t tcr; |
733 |
uint32_t osrh; |
734 |
uint32_t osrl; |
735 |
uint32_t tsrh; |
736 |
uint32_t tsrl; |
737 |
uint32_t odr; |
738 |
uint32_t ir; |
739 |
uint32_t rr1; |
740 |
uint32_t isr1h; |
741 |
uint32_t isr1l; |
742 |
}; |
743 |
|
744 |
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
745 |
{ |
746 |
ppc405_gpio_t *gpio; |
747 |
|
748 |
gpio = opaque; |
749 |
#ifdef DEBUG_GPIO
|
750 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
751 |
#endif
|
752 |
|
753 |
return 0; |
754 |
} |
755 |
|
756 |
static void ppc405_gpio_writeb (void *opaque, |
757 |
target_phys_addr_t addr, uint32_t value) |
758 |
{ |
759 |
ppc405_gpio_t *gpio; |
760 |
|
761 |
gpio = opaque; |
762 |
#ifdef DEBUG_GPIO
|
763 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
764 |
value); |
765 |
#endif
|
766 |
} |
767 |
|
768 |
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
769 |
{ |
770 |
ppc405_gpio_t *gpio; |
771 |
|
772 |
gpio = opaque; |
773 |
#ifdef DEBUG_GPIO
|
774 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
775 |
#endif
|
776 |
|
777 |
return 0; |
778 |
} |
779 |
|
780 |
static void ppc405_gpio_writew (void *opaque, |
781 |
target_phys_addr_t addr, uint32_t value) |
782 |
{ |
783 |
ppc405_gpio_t *gpio; |
784 |
|
785 |
gpio = opaque; |
786 |
#ifdef DEBUG_GPIO
|
787 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
788 |
value); |
789 |
#endif
|
790 |
} |
791 |
|
792 |
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
793 |
{ |
794 |
ppc405_gpio_t *gpio; |
795 |
|
796 |
gpio = opaque; |
797 |
#ifdef DEBUG_GPIO
|
798 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
799 |
#endif
|
800 |
|
801 |
return 0; |
802 |
} |
803 |
|
804 |
static void ppc405_gpio_writel (void *opaque, |
805 |
target_phys_addr_t addr, uint32_t value) |
806 |
{ |
807 |
ppc405_gpio_t *gpio; |
808 |
|
809 |
gpio = opaque; |
810 |
#ifdef DEBUG_GPIO
|
811 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
812 |
value); |
813 |
#endif
|
814 |
} |
815 |
|
816 |
static CPUReadMemoryFunc * const ppc405_gpio_read[] = { |
817 |
&ppc405_gpio_readb, |
818 |
&ppc405_gpio_readw, |
819 |
&ppc405_gpio_readl, |
820 |
}; |
821 |
|
822 |
static CPUWriteMemoryFunc * const ppc405_gpio_write[] = { |
823 |
&ppc405_gpio_writeb, |
824 |
&ppc405_gpio_writew, |
825 |
&ppc405_gpio_writel, |
826 |
}; |
827 |
|
828 |
static void ppc405_gpio_reset (void *opaque) |
829 |
{ |
830 |
ppc405_gpio_t *gpio; |
831 |
|
832 |
gpio = opaque; |
833 |
} |
834 |
|
835 |
static void ppc405_gpio_init(target_phys_addr_t base) |
836 |
{ |
837 |
ppc405_gpio_t *gpio; |
838 |
int io;
|
839 |
|
840 |
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
841 |
#ifdef DEBUG_GPIO
|
842 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
843 |
#endif
|
844 |
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); |
845 |
cpu_register_physical_memory(base, 0x038, io);
|
846 |
ppc405_gpio_reset(gpio); |
847 |
qemu_register_reset(&ppc405_gpio_reset, gpio); |
848 |
} |
849 |
|
850 |
/*****************************************************************************/
|
851 |
/* On Chip Memory */
|
852 |
enum {
|
853 |
OCM0_ISARC = 0x018,
|
854 |
OCM0_ISACNTL = 0x019,
|
855 |
OCM0_DSARC = 0x01A,
|
856 |
OCM0_DSACNTL = 0x01B,
|
857 |
}; |
858 |
|
859 |
typedef struct ppc405_ocm_t ppc405_ocm_t; |
860 |
struct ppc405_ocm_t {
|
861 |
target_ulong offset; |
862 |
uint32_t isarc; |
863 |
uint32_t isacntl; |
864 |
uint32_t dsarc; |
865 |
uint32_t dsacntl; |
866 |
}; |
867 |
|
868 |
static void ocm_update_mappings (ppc405_ocm_t *ocm, |
869 |
uint32_t isarc, uint32_t isacntl, |
870 |
uint32_t dsarc, uint32_t dsacntl) |
871 |
{ |
872 |
#ifdef DEBUG_OCM
|
873 |
printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
874 |
" %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 |
875 |
" (%08" PRIx32 " %08" PRIx32 ")\n", |
876 |
isarc, isacntl, dsarc, dsacntl, |
877 |
ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
878 |
#endif
|
879 |
if (ocm->isarc != isarc ||
|
880 |
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
881 |
if (ocm->isacntl & 0x80000000) { |
882 |
/* Unmap previously assigned memory region */
|
883 |
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
884 |
cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
885 |
IO_MEM_UNASSIGNED); |
886 |
} |
887 |
if (isacntl & 0x80000000) { |
888 |
/* Map new instruction memory region */
|
889 |
#ifdef DEBUG_OCM
|
890 |
printf("OCM map ISA %08" PRIx32 "\n", isarc); |
891 |
#endif
|
892 |
cpu_register_physical_memory(isarc, 0x04000000,
|
893 |
ocm->offset | IO_MEM_RAM); |
894 |
} |
895 |
} |
896 |
if (ocm->dsarc != dsarc ||
|
897 |
(ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
898 |
if (ocm->dsacntl & 0x80000000) { |
899 |
/* Beware not to unmap the region we just mapped */
|
900 |
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
901 |
/* Unmap previously assigned memory region */
|
902 |
#ifdef DEBUG_OCM
|
903 |
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
904 |
#endif
|
905 |
cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
906 |
IO_MEM_UNASSIGNED); |
907 |
} |
908 |
} |
909 |
if (dsacntl & 0x80000000) { |
910 |
/* Beware not to remap the region we just mapped */
|
911 |
if (!(isacntl & 0x80000000) || dsarc != isarc) { |
912 |
/* Map new data memory region */
|
913 |
#ifdef DEBUG_OCM
|
914 |
printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
915 |
#endif
|
916 |
cpu_register_physical_memory(dsarc, 0x04000000,
|
917 |
ocm->offset | IO_MEM_RAM); |
918 |
} |
919 |
} |
920 |
} |
921 |
} |
922 |
|
923 |
static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
924 |
{ |
925 |
ppc405_ocm_t *ocm; |
926 |
target_ulong ret; |
927 |
|
928 |
ocm = opaque; |
929 |
switch (dcrn) {
|
930 |
case OCM0_ISARC:
|
931 |
ret = ocm->isarc; |
932 |
break;
|
933 |
case OCM0_ISACNTL:
|
934 |
ret = ocm->isacntl; |
935 |
break;
|
936 |
case OCM0_DSARC:
|
937 |
ret = ocm->dsarc; |
938 |
break;
|
939 |
case OCM0_DSACNTL:
|
940 |
ret = ocm->dsacntl; |
941 |
break;
|
942 |
default:
|
943 |
ret = 0;
|
944 |
break;
|
945 |
} |
946 |
|
947 |
return ret;
|
948 |
} |
949 |
|
950 |
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
951 |
{ |
952 |
ppc405_ocm_t *ocm; |
953 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
954 |
|
955 |
ocm = opaque; |
956 |
isarc = ocm->isarc; |
957 |
dsarc = ocm->dsarc; |
958 |
isacntl = ocm->isacntl; |
959 |
dsacntl = ocm->dsacntl; |
960 |
switch (dcrn) {
|
961 |
case OCM0_ISARC:
|
962 |
isarc = val & 0xFC000000;
|
963 |
break;
|
964 |
case OCM0_ISACNTL:
|
965 |
isacntl = val & 0xC0000000;
|
966 |
break;
|
967 |
case OCM0_DSARC:
|
968 |
isarc = val & 0xFC000000;
|
969 |
break;
|
970 |
case OCM0_DSACNTL:
|
971 |
isacntl = val & 0xC0000000;
|
972 |
break;
|
973 |
} |
974 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
975 |
ocm->isarc = isarc; |
976 |
ocm->dsarc = dsarc; |
977 |
ocm->isacntl = isacntl; |
978 |
ocm->dsacntl = dsacntl; |
979 |
} |
980 |
|
981 |
static void ocm_reset (void *opaque) |
982 |
{ |
983 |
ppc405_ocm_t *ocm; |
984 |
uint32_t isarc, dsarc, isacntl, dsacntl; |
985 |
|
986 |
ocm = opaque; |
987 |
isarc = 0x00000000;
|
988 |
isacntl = 0x00000000;
|
989 |
dsarc = 0x00000000;
|
990 |
dsacntl = 0x00000000;
|
991 |
ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
992 |
ocm->isarc = isarc; |
993 |
ocm->dsarc = dsarc; |
994 |
ocm->isacntl = isacntl; |
995 |
ocm->dsacntl = dsacntl; |
996 |
} |
997 |
|
998 |
static void ppc405_ocm_init(CPUState *env) |
999 |
{ |
1000 |
ppc405_ocm_t *ocm; |
1001 |
|
1002 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
1003 |
ocm->offset = qemu_ram_alloc(4096);
|
1004 |
ocm_reset(ocm); |
1005 |
qemu_register_reset(&ocm_reset, ocm); |
1006 |
ppc_dcr_register(env, OCM0_ISARC, |
1007 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1008 |
ppc_dcr_register(env, OCM0_ISACNTL, |
1009 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1010 |
ppc_dcr_register(env, OCM0_DSARC, |
1011 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1012 |
ppc_dcr_register(env, OCM0_DSACNTL, |
1013 |
ocm, &dcr_read_ocm, &dcr_write_ocm); |
1014 |
} |
1015 |
|
1016 |
/*****************************************************************************/
|
1017 |
/* I2C controller */
|
1018 |
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
1019 |
struct ppc4xx_i2c_t {
|
1020 |
qemu_irq irq; |
1021 |
uint8_t mdata; |
1022 |
uint8_t lmadr; |
1023 |
uint8_t hmadr; |
1024 |
uint8_t cntl; |
1025 |
uint8_t mdcntl; |
1026 |
uint8_t sts; |
1027 |
uint8_t extsts; |
1028 |
uint8_t sdata; |
1029 |
uint8_t lsadr; |
1030 |
uint8_t hsadr; |
1031 |
uint8_t clkdiv; |
1032 |
uint8_t intrmsk; |
1033 |
uint8_t xfrcnt; |
1034 |
uint8_t xtcntlss; |
1035 |
uint8_t directcntl; |
1036 |
}; |
1037 |
|
1038 |
static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
1039 |
{ |
1040 |
ppc4xx_i2c_t *i2c; |
1041 |
uint32_t ret; |
1042 |
|
1043 |
#ifdef DEBUG_I2C
|
1044 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1045 |
#endif
|
1046 |
i2c = opaque; |
1047 |
switch (addr) {
|
1048 |
case 0x00: |
1049 |
// i2c_readbyte(&i2c->mdata);
|
1050 |
ret = i2c->mdata; |
1051 |
break;
|
1052 |
case 0x02: |
1053 |
ret = i2c->sdata; |
1054 |
break;
|
1055 |
case 0x04: |
1056 |
ret = i2c->lmadr; |
1057 |
break;
|
1058 |
case 0x05: |
1059 |
ret = i2c->hmadr; |
1060 |
break;
|
1061 |
case 0x06: |
1062 |
ret = i2c->cntl; |
1063 |
break;
|
1064 |
case 0x07: |
1065 |
ret = i2c->mdcntl; |
1066 |
break;
|
1067 |
case 0x08: |
1068 |
ret = i2c->sts; |
1069 |
break;
|
1070 |
case 0x09: |
1071 |
ret = i2c->extsts; |
1072 |
break;
|
1073 |
case 0x0A: |
1074 |
ret = i2c->lsadr; |
1075 |
break;
|
1076 |
case 0x0B: |
1077 |
ret = i2c->hsadr; |
1078 |
break;
|
1079 |
case 0x0C: |
1080 |
ret = i2c->clkdiv; |
1081 |
break;
|
1082 |
case 0x0D: |
1083 |
ret = i2c->intrmsk; |
1084 |
break;
|
1085 |
case 0x0E: |
1086 |
ret = i2c->xfrcnt; |
1087 |
break;
|
1088 |
case 0x0F: |
1089 |
ret = i2c->xtcntlss; |
1090 |
break;
|
1091 |
case 0x10: |
1092 |
ret = i2c->directcntl; |
1093 |
break;
|
1094 |
default:
|
1095 |
ret = 0x00;
|
1096 |
break;
|
1097 |
} |
1098 |
#ifdef DEBUG_I2C
|
1099 |
printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret); |
1100 |
#endif
|
1101 |
|
1102 |
return ret;
|
1103 |
} |
1104 |
|
1105 |
static void ppc4xx_i2c_writeb (void *opaque, |
1106 |
target_phys_addr_t addr, uint32_t value) |
1107 |
{ |
1108 |
ppc4xx_i2c_t *i2c; |
1109 |
|
1110 |
#ifdef DEBUG_I2C
|
1111 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1112 |
value); |
1113 |
#endif
|
1114 |
i2c = opaque; |
1115 |
switch (addr) {
|
1116 |
case 0x00: |
1117 |
i2c->mdata = value; |
1118 |
// i2c_sendbyte(&i2c->mdata);
|
1119 |
break;
|
1120 |
case 0x02: |
1121 |
i2c->sdata = value; |
1122 |
break;
|
1123 |
case 0x04: |
1124 |
i2c->lmadr = value; |
1125 |
break;
|
1126 |
case 0x05: |
1127 |
i2c->hmadr = value; |
1128 |
break;
|
1129 |
case 0x06: |
1130 |
i2c->cntl = value; |
1131 |
break;
|
1132 |
case 0x07: |
1133 |
i2c->mdcntl = value & 0xDF;
|
1134 |
break;
|
1135 |
case 0x08: |
1136 |
i2c->sts &= ~(value & 0x0A);
|
1137 |
break;
|
1138 |
case 0x09: |
1139 |
i2c->extsts &= ~(value & 0x8F);
|
1140 |
break;
|
1141 |
case 0x0A: |
1142 |
i2c->lsadr = value; |
1143 |
break;
|
1144 |
case 0x0B: |
1145 |
i2c->hsadr = value; |
1146 |
break;
|
1147 |
case 0x0C: |
1148 |
i2c->clkdiv = value; |
1149 |
break;
|
1150 |
case 0x0D: |
1151 |
i2c->intrmsk = value; |
1152 |
break;
|
1153 |
case 0x0E: |
1154 |
i2c->xfrcnt = value & 0x77;
|
1155 |
break;
|
1156 |
case 0x0F: |
1157 |
i2c->xtcntlss = value; |
1158 |
break;
|
1159 |
case 0x10: |
1160 |
i2c->directcntl = value & 0x7;
|
1161 |
break;
|
1162 |
} |
1163 |
} |
1164 |
|
1165 |
static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
1166 |
{ |
1167 |
uint32_t ret; |
1168 |
|
1169 |
#ifdef DEBUG_I2C
|
1170 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1171 |
#endif
|
1172 |
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
1173 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
1174 |
|
1175 |
return ret;
|
1176 |
} |
1177 |
|
1178 |
static void ppc4xx_i2c_writew (void *opaque, |
1179 |
target_phys_addr_t addr, uint32_t value) |
1180 |
{ |
1181 |
#ifdef DEBUG_I2C
|
1182 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1183 |
value); |
1184 |
#endif
|
1185 |
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
1186 |
ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
1187 |
} |
1188 |
|
1189 |
static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
1190 |
{ |
1191 |
uint32_t ret; |
1192 |
|
1193 |
#ifdef DEBUG_I2C
|
1194 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1195 |
#endif
|
1196 |
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
1197 |
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
1198 |
ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
1199 |
ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
1200 |
|
1201 |
return ret;
|
1202 |
} |
1203 |
|
1204 |
static void ppc4xx_i2c_writel (void *opaque, |
1205 |
target_phys_addr_t addr, uint32_t value) |
1206 |
{ |
1207 |
#ifdef DEBUG_I2C
|
1208 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1209 |
value); |
1210 |
#endif
|
1211 |
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
1212 |
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
1213 |
ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
1214 |
ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
1215 |
} |
1216 |
|
1217 |
static CPUReadMemoryFunc * const i2c_read[] = { |
1218 |
&ppc4xx_i2c_readb, |
1219 |
&ppc4xx_i2c_readw, |
1220 |
&ppc4xx_i2c_readl, |
1221 |
}; |
1222 |
|
1223 |
static CPUWriteMemoryFunc * const i2c_write[] = { |
1224 |
&ppc4xx_i2c_writeb, |
1225 |
&ppc4xx_i2c_writew, |
1226 |
&ppc4xx_i2c_writel, |
1227 |
}; |
1228 |
|
1229 |
static void ppc4xx_i2c_reset (void *opaque) |
1230 |
{ |
1231 |
ppc4xx_i2c_t *i2c; |
1232 |
|
1233 |
i2c = opaque; |
1234 |
i2c->mdata = 0x00;
|
1235 |
i2c->sdata = 0x00;
|
1236 |
i2c->cntl = 0x00;
|
1237 |
i2c->mdcntl = 0x00;
|
1238 |
i2c->sts = 0x00;
|
1239 |
i2c->extsts = 0x00;
|
1240 |
i2c->clkdiv = 0x00;
|
1241 |
i2c->xfrcnt = 0x00;
|
1242 |
i2c->directcntl = 0x0F;
|
1243 |
} |
1244 |
|
1245 |
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) |
1246 |
{ |
1247 |
ppc4xx_i2c_t *i2c; |
1248 |
int io;
|
1249 |
|
1250 |
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
1251 |
i2c->irq = irq; |
1252 |
#ifdef DEBUG_I2C
|
1253 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1254 |
#endif
|
1255 |
io = cpu_register_io_memory(i2c_read, i2c_write, i2c); |
1256 |
cpu_register_physical_memory(base, 0x011, io);
|
1257 |
ppc4xx_i2c_reset(i2c); |
1258 |
qemu_register_reset(ppc4xx_i2c_reset, i2c); |
1259 |
} |
1260 |
|
1261 |
/*****************************************************************************/
|
1262 |
/* General purpose timers */
|
1263 |
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
1264 |
struct ppc4xx_gpt_t {
|
1265 |
int64_t tb_offset; |
1266 |
uint32_t tb_freq; |
1267 |
struct QEMUTimer *timer;
|
1268 |
qemu_irq irqs[5];
|
1269 |
uint32_t oe; |
1270 |
uint32_t ol; |
1271 |
uint32_t im; |
1272 |
uint32_t is; |
1273 |
uint32_t ie; |
1274 |
uint32_t comp[5];
|
1275 |
uint32_t mask[5];
|
1276 |
}; |
1277 |
|
1278 |
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
1279 |
{ |
1280 |
#ifdef DEBUG_GPT
|
1281 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1282 |
#endif
|
1283 |
/* XXX: generate a bus fault */
|
1284 |
return -1; |
1285 |
} |
1286 |
|
1287 |
static void ppc4xx_gpt_writeb (void *opaque, |
1288 |
target_phys_addr_t addr, uint32_t value) |
1289 |
{ |
1290 |
#ifdef DEBUG_I2C
|
1291 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1292 |
value); |
1293 |
#endif
|
1294 |
/* XXX: generate a bus fault */
|
1295 |
} |
1296 |
|
1297 |
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
1298 |
{ |
1299 |
#ifdef DEBUG_GPT
|
1300 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1301 |
#endif
|
1302 |
/* XXX: generate a bus fault */
|
1303 |
return -1; |
1304 |
} |
1305 |
|
1306 |
static void ppc4xx_gpt_writew (void *opaque, |
1307 |
target_phys_addr_t addr, uint32_t value) |
1308 |
{ |
1309 |
#ifdef DEBUG_I2C
|
1310 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1311 |
value); |
1312 |
#endif
|
1313 |
/* XXX: generate a bus fault */
|
1314 |
} |
1315 |
|
1316 |
static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
1317 |
{ |
1318 |
/* XXX: TODO */
|
1319 |
return 0; |
1320 |
} |
1321 |
|
1322 |
static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
1323 |
{ |
1324 |
/* XXX: TODO */
|
1325 |
} |
1326 |
|
1327 |
static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
1328 |
{ |
1329 |
uint32_t mask; |
1330 |
int i;
|
1331 |
|
1332 |
mask = 0x80000000;
|
1333 |
for (i = 0; i < 5; i++) { |
1334 |
if (gpt->oe & mask) {
|
1335 |
/* Output is enabled */
|
1336 |
if (ppc4xx_gpt_compare(gpt, i)) {
|
1337 |
/* Comparison is OK */
|
1338 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
1339 |
} else {
|
1340 |
/* Comparison is KO */
|
1341 |
ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
1342 |
} |
1343 |
} |
1344 |
mask = mask >> 1;
|
1345 |
} |
1346 |
} |
1347 |
|
1348 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
1349 |
{ |
1350 |
uint32_t mask; |
1351 |
int i;
|
1352 |
|
1353 |
mask = 0x00008000;
|
1354 |
for (i = 0; i < 5; i++) { |
1355 |
if (gpt->is & gpt->im & mask)
|
1356 |
qemu_irq_raise(gpt->irqs[i]); |
1357 |
else
|
1358 |
qemu_irq_lower(gpt->irqs[i]); |
1359 |
mask = mask >> 1;
|
1360 |
} |
1361 |
} |
1362 |
|
1363 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
1364 |
{ |
1365 |
/* XXX: TODO */
|
1366 |
} |
1367 |
|
1368 |
static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
1369 |
{ |
1370 |
ppc4xx_gpt_t *gpt; |
1371 |
uint32_t ret; |
1372 |
int idx;
|
1373 |
|
1374 |
#ifdef DEBUG_GPT
|
1375 |
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1376 |
#endif
|
1377 |
gpt = opaque; |
1378 |
switch (addr) {
|
1379 |
case 0x00: |
1380 |
/* Time base counter */
|
1381 |
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
1382 |
gpt->tb_freq, get_ticks_per_sec()); |
1383 |
break;
|
1384 |
case 0x10: |
1385 |
/* Output enable */
|
1386 |
ret = gpt->oe; |
1387 |
break;
|
1388 |
case 0x14: |
1389 |
/* Output level */
|
1390 |
ret = gpt->ol; |
1391 |
break;
|
1392 |
case 0x18: |
1393 |
/* Interrupt mask */
|
1394 |
ret = gpt->im; |
1395 |
break;
|
1396 |
case 0x1C: |
1397 |
case 0x20: |
1398 |
/* Interrupt status */
|
1399 |
ret = gpt->is; |
1400 |
break;
|
1401 |
case 0x24: |
1402 |
/* Interrupt enable */
|
1403 |
ret = gpt->ie; |
1404 |
break;
|
1405 |
case 0x80 ... 0x90: |
1406 |
/* Compare timer */
|
1407 |
idx = (addr - 0x80) >> 2; |
1408 |
ret = gpt->comp[idx]; |
1409 |
break;
|
1410 |
case 0xC0 ... 0xD0: |
1411 |
/* Compare mask */
|
1412 |
idx = (addr - 0xC0) >> 2; |
1413 |
ret = gpt->mask[idx]; |
1414 |
break;
|
1415 |
default:
|
1416 |
ret = -1;
|
1417 |
break;
|
1418 |
} |
1419 |
|
1420 |
return ret;
|
1421 |
} |
1422 |
|
1423 |
static void ppc4xx_gpt_writel (void *opaque, |
1424 |
target_phys_addr_t addr, uint32_t value) |
1425 |
{ |
1426 |
ppc4xx_gpt_t *gpt; |
1427 |
int idx;
|
1428 |
|
1429 |
#ifdef DEBUG_I2C
|
1430 |
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1431 |
value); |
1432 |
#endif
|
1433 |
gpt = opaque; |
1434 |
switch (addr) {
|
1435 |
case 0x00: |
1436 |
/* Time base counter */
|
1437 |
gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq) |
1438 |
- qemu_get_clock(vm_clock); |
1439 |
ppc4xx_gpt_compute_timer(gpt); |
1440 |
break;
|
1441 |
case 0x10: |
1442 |
/* Output enable */
|
1443 |
gpt->oe = value & 0xF8000000;
|
1444 |
ppc4xx_gpt_set_outputs(gpt); |
1445 |
break;
|
1446 |
case 0x14: |
1447 |
/* Output level */
|
1448 |
gpt->ol = value & 0xF8000000;
|
1449 |
ppc4xx_gpt_set_outputs(gpt); |
1450 |
break;
|
1451 |
case 0x18: |
1452 |
/* Interrupt mask */
|
1453 |
gpt->im = value & 0x0000F800;
|
1454 |
break;
|
1455 |
case 0x1C: |
1456 |
/* Interrupt status set */
|
1457 |
gpt->is |= value & 0x0000F800;
|
1458 |
ppc4xx_gpt_set_irqs(gpt); |
1459 |
break;
|
1460 |
case 0x20: |
1461 |
/* Interrupt status clear */
|
1462 |
gpt->is &= ~(value & 0x0000F800);
|
1463 |
ppc4xx_gpt_set_irqs(gpt); |
1464 |
break;
|
1465 |
case 0x24: |
1466 |
/* Interrupt enable */
|
1467 |
gpt->ie = value & 0x0000F800;
|
1468 |
ppc4xx_gpt_set_irqs(gpt); |
1469 |
break;
|
1470 |
case 0x80 ... 0x90: |
1471 |
/* Compare timer */
|
1472 |
idx = (addr - 0x80) >> 2; |
1473 |
gpt->comp[idx] = value & 0xF8000000;
|
1474 |
ppc4xx_gpt_compute_timer(gpt); |
1475 |
break;
|
1476 |
case 0xC0 ... 0xD0: |
1477 |
/* Compare mask */
|
1478 |
idx = (addr - 0xC0) >> 2; |
1479 |
gpt->mask[idx] = value & 0xF8000000;
|
1480 |
ppc4xx_gpt_compute_timer(gpt); |
1481 |
break;
|
1482 |
} |
1483 |
} |
1484 |
|
1485 |
static CPUReadMemoryFunc * const gpt_read[] = { |
1486 |
&ppc4xx_gpt_readb, |
1487 |
&ppc4xx_gpt_readw, |
1488 |
&ppc4xx_gpt_readl, |
1489 |
}; |
1490 |
|
1491 |
static CPUWriteMemoryFunc * const gpt_write[] = { |
1492 |
&ppc4xx_gpt_writeb, |
1493 |
&ppc4xx_gpt_writew, |
1494 |
&ppc4xx_gpt_writel, |
1495 |
}; |
1496 |
|
1497 |
static void ppc4xx_gpt_cb (void *opaque) |
1498 |
{ |
1499 |
ppc4xx_gpt_t *gpt; |
1500 |
|
1501 |
gpt = opaque; |
1502 |
ppc4xx_gpt_set_irqs(gpt); |
1503 |
ppc4xx_gpt_set_outputs(gpt); |
1504 |
ppc4xx_gpt_compute_timer(gpt); |
1505 |
} |
1506 |
|
1507 |
static void ppc4xx_gpt_reset (void *opaque) |
1508 |
{ |
1509 |
ppc4xx_gpt_t *gpt; |
1510 |
int i;
|
1511 |
|
1512 |
gpt = opaque; |
1513 |
qemu_del_timer(gpt->timer); |
1514 |
gpt->oe = 0x00000000;
|
1515 |
gpt->ol = 0x00000000;
|
1516 |
gpt->im = 0x00000000;
|
1517 |
gpt->is = 0x00000000;
|
1518 |
gpt->ie = 0x00000000;
|
1519 |
for (i = 0; i < 5; i++) { |
1520 |
gpt->comp[i] = 0x00000000;
|
1521 |
gpt->mask[i] = 0x00000000;
|
1522 |
} |
1523 |
} |
1524 |
|
1525 |
static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) |
1526 |
{ |
1527 |
ppc4xx_gpt_t *gpt; |
1528 |
int i;
|
1529 |
int io;
|
1530 |
|
1531 |
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
1532 |
for (i = 0; i < 5; i++) { |
1533 |
gpt->irqs[i] = irqs[i]; |
1534 |
} |
1535 |
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
1536 |
#ifdef DEBUG_GPT
|
1537 |
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
1538 |
#endif
|
1539 |
io = cpu_register_io_memory(gpt_read, gpt_write, gpt); |
1540 |
cpu_register_physical_memory(base, 0x0d4, io);
|
1541 |
qemu_register_reset(ppc4xx_gpt_reset, gpt); |
1542 |
ppc4xx_gpt_reset(gpt); |
1543 |
} |
1544 |
|
1545 |
/*****************************************************************************/
|
1546 |
/* MAL */
|
1547 |
enum {
|
1548 |
MAL0_CFG = 0x180,
|
1549 |
MAL0_ESR = 0x181,
|
1550 |
MAL0_IER = 0x182,
|
1551 |
MAL0_TXCASR = 0x184,
|
1552 |
MAL0_TXCARR = 0x185,
|
1553 |
MAL0_TXEOBISR = 0x186,
|
1554 |
MAL0_TXDEIR = 0x187,
|
1555 |
MAL0_RXCASR = 0x190,
|
1556 |
MAL0_RXCARR = 0x191,
|
1557 |
MAL0_RXEOBISR = 0x192,
|
1558 |
MAL0_RXDEIR = 0x193,
|
1559 |
MAL0_TXCTP0R = 0x1A0,
|
1560 |
MAL0_TXCTP1R = 0x1A1,
|
1561 |
MAL0_TXCTP2R = 0x1A2,
|
1562 |
MAL0_TXCTP3R = 0x1A3,
|
1563 |
MAL0_RXCTP0R = 0x1C0,
|
1564 |
MAL0_RXCTP1R = 0x1C1,
|
1565 |
MAL0_RCBS0 = 0x1E0,
|
1566 |
MAL0_RCBS1 = 0x1E1,
|
1567 |
}; |
1568 |
|
1569 |
typedef struct ppc40x_mal_t ppc40x_mal_t; |
1570 |
struct ppc40x_mal_t {
|
1571 |
qemu_irq irqs[4];
|
1572 |
uint32_t cfg; |
1573 |
uint32_t esr; |
1574 |
uint32_t ier; |
1575 |
uint32_t txcasr; |
1576 |
uint32_t txcarr; |
1577 |
uint32_t txeobisr; |
1578 |
uint32_t txdeir; |
1579 |
uint32_t rxcasr; |
1580 |
uint32_t rxcarr; |
1581 |
uint32_t rxeobisr; |
1582 |
uint32_t rxdeir; |
1583 |
uint32_t txctpr[4];
|
1584 |
uint32_t rxctpr[2];
|
1585 |
uint32_t rcbs[2];
|
1586 |
}; |
1587 |
|
1588 |
static void ppc40x_mal_reset (void *opaque); |
1589 |
|
1590 |
static target_ulong dcr_read_mal (void *opaque, int dcrn) |
1591 |
{ |
1592 |
ppc40x_mal_t *mal; |
1593 |
target_ulong ret; |
1594 |
|
1595 |
mal = opaque; |
1596 |
switch (dcrn) {
|
1597 |
case MAL0_CFG:
|
1598 |
ret = mal->cfg; |
1599 |
break;
|
1600 |
case MAL0_ESR:
|
1601 |
ret = mal->esr; |
1602 |
break;
|
1603 |
case MAL0_IER:
|
1604 |
ret = mal->ier; |
1605 |
break;
|
1606 |
case MAL0_TXCASR:
|
1607 |
ret = mal->txcasr; |
1608 |
break;
|
1609 |
case MAL0_TXCARR:
|
1610 |
ret = mal->txcarr; |
1611 |
break;
|
1612 |
case MAL0_TXEOBISR:
|
1613 |
ret = mal->txeobisr; |
1614 |
break;
|
1615 |
case MAL0_TXDEIR:
|
1616 |
ret = mal->txdeir; |
1617 |
break;
|
1618 |
case MAL0_RXCASR:
|
1619 |
ret = mal->rxcasr; |
1620 |
break;
|
1621 |
case MAL0_RXCARR:
|
1622 |
ret = mal->rxcarr; |
1623 |
break;
|
1624 |
case MAL0_RXEOBISR:
|
1625 |
ret = mal->rxeobisr; |
1626 |
break;
|
1627 |
case MAL0_RXDEIR:
|
1628 |
ret = mal->rxdeir; |
1629 |
break;
|
1630 |
case MAL0_TXCTP0R:
|
1631 |
ret = mal->txctpr[0];
|
1632 |
break;
|
1633 |
case MAL0_TXCTP1R:
|
1634 |
ret = mal->txctpr[1];
|
1635 |
break;
|
1636 |
case MAL0_TXCTP2R:
|
1637 |
ret = mal->txctpr[2];
|
1638 |
break;
|
1639 |
case MAL0_TXCTP3R:
|
1640 |
ret = mal->txctpr[3];
|
1641 |
break;
|
1642 |
case MAL0_RXCTP0R:
|
1643 |
ret = mal->rxctpr[0];
|
1644 |
break;
|
1645 |
case MAL0_RXCTP1R:
|
1646 |
ret = mal->rxctpr[1];
|
1647 |
break;
|
1648 |
case MAL0_RCBS0:
|
1649 |
ret = mal->rcbs[0];
|
1650 |
break;
|
1651 |
case MAL0_RCBS1:
|
1652 |
ret = mal->rcbs[1];
|
1653 |
break;
|
1654 |
default:
|
1655 |
ret = 0;
|
1656 |
break;
|
1657 |
} |
1658 |
|
1659 |
return ret;
|
1660 |
} |
1661 |
|
1662 |
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
1663 |
{ |
1664 |
ppc40x_mal_t *mal; |
1665 |
int idx;
|
1666 |
|
1667 |
mal = opaque; |
1668 |
switch (dcrn) {
|
1669 |
case MAL0_CFG:
|
1670 |
if (val & 0x80000000) |
1671 |
ppc40x_mal_reset(mal); |
1672 |
mal->cfg = val & 0x00FFC087;
|
1673 |
break;
|
1674 |
case MAL0_ESR:
|
1675 |
/* Read/clear */
|
1676 |
mal->esr &= ~val; |
1677 |
break;
|
1678 |
case MAL0_IER:
|
1679 |
mal->ier = val & 0x0000001F;
|
1680 |
break;
|
1681 |
case MAL0_TXCASR:
|
1682 |
mal->txcasr = val & 0xF0000000;
|
1683 |
break;
|
1684 |
case MAL0_TXCARR:
|
1685 |
mal->txcarr = val & 0xF0000000;
|
1686 |
break;
|
1687 |
case MAL0_TXEOBISR:
|
1688 |
/* Read/clear */
|
1689 |
mal->txeobisr &= ~val; |
1690 |
break;
|
1691 |
case MAL0_TXDEIR:
|
1692 |
/* Read/clear */
|
1693 |
mal->txdeir &= ~val; |
1694 |
break;
|
1695 |
case MAL0_RXCASR:
|
1696 |
mal->rxcasr = val & 0xC0000000;
|
1697 |
break;
|
1698 |
case MAL0_RXCARR:
|
1699 |
mal->rxcarr = val & 0xC0000000;
|
1700 |
break;
|
1701 |
case MAL0_RXEOBISR:
|
1702 |
/* Read/clear */
|
1703 |
mal->rxeobisr &= ~val; |
1704 |
break;
|
1705 |
case MAL0_RXDEIR:
|
1706 |
/* Read/clear */
|
1707 |
mal->rxdeir &= ~val; |
1708 |
break;
|
1709 |
case MAL0_TXCTP0R:
|
1710 |
idx = 0;
|
1711 |
goto update_tx_ptr;
|
1712 |
case MAL0_TXCTP1R:
|
1713 |
idx = 1;
|
1714 |
goto update_tx_ptr;
|
1715 |
case MAL0_TXCTP2R:
|
1716 |
idx = 2;
|
1717 |
goto update_tx_ptr;
|
1718 |
case MAL0_TXCTP3R:
|
1719 |
idx = 3;
|
1720 |
update_tx_ptr:
|
1721 |
mal->txctpr[idx] = val; |
1722 |
break;
|
1723 |
case MAL0_RXCTP0R:
|
1724 |
idx = 0;
|
1725 |
goto update_rx_ptr;
|
1726 |
case MAL0_RXCTP1R:
|
1727 |
idx = 1;
|
1728 |
update_rx_ptr:
|
1729 |
mal->rxctpr[idx] = val; |
1730 |
break;
|
1731 |
case MAL0_RCBS0:
|
1732 |
idx = 0;
|
1733 |
goto update_rx_size;
|
1734 |
case MAL0_RCBS1:
|
1735 |
idx = 1;
|
1736 |
update_rx_size:
|
1737 |
mal->rcbs[idx] = val & 0x000000FF;
|
1738 |
break;
|
1739 |
} |
1740 |
} |
1741 |
|
1742 |
static void ppc40x_mal_reset (void *opaque) |
1743 |
{ |
1744 |
ppc40x_mal_t *mal; |
1745 |
|
1746 |
mal = opaque; |
1747 |
mal->cfg = 0x0007C000;
|
1748 |
mal->esr = 0x00000000;
|
1749 |
mal->ier = 0x00000000;
|
1750 |
mal->rxcasr = 0x00000000;
|
1751 |
mal->rxdeir = 0x00000000;
|
1752 |
mal->rxeobisr = 0x00000000;
|
1753 |
mal->txcasr = 0x00000000;
|
1754 |
mal->txdeir = 0x00000000;
|
1755 |
mal->txeobisr = 0x00000000;
|
1756 |
} |
1757 |
|
1758 |
static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) |
1759 |
{ |
1760 |
ppc40x_mal_t *mal; |
1761 |
int i;
|
1762 |
|
1763 |
mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
1764 |
for (i = 0; i < 4; i++) |
1765 |
mal->irqs[i] = irqs[i]; |
1766 |
ppc40x_mal_reset(mal); |
1767 |
qemu_register_reset(&ppc40x_mal_reset, mal); |
1768 |
ppc_dcr_register(env, MAL0_CFG, |
1769 |
mal, &dcr_read_mal, &dcr_write_mal); |
1770 |
ppc_dcr_register(env, MAL0_ESR, |
1771 |
mal, &dcr_read_mal, &dcr_write_mal); |
1772 |
ppc_dcr_register(env, MAL0_IER, |
1773 |
mal, &dcr_read_mal, &dcr_write_mal); |
1774 |
ppc_dcr_register(env, MAL0_TXCASR, |
1775 |
mal, &dcr_read_mal, &dcr_write_mal); |
1776 |
ppc_dcr_register(env, MAL0_TXCARR, |
1777 |
mal, &dcr_read_mal, &dcr_write_mal); |
1778 |
ppc_dcr_register(env, MAL0_TXEOBISR, |
1779 |
mal, &dcr_read_mal, &dcr_write_mal); |
1780 |
ppc_dcr_register(env, MAL0_TXDEIR, |
1781 |
mal, &dcr_read_mal, &dcr_write_mal); |
1782 |
ppc_dcr_register(env, MAL0_RXCASR, |
1783 |
mal, &dcr_read_mal, &dcr_write_mal); |
1784 |
ppc_dcr_register(env, MAL0_RXCARR, |
1785 |
mal, &dcr_read_mal, &dcr_write_mal); |
1786 |
ppc_dcr_register(env, MAL0_RXEOBISR, |
1787 |
mal, &dcr_read_mal, &dcr_write_mal); |
1788 |
ppc_dcr_register(env, MAL0_RXDEIR, |
1789 |
mal, &dcr_read_mal, &dcr_write_mal); |
1790 |
ppc_dcr_register(env, MAL0_TXCTP0R, |
1791 |
mal, &dcr_read_mal, &dcr_write_mal); |
1792 |
ppc_dcr_register(env, MAL0_TXCTP1R, |
1793 |
mal, &dcr_read_mal, &dcr_write_mal); |
1794 |
ppc_dcr_register(env, MAL0_TXCTP2R, |
1795 |
mal, &dcr_read_mal, &dcr_write_mal); |
1796 |
ppc_dcr_register(env, MAL0_TXCTP3R, |
1797 |
mal, &dcr_read_mal, &dcr_write_mal); |
1798 |
ppc_dcr_register(env, MAL0_RXCTP0R, |
1799 |
mal, &dcr_read_mal, &dcr_write_mal); |
1800 |
ppc_dcr_register(env, MAL0_RXCTP1R, |
1801 |
mal, &dcr_read_mal, &dcr_write_mal); |
1802 |
ppc_dcr_register(env, MAL0_RCBS0, |
1803 |
mal, &dcr_read_mal, &dcr_write_mal); |
1804 |
ppc_dcr_register(env, MAL0_RCBS1, |
1805 |
mal, &dcr_read_mal, &dcr_write_mal); |
1806 |
} |
1807 |
|
1808 |
/*****************************************************************************/
|
1809 |
/* SPR */
|
1810 |
void ppc40x_core_reset (CPUState *env)
|
1811 |
{ |
1812 |
target_ulong dbsr; |
1813 |
|
1814 |
printf("Reset PowerPC core\n");
|
1815 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1816 |
/* XXX: TOFIX */
|
1817 |
#if 0
|
1818 |
cpu_ppc_reset(env);
|
1819 |
#else
|
1820 |
qemu_system_reset_request(); |
1821 |
#endif
|
1822 |
dbsr = env->spr[SPR_40x_DBSR]; |
1823 |
dbsr &= ~0x00000300;
|
1824 |
dbsr |= 0x00000100;
|
1825 |
env->spr[SPR_40x_DBSR] = dbsr; |
1826 |
} |
1827 |
|
1828 |
void ppc40x_chip_reset (CPUState *env)
|
1829 |
{ |
1830 |
target_ulong dbsr; |
1831 |
|
1832 |
printf("Reset PowerPC chip\n");
|
1833 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1834 |
/* XXX: TOFIX */
|
1835 |
#if 0
|
1836 |
cpu_ppc_reset(env);
|
1837 |
#else
|
1838 |
qemu_system_reset_request(); |
1839 |
#endif
|
1840 |
/* XXX: TODO reset all internal peripherals */
|
1841 |
dbsr = env->spr[SPR_40x_DBSR]; |
1842 |
dbsr &= ~0x00000300;
|
1843 |
dbsr |= 0x00000200;
|
1844 |
env->spr[SPR_40x_DBSR] = dbsr; |
1845 |
} |
1846 |
|
1847 |
void ppc40x_system_reset (CPUState *env)
|
1848 |
{ |
1849 |
printf("Reset PowerPC system\n");
|
1850 |
qemu_system_reset_request(); |
1851 |
} |
1852 |
|
1853 |
void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
1854 |
{ |
1855 |
switch ((val >> 28) & 0x3) { |
1856 |
case 0x0: |
1857 |
/* No action */
|
1858 |
break;
|
1859 |
case 0x1: |
1860 |
/* Core reset */
|
1861 |
ppc40x_core_reset(env); |
1862 |
break;
|
1863 |
case 0x2: |
1864 |
/* Chip reset */
|
1865 |
ppc40x_chip_reset(env); |
1866 |
break;
|
1867 |
case 0x3: |
1868 |
/* System reset */
|
1869 |
ppc40x_system_reset(env); |
1870 |
break;
|
1871 |
} |
1872 |
} |
1873 |
|
1874 |
/*****************************************************************************/
|
1875 |
/* PowerPC 405CR */
|
1876 |
enum {
|
1877 |
PPC405CR_CPC0_PLLMR = 0x0B0,
|
1878 |
PPC405CR_CPC0_CR0 = 0x0B1,
|
1879 |
PPC405CR_CPC0_CR1 = 0x0B2,
|
1880 |
PPC405CR_CPC0_PSR = 0x0B4,
|
1881 |
PPC405CR_CPC0_JTAGID = 0x0B5,
|
1882 |
PPC405CR_CPC0_ER = 0x0B9,
|
1883 |
PPC405CR_CPC0_FR = 0x0BA,
|
1884 |
PPC405CR_CPC0_SR = 0x0BB,
|
1885 |
}; |
1886 |
|
1887 |
enum {
|
1888 |
PPC405CR_CPU_CLK = 0,
|
1889 |
PPC405CR_TMR_CLK = 1,
|
1890 |
PPC405CR_PLB_CLK = 2,
|
1891 |
PPC405CR_SDRAM_CLK = 3,
|
1892 |
PPC405CR_OPB_CLK = 4,
|
1893 |
PPC405CR_EXT_CLK = 5,
|
1894 |
PPC405CR_UART_CLK = 6,
|
1895 |
PPC405CR_CLK_NB = 7,
|
1896 |
}; |
1897 |
|
1898 |
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
1899 |
struct ppc405cr_cpc_t {
|
1900 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
1901 |
uint32_t sysclk; |
1902 |
uint32_t psr; |
1903 |
uint32_t cr0; |
1904 |
uint32_t cr1; |
1905 |
uint32_t jtagid; |
1906 |
uint32_t pllmr; |
1907 |
uint32_t er; |
1908 |
uint32_t fr; |
1909 |
}; |
1910 |
|
1911 |
static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
1912 |
{ |
1913 |
uint64_t VCO_out, PLL_out; |
1914 |
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
1915 |
int M, D0, D1, D2;
|
1916 |
|
1917 |
D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
1918 |
if (cpc->pllmr & 0x80000000) { |
1919 |
D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
1920 |
D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
1921 |
M = D0 * D1 * D2; |
1922 |
VCO_out = cpc->sysclk * M; |
1923 |
if (VCO_out < 400000000 || VCO_out > 800000000) { |
1924 |
/* PLL cannot lock */
|
1925 |
cpc->pllmr &= ~0x80000000;
|
1926 |
goto bypass_pll;
|
1927 |
} |
1928 |
PLL_out = VCO_out / D2; |
1929 |
} else {
|
1930 |
/* Bypass PLL */
|
1931 |
bypass_pll:
|
1932 |
M = D0; |
1933 |
PLL_out = cpc->sysclk * M; |
1934 |
} |
1935 |
CPU_clk = PLL_out; |
1936 |
if (cpc->cr1 & 0x00800000) |
1937 |
TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
1938 |
else
|
1939 |
TMR_clk = CPU_clk; |
1940 |
PLB_clk = CPU_clk / D0; |
1941 |
SDRAM_clk = PLB_clk; |
1942 |
D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
1943 |
OPB_clk = PLB_clk / D0; |
1944 |
D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
1945 |
EXT_clk = PLB_clk / D0; |
1946 |
D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
1947 |
UART_clk = CPU_clk / D0; |
1948 |
/* Setup CPU clocks */
|
1949 |
clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
1950 |
/* Setup time-base clock */
|
1951 |
clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
1952 |
/* Setup PLB clock */
|
1953 |
clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
1954 |
/* Setup SDRAM clock */
|
1955 |
clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
1956 |
/* Setup OPB clock */
|
1957 |
clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
1958 |
/* Setup external clock */
|
1959 |
clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
1960 |
/* Setup UART clock */
|
1961 |
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
1962 |
} |
1963 |
|
1964 |
static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
1965 |
{ |
1966 |
ppc405cr_cpc_t *cpc; |
1967 |
target_ulong ret; |
1968 |
|
1969 |
cpc = opaque; |
1970 |
switch (dcrn) {
|
1971 |
case PPC405CR_CPC0_PLLMR:
|
1972 |
ret = cpc->pllmr; |
1973 |
break;
|
1974 |
case PPC405CR_CPC0_CR0:
|
1975 |
ret = cpc->cr0; |
1976 |
break;
|
1977 |
case PPC405CR_CPC0_CR1:
|
1978 |
ret = cpc->cr1; |
1979 |
break;
|
1980 |
case PPC405CR_CPC0_PSR:
|
1981 |
ret = cpc->psr; |
1982 |
break;
|
1983 |
case PPC405CR_CPC0_JTAGID:
|
1984 |
ret = cpc->jtagid; |
1985 |
break;
|
1986 |
case PPC405CR_CPC0_ER:
|
1987 |
ret = cpc->er; |
1988 |
break;
|
1989 |
case PPC405CR_CPC0_FR:
|
1990 |
ret = cpc->fr; |
1991 |
break;
|
1992 |
case PPC405CR_CPC0_SR:
|
1993 |
ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
1994 |
break;
|
1995 |
default:
|
1996 |
/* Avoid gcc warning */
|
1997 |
ret = 0;
|
1998 |
break;
|
1999 |
} |
2000 |
|
2001 |
return ret;
|
2002 |
} |
2003 |
|
2004 |
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2005 |
{ |
2006 |
ppc405cr_cpc_t *cpc; |
2007 |
|
2008 |
cpc = opaque; |
2009 |
switch (dcrn) {
|
2010 |
case PPC405CR_CPC0_PLLMR:
|
2011 |
cpc->pllmr = val & 0xFFF77C3F;
|
2012 |
break;
|
2013 |
case PPC405CR_CPC0_CR0:
|
2014 |
cpc->cr0 = val & 0x0FFFFFFE;
|
2015 |
break;
|
2016 |
case PPC405CR_CPC0_CR1:
|
2017 |
cpc->cr1 = val & 0x00800000;
|
2018 |
break;
|
2019 |
case PPC405CR_CPC0_PSR:
|
2020 |
/* Read-only */
|
2021 |
break;
|
2022 |
case PPC405CR_CPC0_JTAGID:
|
2023 |
/* Read-only */
|
2024 |
break;
|
2025 |
case PPC405CR_CPC0_ER:
|
2026 |
cpc->er = val & 0xBFFC0000;
|
2027 |
break;
|
2028 |
case PPC405CR_CPC0_FR:
|
2029 |
cpc->fr = val & 0xBFFC0000;
|
2030 |
break;
|
2031 |
case PPC405CR_CPC0_SR:
|
2032 |
/* Read-only */
|
2033 |
break;
|
2034 |
} |
2035 |
} |
2036 |
|
2037 |
static void ppc405cr_cpc_reset (void *opaque) |
2038 |
{ |
2039 |
ppc405cr_cpc_t *cpc; |
2040 |
int D;
|
2041 |
|
2042 |
cpc = opaque; |
2043 |
/* Compute PLLMR value from PSR settings */
|
2044 |
cpc->pllmr = 0x80000000;
|
2045 |
/* PFWD */
|
2046 |
switch ((cpc->psr >> 30) & 3) { |
2047 |
case 0: |
2048 |
/* Bypass */
|
2049 |
cpc->pllmr &= ~0x80000000;
|
2050 |
break;
|
2051 |
case 1: |
2052 |
/* Divide by 3 */
|
2053 |
cpc->pllmr |= 5 << 16; |
2054 |
break;
|
2055 |
case 2: |
2056 |
/* Divide by 4 */
|
2057 |
cpc->pllmr |= 4 << 16; |
2058 |
break;
|
2059 |
case 3: |
2060 |
/* Divide by 6 */
|
2061 |
cpc->pllmr |= 2 << 16; |
2062 |
break;
|
2063 |
} |
2064 |
/* PFBD */
|
2065 |
D = (cpc->psr >> 28) & 3; |
2066 |
cpc->pllmr |= (D + 1) << 20; |
2067 |
/* PT */
|
2068 |
D = (cpc->psr >> 25) & 7; |
2069 |
switch (D) {
|
2070 |
case 0x2: |
2071 |
cpc->pllmr |= 0x13;
|
2072 |
break;
|
2073 |
case 0x4: |
2074 |
cpc->pllmr |= 0x15;
|
2075 |
break;
|
2076 |
case 0x5: |
2077 |
cpc->pllmr |= 0x16;
|
2078 |
break;
|
2079 |
default:
|
2080 |
break;
|
2081 |
} |
2082 |
/* PDC */
|
2083 |
D = (cpc->psr >> 23) & 3; |
2084 |
cpc->pllmr |= D << 26;
|
2085 |
/* ODP */
|
2086 |
D = (cpc->psr >> 21) & 3; |
2087 |
cpc->pllmr |= D << 10;
|
2088 |
/* EBPD */
|
2089 |
D = (cpc->psr >> 17) & 3; |
2090 |
cpc->pllmr |= D << 24;
|
2091 |
cpc->cr0 = 0x0000003C;
|
2092 |
cpc->cr1 = 0x2B0D8800;
|
2093 |
cpc->er = 0x00000000;
|
2094 |
cpc->fr = 0x00000000;
|
2095 |
ppc405cr_clk_setup(cpc); |
2096 |
} |
2097 |
|
2098 |
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
2099 |
{ |
2100 |
int D;
|
2101 |
|
2102 |
/* XXX: this should be read from IO pins */
|
2103 |
cpc->psr = 0x00000000; /* 8 bits ROM */ |
2104 |
/* PFWD */
|
2105 |
D = 0x2; /* Divide by 4 */ |
2106 |
cpc->psr |= D << 30;
|
2107 |
/* PFBD */
|
2108 |
D = 0x1; /* Divide by 2 */ |
2109 |
cpc->psr |= D << 28;
|
2110 |
/* PDC */
|
2111 |
D = 0x1; /* Divide by 2 */ |
2112 |
cpc->psr |= D << 23;
|
2113 |
/* PT */
|
2114 |
D = 0x5; /* M = 16 */ |
2115 |
cpc->psr |= D << 25;
|
2116 |
/* ODP */
|
2117 |
D = 0x1; /* Divide by 2 */ |
2118 |
cpc->psr |= D << 21;
|
2119 |
/* EBDP */
|
2120 |
D = 0x2; /* Divide by 4 */ |
2121 |
cpc->psr |= D << 17;
|
2122 |
} |
2123 |
|
2124 |
static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2125 |
uint32_t sysclk) |
2126 |
{ |
2127 |
ppc405cr_cpc_t *cpc; |
2128 |
|
2129 |
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
2130 |
memcpy(cpc->clk_setup, clk_setup, |
2131 |
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
2132 |
cpc->sysclk = sysclk; |
2133 |
cpc->jtagid = 0x42051049;
|
2134 |
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
2135 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2136 |
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
2137 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2138 |
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
2139 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2140 |
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
2141 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2142 |
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
2143 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2144 |
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
2145 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2146 |
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
2147 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2148 |
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
2149 |
&dcr_read_crcpc, &dcr_write_crcpc); |
2150 |
ppc405cr_clk_init(cpc); |
2151 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
2152 |
ppc405cr_cpc_reset(cpc); |
2153 |
} |
2154 |
|
2155 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
2156 |
target_phys_addr_t ram_sizes[4],
|
2157 |
uint32_t sysclk, qemu_irq **picp, |
2158 |
int do_init)
|
2159 |
{ |
2160 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2161 |
qemu_irq dma_irqs[4];
|
2162 |
CPUState *env; |
2163 |
qemu_irq *pic, *irqs; |
2164 |
|
2165 |
memset(clk_setup, 0, sizeof(clk_setup)); |
2166 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
2167 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
2168 |
/* Memory mapped devices registers */
|
2169 |
/* PLB arbitrer */
|
2170 |
ppc4xx_plb_init(env); |
2171 |
/* PLB to OPB bridge */
|
2172 |
ppc4xx_pob_init(env); |
2173 |
/* OBP arbitrer */
|
2174 |
ppc4xx_opba_init(0xef600600);
|
2175 |
/* Universal interrupt controller */
|
2176 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2177 |
irqs[PPCUIC_OUTPUT_INT] = |
2178 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2179 |
irqs[PPCUIC_OUTPUT_CINT] = |
2180 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2181 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2182 |
*picp = pic; |
2183 |
/* SDRAM controller */
|
2184 |
ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
2185 |
/* External bus controller */
|
2186 |
ppc405_ebc_init(env); |
2187 |
/* DMA controller */
|
2188 |
dma_irqs[0] = pic[26]; |
2189 |
dma_irqs[1] = pic[25]; |
2190 |
dma_irqs[2] = pic[24]; |
2191 |
dma_irqs[3] = pic[23]; |
2192 |
ppc405_dma_init(env, dma_irqs); |
2193 |
/* Serial ports */
|
2194 |
if (serial_hds[0] != NULL) { |
2195 |
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2196 |
serial_hds[0], 1); |
2197 |
} |
2198 |
if (serial_hds[1] != NULL) { |
2199 |
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2200 |
serial_hds[1], 1); |
2201 |
} |
2202 |
/* IIC controller */
|
2203 |
ppc405_i2c_init(0xef600500, pic[2]); |
2204 |
/* GPIO */
|
2205 |
ppc405_gpio_init(0xef600700);
|
2206 |
/* CPU control */
|
2207 |
ppc405cr_cpc_init(env, clk_setup, sysclk); |
2208 |
|
2209 |
return env;
|
2210 |
} |
2211 |
|
2212 |
/*****************************************************************************/
|
2213 |
/* PowerPC 405EP */
|
2214 |
/* CPU control */
|
2215 |
enum {
|
2216 |
PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
2217 |
PPC405EP_CPC0_BOOT = 0x0F1,
|
2218 |
PPC405EP_CPC0_EPCTL = 0x0F3,
|
2219 |
PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
2220 |
PPC405EP_CPC0_UCR = 0x0F5,
|
2221 |
PPC405EP_CPC0_SRR = 0x0F6,
|
2222 |
PPC405EP_CPC0_JTAGID = 0x0F7,
|
2223 |
PPC405EP_CPC0_PCI = 0x0F9,
|
2224 |
#if 0
|
2225 |
PPC405EP_CPC0_ER = xxx,
|
2226 |
PPC405EP_CPC0_FR = xxx,
|
2227 |
PPC405EP_CPC0_SR = xxx,
|
2228 |
#endif
|
2229 |
}; |
2230 |
|
2231 |
enum {
|
2232 |
PPC405EP_CPU_CLK = 0,
|
2233 |
PPC405EP_PLB_CLK = 1,
|
2234 |
PPC405EP_OPB_CLK = 2,
|
2235 |
PPC405EP_EBC_CLK = 3,
|
2236 |
PPC405EP_MAL_CLK = 4,
|
2237 |
PPC405EP_PCI_CLK = 5,
|
2238 |
PPC405EP_UART0_CLK = 6,
|
2239 |
PPC405EP_UART1_CLK = 7,
|
2240 |
PPC405EP_CLK_NB = 8,
|
2241 |
}; |
2242 |
|
2243 |
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
2244 |
struct ppc405ep_cpc_t {
|
2245 |
uint32_t sysclk; |
2246 |
clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
2247 |
uint32_t boot; |
2248 |
uint32_t epctl; |
2249 |
uint32_t pllmr[2];
|
2250 |
uint32_t ucr; |
2251 |
uint32_t srr; |
2252 |
uint32_t jtagid; |
2253 |
uint32_t pci; |
2254 |
/* Clock and power management */
|
2255 |
uint32_t er; |
2256 |
uint32_t fr; |
2257 |
uint32_t sr; |
2258 |
}; |
2259 |
|
2260 |
static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
2261 |
{ |
2262 |
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
2263 |
uint32_t UART0_clk, UART1_clk; |
2264 |
uint64_t VCO_out, PLL_out; |
2265 |
int M, D;
|
2266 |
|
2267 |
VCO_out = 0;
|
2268 |
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
2269 |
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
2270 |
#ifdef DEBUG_CLOCKS_LL
|
2271 |
printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); |
2272 |
#endif
|
2273 |
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
2274 |
#ifdef DEBUG_CLOCKS_LL
|
2275 |
printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); |
2276 |
#endif
|
2277 |
VCO_out = cpc->sysclk * M * D; |
2278 |
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
2279 |
/* Error - unlock the PLL */
|
2280 |
printf("VCO out of range %" PRIu64 "\n", VCO_out); |
2281 |
#if 0
|
2282 |
cpc->pllmr[1] &= ~0x80000000;
|
2283 |
goto pll_bypass;
|
2284 |
#endif
|
2285 |
} |
2286 |
PLL_out = VCO_out / D; |
2287 |
/* Pretend the PLL is locked */
|
2288 |
cpc->boot |= 0x00000001;
|
2289 |
} else {
|
2290 |
#if 0
|
2291 |
pll_bypass:
|
2292 |
#endif
|
2293 |
PLL_out = cpc->sysclk; |
2294 |
if (cpc->pllmr[1] & 0x40000000) { |
2295 |
/* Pretend the PLL is not locked */
|
2296 |
cpc->boot &= ~0x00000001;
|
2297 |
} |
2298 |
} |
2299 |
/* Now, compute all other clocks */
|
2300 |
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
2301 |
#ifdef DEBUG_CLOCKS_LL
|
2302 |
printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); |
2303 |
#endif
|
2304 |
CPU_clk = PLL_out / D; |
2305 |
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
2306 |
#ifdef DEBUG_CLOCKS_LL
|
2307 |
printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); |
2308 |
#endif
|
2309 |
PLB_clk = CPU_clk / D; |
2310 |
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
2311 |
#ifdef DEBUG_CLOCKS_LL
|
2312 |
printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); |
2313 |
#endif
|
2314 |
OPB_clk = PLB_clk / D; |
2315 |
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
2316 |
#ifdef DEBUG_CLOCKS_LL
|
2317 |
printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); |
2318 |
#endif
|
2319 |
EBC_clk = PLB_clk / D; |
2320 |
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
2321 |
#ifdef DEBUG_CLOCKS_LL
|
2322 |
printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); |
2323 |
#endif
|
2324 |
MAL_clk = PLB_clk / D; |
2325 |
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
2326 |
#ifdef DEBUG_CLOCKS_LL
|
2327 |
printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); |
2328 |
#endif
|
2329 |
PCI_clk = PLB_clk / D; |
2330 |
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
2331 |
#ifdef DEBUG_CLOCKS_LL
|
2332 |
printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); |
2333 |
#endif
|
2334 |
UART0_clk = PLL_out / D; |
2335 |
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
2336 |
#ifdef DEBUG_CLOCKS_LL
|
2337 |
printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); |
2338 |
#endif
|
2339 |
UART1_clk = PLL_out / D; |
2340 |
#ifdef DEBUG_CLOCKS
|
2341 |
printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
2342 |
" PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
2343 |
printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
2344 |
" MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 |
2345 |
" UART1 %" PRIu32 "\n", |
2346 |
CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
2347 |
UART0_clk, UART1_clk); |
2348 |
#endif
|
2349 |
/* Setup CPU clocks */
|
2350 |
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
2351 |
/* Setup PLB clock */
|
2352 |
clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
2353 |
/* Setup OPB clock */
|
2354 |
clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
2355 |
/* Setup external clock */
|
2356 |
clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
2357 |
/* Setup MAL clock */
|
2358 |
clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
2359 |
/* Setup PCI clock */
|
2360 |
clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
2361 |
/* Setup UART0 clock */
|
2362 |
clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
2363 |
/* Setup UART1 clock */
|
2364 |
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
2365 |
} |
2366 |
|
2367 |
static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
2368 |
{ |
2369 |
ppc405ep_cpc_t *cpc; |
2370 |
target_ulong ret; |
2371 |
|
2372 |
cpc = opaque; |
2373 |
switch (dcrn) {
|
2374 |
case PPC405EP_CPC0_BOOT:
|
2375 |
ret = cpc->boot; |
2376 |
break;
|
2377 |
case PPC405EP_CPC0_EPCTL:
|
2378 |
ret = cpc->epctl; |
2379 |
break;
|
2380 |
case PPC405EP_CPC0_PLLMR0:
|
2381 |
ret = cpc->pllmr[0];
|
2382 |
break;
|
2383 |
case PPC405EP_CPC0_PLLMR1:
|
2384 |
ret = cpc->pllmr[1];
|
2385 |
break;
|
2386 |
case PPC405EP_CPC0_UCR:
|
2387 |
ret = cpc->ucr; |
2388 |
break;
|
2389 |
case PPC405EP_CPC0_SRR:
|
2390 |
ret = cpc->srr; |
2391 |
break;
|
2392 |
case PPC405EP_CPC0_JTAGID:
|
2393 |
ret = cpc->jtagid; |
2394 |
break;
|
2395 |
case PPC405EP_CPC0_PCI:
|
2396 |
ret = cpc->pci; |
2397 |
break;
|
2398 |
default:
|
2399 |
/* Avoid gcc warning */
|
2400 |
ret = 0;
|
2401 |
break;
|
2402 |
} |
2403 |
|
2404 |
return ret;
|
2405 |
} |
2406 |
|
2407 |
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
2408 |
{ |
2409 |
ppc405ep_cpc_t *cpc; |
2410 |
|
2411 |
cpc = opaque; |
2412 |
switch (dcrn) {
|
2413 |
case PPC405EP_CPC0_BOOT:
|
2414 |
/* Read-only register */
|
2415 |
break;
|
2416 |
case PPC405EP_CPC0_EPCTL:
|
2417 |
/* Don't care for now */
|
2418 |
cpc->epctl = val & 0xC00000F3;
|
2419 |
break;
|
2420 |
case PPC405EP_CPC0_PLLMR0:
|
2421 |
cpc->pllmr[0] = val & 0x00633333; |
2422 |
ppc405ep_compute_clocks(cpc); |
2423 |
break;
|
2424 |
case PPC405EP_CPC0_PLLMR1:
|
2425 |
cpc->pllmr[1] = val & 0xC0F73FFF; |
2426 |
ppc405ep_compute_clocks(cpc); |
2427 |
break;
|
2428 |
case PPC405EP_CPC0_UCR:
|
2429 |
/* UART control - don't care for now */
|
2430 |
cpc->ucr = val & 0x003F7F7F;
|
2431 |
break;
|
2432 |
case PPC405EP_CPC0_SRR:
|
2433 |
cpc->srr = val; |
2434 |
break;
|
2435 |
case PPC405EP_CPC0_JTAGID:
|
2436 |
/* Read-only */
|
2437 |
break;
|
2438 |
case PPC405EP_CPC0_PCI:
|
2439 |
cpc->pci = val; |
2440 |
break;
|
2441 |
} |
2442 |
} |
2443 |
|
2444 |
static void ppc405ep_cpc_reset (void *opaque) |
2445 |
{ |
2446 |
ppc405ep_cpc_t *cpc = opaque; |
2447 |
|
2448 |
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
2449 |
cpc->epctl = 0x00000000;
|
2450 |
cpc->pllmr[0] = 0x00011010; |
2451 |
cpc->pllmr[1] = 0x40000000; |
2452 |
cpc->ucr = 0x00000000;
|
2453 |
cpc->srr = 0x00040000;
|
2454 |
cpc->pci = 0x00000000;
|
2455 |
cpc->er = 0x00000000;
|
2456 |
cpc->fr = 0x00000000;
|
2457 |
cpc->sr = 0x00000000;
|
2458 |
ppc405ep_compute_clocks(cpc); |
2459 |
} |
2460 |
|
2461 |
/* XXX: sysclk should be between 25 and 100 MHz */
|
2462 |
static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
2463 |
uint32_t sysclk) |
2464 |
{ |
2465 |
ppc405ep_cpc_t *cpc; |
2466 |
|
2467 |
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
2468 |
memcpy(cpc->clk_setup, clk_setup, |
2469 |
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
2470 |
cpc->jtagid = 0x20267049;
|
2471 |
cpc->sysclk = sysclk; |
2472 |
ppc405ep_cpc_reset(cpc); |
2473 |
qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
2474 |
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
2475 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2476 |
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
2477 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2478 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
2479 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2480 |
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
2481 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2482 |
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
2483 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2484 |
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
2485 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2486 |
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
2487 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2488 |
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
2489 |
&dcr_read_epcpc, &dcr_write_epcpc); |
2490 |
#if 0
|
2491 |
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
2492 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2493 |
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
2494 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2495 |
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
2496 |
&dcr_read_epcpc, &dcr_write_epcpc);
|
2497 |
#endif
|
2498 |
} |
2499 |
|
2500 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
2501 |
target_phys_addr_t ram_sizes[2],
|
2502 |
uint32_t sysclk, qemu_irq **picp, |
2503 |
int do_init)
|
2504 |
{ |
2505 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2506 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2507 |
CPUState *env; |
2508 |
qemu_irq *pic, *irqs; |
2509 |
|
2510 |
memset(clk_setup, 0, sizeof(clk_setup)); |
2511 |
/* init CPUs */
|
2512 |
env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
2513 |
&tlb_clk_setup, sysclk); |
2514 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
2515 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
2516 |
/* Internal devices init */
|
2517 |
/* Memory mapped devices registers */
|
2518 |
/* PLB arbitrer */
|
2519 |
ppc4xx_plb_init(env); |
2520 |
/* PLB to OPB bridge */
|
2521 |
ppc4xx_pob_init(env); |
2522 |
/* OBP arbitrer */
|
2523 |
ppc4xx_opba_init(0xef600600);
|
2524 |
/* Universal interrupt controller */
|
2525 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2526 |
irqs[PPCUIC_OUTPUT_INT] = |
2527 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2528 |
irqs[PPCUIC_OUTPUT_CINT] = |
2529 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2530 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2531 |
*picp = pic; |
2532 |
/* SDRAM controller */
|
2533 |
/* XXX 405EP has no ECC interrupt */
|
2534 |
ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
2535 |
/* External bus controller */
|
2536 |
ppc405_ebc_init(env); |
2537 |
/* DMA controller */
|
2538 |
dma_irqs[0] = pic[5]; |
2539 |
dma_irqs[1] = pic[6]; |
2540 |
dma_irqs[2] = pic[7]; |
2541 |
dma_irqs[3] = pic[8]; |
2542 |
ppc405_dma_init(env, dma_irqs); |
2543 |
/* IIC controller */
|
2544 |
ppc405_i2c_init(0xef600500, pic[2]); |
2545 |
/* GPIO */
|
2546 |
ppc405_gpio_init(0xef600700);
|
2547 |
/* Serial ports */
|
2548 |
if (serial_hds[0] != NULL) { |
2549 |
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, |
2550 |
serial_hds[0], 1); |
2551 |
} |
2552 |
if (serial_hds[1] != NULL) { |
2553 |
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, |
2554 |
serial_hds[1], 1); |
2555 |
} |
2556 |
/* OCM */
|
2557 |
ppc405_ocm_init(env); |
2558 |
/* GPT */
|
2559 |
gpt_irqs[0] = pic[19]; |
2560 |
gpt_irqs[1] = pic[20]; |
2561 |
gpt_irqs[2] = pic[21]; |
2562 |
gpt_irqs[3] = pic[22]; |
2563 |
gpt_irqs[4] = pic[23]; |
2564 |
ppc4xx_gpt_init(0xef600000, gpt_irqs);
|
2565 |
/* PCI */
|
2566 |
/* Uses pic[3], pic[16], pic[18] */
|
2567 |
/* MAL */
|
2568 |
mal_irqs[0] = pic[11]; |
2569 |
mal_irqs[1] = pic[12]; |
2570 |
mal_irqs[2] = pic[13]; |
2571 |
mal_irqs[3] = pic[14]; |
2572 |
ppc405_mal_init(env, mal_irqs); |
2573 |
/* Ethernet */
|
2574 |
/* Uses pic[9], pic[15], pic[17] */
|
2575 |
/* CPU control */
|
2576 |
ppc405ep_cpc_init(env, clk_setup, sysclk); |
2577 |
|
2578 |
return env;
|
2579 |
} |