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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * TI OMAP processors emulation.
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3 | c3d2689d | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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17 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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18 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | c3d2689d | balrog | * MA 02111-1307 USA
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20 | c3d2689d | balrog | */
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21 | 87ecb68b | pbrook | #include "hw.h" |
22 | 87ecb68b | pbrook | #include "arm-misc.h" |
23 | 87ecb68b | pbrook | #include "omap.h" |
24 | 87ecb68b | pbrook | #include "sysemu.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 827df9f3 | balrog | #include "qemu-char.h" |
27 | afbb5194 | balrog | #include "soc_dma.h" |
28 | 87ecb68b | pbrook | /* We use pc-style serial ports. */
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29 | 87ecb68b | pbrook | #include "pc.h" |
30 | c3d2689d | balrog | |
31 | 827df9f3 | balrog | /* Should signal the TCMI/GPMC */
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32 | 66450b15 | balrog | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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33 | 66450b15 | balrog | { |
34 | 02645926 | balrog | uint8_t ret; |
35 | 02645926 | balrog | |
36 | 66450b15 | balrog | OMAP_8B_REG(addr); |
37 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 1); |
38 | 02645926 | balrog | return ret;
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39 | 66450b15 | balrog | } |
40 | 66450b15 | balrog | |
41 | 66450b15 | balrog | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
42 | 66450b15 | balrog | uint32_t value) |
43 | 66450b15 | balrog | { |
44 | b854bc19 | balrog | uint8_t val8 = value; |
45 | b854bc19 | balrog | |
46 | 66450b15 | balrog | OMAP_8B_REG(addr); |
47 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val8, 1); |
48 | 66450b15 | balrog | } |
49 | 66450b15 | balrog | |
50 | b30bb3a2 | balrog | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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51 | c3d2689d | balrog | { |
52 | b854bc19 | balrog | uint16_t ret; |
53 | b854bc19 | balrog | |
54 | c3d2689d | balrog | OMAP_16B_REG(addr); |
55 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 2); |
56 | b854bc19 | balrog | return ret;
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57 | c3d2689d | balrog | } |
58 | c3d2689d | balrog | |
59 | b30bb3a2 | balrog | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
60 | c3d2689d | balrog | uint32_t value) |
61 | c3d2689d | balrog | { |
62 | b854bc19 | balrog | uint16_t val16 = value; |
63 | b854bc19 | balrog | |
64 | c3d2689d | balrog | OMAP_16B_REG(addr); |
65 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val16, 2); |
66 | c3d2689d | balrog | } |
67 | c3d2689d | balrog | |
68 | b30bb3a2 | balrog | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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69 | c3d2689d | balrog | { |
70 | b854bc19 | balrog | uint32_t ret; |
71 | b854bc19 | balrog | |
72 | c3d2689d | balrog | OMAP_32B_REG(addr); |
73 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 4); |
74 | b854bc19 | balrog | return ret;
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75 | c3d2689d | balrog | } |
76 | c3d2689d | balrog | |
77 | b30bb3a2 | balrog | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
78 | c3d2689d | balrog | uint32_t value) |
79 | c3d2689d | balrog | { |
80 | c3d2689d | balrog | OMAP_32B_REG(addr); |
81 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &value, 4); |
82 | c3d2689d | balrog | } |
83 | c3d2689d | balrog | |
84 | c3d2689d | balrog | /* Interrupt Handlers */
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85 | 106627d0 | balrog | struct omap_intr_handler_bank_s {
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86 | c3d2689d | balrog | uint32_t irqs; |
87 | 106627d0 | balrog | uint32_t inputs; |
88 | c3d2689d | balrog | uint32_t mask; |
89 | c3d2689d | balrog | uint32_t fiq; |
90 | 106627d0 | balrog | uint32_t sens_edge; |
91 | 827df9f3 | balrog | uint32_t swi; |
92 | 106627d0 | balrog | unsigned char priority[32]; |
93 | c3d2689d | balrog | }; |
94 | c3d2689d | balrog | |
95 | 106627d0 | balrog | struct omap_intr_handler_s {
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96 | 106627d0 | balrog | qemu_irq *pins; |
97 | 106627d0 | balrog | qemu_irq parent_intr[2];
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98 | 106627d0 | balrog | target_phys_addr_t base; |
99 | 106627d0 | balrog | unsigned char nbanks; |
100 | 827df9f3 | balrog | int level_only;
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101 | c3d2689d | balrog | |
102 | 106627d0 | balrog | /* state */
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103 | 106627d0 | balrog | uint32_t new_agr[2];
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104 | 106627d0 | balrog | int sir_intr[2]; |
105 | 827df9f3 | balrog | int autoidle;
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106 | 827df9f3 | balrog | uint32_t mask; |
107 | 827df9f3 | balrog | struct omap_intr_handler_bank_s bank[];
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108 | 106627d0 | balrog | }; |
109 | c3d2689d | balrog | |
110 | 106627d0 | balrog | static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
111 | 106627d0 | balrog | { |
112 | 106627d0 | balrog | int i, j, sir_intr, p_intr, p, f;
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113 | 106627d0 | balrog | uint32_t level; |
114 | 106627d0 | balrog | sir_intr = 0;
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115 | 106627d0 | balrog | p_intr = 255;
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116 | 106627d0 | balrog | |
117 | 106627d0 | balrog | /* Find the interrupt line with the highest dynamic priority.
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118 | 106627d0 | balrog | * Note: 0 denotes the hightest priority.
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119 | 106627d0 | balrog | * If all interrupts have the same priority, the default order is IRQ_N,
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120 | 106627d0 | balrog | * IRQ_N-1,...,IRQ_0. */
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121 | 106627d0 | balrog | for (j = 0; j < s->nbanks; ++j) { |
122 | 827df9f3 | balrog | level = s->bank[j].irqs & ~s->bank[j].mask & |
123 | 827df9f3 | balrog | (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
124 | 106627d0 | balrog | for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
125 | 106627d0 | balrog | level >>= f) { |
126 | 827df9f3 | balrog | p = s->bank[j].priority[i]; |
127 | 106627d0 | balrog | if (p <= p_intr) {
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128 | 106627d0 | balrog | p_intr = p; |
129 | 106627d0 | balrog | sir_intr = 32 * j + i;
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130 | 106627d0 | balrog | } |
131 | 106627d0 | balrog | f = ffs(level >> 1);
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132 | 106627d0 | balrog | } |
133 | cfa0b71d | balrog | } |
134 | 106627d0 | balrog | s->sir_intr[is_fiq] = sir_intr; |
135 | c3d2689d | balrog | } |
136 | c3d2689d | balrog | |
137 | 106627d0 | balrog | static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
138 | c3d2689d | balrog | { |
139 | 106627d0 | balrog | int i;
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140 | 106627d0 | balrog | uint32_t has_intr = 0;
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141 | c3d2689d | balrog | |
142 | 106627d0 | balrog | for (i = 0; i < s->nbanks; ++i) |
143 | 827df9f3 | balrog | has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
144 | 827df9f3 | balrog | (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
145 | c3d2689d | balrog | |
146 | 827df9f3 | balrog | if (s->new_agr[is_fiq] & has_intr & s->mask) {
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147 | 106627d0 | balrog | s->new_agr[is_fiq] = 0;
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148 | 106627d0 | balrog | omap_inth_sir_update(s, is_fiq); |
149 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[is_fiq], 1);
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150 | c3d2689d | balrog | } |
151 | c3d2689d | balrog | } |
152 | c3d2689d | balrog | |
153 | c3d2689d | balrog | #define INT_FALLING_EDGE 0 |
154 | c3d2689d | balrog | #define INT_LOW_LEVEL 1 |
155 | c3d2689d | balrog | |
156 | c3d2689d | balrog | static void omap_set_intr(void *opaque, int irq, int req) |
157 | c3d2689d | balrog | { |
158 | c3d2689d | balrog | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
159 | c3d2689d | balrog | uint32_t rise; |
160 | c3d2689d | balrog | |
161 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
162 | 106627d0 | balrog | int n = irq & 31; |
163 | 106627d0 | balrog | |
164 | c3d2689d | balrog | if (req) {
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165 | 106627d0 | balrog | rise = ~bank->irqs & (1 << n);
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166 | 106627d0 | balrog | if (~bank->sens_edge & (1 << n)) |
167 | 827df9f3 | balrog | rise &= ~bank->inputs; |
168 | 106627d0 | balrog | |
169 | 106627d0 | balrog | bank->inputs |= (1 << n);
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170 | 106627d0 | balrog | if (rise) {
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171 | 106627d0 | balrog | bank->irqs |= rise; |
172 | 106627d0 | balrog | omap_inth_update(ih, 0);
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173 | 106627d0 | balrog | omap_inth_update(ih, 1);
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174 | 106627d0 | balrog | } |
175 | c3d2689d | balrog | } else {
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176 | 106627d0 | balrog | rise = bank->sens_edge & bank->irqs & (1 << n);
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177 | 106627d0 | balrog | bank->irqs &= ~rise; |
178 | 106627d0 | balrog | bank->inputs &= ~(1 << n);
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179 | c3d2689d | balrog | } |
180 | c3d2689d | balrog | } |
181 | c3d2689d | balrog | |
182 | 827df9f3 | balrog | /* Simplified version with no edge detection */
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183 | 827df9f3 | balrog | static void omap_set_intr_noedge(void *opaque, int irq, int req) |
184 | 827df9f3 | balrog | { |
185 | 827df9f3 | balrog | struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
186 | 827df9f3 | balrog | uint32_t rise; |
187 | 827df9f3 | balrog | |
188 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
189 | 827df9f3 | balrog | int n = irq & 31; |
190 | 827df9f3 | balrog | |
191 | 827df9f3 | balrog | if (req) {
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192 | 827df9f3 | balrog | rise = ~bank->inputs & (1 << n);
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193 | 827df9f3 | balrog | if (rise) {
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194 | 827df9f3 | balrog | bank->irqs |= bank->inputs |= rise; |
195 | 827df9f3 | balrog | omap_inth_update(ih, 0);
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196 | 827df9f3 | balrog | omap_inth_update(ih, 1);
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197 | 827df9f3 | balrog | } |
198 | 827df9f3 | balrog | } else
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199 | 827df9f3 | balrog | bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
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200 | 827df9f3 | balrog | } |
201 | 827df9f3 | balrog | |
202 | c3d2689d | balrog | static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
203 | c3d2689d | balrog | { |
204 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
205 | c3d2689d | balrog | int i, offset = addr - s->base;
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206 | 106627d0 | balrog | int bank_no = offset >> 8; |
207 | 106627d0 | balrog | int line_no;
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208 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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209 | 106627d0 | balrog | offset &= 0xff;
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210 | c3d2689d | balrog | |
211 | c3d2689d | balrog | switch (offset) {
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212 | c3d2689d | balrog | case 0x00: /* ITR */ |
213 | 106627d0 | balrog | return bank->irqs;
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214 | c3d2689d | balrog | |
215 | c3d2689d | balrog | case 0x04: /* MIR */ |
216 | 106627d0 | balrog | return bank->mask;
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217 | c3d2689d | balrog | |
218 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
219 | 106627d0 | balrog | case 0x14: /* SIR_FIQ_CODE */ |
220 | 106627d0 | balrog | if (bank_no != 0) |
221 | 106627d0 | balrog | break;
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222 | 106627d0 | balrog | line_no = s->sir_intr[(offset - 0x10) >> 2]; |
223 | 827df9f3 | balrog | bank = &s->bank[line_no >> 5];
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224 | 106627d0 | balrog | i = line_no & 31;
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225 | 106627d0 | balrog | if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
226 | 106627d0 | balrog | bank->irqs &= ~(1 << i);
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227 | f2df5260 | balrog | return line_no;
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228 | c3d2689d | balrog | |
229 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
230 | 106627d0 | balrog | if (bank_no != 0) |
231 | 106627d0 | balrog | break;
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232 | c3d2689d | balrog | return 0; |
233 | c3d2689d | balrog | |
234 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
235 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
236 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
237 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
238 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
239 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
240 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
241 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
242 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
243 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
244 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
245 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
246 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
247 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
248 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
249 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
250 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
251 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
252 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
253 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
254 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
255 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
256 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
257 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
258 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
259 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
260 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
261 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
262 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
263 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
264 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
265 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
266 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
267 | 106627d0 | balrog | return (bank->priority[i] << 2) | |
268 | 106627d0 | balrog | (((bank->sens_edge >> i) & 1) << 1) | |
269 | 106627d0 | balrog | ((bank->fiq >> i) & 1);
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270 | c3d2689d | balrog | |
271 | c3d2689d | balrog | case 0x9c: /* ISR */ |
272 | c3d2689d | balrog | return 0x00000000; |
273 | c3d2689d | balrog | |
274 | c3d2689d | balrog | } |
275 | 106627d0 | balrog | OMAP_BAD_REG(addr); |
276 | c3d2689d | balrog | return 0; |
277 | c3d2689d | balrog | } |
278 | c3d2689d | balrog | |
279 | c3d2689d | balrog | static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
280 | c3d2689d | balrog | uint32_t value) |
281 | c3d2689d | balrog | { |
282 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
283 | c3d2689d | balrog | int i, offset = addr - s->base;
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284 | 106627d0 | balrog | int bank_no = offset >> 8; |
285 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
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286 | 106627d0 | balrog | offset &= 0xff;
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287 | c3d2689d | balrog | |
288 | c3d2689d | balrog | switch (offset) {
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289 | c3d2689d | balrog | case 0x00: /* ITR */ |
290 | 106627d0 | balrog | /* Important: ignore the clearing if the IRQ is level-triggered and
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291 | 106627d0 | balrog | the input bit is 1 */
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292 | 106627d0 | balrog | bank->irqs &= value | (bank->inputs & bank->sens_edge); |
293 | c3d2689d | balrog | return;
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294 | c3d2689d | balrog | |
295 | c3d2689d | balrog | case 0x04: /* MIR */ |
296 | 106627d0 | balrog | bank->mask = value; |
297 | 106627d0 | balrog | omap_inth_update(s, 0);
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298 | 106627d0 | balrog | omap_inth_update(s, 1);
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299 | c3d2689d | balrog | return;
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300 | c3d2689d | balrog | |
301 | c3d2689d | balrog | case 0x10: /* SIR_IRQ_CODE */ |
302 | c3d2689d | balrog | case 0x14: /* SIR_FIQ_CODE */ |
303 | c3d2689d | balrog | OMAP_RO_REG(addr); |
304 | c3d2689d | balrog | break;
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305 | c3d2689d | balrog | |
306 | c3d2689d | balrog | case 0x18: /* CONTROL_REG */ |
307 | 106627d0 | balrog | if (bank_no != 0) |
308 | 106627d0 | balrog | break;
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309 | 106627d0 | balrog | if (value & 2) { |
310 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[1], 0); |
311 | 106627d0 | balrog | s->new_agr[1] = ~0; |
312 | 106627d0 | balrog | omap_inth_update(s, 1);
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313 | 106627d0 | balrog | } |
314 | 106627d0 | balrog | if (value & 1) { |
315 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[0], 0); |
316 | 106627d0 | balrog | s->new_agr[0] = ~0; |
317 | 106627d0 | balrog | omap_inth_update(s, 0);
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318 | 106627d0 | balrog | } |
319 | c3d2689d | balrog | return;
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320 | c3d2689d | balrog | |
321 | c3d2689d | balrog | case 0x1c: /* ILR0 */ |
322 | c3d2689d | balrog | case 0x20: /* ILR1 */ |
323 | c3d2689d | balrog | case 0x24: /* ILR2 */ |
324 | c3d2689d | balrog | case 0x28: /* ILR3 */ |
325 | c3d2689d | balrog | case 0x2c: /* ILR4 */ |
326 | c3d2689d | balrog | case 0x30: /* ILR5 */ |
327 | c3d2689d | balrog | case 0x34: /* ILR6 */ |
328 | c3d2689d | balrog | case 0x38: /* ILR7 */ |
329 | c3d2689d | balrog | case 0x3c: /* ILR8 */ |
330 | c3d2689d | balrog | case 0x40: /* ILR9 */ |
331 | c3d2689d | balrog | case 0x44: /* ILR10 */ |
332 | c3d2689d | balrog | case 0x48: /* ILR11 */ |
333 | c3d2689d | balrog | case 0x4c: /* ILR12 */ |
334 | c3d2689d | balrog | case 0x50: /* ILR13 */ |
335 | c3d2689d | balrog | case 0x54: /* ILR14 */ |
336 | c3d2689d | balrog | case 0x58: /* ILR15 */ |
337 | c3d2689d | balrog | case 0x5c: /* ILR16 */ |
338 | c3d2689d | balrog | case 0x60: /* ILR17 */ |
339 | c3d2689d | balrog | case 0x64: /* ILR18 */ |
340 | c3d2689d | balrog | case 0x68: /* ILR19 */ |
341 | c3d2689d | balrog | case 0x6c: /* ILR20 */ |
342 | c3d2689d | balrog | case 0x70: /* ILR21 */ |
343 | c3d2689d | balrog | case 0x74: /* ILR22 */ |
344 | c3d2689d | balrog | case 0x78: /* ILR23 */ |
345 | c3d2689d | balrog | case 0x7c: /* ILR24 */ |
346 | c3d2689d | balrog | case 0x80: /* ILR25 */ |
347 | c3d2689d | balrog | case 0x84: /* ILR26 */ |
348 | c3d2689d | balrog | case 0x88: /* ILR27 */ |
349 | c3d2689d | balrog | case 0x8c: /* ILR28 */ |
350 | c3d2689d | balrog | case 0x90: /* ILR29 */ |
351 | c3d2689d | balrog | case 0x94: /* ILR30 */ |
352 | c3d2689d | balrog | case 0x98: /* ILR31 */ |
353 | c3d2689d | balrog | i = (offset - 0x1c) >> 2; |
354 | 106627d0 | balrog | bank->priority[i] = (value >> 2) & 0x1f; |
355 | 106627d0 | balrog | bank->sens_edge &= ~(1 << i);
|
356 | 106627d0 | balrog | bank->sens_edge |= ((value >> 1) & 1) << i; |
357 | 106627d0 | balrog | bank->fiq &= ~(1 << i);
|
358 | 106627d0 | balrog | bank->fiq |= (value & 1) << i;
|
359 | c3d2689d | balrog | return;
|
360 | c3d2689d | balrog | |
361 | c3d2689d | balrog | case 0x9c: /* ISR */ |
362 | c3d2689d | balrog | for (i = 0; i < 32; i ++) |
363 | c3d2689d | balrog | if (value & (1 << i)) { |
364 | 106627d0 | balrog | omap_set_intr(s, 32 * bank_no + i, 1); |
365 | c3d2689d | balrog | return;
|
366 | c3d2689d | balrog | } |
367 | c3d2689d | balrog | return;
|
368 | c3d2689d | balrog | } |
369 | 106627d0 | balrog | OMAP_BAD_REG(addr); |
370 | c3d2689d | balrog | } |
371 | c3d2689d | balrog | |
372 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_inth_readfn[] = {
|
373 | c3d2689d | balrog | omap_badwidth_read32, |
374 | c3d2689d | balrog | omap_badwidth_read32, |
375 | c3d2689d | balrog | omap_inth_read, |
376 | c3d2689d | balrog | }; |
377 | c3d2689d | balrog | |
378 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_inth_writefn[] = {
|
379 | c3d2689d | balrog | omap_inth_write, |
380 | c3d2689d | balrog | omap_inth_write, |
381 | c3d2689d | balrog | omap_inth_write, |
382 | c3d2689d | balrog | }; |
383 | c3d2689d | balrog | |
384 | 106627d0 | balrog | void omap_inth_reset(struct omap_intr_handler_s *s) |
385 | c3d2689d | balrog | { |
386 | 106627d0 | balrog | int i;
|
387 | 106627d0 | balrog | |
388 | 106627d0 | balrog | for (i = 0; i < s->nbanks; ++i){ |
389 | 827df9f3 | balrog | s->bank[i].irqs = 0x00000000;
|
390 | 827df9f3 | balrog | s->bank[i].mask = 0xffffffff;
|
391 | 827df9f3 | balrog | s->bank[i].sens_edge = 0x00000000;
|
392 | 827df9f3 | balrog | s->bank[i].fiq = 0x00000000;
|
393 | 827df9f3 | balrog | s->bank[i].inputs = 0x00000000;
|
394 | 827df9f3 | balrog | s->bank[i].swi = 0x00000000;
|
395 | 827df9f3 | balrog | memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
396 | 827df9f3 | balrog | |
397 | 827df9f3 | balrog | if (s->level_only)
|
398 | 827df9f3 | balrog | s->bank[i].sens_edge = 0xffffffff;
|
399 | 106627d0 | balrog | } |
400 | c3d2689d | balrog | |
401 | 106627d0 | balrog | s->new_agr[0] = ~0; |
402 | 106627d0 | balrog | s->new_agr[1] = ~0; |
403 | 106627d0 | balrog | s->sir_intr[0] = 0; |
404 | 106627d0 | balrog | s->sir_intr[1] = 0; |
405 | 827df9f3 | balrog | s->autoidle = 0;
|
406 | 827df9f3 | balrog | s->mask = ~0;
|
407 | 106627d0 | balrog | |
408 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[0], 0); |
409 | 106627d0 | balrog | qemu_set_irq(s->parent_intr[1], 0); |
410 | c3d2689d | balrog | } |
411 | c3d2689d | balrog | |
412 | c3d2689d | balrog | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
413 | 827df9f3 | balrog | unsigned long size, unsigned char nbanks, qemu_irq **pins, |
414 | 106627d0 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
415 | c3d2689d | balrog | { |
416 | c3d2689d | balrog | int iomemtype;
|
417 | c3d2689d | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
418 | 106627d0 | balrog | qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
419 | 106627d0 | balrog | sizeof(struct omap_intr_handler_bank_s) * nbanks); |
420 | c3d2689d | balrog | |
421 | 106627d0 | balrog | s->parent_intr[0] = parent_irq;
|
422 | 106627d0 | balrog | s->parent_intr[1] = parent_fiq;
|
423 | c3d2689d | balrog | s->base = base; |
424 | 106627d0 | balrog | s->nbanks = nbanks; |
425 | 106627d0 | balrog | s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
|
426 | 827df9f3 | balrog | if (pins)
|
427 | 827df9f3 | balrog | *pins = s->pins; |
428 | 106627d0 | balrog | |
429 | c3d2689d | balrog | omap_inth_reset(s); |
430 | c3d2689d | balrog | |
431 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
432 | c3d2689d | balrog | omap_inth_writefn, s); |
433 | c3d2689d | balrog | cpu_register_physical_memory(s->base, size, iomemtype); |
434 | c3d2689d | balrog | |
435 | c3d2689d | balrog | return s;
|
436 | c3d2689d | balrog | } |
437 | c3d2689d | balrog | |
438 | 827df9f3 | balrog | static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
439 | 827df9f3 | balrog | { |
440 | 827df9f3 | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
441 | 827df9f3 | balrog | int offset = addr - s->base;
|
442 | 827df9f3 | balrog | int bank_no, line_no;
|
443 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = 0; |
444 | 827df9f3 | balrog | |
445 | 827df9f3 | balrog | if ((offset & 0xf80) == 0x80) { |
446 | 827df9f3 | balrog | bank_no = (offset & 0x60) >> 5; |
447 | 827df9f3 | balrog | if (bank_no < s->nbanks) {
|
448 | 827df9f3 | balrog | offset &= ~0x60;
|
449 | 827df9f3 | balrog | bank = &s->bank[bank_no]; |
450 | 827df9f3 | balrog | } |
451 | 827df9f3 | balrog | } |
452 | 827df9f3 | balrog | |
453 | 827df9f3 | balrog | switch (offset) {
|
454 | 827df9f3 | balrog | case 0x00: /* INTC_REVISION */ |
455 | 827df9f3 | balrog | return 0x21; |
456 | 827df9f3 | balrog | |
457 | 827df9f3 | balrog | case 0x10: /* INTC_SYSCONFIG */ |
458 | 827df9f3 | balrog | return (s->autoidle >> 2) & 1; |
459 | 827df9f3 | balrog | |
460 | 827df9f3 | balrog | case 0x14: /* INTC_SYSSTATUS */ |
461 | 827df9f3 | balrog | return 1; /* RESETDONE */ |
462 | 827df9f3 | balrog | |
463 | 827df9f3 | balrog | case 0x40: /* INTC_SIR_IRQ */ |
464 | 827df9f3 | balrog | return s->sir_intr[0]; |
465 | 827df9f3 | balrog | |
466 | 827df9f3 | balrog | case 0x44: /* INTC_SIR_FIQ */ |
467 | 827df9f3 | balrog | return s->sir_intr[1]; |
468 | 827df9f3 | balrog | |
469 | 827df9f3 | balrog | case 0x48: /* INTC_CONTROL */ |
470 | 827df9f3 | balrog | return (!s->mask) << 2; /* GLOBALMASK */ |
471 | 827df9f3 | balrog | |
472 | 827df9f3 | balrog | case 0x4c: /* INTC_PROTECTION */ |
473 | 827df9f3 | balrog | return 0; |
474 | 827df9f3 | balrog | |
475 | 827df9f3 | balrog | case 0x50: /* INTC_IDLE */ |
476 | 827df9f3 | balrog | return s->autoidle & 3; |
477 | 827df9f3 | balrog | |
478 | 827df9f3 | balrog | /* Per-bank registers */
|
479 | 827df9f3 | balrog | case 0x80: /* INTC_ITR */ |
480 | 827df9f3 | balrog | return bank->inputs;
|
481 | 827df9f3 | balrog | |
482 | 827df9f3 | balrog | case 0x84: /* INTC_MIR */ |
483 | 827df9f3 | balrog | return bank->mask;
|
484 | 827df9f3 | balrog | |
485 | 827df9f3 | balrog | case 0x88: /* INTC_MIR_CLEAR */ |
486 | 827df9f3 | balrog | case 0x8c: /* INTC_MIR_SET */ |
487 | 827df9f3 | balrog | return 0; |
488 | 827df9f3 | balrog | |
489 | 827df9f3 | balrog | case 0x90: /* INTC_ISR_SET */ |
490 | 827df9f3 | balrog | return bank->swi;
|
491 | 827df9f3 | balrog | |
492 | 827df9f3 | balrog | case 0x94: /* INTC_ISR_CLEAR */ |
493 | 827df9f3 | balrog | return 0; |
494 | 827df9f3 | balrog | |
495 | 827df9f3 | balrog | case 0x98: /* INTC_PENDING_IRQ */ |
496 | 827df9f3 | balrog | return bank->irqs & ~bank->mask & ~bank->fiq;
|
497 | 827df9f3 | balrog | |
498 | 827df9f3 | balrog | case 0x9c: /* INTC_PENDING_FIQ */ |
499 | 827df9f3 | balrog | return bank->irqs & ~bank->mask & bank->fiq;
|
500 | 827df9f3 | balrog | |
501 | 827df9f3 | balrog | /* Per-line registers */
|
502 | 827df9f3 | balrog | case 0x100 ... 0x300: /* INTC_ILR */ |
503 | 827df9f3 | balrog | bank_no = (offset - 0x100) >> 7; |
504 | 827df9f3 | balrog | if (bank_no > s->nbanks)
|
505 | 827df9f3 | balrog | break;
|
506 | 827df9f3 | balrog | bank = &s->bank[bank_no]; |
507 | 827df9f3 | balrog | line_no = (offset & 0x7f) >> 2; |
508 | 827df9f3 | balrog | return (bank->priority[line_no] << 2) | |
509 | 827df9f3 | balrog | ((bank->fiq >> line_no) & 1);
|
510 | 827df9f3 | balrog | } |
511 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
512 | 827df9f3 | balrog | return 0; |
513 | 827df9f3 | balrog | } |
514 | 827df9f3 | balrog | |
515 | 827df9f3 | balrog | static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
516 | 827df9f3 | balrog | uint32_t value) |
517 | 827df9f3 | balrog | { |
518 | 827df9f3 | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
519 | 827df9f3 | balrog | int offset = addr - s->base;
|
520 | 827df9f3 | balrog | int bank_no, line_no;
|
521 | 827df9f3 | balrog | struct omap_intr_handler_bank_s *bank = 0; |
522 | 827df9f3 | balrog | |
523 | 827df9f3 | balrog | if ((offset & 0xf80) == 0x80) { |
524 | 827df9f3 | balrog | bank_no = (offset & 0x60) >> 5; |
525 | 827df9f3 | balrog | if (bank_no < s->nbanks) {
|
526 | 827df9f3 | balrog | offset &= ~0x60;
|
527 | 827df9f3 | balrog | bank = &s->bank[bank_no]; |
528 | 827df9f3 | balrog | } |
529 | 827df9f3 | balrog | } |
530 | 827df9f3 | balrog | |
531 | 827df9f3 | balrog | switch (offset) {
|
532 | 827df9f3 | balrog | case 0x10: /* INTC_SYSCONFIG */ |
533 | 827df9f3 | balrog | s->autoidle &= 4;
|
534 | 827df9f3 | balrog | s->autoidle |= (value & 1) << 2; |
535 | 827df9f3 | balrog | if (value & 2) /* SOFTRESET */ |
536 | 827df9f3 | balrog | omap_inth_reset(s); |
537 | 827df9f3 | balrog | return;
|
538 | 827df9f3 | balrog | |
539 | 827df9f3 | balrog | case 0x48: /* INTC_CONTROL */ |
540 | 827df9f3 | balrog | s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
541 | 827df9f3 | balrog | if (value & 2) { /* NEWFIQAGR */ |
542 | 827df9f3 | balrog | qemu_set_irq(s->parent_intr[1], 0); |
543 | 827df9f3 | balrog | s->new_agr[1] = ~0; |
544 | 827df9f3 | balrog | omap_inth_update(s, 1);
|
545 | 827df9f3 | balrog | } |
546 | 827df9f3 | balrog | if (value & 1) { /* NEWIRQAGR */ |
547 | 827df9f3 | balrog | qemu_set_irq(s->parent_intr[0], 0); |
548 | 827df9f3 | balrog | s->new_agr[0] = ~0; |
549 | 827df9f3 | balrog | omap_inth_update(s, 0);
|
550 | 827df9f3 | balrog | } |
551 | 827df9f3 | balrog | return;
|
552 | 827df9f3 | balrog | |
553 | 827df9f3 | balrog | case 0x4c: /* INTC_PROTECTION */ |
554 | 827df9f3 | balrog | /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
|
555 | 827df9f3 | balrog | * for every register, see Chapter 3 and 4 for privileged mode. */
|
556 | 827df9f3 | balrog | if (value & 1) |
557 | 827df9f3 | balrog | fprintf(stderr, "%s: protection mode enable attempt\n",
|
558 | 827df9f3 | balrog | __FUNCTION__); |
559 | 827df9f3 | balrog | return;
|
560 | 827df9f3 | balrog | |
561 | 827df9f3 | balrog | case 0x50: /* INTC_IDLE */ |
562 | 827df9f3 | balrog | s->autoidle &= ~3;
|
563 | 827df9f3 | balrog | s->autoidle |= value & 3;
|
564 | 827df9f3 | balrog | return;
|
565 | 827df9f3 | balrog | |
566 | 827df9f3 | balrog | /* Per-bank registers */
|
567 | 827df9f3 | balrog | case 0x84: /* INTC_MIR */ |
568 | 827df9f3 | balrog | bank->mask = value; |
569 | 827df9f3 | balrog | omap_inth_update(s, 0);
|
570 | 827df9f3 | balrog | omap_inth_update(s, 1);
|
571 | 827df9f3 | balrog | return;
|
572 | 827df9f3 | balrog | |
573 | 827df9f3 | balrog | case 0x88: /* INTC_MIR_CLEAR */ |
574 | 827df9f3 | balrog | bank->mask &= ~value; |
575 | 827df9f3 | balrog | omap_inth_update(s, 0);
|
576 | 827df9f3 | balrog | omap_inth_update(s, 1);
|
577 | 827df9f3 | balrog | return;
|
578 | 827df9f3 | balrog | |
579 | 827df9f3 | balrog | case 0x8c: /* INTC_MIR_SET */ |
580 | 827df9f3 | balrog | bank->mask |= value; |
581 | 827df9f3 | balrog | return;
|
582 | 827df9f3 | balrog | |
583 | 827df9f3 | balrog | case 0x90: /* INTC_ISR_SET */ |
584 | 827df9f3 | balrog | bank->irqs |= bank->swi |= value; |
585 | 827df9f3 | balrog | omap_inth_update(s, 0);
|
586 | 827df9f3 | balrog | omap_inth_update(s, 1);
|
587 | 827df9f3 | balrog | return;
|
588 | 827df9f3 | balrog | |
589 | 827df9f3 | balrog | case 0x94: /* INTC_ISR_CLEAR */ |
590 | 827df9f3 | balrog | bank->swi &= ~value; |
591 | 827df9f3 | balrog | bank->irqs = bank->swi & bank->inputs; |
592 | 827df9f3 | balrog | return;
|
593 | 827df9f3 | balrog | |
594 | 827df9f3 | balrog | /* Per-line registers */
|
595 | 827df9f3 | balrog | case 0x100 ... 0x300: /* INTC_ILR */ |
596 | 827df9f3 | balrog | bank_no = (offset - 0x100) >> 7; |
597 | 827df9f3 | balrog | if (bank_no > s->nbanks)
|
598 | 827df9f3 | balrog | break;
|
599 | 827df9f3 | balrog | bank = &s->bank[bank_no]; |
600 | 827df9f3 | balrog | line_no = (offset & 0x7f) >> 2; |
601 | 827df9f3 | balrog | bank->priority[line_no] = (value >> 2) & 0x3f; |
602 | 827df9f3 | balrog | bank->fiq &= ~(1 << line_no);
|
603 | 827df9f3 | balrog | bank->fiq |= (value & 1) << line_no;
|
604 | 827df9f3 | balrog | return;
|
605 | 827df9f3 | balrog | |
606 | 827df9f3 | balrog | case 0x00: /* INTC_REVISION */ |
607 | 827df9f3 | balrog | case 0x14: /* INTC_SYSSTATUS */ |
608 | 827df9f3 | balrog | case 0x40: /* INTC_SIR_IRQ */ |
609 | 827df9f3 | balrog | case 0x44: /* INTC_SIR_FIQ */ |
610 | 827df9f3 | balrog | case 0x80: /* INTC_ITR */ |
611 | 827df9f3 | balrog | case 0x98: /* INTC_PENDING_IRQ */ |
612 | 827df9f3 | balrog | case 0x9c: /* INTC_PENDING_FIQ */ |
613 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
614 | 827df9f3 | balrog | return;
|
615 | 827df9f3 | balrog | } |
616 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
617 | 827df9f3 | balrog | } |
618 | 827df9f3 | balrog | |
619 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap2_inth_readfn[] = {
|
620 | 827df9f3 | balrog | omap_badwidth_read32, |
621 | 827df9f3 | balrog | omap_badwidth_read32, |
622 | 827df9f3 | balrog | omap2_inth_read, |
623 | 827df9f3 | balrog | }; |
624 | 827df9f3 | balrog | |
625 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
|
626 | 827df9f3 | balrog | omap2_inth_write, |
627 | 827df9f3 | balrog | omap2_inth_write, |
628 | 827df9f3 | balrog | omap2_inth_write, |
629 | 827df9f3 | balrog | }; |
630 | 827df9f3 | balrog | |
631 | 827df9f3 | balrog | struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
|
632 | 827df9f3 | balrog | int size, int nbanks, qemu_irq **pins, |
633 | 827df9f3 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, |
634 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk) |
635 | 827df9f3 | balrog | { |
636 | 827df9f3 | balrog | int iomemtype;
|
637 | 827df9f3 | balrog | struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
638 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
639 | 827df9f3 | balrog | sizeof(struct omap_intr_handler_bank_s) * nbanks); |
640 | 827df9f3 | balrog | |
641 | 827df9f3 | balrog | s->parent_intr[0] = parent_irq;
|
642 | 827df9f3 | balrog | s->parent_intr[1] = parent_fiq;
|
643 | 827df9f3 | balrog | s->base = base; |
644 | 827df9f3 | balrog | s->nbanks = nbanks; |
645 | 827df9f3 | balrog | s->level_only = 1;
|
646 | 827df9f3 | balrog | s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
|
647 | 827df9f3 | balrog | if (pins)
|
648 | 827df9f3 | balrog | *pins = s->pins; |
649 | 827df9f3 | balrog | |
650 | 827df9f3 | balrog | omap_inth_reset(s); |
651 | 827df9f3 | balrog | |
652 | 827df9f3 | balrog | iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
|
653 | 827df9f3 | balrog | omap2_inth_writefn, s); |
654 | 827df9f3 | balrog | cpu_register_physical_memory(s->base, size, iomemtype); |
655 | 827df9f3 | balrog | |
656 | 827df9f3 | balrog | return s;
|
657 | 827df9f3 | balrog | } |
658 | 827df9f3 | balrog | |
659 | c3d2689d | balrog | /* MPU OS timers */
|
660 | c3d2689d | balrog | struct omap_mpu_timer_s {
|
661 | c3d2689d | balrog | qemu_irq irq; |
662 | c3d2689d | balrog | omap_clk clk; |
663 | c3d2689d | balrog | target_phys_addr_t base; |
664 | c3d2689d | balrog | uint32_t val; |
665 | c3d2689d | balrog | int64_t time; |
666 | c3d2689d | balrog | QEMUTimer *timer; |
667 | e856f2ad | balrog | QEMUBH *tick; |
668 | c3d2689d | balrog | int64_t rate; |
669 | c3d2689d | balrog | int it_ena;
|
670 | c3d2689d | balrog | |
671 | c3d2689d | balrog | int enable;
|
672 | c3d2689d | balrog | int ptv;
|
673 | c3d2689d | balrog | int ar;
|
674 | c3d2689d | balrog | int st;
|
675 | c3d2689d | balrog | uint32_t reset_val; |
676 | c3d2689d | balrog | }; |
677 | c3d2689d | balrog | |
678 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
679 | c3d2689d | balrog | { |
680 | c3d2689d | balrog | uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
681 | c3d2689d | balrog | |
682 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
|
683 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
684 | c3d2689d | balrog | timer->rate, ticks_per_sec); |
685 | c3d2689d | balrog | else
|
686 | c3d2689d | balrog | return timer->val;
|
687 | c3d2689d | balrog | } |
688 | c3d2689d | balrog | |
689 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
690 | c3d2689d | balrog | { |
691 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
692 | c3d2689d | balrog | timer->time = qemu_get_clock(vm_clock); |
693 | c3d2689d | balrog | } |
694 | c3d2689d | balrog | |
695 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
696 | c3d2689d | balrog | { |
697 | c3d2689d | balrog | int64_t expires; |
698 | c3d2689d | balrog | |
699 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
|
700 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
|
701 | b8b137d6 | balrog | expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
|
702 | c3d2689d | balrog | ticks_per_sec, timer->rate); |
703 | b854bc19 | balrog | |
704 | b854bc19 | balrog | /* If timer expiry would be sooner than in about 1 ms and
|
705 | b854bc19 | balrog | * auto-reload isn't set, then fire immediately. This is a hack
|
706 | b854bc19 | balrog | * to make systems like PalmOS run in acceptable time. PalmOS
|
707 | b854bc19 | balrog | * sets the interval to a very low value and polls the status bit
|
708 | b854bc19 | balrog | * in a busy loop when it wants to sleep just a couple of CPU
|
709 | b854bc19 | balrog | * ticks. */
|
710 | b854bc19 | balrog | if (expires > (ticks_per_sec >> 10) || timer->ar) |
711 | b854bc19 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
712 | e856f2ad | balrog | else
|
713 | e856f2ad | balrog | qemu_bh_schedule(timer->tick); |
714 | c3d2689d | balrog | } else
|
715 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
716 | c3d2689d | balrog | } |
717 | c3d2689d | balrog | |
718 | e856f2ad | balrog | static void omap_timer_fire(void *opaque) |
719 | c3d2689d | balrog | { |
720 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = opaque;
|
721 | c3d2689d | balrog | |
722 | c3d2689d | balrog | if (!timer->ar) {
|
723 | c3d2689d | balrog | timer->val = 0;
|
724 | c3d2689d | balrog | timer->st = 0;
|
725 | c3d2689d | balrog | } |
726 | c3d2689d | balrog | |
727 | c3d2689d | balrog | if (timer->it_ena)
|
728 | 106627d0 | balrog | /* Edge-triggered irq */
|
729 | 106627d0 | balrog | qemu_irq_pulse(timer->irq); |
730 | e856f2ad | balrog | } |
731 | e856f2ad | balrog | |
732 | e856f2ad | balrog | static void omap_timer_tick(void *opaque) |
733 | e856f2ad | balrog | { |
734 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
735 | e856f2ad | balrog | |
736 | e856f2ad | balrog | omap_timer_sync(timer); |
737 | e856f2ad | balrog | omap_timer_fire(timer); |
738 | c3d2689d | balrog | omap_timer_update(timer); |
739 | c3d2689d | balrog | } |
740 | c3d2689d | balrog | |
741 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
742 | c3d2689d | balrog | { |
743 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
744 | c3d2689d | balrog | |
745 | c3d2689d | balrog | omap_timer_sync(timer); |
746 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
747 | c3d2689d | balrog | omap_timer_update(timer); |
748 | c3d2689d | balrog | } |
749 | c3d2689d | balrog | |
750 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
751 | c3d2689d | balrog | { |
752 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
753 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
754 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
755 | c3d2689d | balrog | } |
756 | c3d2689d | balrog | |
757 | c3d2689d | balrog | static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
758 | c3d2689d | balrog | { |
759 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
760 | c3d2689d | balrog | int offset = addr - s->base;
|
761 | c3d2689d | balrog | |
762 | c3d2689d | balrog | switch (offset) {
|
763 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
764 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
765 | c3d2689d | balrog | |
766 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
767 | c3d2689d | balrog | break;
|
768 | c3d2689d | balrog | |
769 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
770 | c3d2689d | balrog | return omap_timer_read(s);
|
771 | c3d2689d | balrog | } |
772 | c3d2689d | balrog | |
773 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
774 | c3d2689d | balrog | return 0; |
775 | c3d2689d | balrog | } |
776 | c3d2689d | balrog | |
777 | c3d2689d | balrog | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
778 | c3d2689d | balrog | uint32_t value) |
779 | c3d2689d | balrog | { |
780 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
781 | c3d2689d | balrog | int offset = addr - s->base;
|
782 | c3d2689d | balrog | |
783 | c3d2689d | balrog | switch (offset) {
|
784 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
785 | c3d2689d | balrog | omap_timer_sync(s); |
786 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
787 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
788 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
789 | c3d2689d | balrog | s->st = value & 1;
|
790 | c3d2689d | balrog | omap_timer_update(s); |
791 | c3d2689d | balrog | return;
|
792 | c3d2689d | balrog | |
793 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
794 | c3d2689d | balrog | s->reset_val = value; |
795 | c3d2689d | balrog | return;
|
796 | c3d2689d | balrog | |
797 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
798 | c3d2689d | balrog | OMAP_RO_REG(addr); |
799 | c3d2689d | balrog | break;
|
800 | c3d2689d | balrog | |
801 | c3d2689d | balrog | default:
|
802 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
803 | c3d2689d | balrog | } |
804 | c3d2689d | balrog | } |
805 | c3d2689d | balrog | |
806 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
807 | c3d2689d | balrog | omap_badwidth_read32, |
808 | c3d2689d | balrog | omap_badwidth_read32, |
809 | c3d2689d | balrog | omap_mpu_timer_read, |
810 | c3d2689d | balrog | }; |
811 | c3d2689d | balrog | |
812 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
813 | c3d2689d | balrog | omap_badwidth_write32, |
814 | c3d2689d | balrog | omap_badwidth_write32, |
815 | c3d2689d | balrog | omap_mpu_timer_write, |
816 | c3d2689d | balrog | }; |
817 | c3d2689d | balrog | |
818 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
819 | c3d2689d | balrog | { |
820 | c3d2689d | balrog | qemu_del_timer(s->timer); |
821 | c3d2689d | balrog | s->enable = 0;
|
822 | c3d2689d | balrog | s->reset_val = 31337;
|
823 | c3d2689d | balrog | s->val = 0;
|
824 | c3d2689d | balrog | s->ptv = 0;
|
825 | c3d2689d | balrog | s->ar = 0;
|
826 | c3d2689d | balrog | s->st = 0;
|
827 | c3d2689d | balrog | s->it_ena = 1;
|
828 | c3d2689d | balrog | } |
829 | c3d2689d | balrog | |
830 | c3d2689d | balrog | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
831 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
832 | c3d2689d | balrog | { |
833 | c3d2689d | balrog | int iomemtype;
|
834 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
835 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
836 | c3d2689d | balrog | |
837 | c3d2689d | balrog | s->irq = irq; |
838 | c3d2689d | balrog | s->clk = clk; |
839 | c3d2689d | balrog | s->base = base; |
840 | c3d2689d | balrog | s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
841 | e856f2ad | balrog | s->tick = qemu_bh_new(omap_timer_fire, s); |
842 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
843 | c3d2689d | balrog | omap_timer_clk_setup(s); |
844 | c3d2689d | balrog | |
845 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
846 | c3d2689d | balrog | omap_mpu_timer_writefn, s); |
847 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
848 | c3d2689d | balrog | |
849 | c3d2689d | balrog | return s;
|
850 | c3d2689d | balrog | } |
851 | c3d2689d | balrog | |
852 | c3d2689d | balrog | /* Watchdog timer */
|
853 | c3d2689d | balrog | struct omap_watchdog_timer_s {
|
854 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
855 | c3d2689d | balrog | uint8_t last_wr; |
856 | c3d2689d | balrog | int mode;
|
857 | c3d2689d | balrog | int free;
|
858 | c3d2689d | balrog | int reset;
|
859 | c3d2689d | balrog | }; |
860 | c3d2689d | balrog | |
861 | c3d2689d | balrog | static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
862 | c3d2689d | balrog | { |
863 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
864 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
865 | c3d2689d | balrog | |
866 | c3d2689d | balrog | switch (offset) {
|
867 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
868 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
869 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
870 | c3d2689d | balrog | |
871 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
872 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
873 | c3d2689d | balrog | |
874 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
875 | c3d2689d | balrog | return s->mode << 15; |
876 | c3d2689d | balrog | } |
877 | c3d2689d | balrog | |
878 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
879 | c3d2689d | balrog | return 0; |
880 | c3d2689d | balrog | } |
881 | c3d2689d | balrog | |
882 | c3d2689d | balrog | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
883 | c3d2689d | balrog | uint32_t value) |
884 | c3d2689d | balrog | { |
885 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
886 | c3d2689d | balrog | int offset = addr - s->timer.base;
|
887 | c3d2689d | balrog | |
888 | c3d2689d | balrog | switch (offset) {
|
889 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
890 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
891 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
892 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
893 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
894 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
895 | c3d2689d | balrog | omap_timer_update(&s->timer); |
896 | c3d2689d | balrog | break;
|
897 | c3d2689d | balrog | |
898 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
899 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
|
900 | c3d2689d | balrog | break;
|
901 | c3d2689d | balrog | |
902 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
903 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
904 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
905 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
906 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
907 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
908 | d8f699cb | balrog | if (s->mode) {
|
909 | d8f699cb | balrog | s->mode = 0;
|
910 | d8f699cb | balrog | omap_clk_put(s->timer.clk); |
911 | d8f699cb | balrog | } |
912 | c3d2689d | balrog | } else {
|
913 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
|
914 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
915 | c3d2689d | balrog | s->reset = 1;
|
916 | c3d2689d | balrog | qemu_system_reset_request(); |
917 | c3d2689d | balrog | } |
918 | c3d2689d | balrog | } |
919 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
920 | c3d2689d | balrog | break;
|
921 | c3d2689d | balrog | |
922 | c3d2689d | balrog | default:
|
923 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
924 | c3d2689d | balrog | } |
925 | c3d2689d | balrog | } |
926 | c3d2689d | balrog | |
927 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
928 | c3d2689d | balrog | omap_badwidth_read16, |
929 | c3d2689d | balrog | omap_wd_timer_read, |
930 | c3d2689d | balrog | omap_badwidth_read16, |
931 | c3d2689d | balrog | }; |
932 | c3d2689d | balrog | |
933 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
934 | c3d2689d | balrog | omap_badwidth_write16, |
935 | c3d2689d | balrog | omap_wd_timer_write, |
936 | c3d2689d | balrog | omap_badwidth_write16, |
937 | c3d2689d | balrog | }; |
938 | c3d2689d | balrog | |
939 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
940 | c3d2689d | balrog | { |
941 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
942 | c3d2689d | balrog | if (!s->mode)
|
943 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
944 | c3d2689d | balrog | s->mode = 1;
|
945 | c3d2689d | balrog | s->free = 1;
|
946 | c3d2689d | balrog | s->reset = 0;
|
947 | c3d2689d | balrog | s->timer.enable = 1;
|
948 | c3d2689d | balrog | s->timer.it_ena = 1;
|
949 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
950 | c3d2689d | balrog | s->timer.val = 0;
|
951 | c3d2689d | balrog | s->timer.st = 0;
|
952 | c3d2689d | balrog | s->timer.ptv = 0;
|
953 | c3d2689d | balrog | s->timer.ar = 0;
|
954 | c3d2689d | balrog | omap_timer_update(&s->timer); |
955 | c3d2689d | balrog | } |
956 | c3d2689d | balrog | |
957 | c3d2689d | balrog | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
958 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
959 | c3d2689d | balrog | { |
960 | c3d2689d | balrog | int iomemtype;
|
961 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
962 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
963 | c3d2689d | balrog | |
964 | c3d2689d | balrog | s->timer.irq = irq; |
965 | c3d2689d | balrog | s->timer.clk = clk; |
966 | c3d2689d | balrog | s->timer.base = base; |
967 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
968 | c3d2689d | balrog | omap_wd_timer_reset(s); |
969 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
970 | c3d2689d | balrog | |
971 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
972 | c3d2689d | balrog | omap_wd_timer_writefn, s); |
973 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
974 | c3d2689d | balrog | |
975 | c3d2689d | balrog | return s;
|
976 | c3d2689d | balrog | } |
977 | c3d2689d | balrog | |
978 | c3d2689d | balrog | /* 32-kHz timer */
|
979 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
980 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
981 | c3d2689d | balrog | }; |
982 | c3d2689d | balrog | |
983 | c3d2689d | balrog | static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
984 | c3d2689d | balrog | { |
985 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
986 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
987 | c3d2689d | balrog | |
988 | c3d2689d | balrog | switch (offset) {
|
989 | c3d2689d | balrog | case 0x00: /* TVR */ |
990 | c3d2689d | balrog | return s->timer.reset_val;
|
991 | c3d2689d | balrog | |
992 | c3d2689d | balrog | case 0x04: /* TCR */ |
993 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
994 | c3d2689d | balrog | |
995 | c3d2689d | balrog | case 0x08: /* CR */ |
996 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
997 | c3d2689d | balrog | |
998 | c3d2689d | balrog | default:
|
999 | c3d2689d | balrog | break;
|
1000 | c3d2689d | balrog | } |
1001 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1002 | c3d2689d | balrog | return 0; |
1003 | c3d2689d | balrog | } |
1004 | c3d2689d | balrog | |
1005 | c3d2689d | balrog | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
1006 | c3d2689d | balrog | uint32_t value) |
1007 | c3d2689d | balrog | { |
1008 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1009 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1010 | c3d2689d | balrog | |
1011 | c3d2689d | balrog | switch (offset) {
|
1012 | c3d2689d | balrog | case 0x00: /* TVR */ |
1013 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
1014 | c3d2689d | balrog | break;
|
1015 | c3d2689d | balrog | |
1016 | c3d2689d | balrog | case 0x04: /* TCR */ |
1017 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1018 | c3d2689d | balrog | break;
|
1019 | c3d2689d | balrog | |
1020 | c3d2689d | balrog | case 0x08: /* CR */ |
1021 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
1022 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
1023 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
1024 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
1025 | c3d2689d | balrog | s->timer.enable = value & 1;
|
1026 | c3d2689d | balrog | s->timer.st = value & 1;
|
1027 | c3d2689d | balrog | omap_timer_update(&s->timer); |
1028 | c3d2689d | balrog | } |
1029 | c3d2689d | balrog | break;
|
1030 | c3d2689d | balrog | |
1031 | c3d2689d | balrog | default:
|
1032 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1033 | c3d2689d | balrog | } |
1034 | c3d2689d | balrog | } |
1035 | c3d2689d | balrog | |
1036 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
1037 | c3d2689d | balrog | omap_badwidth_read32, |
1038 | c3d2689d | balrog | omap_badwidth_read32, |
1039 | c3d2689d | balrog | omap_os_timer_read, |
1040 | c3d2689d | balrog | }; |
1041 | c3d2689d | balrog | |
1042 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
1043 | c3d2689d | balrog | omap_badwidth_write32, |
1044 | c3d2689d | balrog | omap_badwidth_write32, |
1045 | c3d2689d | balrog | omap_os_timer_write, |
1046 | c3d2689d | balrog | }; |
1047 | c3d2689d | balrog | |
1048 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
1049 | c3d2689d | balrog | { |
1050 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
1051 | c3d2689d | balrog | s->timer.enable = 0;
|
1052 | c3d2689d | balrog | s->timer.it_ena = 0;
|
1053 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
1054 | c3d2689d | balrog | s->timer.val = 0;
|
1055 | c3d2689d | balrog | s->timer.st = 0;
|
1056 | c3d2689d | balrog | s->timer.ptv = 0;
|
1057 | c3d2689d | balrog | s->timer.ar = 1;
|
1058 | c3d2689d | balrog | } |
1059 | c3d2689d | balrog | |
1060 | c3d2689d | balrog | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
1061 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
1062 | c3d2689d | balrog | { |
1063 | c3d2689d | balrog | int iomemtype;
|
1064 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
1065 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
1066 | c3d2689d | balrog | |
1067 | c3d2689d | balrog | s->timer.irq = irq; |
1068 | c3d2689d | balrog | s->timer.clk = clk; |
1069 | c3d2689d | balrog | s->timer.base = base; |
1070 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1071 | c3d2689d | balrog | omap_os_timer_reset(s); |
1072 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
1073 | c3d2689d | balrog | |
1074 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
1075 | c3d2689d | balrog | omap_os_timer_writefn, s); |
1076 | c3d2689d | balrog | cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
1077 | c3d2689d | balrog | |
1078 | c3d2689d | balrog | return s;
|
1079 | c3d2689d | balrog | } |
1080 | c3d2689d | balrog | |
1081 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
1082 | c3d2689d | balrog | static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
1083 | c3d2689d | balrog | { |
1084 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1085 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1086 | c3d2689d | balrog | uint16_t ret; |
1087 | c3d2689d | balrog | |
1088 | c3d2689d | balrog | switch (offset) {
|
1089 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1090 | c3d2689d | balrog | ret = s->ulpd_pm_regs[offset >> 2];
|
1091 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = 0; |
1092 | c3d2689d | balrog | qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1093 | c3d2689d | balrog | return ret;
|
1094 | c3d2689d | balrog | |
1095 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1096 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1097 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1098 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1099 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1100 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1101 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1102 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1103 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1104 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1105 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1106 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1107 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1108 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1109 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1110 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1111 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1112 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
1113 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1114 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1115 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1116 | c3d2689d | balrog | return s->ulpd_pm_regs[offset >> 2]; |
1117 | c3d2689d | balrog | } |
1118 | c3d2689d | balrog | |
1119 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1120 | c3d2689d | balrog | return 0; |
1121 | c3d2689d | balrog | } |
1122 | c3d2689d | balrog | |
1123 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
1124 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1125 | c3d2689d | balrog | { |
1126 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
1127 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
1128 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
1129 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
1130 | c3d2689d | balrog | } |
1131 | c3d2689d | balrog | |
1132 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
1133 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1134 | c3d2689d | balrog | { |
1135 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
1136 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
1137 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
1138 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
1139 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
1140 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
1141 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
1142 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
1143 | c3d2689d | balrog | } |
1144 | c3d2689d | balrog | |
1145 | c3d2689d | balrog | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
1146 | c3d2689d | balrog | uint32_t value) |
1147 | c3d2689d | balrog | { |
1148 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1149 | c3d2689d | balrog | int offset = addr - s->ulpd_pm_base;
|
1150 | c3d2689d | balrog | int64_t now, ticks; |
1151 | c3d2689d | balrog | int div, mult;
|
1152 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1153 | c3d2689d | balrog | uint16_t diff; |
1154 | c3d2689d | balrog | |
1155 | c3d2689d | balrog | switch (offset) {
|
1156 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
1157 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
1158 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1159 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1160 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
1161 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
1162 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1163 | c3d2689d | balrog | break;
|
1164 | c3d2689d | balrog | |
1165 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
1166 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
1167 | c3d2689d | balrog | if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
1168 | c3d2689d | balrog | now = qemu_get_clock(vm_clock); |
1169 | c3d2689d | balrog | |
1170 | c3d2689d | balrog | if (value & 1) |
1171 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
1172 | c3d2689d | balrog | else {
|
1173 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
1174 | c3d2689d | balrog | |
1175 | c3d2689d | balrog | /* 32-kHz ticks */
|
1176 | c3d2689d | balrog | ticks = muldiv64(now, 32768, ticks_per_sec);
|
1177 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
1178 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
1179 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
1180 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
1181 | c3d2689d | balrog | |
1182 | c3d2689d | balrog | /* High frequency ticks */
|
1183 | c3d2689d | balrog | ticks = muldiv64(now, 12000000, ticks_per_sec);
|
1184 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
1185 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
1186 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
1187 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
1188 | c3d2689d | balrog | |
1189 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
1190 | c3d2689d | balrog | qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1191 | c3d2689d | balrog | } |
1192 | c3d2689d | balrog | } |
1193 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1194 | c3d2689d | balrog | break;
|
1195 | c3d2689d | balrog | |
1196 | c3d2689d | balrog | case 0x18: /* Reserved */ |
1197 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
1198 | c3d2689d | balrog | case 0x20: /* Reserved */ |
1199 | c3d2689d | balrog | case 0x28: /* Reserved */ |
1200 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
1201 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1202 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1203 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
1204 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
1205 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
1206 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value;
|
1207 | c3d2689d | balrog | break;
|
1208 | c3d2689d | balrog | |
1209 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
1210 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1211 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
1212 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
1213 | c3d2689d | balrog | break;
|
1214 | c3d2689d | balrog | |
1215 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
1216 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1217 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
1218 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
1219 | c3d2689d | balrog | break;
|
1220 | c3d2689d | balrog | |
1221 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
1222 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
1223 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
1224 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
1225 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
1226 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1227 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
1228 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1229 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1230 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1231 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1232 | c3d2689d | balrog | } else {
|
1233 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1234 | c3d2689d | balrog | mult = 1;
|
1235 | c3d2689d | balrog | } |
1236 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
1237 | c3d2689d | balrog | } |
1238 | c3d2689d | balrog | |
1239 | c3d2689d | balrog | /* Enter the desired mode. */
|
1240 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] =
|
1241 | c3d2689d | balrog | (s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
1242 | c3d2689d | balrog | ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
1243 | c3d2689d | balrog | |
1244 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1245 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] |= 2; |
1246 | c3d2689d | balrog | break;
|
1247 | c3d2689d | balrog | |
1248 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
1249 | c3d2689d | balrog | diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1250 | c3d2689d | balrog | s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
1251 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
1252 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
1253 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
1254 | c3d2689d | balrog | break;
|
1255 | c3d2689d | balrog | |
1256 | c3d2689d | balrog | default:
|
1257 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1258 | c3d2689d | balrog | } |
1259 | c3d2689d | balrog | } |
1260 | c3d2689d | balrog | |
1261 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1262 | c3d2689d | balrog | omap_badwidth_read16, |
1263 | c3d2689d | balrog | omap_ulpd_pm_read, |
1264 | c3d2689d | balrog | omap_badwidth_read16, |
1265 | c3d2689d | balrog | }; |
1266 | c3d2689d | balrog | |
1267 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1268 | c3d2689d | balrog | omap_badwidth_write16, |
1269 | c3d2689d | balrog | omap_ulpd_pm_write, |
1270 | c3d2689d | balrog | omap_badwidth_write16, |
1271 | c3d2689d | balrog | }; |
1272 | c3d2689d | balrog | |
1273 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1274 | c3d2689d | balrog | { |
1275 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1276 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1277 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1278 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1279 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1280 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1281 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1282 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1283 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1284 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1285 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1286 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1287 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1288 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1289 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1290 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1291 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1292 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1293 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1294 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1295 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1296 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1297 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1298 | c3d2689d | balrog | } |
1299 | c3d2689d | balrog | |
1300 | c3d2689d | balrog | static void omap_ulpd_pm_init(target_phys_addr_t base, |
1301 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1302 | c3d2689d | balrog | { |
1303 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1304 | c3d2689d | balrog | omap_ulpd_pm_writefn, mpu); |
1305 | c3d2689d | balrog | |
1306 | c3d2689d | balrog | mpu->ulpd_pm_base = base; |
1307 | c3d2689d | balrog | cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1308 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
1309 | c3d2689d | balrog | } |
1310 | c3d2689d | balrog | |
1311 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
1312 | c3d2689d | balrog | static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1313 | c3d2689d | balrog | { |
1314 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1315 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1316 | c3d2689d | balrog | |
1317 | c3d2689d | balrog | switch (offset) {
|
1318 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1319 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1320 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1321 | c3d2689d | balrog | return s->func_mux_ctrl[offset >> 2]; |
1322 | c3d2689d | balrog | |
1323 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1324 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
1325 | c3d2689d | balrog | |
1326 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1327 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1328 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1329 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1330 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1331 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1332 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1333 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1334 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1335 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1336 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1337 | c3d2689d | balrog | return s->func_mux_ctrl[(offset >> 2) - 1]; |
1338 | c3d2689d | balrog | |
1339 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1340 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1341 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1342 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1343 | c3d2689d | balrog | return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1344 | c3d2689d | balrog | |
1345 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1346 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
1347 | c3d2689d | balrog | |
1348 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1349 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
1350 | c3d2689d | balrog | |
1351 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1352 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
1353 | c3d2689d | balrog | |
1354 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1355 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
1356 | c3d2689d | balrog | } |
1357 | c3d2689d | balrog | |
1358 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1359 | c3d2689d | balrog | return 0; |
1360 | c3d2689d | balrog | } |
1361 | c3d2689d | balrog | |
1362 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1363 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1364 | c3d2689d | balrog | { |
1365 | c3d2689d | balrog | if (s->compat1509) {
|
1366 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
1367 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1368 | c3d2689d | balrog | (~value >> 9) & 1); |
1369 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
1370 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1371 | c3d2689d | balrog | (value >> 7) & 1); |
1372 | c3d2689d | balrog | } |
1373 | c3d2689d | balrog | } |
1374 | c3d2689d | balrog | |
1375 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1376 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1377 | c3d2689d | balrog | { |
1378 | c3d2689d | balrog | if (s->compat1509) {
|
1379 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1380 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1381 | c3d2689d | balrog | (value >> 31) & 1); |
1382 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
1383 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1384 | c3d2689d | balrog | (~value >> 1) & 1); |
1385 | c3d2689d | balrog | } |
1386 | c3d2689d | balrog | } |
1387 | c3d2689d | balrog | |
1388 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1389 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
1390 | c3d2689d | balrog | { |
1391 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1392 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1393 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
1394 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1395 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1396 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1397 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
1398 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1399 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1400 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1401 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
1402 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1403 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1404 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1405 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
1406 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1407 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1408 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1409 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
1410 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
1411 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1412 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1413 | c3d2689d | balrog | } |
1414 | c3d2689d | balrog | |
1415 | c3d2689d | balrog | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1416 | c3d2689d | balrog | uint32_t value) |
1417 | c3d2689d | balrog | { |
1418 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1419 | c3d2689d | balrog | int offset = addr - s->pin_cfg_base;
|
1420 | c3d2689d | balrog | uint32_t diff; |
1421 | c3d2689d | balrog | |
1422 | c3d2689d | balrog | switch (offset) {
|
1423 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
1424 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1425 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1426 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
1427 | c3d2689d | balrog | return;
|
1428 | c3d2689d | balrog | |
1429 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
1430 | c3d2689d | balrog | diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1431 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1432 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
1433 | c3d2689d | balrog | return;
|
1434 | c3d2689d | balrog | |
1435 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
1436 | c3d2689d | balrog | s->func_mux_ctrl[offset >> 2] = value;
|
1437 | c3d2689d | balrog | return;
|
1438 | c3d2689d | balrog | |
1439 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
1440 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
1441 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
1442 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1443 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1444 | c3d2689d | balrog | return;
|
1445 | c3d2689d | balrog | |
1446 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
1447 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
1448 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
1449 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1450 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
1451 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
1452 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
1453 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
1454 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
1455 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
1456 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
1457 | c3d2689d | balrog | s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1458 | c3d2689d | balrog | return;
|
1459 | c3d2689d | balrog | |
1460 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
1461 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
1462 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
1463 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
1464 | c3d2689d | balrog | s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1465 | c3d2689d | balrog | return;
|
1466 | c3d2689d | balrog | |
1467 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
1468 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
1469 | c3d2689d | balrog | return;
|
1470 | c3d2689d | balrog | |
1471 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
1472 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
1473 | c3d2689d | balrog | return;
|
1474 | c3d2689d | balrog | |
1475 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
1476 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
1477 | c3d2689d | balrog | return;
|
1478 | c3d2689d | balrog | |
1479 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
1480 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
1481 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
1482 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
1483 | c3d2689d | balrog | return;
|
1484 | c3d2689d | balrog | |
1485 | c3d2689d | balrog | default:
|
1486 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1487 | c3d2689d | balrog | } |
1488 | c3d2689d | balrog | } |
1489 | c3d2689d | balrog | |
1490 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1491 | c3d2689d | balrog | omap_badwidth_read32, |
1492 | c3d2689d | balrog | omap_badwidth_read32, |
1493 | c3d2689d | balrog | omap_pin_cfg_read, |
1494 | c3d2689d | balrog | }; |
1495 | c3d2689d | balrog | |
1496 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1497 | c3d2689d | balrog | omap_badwidth_write32, |
1498 | c3d2689d | balrog | omap_badwidth_write32, |
1499 | c3d2689d | balrog | omap_pin_cfg_write, |
1500 | c3d2689d | balrog | }; |
1501 | c3d2689d | balrog | |
1502 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1503 | c3d2689d | balrog | { |
1504 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
1505 | c3d2689d | balrog | mpu->compat1509 = 1;
|
1506 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1507 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1508 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1509 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1510 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1511 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1512 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1513 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1514 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1515 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1516 | c3d2689d | balrog | } |
1517 | c3d2689d | balrog | |
1518 | c3d2689d | balrog | static void omap_pin_cfg_init(target_phys_addr_t base, |
1519 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1520 | c3d2689d | balrog | { |
1521 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1522 | c3d2689d | balrog | omap_pin_cfg_writefn, mpu); |
1523 | c3d2689d | balrog | |
1524 | c3d2689d | balrog | mpu->pin_cfg_base = base; |
1525 | c3d2689d | balrog | cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1526 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
1527 | c3d2689d | balrog | } |
1528 | c3d2689d | balrog | |
1529 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
1530 | c3d2689d | balrog | static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1531 | c3d2689d | balrog | { |
1532 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1533 | c3d2689d | balrog | |
1534 | c3d2689d | balrog | switch (addr) {
|
1535 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
1536 | c3d2689d | balrog | return 0xc9581f0e; |
1537 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
1538 | c3d2689d | balrog | return 0xa8858bfa; |
1539 | c3d2689d | balrog | |
1540 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1541 | c3d2689d | balrog | return 0x00aaaafc; |
1542 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1543 | c3d2689d | balrog | return 0xcafeb574; |
1544 | c3d2689d | balrog | |
1545 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
1546 | c3d2689d | balrog | switch (s->mpu_model) {
|
1547 | c3d2689d | balrog | case omap310:
|
1548 | c3d2689d | balrog | return 0x03310315; |
1549 | c3d2689d | balrog | case omap1510:
|
1550 | c3d2689d | balrog | return 0x03310115; |
1551 | 827df9f3 | balrog | default:
|
1552 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
|
1553 | c3d2689d | balrog | } |
1554 | c3d2689d | balrog | break;
|
1555 | c3d2689d | balrog | |
1556 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
1557 | c3d2689d | balrog | switch (s->mpu_model) {
|
1558 | c3d2689d | balrog | case omap310:
|
1559 | c3d2689d | balrog | return 0xfb57402f; |
1560 | c3d2689d | balrog | case omap1510:
|
1561 | c3d2689d | balrog | return 0xfb47002f; |
1562 | 827df9f3 | balrog | default:
|
1563 | 827df9f3 | balrog | cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
|
1564 | c3d2689d | balrog | } |
1565 | c3d2689d | balrog | break;
|
1566 | c3d2689d | balrog | } |
1567 | c3d2689d | balrog | |
1568 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1569 | c3d2689d | balrog | return 0; |
1570 | c3d2689d | balrog | } |
1571 | c3d2689d | balrog | |
1572 | c3d2689d | balrog | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1573 | c3d2689d | balrog | uint32_t value) |
1574 | c3d2689d | balrog | { |
1575 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1576 | c3d2689d | balrog | } |
1577 | c3d2689d | balrog | |
1578 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_id_readfn[] = {
|
1579 | c3d2689d | balrog | omap_badwidth_read32, |
1580 | c3d2689d | balrog | omap_badwidth_read32, |
1581 | c3d2689d | balrog | omap_id_read, |
1582 | c3d2689d | balrog | }; |
1583 | c3d2689d | balrog | |
1584 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
1585 | c3d2689d | balrog | omap_badwidth_write32, |
1586 | c3d2689d | balrog | omap_badwidth_write32, |
1587 | c3d2689d | balrog | omap_id_write, |
1588 | c3d2689d | balrog | }; |
1589 | c3d2689d | balrog | |
1590 | c3d2689d | balrog | static void omap_id_init(struct omap_mpu_state_s *mpu) |
1591 | c3d2689d | balrog | { |
1592 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
1593 | c3d2689d | balrog | omap_id_writefn, mpu); |
1594 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
1595 | c3d2689d | balrog | cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
1596 | c3d2689d | balrog | if (!cpu_is_omap15xx(mpu))
|
1597 | c3d2689d | balrog | cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
1598 | c3d2689d | balrog | } |
1599 | c3d2689d | balrog | |
1600 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
1601 | c3d2689d | balrog | static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1602 | c3d2689d | balrog | { |
1603 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1604 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
1605 | c3d2689d | balrog | |
1606 | c3d2689d | balrog | switch (offset) {
|
1607 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1608 | c3d2689d | balrog | return s->mpui_ctrl;
|
1609 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1610 | c3d2689d | balrog | return 0x01ffffff; |
1611 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1612 | c3d2689d | balrog | return 0xffffffff; |
1613 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1614 | c3d2689d | balrog | return 0x00000800; |
1615 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1616 | c3d2689d | balrog | return 0x00000000; |
1617 | c3d2689d | balrog | |
1618 | c3d2689d | balrog | /* Not in OMAP310 */
|
1619 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1620 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1621 | c3d2689d | balrog | return 0x00000000; |
1622 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1623 | c3d2689d | balrog | return 0x0000ffff; |
1624 | c3d2689d | balrog | } |
1625 | c3d2689d | balrog | |
1626 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1627 | c3d2689d | balrog | return 0; |
1628 | c3d2689d | balrog | } |
1629 | c3d2689d | balrog | |
1630 | c3d2689d | balrog | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
1631 | c3d2689d | balrog | uint32_t value) |
1632 | c3d2689d | balrog | { |
1633 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1634 | c3d2689d | balrog | int offset = addr - s->mpui_base;
|
1635 | c3d2689d | balrog | |
1636 | c3d2689d | balrog | switch (offset) {
|
1637 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1638 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
1639 | c3d2689d | balrog | break;
|
1640 | c3d2689d | balrog | |
1641 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1642 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1643 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1644 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1645 | c3d2689d | balrog | /* Not in OMAP310 */
|
1646 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1647 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1648 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1649 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1650 | c3d2689d | balrog | break;
|
1651 | c3d2689d | balrog | |
1652 | c3d2689d | balrog | default:
|
1653 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1654 | c3d2689d | balrog | } |
1655 | c3d2689d | balrog | } |
1656 | c3d2689d | balrog | |
1657 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
1658 | c3d2689d | balrog | omap_badwidth_read32, |
1659 | c3d2689d | balrog | omap_badwidth_read32, |
1660 | c3d2689d | balrog | omap_mpui_read, |
1661 | c3d2689d | balrog | }; |
1662 | c3d2689d | balrog | |
1663 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
1664 | c3d2689d | balrog | omap_badwidth_write32, |
1665 | c3d2689d | balrog | omap_badwidth_write32, |
1666 | c3d2689d | balrog | omap_mpui_write, |
1667 | c3d2689d | balrog | }; |
1668 | c3d2689d | balrog | |
1669 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
1670 | c3d2689d | balrog | { |
1671 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
1672 | c3d2689d | balrog | } |
1673 | c3d2689d | balrog | |
1674 | c3d2689d | balrog | static void omap_mpui_init(target_phys_addr_t base, |
1675 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1676 | c3d2689d | balrog | { |
1677 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
1678 | c3d2689d | balrog | omap_mpui_writefn, mpu); |
1679 | c3d2689d | balrog | |
1680 | c3d2689d | balrog | mpu->mpui_base = base; |
1681 | c3d2689d | balrog | cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
1682 | c3d2689d | balrog | |
1683 | c3d2689d | balrog | omap_mpui_reset(mpu); |
1684 | c3d2689d | balrog | } |
1685 | c3d2689d | balrog | |
1686 | c3d2689d | balrog | /* TIPB Bridges */
|
1687 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
1688 | c3d2689d | balrog | target_phys_addr_t base; |
1689 | c3d2689d | balrog | qemu_irq abort; |
1690 | c3d2689d | balrog | |
1691 | c3d2689d | balrog | int width_intr;
|
1692 | c3d2689d | balrog | uint16_t control; |
1693 | c3d2689d | balrog | uint16_t alloc; |
1694 | c3d2689d | balrog | uint16_t buffer; |
1695 | c3d2689d | balrog | uint16_t enh_control; |
1696 | c3d2689d | balrog | }; |
1697 | c3d2689d | balrog | |
1698 | c3d2689d | balrog | static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
1699 | c3d2689d | balrog | { |
1700 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1701 | c3d2689d | balrog | int offset = addr - s->base;
|
1702 | c3d2689d | balrog | |
1703 | c3d2689d | balrog | switch (offset) {
|
1704 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1705 | c3d2689d | balrog | return s->control;
|
1706 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1707 | c3d2689d | balrog | return s->alloc;
|
1708 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1709 | c3d2689d | balrog | return s->buffer;
|
1710 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1711 | c3d2689d | balrog | return s->enh_control;
|
1712 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1713 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1714 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1715 | c3d2689d | balrog | return 0xffff; |
1716 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1717 | c3d2689d | balrog | return 0x00f8; |
1718 | c3d2689d | balrog | } |
1719 | c3d2689d | balrog | |
1720 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1721 | c3d2689d | balrog | return 0; |
1722 | c3d2689d | balrog | } |
1723 | c3d2689d | balrog | |
1724 | c3d2689d | balrog | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
1725 | c3d2689d | balrog | uint32_t value) |
1726 | c3d2689d | balrog | { |
1727 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1728 | c3d2689d | balrog | int offset = addr - s->base;
|
1729 | c3d2689d | balrog | |
1730 | c3d2689d | balrog | switch (offset) {
|
1731 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1732 | c3d2689d | balrog | s->control = value & 0xffff;
|
1733 | c3d2689d | balrog | break;
|
1734 | c3d2689d | balrog | |
1735 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1736 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
1737 | c3d2689d | balrog | break;
|
1738 | c3d2689d | balrog | |
1739 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1740 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
1741 | c3d2689d | balrog | break;
|
1742 | c3d2689d | balrog | |
1743 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1744 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
1745 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
1746 | c3d2689d | balrog | break;
|
1747 | c3d2689d | balrog | |
1748 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1749 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1750 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1751 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1752 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1753 | c3d2689d | balrog | break;
|
1754 | c3d2689d | balrog | |
1755 | c3d2689d | balrog | default:
|
1756 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1757 | c3d2689d | balrog | } |
1758 | c3d2689d | balrog | } |
1759 | c3d2689d | balrog | |
1760 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
1761 | c3d2689d | balrog | omap_badwidth_read16, |
1762 | c3d2689d | balrog | omap_tipb_bridge_read, |
1763 | c3d2689d | balrog | omap_tipb_bridge_read, |
1764 | c3d2689d | balrog | }; |
1765 | c3d2689d | balrog | |
1766 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
1767 | c3d2689d | balrog | omap_badwidth_write16, |
1768 | c3d2689d | balrog | omap_tipb_bridge_write, |
1769 | c3d2689d | balrog | omap_tipb_bridge_write, |
1770 | c3d2689d | balrog | }; |
1771 | c3d2689d | balrog | |
1772 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
1773 | c3d2689d | balrog | { |
1774 | c3d2689d | balrog | s->control = 0xffff;
|
1775 | c3d2689d | balrog | s->alloc = 0x0009;
|
1776 | c3d2689d | balrog | s->buffer = 0x0000;
|
1777 | c3d2689d | balrog | s->enh_control = 0x000f;
|
1778 | c3d2689d | balrog | } |
1779 | c3d2689d | balrog | |
1780 | c3d2689d | balrog | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
1781 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk) |
1782 | c3d2689d | balrog | { |
1783 | c3d2689d | balrog | int iomemtype;
|
1784 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
1785 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
1786 | c3d2689d | balrog | |
1787 | c3d2689d | balrog | s->abort = abort_irq; |
1788 | c3d2689d | balrog | s->base = base; |
1789 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
1790 | c3d2689d | balrog | |
1791 | c3d2689d | balrog | iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
1792 | c3d2689d | balrog | omap_tipb_bridge_writefn, s); |
1793 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1794 | c3d2689d | balrog | |
1795 | c3d2689d | balrog | return s;
|
1796 | c3d2689d | balrog | } |
1797 | c3d2689d | balrog | |
1798 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
1799 | c3d2689d | balrog | static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
1800 | c3d2689d | balrog | { |
1801 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1802 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
1803 | c3d2689d | balrog | uint32_t ret; |
1804 | c3d2689d | balrog | |
1805 | c3d2689d | balrog | switch (offset) {
|
1806 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1807 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1808 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1809 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1810 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1811 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1812 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1813 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1814 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1815 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1816 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1817 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1818 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1819 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1820 | c3d2689d | balrog | return s->tcmi_regs[offset >> 2]; |
1821 | c3d2689d | balrog | |
1822 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1823 | c3d2689d | balrog | ret = s->tcmi_regs[offset >> 2];
|
1824 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
1825 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
1826 | c3d2689d | balrog | return ret;
|
1827 | c3d2689d | balrog | } |
1828 | c3d2689d | balrog | |
1829 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1830 | c3d2689d | balrog | return 0; |
1831 | c3d2689d | balrog | } |
1832 | c3d2689d | balrog | |
1833 | c3d2689d | balrog | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
1834 | c3d2689d | balrog | uint32_t value) |
1835 | c3d2689d | balrog | { |
1836 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1837 | c3d2689d | balrog | int offset = addr - s->tcmi_base;
|
1838 | c3d2689d | balrog | |
1839 | c3d2689d | balrog | switch (offset) {
|
1840 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1841 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1842 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1843 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1844 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1845 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1846 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1847 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1848 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1849 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1850 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1851 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1852 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1853 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1854 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = value;
|
1855 | c3d2689d | balrog | break;
|
1856 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1857 | c3d2689d | balrog | s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
1858 | c3d2689d | balrog | break;
|
1859 | c3d2689d | balrog | |
1860 | c3d2689d | balrog | default:
|
1861 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1862 | c3d2689d | balrog | } |
1863 | c3d2689d | balrog | } |
1864 | c3d2689d | balrog | |
1865 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
1866 | c3d2689d | balrog | omap_badwidth_read32, |
1867 | c3d2689d | balrog | omap_badwidth_read32, |
1868 | c3d2689d | balrog | omap_tcmi_read, |
1869 | c3d2689d | balrog | }; |
1870 | c3d2689d | balrog | |
1871 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
1872 | c3d2689d | balrog | omap_badwidth_write32, |
1873 | c3d2689d | balrog | omap_badwidth_write32, |
1874 | c3d2689d | balrog | omap_tcmi_write, |
1875 | c3d2689d | balrog | }; |
1876 | c3d2689d | balrog | |
1877 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
1878 | c3d2689d | balrog | { |
1879 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
1880 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
1881 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
1882 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
1883 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
1884 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
1885 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
1886 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
1887 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
1888 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
1889 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
1890 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
1891 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
1892 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
1893 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
1894 | c3d2689d | balrog | } |
1895 | c3d2689d | balrog | |
1896 | c3d2689d | balrog | static void omap_tcmi_init(target_phys_addr_t base, |
1897 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1898 | c3d2689d | balrog | { |
1899 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
1900 | c3d2689d | balrog | omap_tcmi_writefn, mpu); |
1901 | c3d2689d | balrog | |
1902 | c3d2689d | balrog | mpu->tcmi_base = base; |
1903 | c3d2689d | balrog | cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
1904 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
1905 | c3d2689d | balrog | } |
1906 | c3d2689d | balrog | |
1907 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
1908 | c3d2689d | balrog | static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
1909 | c3d2689d | balrog | { |
1910 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1911 | c3d2689d | balrog | int offset = addr - s->base;
|
1912 | c3d2689d | balrog | |
1913 | c3d2689d | balrog | if (offset == 0x00) /* CTL_REG */ |
1914 | c3d2689d | balrog | return s->mode;
|
1915 | c3d2689d | balrog | |
1916 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1917 | c3d2689d | balrog | return 0; |
1918 | c3d2689d | balrog | } |
1919 | c3d2689d | balrog | |
1920 | c3d2689d | balrog | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
1921 | c3d2689d | balrog | uint32_t value) |
1922 | c3d2689d | balrog | { |
1923 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1924 | c3d2689d | balrog | uint16_t diff; |
1925 | c3d2689d | balrog | int offset = addr - s->base;
|
1926 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1927 | c3d2689d | balrog | int div, mult;
|
1928 | c3d2689d | balrog | |
1929 | c3d2689d | balrog | if (offset == 0x00) { /* CTL_REG */ |
1930 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
1931 | c3d2689d | balrog | diff = s->mode & value; |
1932 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
1933 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1934 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1935 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1936 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1937 | c3d2689d | balrog | } else {
|
1938 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1939 | c3d2689d | balrog | mult = 1;
|
1940 | c3d2689d | balrog | } |
1941 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
1942 | c3d2689d | balrog | } |
1943 | c3d2689d | balrog | |
1944 | c3d2689d | balrog | /* Enter the desired mode. */
|
1945 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
1946 | c3d2689d | balrog | |
1947 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1948 | c3d2689d | balrog | s->mode |= 2;
|
1949 | c3d2689d | balrog | } else {
|
1950 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1951 | c3d2689d | balrog | } |
1952 | c3d2689d | balrog | } |
1953 | c3d2689d | balrog | |
1954 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
1955 | c3d2689d | balrog | omap_badwidth_read16, |
1956 | c3d2689d | balrog | omap_dpll_read, |
1957 | c3d2689d | balrog | omap_badwidth_read16, |
1958 | c3d2689d | balrog | }; |
1959 | c3d2689d | balrog | |
1960 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
1961 | c3d2689d | balrog | omap_badwidth_write16, |
1962 | c3d2689d | balrog | omap_dpll_write, |
1963 | c3d2689d | balrog | omap_badwidth_write16, |
1964 | c3d2689d | balrog | }; |
1965 | c3d2689d | balrog | |
1966 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
1967 | c3d2689d | balrog | { |
1968 | c3d2689d | balrog | s->mode = 0x2002;
|
1969 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
1970 | c3d2689d | balrog | } |
1971 | c3d2689d | balrog | |
1972 | c3d2689d | balrog | static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
1973 | c3d2689d | balrog | omap_clk clk) |
1974 | c3d2689d | balrog | { |
1975 | c3d2689d | balrog | int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
1976 | c3d2689d | balrog | omap_dpll_writefn, s); |
1977 | c3d2689d | balrog | |
1978 | c3d2689d | balrog | s->base = base; |
1979 | c3d2689d | balrog | s->dpll = clk; |
1980 | c3d2689d | balrog | omap_dpll_reset(s); |
1981 | c3d2689d | balrog | |
1982 | c3d2689d | balrog | cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1983 | c3d2689d | balrog | } |
1984 | c3d2689d | balrog | |
1985 | c3d2689d | balrog | /* UARTs */
|
1986 | c3d2689d | balrog | struct omap_uart_s {
|
1987 | c3d2689d | balrog | SerialState *serial; /* TODO */
|
1988 | 827df9f3 | balrog | struct omap_target_agent_s *ta;
|
1989 | 827df9f3 | balrog | target_phys_addr_t base; |
1990 | 75554a3c | balrog | omap_clk fclk; |
1991 | 75554a3c | balrog | qemu_irq irq; |
1992 | 827df9f3 | balrog | |
1993 | 827df9f3 | balrog | uint8_t eblr; |
1994 | 827df9f3 | balrog | uint8_t syscontrol; |
1995 | 827df9f3 | balrog | uint8_t wkup; |
1996 | 827df9f3 | balrog | uint8_t cfps; |
1997 | 54585ffe | balrog | uint8_t mdr[2];
|
1998 | 54585ffe | balrog | uint8_t scr; |
1999 | c3d2689d | balrog | }; |
2000 | c3d2689d | balrog | |
2001 | 827df9f3 | balrog | void omap_uart_reset(struct omap_uart_s *s) |
2002 | c3d2689d | balrog | { |
2003 | 827df9f3 | balrog | s->eblr = 0x00;
|
2004 | 827df9f3 | balrog | s->syscontrol = 0;
|
2005 | 827df9f3 | balrog | s->wkup = 0x3f;
|
2006 | 827df9f3 | balrog | s->cfps = 0x69;
|
2007 | c3d2689d | balrog | } |
2008 | c3d2689d | balrog | |
2009 | c3d2689d | balrog | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
2010 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
2011 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
2012 | c3d2689d | balrog | { |
2013 | c3d2689d | balrog | struct omap_uart_s *s = (struct omap_uart_s *) |
2014 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_uart_s)); |
2015 | 827df9f3 | balrog | |
2016 | 75554a3c | balrog | s->base = base; |
2017 | 75554a3c | balrog | s->fclk = fclk; |
2018 | 75554a3c | balrog | s->irq = irq; |
2019 | b6cd0ea1 | aurel32 | s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
2020 | b6cd0ea1 | aurel32 | chr ?: qemu_chr_open("null"), 1); |
2021 | 827df9f3 | balrog | |
2022 | 827df9f3 | balrog | return s;
|
2023 | 827df9f3 | balrog | } |
2024 | 827df9f3 | balrog | |
2025 | 827df9f3 | balrog | static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) |
2026 | 827df9f3 | balrog | { |
2027 | 827df9f3 | balrog | struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
2028 | 827df9f3 | balrog | int offset = addr - s->base;
|
2029 | 827df9f3 | balrog | |
2030 | 827df9f3 | balrog | switch (offset) {
|
2031 | 54585ffe | balrog | case 0x20: /* MDR1 */ |
2032 | 54585ffe | balrog | return s->mdr[0]; |
2033 | 54585ffe | balrog | case 0x24: /* MDR2 */ |
2034 | 54585ffe | balrog | return s->mdr[1]; |
2035 | 54585ffe | balrog | case 0x40: /* SCR */ |
2036 | 54585ffe | balrog | return s->scr;
|
2037 | 54585ffe | balrog | case 0x44: /* SSR */ |
2038 | 54585ffe | balrog | return 0x0; |
2039 | 827df9f3 | balrog | case 0x48: /* EBLR */ |
2040 | 827df9f3 | balrog | return s->eblr;
|
2041 | 827df9f3 | balrog | case 0x50: /* MVR */ |
2042 | 827df9f3 | balrog | return 0x30; |
2043 | 827df9f3 | balrog | case 0x54: /* SYSC */ |
2044 | 827df9f3 | balrog | return s->syscontrol;
|
2045 | 827df9f3 | balrog | case 0x58: /* SYSS */ |
2046 | 827df9f3 | balrog | return 1; |
2047 | 827df9f3 | balrog | case 0x5c: /* WER */ |
2048 | 827df9f3 | balrog | return s->wkup;
|
2049 | 827df9f3 | balrog | case 0x60: /* CFPS */ |
2050 | 827df9f3 | balrog | return s->cfps;
|
2051 | 827df9f3 | balrog | } |
2052 | 827df9f3 | balrog | |
2053 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2054 | 827df9f3 | balrog | return 0; |
2055 | 827df9f3 | balrog | } |
2056 | 827df9f3 | balrog | |
2057 | 827df9f3 | balrog | static void omap_uart_write(void *opaque, target_phys_addr_t addr, |
2058 | 827df9f3 | balrog | uint32_t value) |
2059 | 827df9f3 | balrog | { |
2060 | 827df9f3 | balrog | struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
2061 | 827df9f3 | balrog | int offset = addr - s->base;
|
2062 | 827df9f3 | balrog | |
2063 | 827df9f3 | balrog | switch (offset) {
|
2064 | 54585ffe | balrog | case 0x20: /* MDR1 */ |
2065 | 54585ffe | balrog | s->mdr[0] = value & 0x7f; |
2066 | 54585ffe | balrog | break;
|
2067 | 54585ffe | balrog | case 0x24: /* MDR2 */ |
2068 | 54585ffe | balrog | s->mdr[1] = value & 0xff; |
2069 | 54585ffe | balrog | break;
|
2070 | 54585ffe | balrog | case 0x40: /* SCR */ |
2071 | 54585ffe | balrog | s->scr = value & 0xff;
|
2072 | 54585ffe | balrog | break;
|
2073 | 827df9f3 | balrog | case 0x48: /* EBLR */ |
2074 | 827df9f3 | balrog | s->eblr = value & 0xff;
|
2075 | 827df9f3 | balrog | break;
|
2076 | 54585ffe | balrog | case 0x44: /* SSR */ |
2077 | 827df9f3 | balrog | case 0x50: /* MVR */ |
2078 | 827df9f3 | balrog | case 0x58: /* SYSS */ |
2079 | 827df9f3 | balrog | OMAP_RO_REG(addr); |
2080 | 827df9f3 | balrog | break;
|
2081 | 827df9f3 | balrog | case 0x54: /* SYSC */ |
2082 | 827df9f3 | balrog | s->syscontrol = value & 0x1d;
|
2083 | 827df9f3 | balrog | if (value & 2) |
2084 | 827df9f3 | balrog | omap_uart_reset(s); |
2085 | 827df9f3 | balrog | break;
|
2086 | 827df9f3 | balrog | case 0x5c: /* WER */ |
2087 | 827df9f3 | balrog | s->wkup = value & 0x7f;
|
2088 | 827df9f3 | balrog | break;
|
2089 | 827df9f3 | balrog | case 0x60: /* CFPS */ |
2090 | 827df9f3 | balrog | s->cfps = value & 0xff;
|
2091 | 827df9f3 | balrog | break;
|
2092 | 827df9f3 | balrog | default:
|
2093 | 827df9f3 | balrog | OMAP_BAD_REG(addr); |
2094 | 827df9f3 | balrog | } |
2095 | 827df9f3 | balrog | } |
2096 | 827df9f3 | balrog | |
2097 | 827df9f3 | balrog | static CPUReadMemoryFunc *omap_uart_readfn[] = {
|
2098 | 827df9f3 | balrog | omap_uart_read, |
2099 | 827df9f3 | balrog | omap_uart_read, |
2100 | 827df9f3 | balrog | omap_badwidth_read8, |
2101 | 827df9f3 | balrog | }; |
2102 | 827df9f3 | balrog | |
2103 | 827df9f3 | balrog | static CPUWriteMemoryFunc *omap_uart_writefn[] = {
|
2104 | 827df9f3 | balrog | omap_uart_write, |
2105 | 827df9f3 | balrog | omap_uart_write, |
2106 | 827df9f3 | balrog | omap_badwidth_write8, |
2107 | 827df9f3 | balrog | }; |
2108 | 827df9f3 | balrog | |
2109 | 827df9f3 | balrog | struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
2110 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
2111 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
2112 | 827df9f3 | balrog | { |
2113 | 827df9f3 | balrog | target_phys_addr_t base = omap_l4_attach(ta, 0, 0); |
2114 | 827df9f3 | balrog | struct omap_uart_s *s = omap_uart_init(base, irq,
|
2115 | 827df9f3 | balrog | fclk, iclk, txdma, rxdma, chr); |
2116 | 827df9f3 | balrog | int iomemtype = cpu_register_io_memory(0, omap_uart_readfn, |
2117 | 827df9f3 | balrog | omap_uart_writefn, s); |
2118 | 827df9f3 | balrog | |
2119 | 827df9f3 | balrog | s->ta = ta; |
2120 | 827df9f3 | balrog | |
2121 | 827df9f3 | balrog | cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype); |
2122 | 827df9f3 | balrog | |
2123 | c3d2689d | balrog | return s;
|
2124 | c3d2689d | balrog | } |
2125 | c3d2689d | balrog | |
2126 | 75554a3c | balrog | void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) |
2127 | 75554a3c | balrog | { |
2128 | 75554a3c | balrog | /* TODO: Should reuse or destroy current s->serial */
|
2129 | 75554a3c | balrog | s->serial = serial_mm_init(s->base, 2, s->irq,
|
2130 | 75554a3c | balrog | omap_clk_getrate(s->fclk) / 16,
|
2131 | 75554a3c | balrog | chr ?: qemu_chr_open("null"), 1); |
2132 | 75554a3c | balrog | } |
2133 | 75554a3c | balrog | |
2134 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
2135 | c3d2689d | balrog | static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
2136 | c3d2689d | balrog | { |
2137 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2138 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2139 | c3d2689d | balrog | |
2140 | c3d2689d | balrog | switch (offset) {
|
2141 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2142 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
2143 | c3d2689d | balrog | |
2144 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2145 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
2146 | c3d2689d | balrog | |
2147 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2148 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
2149 | c3d2689d | balrog | |
2150 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2151 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
2152 | c3d2689d | balrog | |
2153 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2154 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
2155 | c3d2689d | balrog | |
2156 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2157 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
2158 | c3d2689d | balrog | |
2159 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2160 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
2161 | c3d2689d | balrog | |
2162 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2163 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
2164 | c3d2689d | balrog | |
2165 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2166 | c3d2689d | balrog | break;
|
2167 | c3d2689d | balrog | } |
2168 | c3d2689d | balrog | |
2169 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2170 | c3d2689d | balrog | return 0; |
2171 | c3d2689d | balrog | } |
2172 | c3d2689d | balrog | |
2173 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
2174 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2175 | c3d2689d | balrog | { |
2176 | c3d2689d | balrog | omap_clk clk; |
2177 | c3d2689d | balrog | |
2178 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
2179 | c3d2689d | balrog | if (value & (1 << 14)) |
2180 | c3d2689d | balrog | /* Reserved */;
|
2181 | c3d2689d | balrog | else {
|
2182 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
2183 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2184 | c3d2689d | balrog | } |
2185 | c3d2689d | balrog | } |
2186 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
2187 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
2188 | c3d2689d | balrog | if (value & (1 << 12)) |
2189 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
2190 | c3d2689d | balrog | else
|
2191 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2192 | c3d2689d | balrog | } |
2193 | c3d2689d | balrog | /* XXX: en_dspck */
|
2194 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
2195 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
2196 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
2197 | c3d2689d | balrog | } |
2198 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
2199 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
2200 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
2201 | c3d2689d | balrog | } |
2202 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
2203 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2204 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
2205 | c3d2689d | balrog | } |
2206 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
2207 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
2208 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
2209 | c3d2689d | balrog | } |
2210 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
2211 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
2212 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
2213 | c3d2689d | balrog | } |
2214 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
2215 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
2216 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
2217 | c3d2689d | balrog | } |
2218 | c3d2689d | balrog | } |
2219 | c3d2689d | balrog | |
2220 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
2221 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2222 | c3d2689d | balrog | { |
2223 | c3d2689d | balrog | omap_clk clk; |
2224 | c3d2689d | balrog | |
2225 | c3d2689d | balrog | if (value & (1 << 11)) /* SETARM_IDLE */ |
2226 | c3d2689d | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
2227 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
2228 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
2229 | c3d2689d | balrog | |
2230 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
2231 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2232 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2233 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
2234 | c3d2689d | balrog | } |
2235 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
2236 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
2237 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
2238 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
2239 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
2240 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
2241 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
2242 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
2243 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
2244 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
2245 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
2246 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
2247 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
2248 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
2249 | c3d2689d | balrog | } |
2250 | c3d2689d | balrog | |
2251 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
2252 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2253 | c3d2689d | balrog | { |
2254 | c3d2689d | balrog | omap_clk clk; |
2255 | c3d2689d | balrog | |
2256 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
2257 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
2258 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
2259 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
2260 | c3d2689d | balrog | } |
2261 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
2262 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
2263 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
2264 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
2265 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
2266 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
2267 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
2268 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
2269 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
2270 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
2271 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
2272 | c3d2689d | balrog | } |
2273 | c3d2689d | balrog | |
2274 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
2275 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2276 | c3d2689d | balrog | { |
2277 | c3d2689d | balrog | omap_clk clk; |
2278 | c3d2689d | balrog | |
2279 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
2280 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
2281 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
2282 | c3d2689d | balrog | case 1: |
2283 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
2284 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2285 | c3d2689d | balrog | break;
|
2286 | c3d2689d | balrog | case 2: |
2287 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2288 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2289 | c3d2689d | balrog | break;
|
2290 | c3d2689d | balrog | default:
|
2291 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2292 | c3d2689d | balrog | } |
2293 | c3d2689d | balrog | } |
2294 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
2295 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
2296 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
2297 | c3d2689d | balrog | case 0: |
2298 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
2299 | c3d2689d | balrog | break;
|
2300 | c3d2689d | balrog | case 1: |
2301 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
2302 | c3d2689d | balrog | break;
|
2303 | c3d2689d | balrog | case 2: |
2304 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
2305 | c3d2689d | balrog | break;
|
2306 | c3d2689d | balrog | case 3: |
2307 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2308 | c3d2689d | balrog | break;
|
2309 | c3d2689d | balrog | } |
2310 | c3d2689d | balrog | } |
2311 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
2312 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
2313 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
2314 | c3d2689d | balrog | case 1: |
2315 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2316 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2317 | c3d2689d | balrog | break;
|
2318 | c3d2689d | balrog | case 2: |
2319 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
2320 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2321 | c3d2689d | balrog | break;
|
2322 | c3d2689d | balrog | case 3: |
2323 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2324 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
2325 | c3d2689d | balrog | break;
|
2326 | c3d2689d | balrog | default:
|
2327 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
2328 | c3d2689d | balrog | } |
2329 | c3d2689d | balrog | } |
2330 | c3d2689d | balrog | } |
2331 | c3d2689d | balrog | |
2332 | c3d2689d | balrog | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
2333 | c3d2689d | balrog | uint32_t value) |
2334 | c3d2689d | balrog | { |
2335 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2336 | c3d2689d | balrog | int offset = addr - s->clkm.mpu_base;
|
2337 | c3d2689d | balrog | uint16_t diff; |
2338 | c3d2689d | balrog | omap_clk clk; |
2339 | c3d2689d | balrog | static const char *clkschemename[8] = { |
2340 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
2341 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
2342 | c3d2689d | balrog | }; |
2343 | c3d2689d | balrog | |
2344 | c3d2689d | balrog | switch (offset) {
|
2345 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
2346 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
2347 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
2348 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
2349 | c3d2689d | balrog | return;
|
2350 | c3d2689d | balrog | |
2351 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
2352 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
2353 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
2354 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
2355 | c3d2689d | balrog | return;
|
2356 | c3d2689d | balrog | |
2357 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
2358 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
2359 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
2360 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
2361 | c3d2689d | balrog | return;
|
2362 | c3d2689d | balrog | |
2363 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
2364 | c3d2689d | balrog | diff = s->clkm.arm_ewupct ^ value; |
2365 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
2366 | c3d2689d | balrog | return;
|
2367 | c3d2689d | balrog | |
2368 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
2369 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
2370 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
2371 | c3d2689d | balrog | if (value & 9) { |
2372 | c3d2689d | balrog | qemu_system_reset_request(); |
2373 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
2374 | c3d2689d | balrog | } |
2375 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
2376 | c3d2689d | balrog | omap_mpui_reset(s); |
2377 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
2378 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
2379 | c3d2689d | balrog | } |
2380 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
2381 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
2382 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
2383 | c3d2689d | balrog | } |
2384 | c3d2689d | balrog | return;
|
2385 | c3d2689d | balrog | |
2386 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
2387 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
2388 | c3d2689d | balrog | return;
|
2389 | c3d2689d | balrog | |
2390 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
2391 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
2392 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
2393 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2394 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
2395 | c3d2689d | balrog | } |
2396 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2397 | c3d2689d | balrog | return;
|
2398 | c3d2689d | balrog | |
2399 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
2400 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
2401 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
2402 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
2403 | c3d2689d | balrog | return;
|
2404 | c3d2689d | balrog | |
2405 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
2406 | c3d2689d | balrog | default:
|
2407 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2408 | c3d2689d | balrog | } |
2409 | c3d2689d | balrog | } |
2410 | c3d2689d | balrog | |
2411 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2412 | c3d2689d | balrog | omap_badwidth_read16, |
2413 | c3d2689d | balrog | omap_clkm_read, |
2414 | c3d2689d | balrog | omap_badwidth_read16, |
2415 | c3d2689d | balrog | }; |
2416 | c3d2689d | balrog | |
2417 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2418 | c3d2689d | balrog | omap_badwidth_write16, |
2419 | c3d2689d | balrog | omap_clkm_write, |
2420 | c3d2689d | balrog | omap_badwidth_write16, |
2421 | c3d2689d | balrog | }; |
2422 | c3d2689d | balrog | |
2423 | c3d2689d | balrog | static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2424 | c3d2689d | balrog | { |
2425 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2426 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2427 | c3d2689d | balrog | |
2428 | c3d2689d | balrog | switch (offset) {
|
2429 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2430 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
2431 | c3d2689d | balrog | |
2432 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2433 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
2434 | c3d2689d | balrog | |
2435 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2436 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
2437 | c3d2689d | balrog | |
2438 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2439 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
2440 | c3d2689d | balrog | (s->env->halted << 6); /* Quite useless... */ |
2441 | c3d2689d | balrog | } |
2442 | c3d2689d | balrog | |
2443 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2444 | c3d2689d | balrog | return 0; |
2445 | c3d2689d | balrog | } |
2446 | c3d2689d | balrog | |
2447 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2448 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2449 | c3d2689d | balrog | { |
2450 | c3d2689d | balrog | omap_clk clk; |
2451 | c3d2689d | balrog | |
2452 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2453 | c3d2689d | balrog | } |
2454 | c3d2689d | balrog | |
2455 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2456 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
2457 | c3d2689d | balrog | { |
2458 | c3d2689d | balrog | omap_clk clk; |
2459 | c3d2689d | balrog | |
2460 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2461 | c3d2689d | balrog | } |
2462 | c3d2689d | balrog | |
2463 | c3d2689d | balrog | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2464 | c3d2689d | balrog | uint32_t value) |
2465 | c3d2689d | balrog | { |
2466 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2467 | c3d2689d | balrog | int offset = addr - s->clkm.dsp_base;
|
2468 | c3d2689d | balrog | uint16_t diff; |
2469 | c3d2689d | balrog | |
2470 | c3d2689d | balrog | switch (offset) {
|
2471 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
2472 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2473 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
2474 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
2475 | c3d2689d | balrog | break;
|
2476 | c3d2689d | balrog | |
2477 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
2478 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
2479 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
2480 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
2481 | c3d2689d | balrog | break;
|
2482 | c3d2689d | balrog | |
2483 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
2484 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
2485 | c3d2689d | balrog | break;
|
2486 | c3d2689d | balrog | |
2487 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
2488 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
2489 | c3d2689d | balrog | break;
|
2490 | c3d2689d | balrog | |
2491 | c3d2689d | balrog | default:
|
2492 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
2493 | c3d2689d | balrog | } |
2494 | c3d2689d | balrog | } |
2495 | c3d2689d | balrog | |
2496 | c3d2689d | balrog | static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2497 | c3d2689d | balrog | omap_badwidth_read16, |
2498 | c3d2689d | balrog | omap_clkdsp_read, |
2499 | c3d2689d | balrog | omap_badwidth_read16, |
2500 | c3d2689d | balrog | }; |
2501 | c3d2689d | balrog | |
2502 | c3d2689d | balrog | static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2503 | c3d2689d | balrog | omap_badwidth_write16, |
2504 | c3d2689d | balrog | omap_clkdsp_write, |
2505 | c3d2689d | balrog | omap_badwidth_write16, |
2506 | c3d2689d | balrog | }; |
2507 | c3d2689d | balrog | |
2508 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2509 | c3d2689d | balrog | { |
2510 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
2511 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
2512 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
2513 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
2514 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
2515 | d8f699cb | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
2516 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
2517 | d8f699cb | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
2518 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2519 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
2520 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
2521 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
2522 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
2523 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
2524 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2525 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
2526 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2527 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
2528 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
2529 | c3d2689d | balrog | } |
2530 | c3d2689d | balrog | |
2531 | c3d2689d | balrog | static void omap_clkm_init(target_phys_addr_t mpu_base, |
2532 | c3d2689d | balrog | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2533 | c3d2689d | balrog | { |
2534 | c3d2689d | balrog | int iomemtype[2] = { |
2535 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2536 | c3d2689d | balrog | cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2537 | c3d2689d | balrog | }; |
2538 | c3d2689d | balrog | |
2539 | c3d2689d | balrog | s->clkm.mpu_base = mpu_base; |
2540 | c3d2689d | balrog | s->clkm.dsp_base = dsp_base; |
2541 | d8f699cb | balrog | s->clkm.arm_idlect1 = 0x03ff;
|
2542 | d8f699cb | balrog | s->clkm.arm_idlect2 = 0x0100;
|
2543 | d8f699cb | balrog | s->clkm.dsp_idlect1 = 0x0002;
|
2544 | c3d2689d | balrog | omap_clkm_reset(s); |
2545 | d8f699cb | balrog | s->clkm.cold_start = 0x3a;
|
2546 | c3d2689d | balrog | |
2547 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2548 | c3d2689d | balrog | cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2549 | c3d2689d | balrog | } |
2550 | c3d2689d | balrog | |
2551 | fe71e81a | balrog | /* MPU I/O */
|
2552 | fe71e81a | balrog | struct omap_mpuio_s {
|
2553 | fe71e81a | balrog | target_phys_addr_t base; |
2554 | fe71e81a | balrog | qemu_irq irq; |
2555 | fe71e81a | balrog | qemu_irq kbd_irq; |
2556 | fe71e81a | balrog | qemu_irq *in; |
2557 | fe71e81a | balrog | qemu_irq handler[16];
|
2558 | fe71e81a | balrog | qemu_irq wakeup; |
2559 | fe71e81a | balrog | |
2560 | fe71e81a | balrog | uint16_t inputs; |
2561 | fe71e81a | balrog | uint16_t outputs; |
2562 | fe71e81a | balrog | uint16_t dir; |
2563 | fe71e81a | balrog | uint16_t edge; |
2564 | fe71e81a | balrog | uint16_t mask; |
2565 | fe71e81a | balrog | uint16_t ints; |
2566 | fe71e81a | balrog | |
2567 | fe71e81a | balrog | uint16_t debounce; |
2568 | fe71e81a | balrog | uint16_t latch; |
2569 | fe71e81a | balrog | uint8_t event; |
2570 | fe71e81a | balrog | |
2571 | fe71e81a | balrog | uint8_t buttons[5];
|
2572 | fe71e81a | balrog | uint8_t row_latch; |
2573 | fe71e81a | balrog | uint8_t cols; |
2574 | fe71e81a | balrog | int kbd_mask;
|
2575 | fe71e81a | balrog | int clk;
|
2576 | fe71e81a | balrog | }; |
2577 | fe71e81a | balrog | |
2578 | fe71e81a | balrog | static void omap_mpuio_set(void *opaque, int line, int level) |
2579 | fe71e81a | balrog | { |
2580 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2581 | fe71e81a | balrog | uint16_t prev = s->inputs; |
2582 | fe71e81a | balrog | |
2583 | fe71e81a | balrog | if (level)
|
2584 | fe71e81a | balrog | s->inputs |= 1 << line;
|
2585 | fe71e81a | balrog | else
|
2586 | fe71e81a | balrog | s->inputs &= ~(1 << line);
|
2587 | fe71e81a | balrog | |
2588 | fe71e81a | balrog | if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
2589 | fe71e81a | balrog | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
2590 | fe71e81a | balrog | s->ints |= 1 << line;
|
2591 | fe71e81a | balrog | qemu_irq_raise(s->irq); |
2592 | fe71e81a | balrog | /* TODO: wakeup */
|
2593 | fe71e81a | balrog | } |
2594 | fe71e81a | balrog | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
2595 | fe71e81a | balrog | (s->event >> 1) == line) /* PIN_SELECT */ |
2596 | fe71e81a | balrog | s->latch = s->inputs; |
2597 | fe71e81a | balrog | } |
2598 | fe71e81a | balrog | } |
2599 | fe71e81a | balrog | |
2600 | fe71e81a | balrog | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
2601 | fe71e81a | balrog | { |
2602 | fe71e81a | balrog | int i;
|
2603 | fe71e81a | balrog | uint8_t *row, rows = 0, cols = ~s->cols;
|
2604 | fe71e81a | balrog | |
2605 | 38a34e1d | balrog | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
2606 | fe71e81a | balrog | if (*row & cols)
|
2607 | 38a34e1d | balrog | rows |= i; |
2608 | fe71e81a | balrog | |
2609 | cf6d9118 | balrog | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
2610 | cf6d9118 | balrog | s->row_latch = ~rows; |
2611 | fe71e81a | balrog | } |
2612 | fe71e81a | balrog | |
2613 | fe71e81a | balrog | static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
2614 | fe71e81a | balrog | { |
2615 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2616 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2617 | fe71e81a | balrog | uint16_t ret; |
2618 | fe71e81a | balrog | |
2619 | fe71e81a | balrog | switch (offset) {
|
2620 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2621 | fe71e81a | balrog | return s->inputs;
|
2622 | fe71e81a | balrog | |
2623 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2624 | fe71e81a | balrog | return s->outputs;
|
2625 | fe71e81a | balrog | |
2626 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2627 | fe71e81a | balrog | return s->dir;
|
2628 | fe71e81a | balrog | |
2629 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2630 | fe71e81a | balrog | return s->row_latch;
|
2631 | fe71e81a | balrog | |
2632 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2633 | fe71e81a | balrog | return s->cols;
|
2634 | fe71e81a | balrog | |
2635 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2636 | fe71e81a | balrog | return s->event;
|
2637 | fe71e81a | balrog | |
2638 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2639 | fe71e81a | balrog | return s->edge;
|
2640 | fe71e81a | balrog | |
2641 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2642 | cf6d9118 | balrog | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
2643 | fe71e81a | balrog | |
2644 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2645 | fe71e81a | balrog | ret = s->ints; |
2646 | 8e129e07 | balrog | s->ints &= s->mask; |
2647 | 8e129e07 | balrog | if (ret)
|
2648 | 8e129e07 | balrog | qemu_irq_lower(s->irq); |
2649 | fe71e81a | balrog | return ret;
|
2650 | fe71e81a | balrog | |
2651 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2652 | fe71e81a | balrog | return s->kbd_mask;
|
2653 | fe71e81a | balrog | |
2654 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2655 | fe71e81a | balrog | return s->mask;
|
2656 | fe71e81a | balrog | |
2657 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2658 | fe71e81a | balrog | return s->debounce;
|
2659 | fe71e81a | balrog | |
2660 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2661 | fe71e81a | balrog | return s->latch;
|
2662 | fe71e81a | balrog | } |
2663 | fe71e81a | balrog | |
2664 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2665 | fe71e81a | balrog | return 0; |
2666 | fe71e81a | balrog | } |
2667 | fe71e81a | balrog | |
2668 | fe71e81a | balrog | static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
2669 | fe71e81a | balrog | uint32_t value) |
2670 | fe71e81a | balrog | { |
2671 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2672 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2673 | fe71e81a | balrog | uint16_t diff; |
2674 | fe71e81a | balrog | int ln;
|
2675 | fe71e81a | balrog | |
2676 | fe71e81a | balrog | switch (offset) {
|
2677 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
2678 | d8f699cb | balrog | diff = (s->outputs ^ value) & ~s->dir; |
2679 | fe71e81a | balrog | s->outputs = value; |
2680 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2681 | fe71e81a | balrog | ln --; |
2682 | fe71e81a | balrog | if (s->handler[ln])
|
2683 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2684 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2685 | fe71e81a | balrog | } |
2686 | fe71e81a | balrog | break;
|
2687 | fe71e81a | balrog | |
2688 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
2689 | fe71e81a | balrog | diff = s->outputs & (s->dir ^ value); |
2690 | fe71e81a | balrog | s->dir = value; |
2691 | fe71e81a | balrog | |
2692 | fe71e81a | balrog | value = s->outputs & ~s->dir; |
2693 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
2694 | fe71e81a | balrog | ln --; |
2695 | fe71e81a | balrog | if (s->handler[ln])
|
2696 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2697 | fe71e81a | balrog | diff &= ~(1 << ln);
|
2698 | fe71e81a | balrog | } |
2699 | fe71e81a | balrog | break;
|
2700 | fe71e81a | balrog | |
2701 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
2702 | fe71e81a | balrog | s->cols = value; |
2703 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2704 | fe71e81a | balrog | break;
|
2705 | fe71e81a | balrog | |
2706 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
2707 | fe71e81a | balrog | s->event = value & 0x1f;
|
2708 | fe71e81a | balrog | break;
|
2709 | fe71e81a | balrog | |
2710 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
2711 | fe71e81a | balrog | s->edge = value; |
2712 | fe71e81a | balrog | break;
|
2713 | fe71e81a | balrog | |
2714 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
2715 | fe71e81a | balrog | s->kbd_mask = value & 1;
|
2716 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2717 | fe71e81a | balrog | break;
|
2718 | fe71e81a | balrog | |
2719 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
2720 | fe71e81a | balrog | s->mask = value; |
2721 | fe71e81a | balrog | break;
|
2722 | fe71e81a | balrog | |
2723 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
2724 | fe71e81a | balrog | s->debounce = value & 0x1ff;
|
2725 | fe71e81a | balrog | break;
|
2726 | fe71e81a | balrog | |
2727 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
2728 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
2729 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
2730 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
2731 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
2732 | fe71e81a | balrog | OMAP_RO_REG(addr); |
2733 | fe71e81a | balrog | return;
|
2734 | fe71e81a | balrog | |
2735 | fe71e81a | balrog | default:
|
2736 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
2737 | fe71e81a | balrog | return;
|
2738 | fe71e81a | balrog | } |
2739 | fe71e81a | balrog | } |
2740 | fe71e81a | balrog | |
2741 | fe71e81a | balrog | static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
|
2742 | fe71e81a | balrog | omap_badwidth_read16, |
2743 | fe71e81a | balrog | omap_mpuio_read, |
2744 | fe71e81a | balrog | omap_badwidth_read16, |
2745 | fe71e81a | balrog | }; |
2746 | fe71e81a | balrog | |
2747 | fe71e81a | balrog | static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
|
2748 | fe71e81a | balrog | omap_badwidth_write16, |
2749 | fe71e81a | balrog | omap_mpuio_write, |
2750 | fe71e81a | balrog | omap_badwidth_write16, |
2751 | fe71e81a | balrog | }; |
2752 | fe71e81a | balrog | |
2753 | 9596ebb7 | pbrook | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
2754 | fe71e81a | balrog | { |
2755 | fe71e81a | balrog | s->inputs = 0;
|
2756 | fe71e81a | balrog | s->outputs = 0;
|
2757 | fe71e81a | balrog | s->dir = ~0;
|
2758 | fe71e81a | balrog | s->event = 0;
|
2759 | fe71e81a | balrog | s->edge = 0;
|
2760 | fe71e81a | balrog | s->kbd_mask = 0;
|
2761 | fe71e81a | balrog | s->mask = 0;
|
2762 | fe71e81a | balrog | s->debounce = 0;
|
2763 | fe71e81a | balrog | s->latch = 0;
|
2764 | fe71e81a | balrog | s->ints = 0;
|
2765 | fe71e81a | balrog | s->row_latch = 0x1f;
|
2766 | 38a34e1d | balrog | s->clk = 1;
|
2767 | fe71e81a | balrog | } |
2768 | fe71e81a | balrog | |
2769 | fe71e81a | balrog | static void omap_mpuio_onoff(void *opaque, int line, int on) |
2770 | fe71e81a | balrog | { |
2771 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2772 | fe71e81a | balrog | |
2773 | fe71e81a | balrog | s->clk = on; |
2774 | fe71e81a | balrog | if (on)
|
2775 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2776 | fe71e81a | balrog | } |
2777 | fe71e81a | balrog | |
2778 | fe71e81a | balrog | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
2779 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2780 | fe71e81a | balrog | omap_clk clk) |
2781 | fe71e81a | balrog | { |
2782 | fe71e81a | balrog | int iomemtype;
|
2783 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
2784 | fe71e81a | balrog | qemu_mallocz(sizeof(struct omap_mpuio_s)); |
2785 | fe71e81a | balrog | |
2786 | fe71e81a | balrog | s->base = base; |
2787 | fe71e81a | balrog | s->irq = gpio_int; |
2788 | fe71e81a | balrog | s->kbd_irq = kbd_int; |
2789 | fe71e81a | balrog | s->wakeup = wakeup; |
2790 | fe71e81a | balrog | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
2791 | fe71e81a | balrog | omap_mpuio_reset(s); |
2792 | fe71e81a | balrog | |
2793 | fe71e81a | balrog | iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
|
2794 | fe71e81a | balrog | omap_mpuio_writefn, s); |
2795 | fe71e81a | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
2796 | fe71e81a | balrog | |
2797 | fe71e81a | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
2798 | fe71e81a | balrog | |
2799 | fe71e81a | balrog | return s;
|
2800 | fe71e81a | balrog | } |
2801 | fe71e81a | balrog | |
2802 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
2803 | fe71e81a | balrog | { |
2804 | fe71e81a | balrog | return s->in;
|
2805 | fe71e81a | balrog | } |
2806 | fe71e81a | balrog | |
2807 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
2808 | fe71e81a | balrog | { |
2809 | fe71e81a | balrog | if (line >= 16 || line < 0) |
2810 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
2811 | fe71e81a | balrog | s->handler[line] = handler; |
2812 | fe71e81a | balrog | } |
2813 | fe71e81a | balrog | |
2814 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
2815 | fe71e81a | balrog | { |
2816 | fe71e81a | balrog | if (row >= 5 || row < 0) |
2817 | fe71e81a | balrog | cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
|
2818 | fe71e81a | balrog | __FUNCTION__, col, row); |
2819 | fe71e81a | balrog | |
2820 | fe71e81a | balrog | if (down)
|
2821 | 38a34e1d | balrog | s->buttons[row] |= 1 << col;
|
2822 | fe71e81a | balrog | else
|
2823 | 38a34e1d | balrog | s->buttons[row] &= ~(1 << col);
|
2824 | fe71e81a | balrog | |
2825 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2826 | fe71e81a | balrog | } |
2827 | fe71e81a | balrog | |
2828 | 64330148 | balrog | /* General-Purpose I/O */
|
2829 | 64330148 | balrog | struct omap_gpio_s {
|
2830 | 64330148 | balrog | target_phys_addr_t base; |
2831 | 64330148 | balrog | qemu_irq irq; |
2832 | 64330148 | balrog | qemu_irq *in; |
2833 | 64330148 | balrog | qemu_irq handler[16];
|
2834 | 64330148 | balrog | |
2835 | 64330148 | balrog | uint16_t inputs; |
2836 | 64330148 | balrog | uint16_t outputs; |
2837 | 64330148 | balrog | uint16_t dir; |
2838 | 64330148 | balrog | uint16_t edge; |
2839 | 64330148 | balrog | uint16_t mask; |
2840 | 64330148 | balrog | uint16_t ints; |
2841 | d8f699cb | balrog | uint16_t pins; |
2842 | 64330148 | balrog | }; |
2843 | 64330148 | balrog | |
2844 | 64330148 | balrog | static void omap_gpio_set(void *opaque, int line, int level) |
2845 | 64330148 | balrog | { |
2846 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2847 | 64330148 | balrog | uint16_t prev = s->inputs; |
2848 | 64330148 | balrog | |
2849 | 64330148 | balrog | if (level)
|
2850 | 64330148 | balrog | s->inputs |= 1 << line;
|
2851 | 64330148 | balrog | else
|
2852 | 64330148 | balrog | s->inputs &= ~(1 << line);
|
2853 | 64330148 | balrog | |
2854 | 64330148 | balrog | if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
|
2855 | 64330148 | balrog | (1 << line) & s->dir & ~s->mask) {
|
2856 | 64330148 | balrog | s->ints |= 1 << line;
|
2857 | 64330148 | balrog | qemu_irq_raise(s->irq); |
2858 | 64330148 | balrog | } |
2859 | 64330148 | balrog | } |
2860 | 64330148 | balrog | |
2861 | 64330148 | balrog | static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
2862 | 64330148 | balrog | { |
2863 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2864 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2865 | 64330148 | balrog | |
2866 | 64330148 | balrog | switch (offset) {
|
2867 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
2868 | d8f699cb | balrog | return s->inputs & s->pins;
|
2869 | 64330148 | balrog | |
2870 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
2871 | 64330148 | balrog | return s->outputs;
|
2872 | 64330148 | balrog | |
2873 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
2874 | 64330148 | balrog | return s->dir;
|
2875 | 64330148 | balrog | |
2876 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
2877 | 64330148 | balrog | return s->edge;
|
2878 | 64330148 | balrog | |
2879 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
2880 | 64330148 | balrog | return s->mask;
|
2881 | 64330148 | balrog | |
2882 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
2883 | 64330148 | balrog | return s->ints;
|
2884 | d8f699cb | balrog | |
2885 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
2886 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
2887 | d8f699cb | balrog | return s->pins;
|
2888 | 64330148 | balrog | } |
2889 | 64330148 | balrog | |
2890 | 64330148 | balrog | OMAP_BAD_REG(addr); |
2891 | 64330148 | balrog | return 0; |
2892 | 64330148 | balrog | } |
2893 | 64330148 | balrog | |
2894 | 64330148 | balrog | static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
2895 | 64330148 | balrog | uint32_t value) |
2896 | 64330148 | balrog | { |
2897 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
2898 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2899 | 64330148 | balrog | uint16_t diff; |
2900 | 64330148 | balrog | int ln;
|
2901 | 64330148 | balrog | |
2902 | 64330148 | balrog | switch (offset) {
|
2903 | 64330148 | balrog | case 0x00: /* DATA_INPUT */ |
2904 | 64330148 | balrog | OMAP_RO_REG(addr); |
2905 | 64330148 | balrog | return;
|
2906 | 64330148 | balrog | |
2907 | 64330148 | balrog | case 0x04: /* DATA_OUTPUT */ |
2908 | 66450b15 | balrog | diff = (s->outputs ^ value) & ~s->dir; |
2909 | 64330148 | balrog | s->outputs = value; |
2910 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
2911 | 64330148 | balrog | ln --; |
2912 | 64330148 | balrog | if (s->handler[ln])
|
2913 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2914 | 64330148 | balrog | diff &= ~(1 << ln);
|
2915 | 64330148 | balrog | } |
2916 | 64330148 | balrog | break;
|
2917 | 64330148 | balrog | |
2918 | 64330148 | balrog | case 0x08: /* DIRECTION_CONTROL */ |
2919 | 64330148 | balrog | diff = s->outputs & (s->dir ^ value); |
2920 | 64330148 | balrog | s->dir = value; |
2921 | 64330148 | balrog | |
2922 | 64330148 | balrog | value = s->outputs & ~s->dir; |
2923 | 64330148 | balrog | while ((ln = ffs(diff))) {
|
2924 | 64330148 | balrog | ln --; |
2925 | 64330148 | balrog | if (s->handler[ln])
|
2926 | 64330148 | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2927 | 64330148 | balrog | diff &= ~(1 << ln);
|
2928 | 64330148 | balrog | } |
2929 | 64330148 | balrog | break;
|
2930 | 64330148 | balrog | |
2931 | 64330148 | balrog | case 0x0c: /* INTERRUPT_CONTROL */ |
2932 | 64330148 | balrog | s->edge = value; |
2933 | 64330148 | balrog | break;
|
2934 | 64330148 | balrog | |
2935 | 64330148 | balrog | case 0x10: /* INTERRUPT_MASK */ |
2936 | 64330148 | balrog | s->mask = value; |
2937 | 64330148 | balrog | break;
|
2938 | 64330148 | balrog | |
2939 | 64330148 | balrog | case 0x14: /* INTERRUPT_STATUS */ |
2940 | 64330148 | balrog | s->ints &= ~value; |
2941 | 64330148 | balrog | if (!s->ints)
|
2942 | 64330148 | balrog | qemu_irq_lower(s->irq); |
2943 | 64330148 | balrog | break;
|
2944 | 64330148 | balrog | |
2945 | d8f699cb | balrog | case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
2946 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
2947 | d8f699cb | balrog | s->pins = value; |
2948 | d8f699cb | balrog | break;
|
2949 | d8f699cb | balrog | |
2950 | 64330148 | balrog | default:
|
2951 | 64330148 | balrog | OMAP_BAD_REG(addr); |
2952 | 64330148 | balrog | return;
|
2953 | 64330148 | balrog | } |
2954 | 64330148 | balrog | } |
2955 | 64330148 | balrog | |
2956 | 3efda49d | balrog | /* *Some* sources say the memory region is 32-bit. */
|
2957 | 64330148 | balrog | static CPUReadMemoryFunc *omap_gpio_readfn[] = {
|
2958 | 3efda49d | balrog | omap_badwidth_read16, |
2959 | 64330148 | balrog | omap_gpio_read, |
2960 | 3efda49d | balrog | omap_badwidth_read16, |
2961 | 64330148 | balrog | }; |
2962 | 64330148 | balrog | |
2963 | 64330148 | balrog | static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
|
2964 | 3efda49d | balrog | omap_badwidth_write16, |
2965 | 64330148 | balrog | omap_gpio_write, |
2966 | 3efda49d | balrog | omap_badwidth_write16, |
2967 | 64330148 | balrog | }; |
2968 | 64330148 | balrog | |
2969 | 9596ebb7 | pbrook | static void omap_gpio_reset(struct omap_gpio_s *s) |
2970 | 64330148 | balrog | { |
2971 | 64330148 | balrog | s->inputs = 0;
|
2972 | 64330148 | balrog | s->outputs = ~0;
|
2973 | 64330148 | balrog | s->dir = ~0;
|
2974 | 64330148 | balrog | s->edge = ~0;
|
2975 | 64330148 | balrog | s->mask = ~0;
|
2976 | 64330148 | balrog | s->ints = 0;
|
2977 | d8f699cb | balrog | s->pins = ~0;
|
2978 | 64330148 | balrog | } |
2979 | 64330148 | balrog | |
2980 | 64330148 | balrog | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
2981 | 64330148 | balrog | qemu_irq irq, omap_clk clk) |
2982 | 64330148 | balrog | { |
2983 | 64330148 | balrog | int iomemtype;
|
2984 | 64330148 | balrog | struct omap_gpio_s *s = (struct omap_gpio_s *) |
2985 | 64330148 | balrog | qemu_mallocz(sizeof(struct omap_gpio_s)); |
2986 | 64330148 | balrog | |
2987 | 64330148 | balrog | s->base = base; |
2988 | 64330148 | balrog | s->irq = irq; |
2989 | 64330148 | balrog | s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
|
2990 | 64330148 | balrog | omap_gpio_reset(s); |
2991 | 64330148 | balrog | |
2992 | 64330148 | balrog | iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
|
2993 | 64330148 | balrog | omap_gpio_writefn, s); |
2994 | 64330148 | balrog | cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
2995 | 64330148 | balrog | |
2996 | 64330148 | balrog | return s;
|
2997 | 64330148 | balrog | } |
2998 | 64330148 | balrog | |
2999 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
|
3000 | 64330148 | balrog | { |
3001 | 64330148 | balrog | return s->in;
|
3002 | 64330148 | balrog | } |
3003 | 64330148 | balrog | |
3004 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
3005 | 64330148 | balrog | { |
3006 | 64330148 | balrog | if (line >= 16 || line < 0) |
3007 | 64330148 | balrog | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3008 | 64330148 | balrog | s->handler[line] = handler; |
3009 | 64330148 | balrog | } |
3010 | 64330148 | balrog | |
3011 | d951f6ff | balrog | /* MicroWire Interface */
|
3012 | d951f6ff | balrog | struct omap_uwire_s {
|
3013 | d951f6ff | balrog | target_phys_addr_t base; |
3014 | d951f6ff | balrog | qemu_irq txirq; |
3015 | d951f6ff | balrog | qemu_irq rxirq; |
3016 | d951f6ff | balrog | qemu_irq txdrq; |
3017 | d951f6ff | balrog | |
3018 | d951f6ff | balrog | uint16_t txbuf; |
3019 | d951f6ff | balrog | uint16_t rxbuf; |
3020 | d951f6ff | balrog | uint16_t control; |
3021 | d951f6ff | balrog | uint16_t setup[5];
|
3022 | d951f6ff | balrog | |
3023 | d951f6ff | balrog | struct uwire_slave_s *chip[4]; |
3024 | d951f6ff | balrog | }; |
3025 | d951f6ff | balrog | |
3026 | d951f6ff | balrog | static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
3027 | d951f6ff | balrog | { |
3028 | d951f6ff | balrog | int chipselect = (s->control >> 10) & 3; /* INDEX */ |
3029 | d951f6ff | balrog | struct uwire_slave_s *slave = s->chip[chipselect];
|
3030 | d951f6ff | balrog | |
3031 | d951f6ff | balrog | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
3032 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
3033 | d951f6ff | balrog | if (slave && slave->send)
|
3034 | d951f6ff | balrog | slave->send(slave->opaque, |
3035 | d951f6ff | balrog | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
3036 | d951f6ff | balrog | s->control &= ~(1 << 14); /* CSRB */ |
3037 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3038 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
3039 | d951f6ff | balrog | } |
3040 | d951f6ff | balrog | |
3041 | d951f6ff | balrog | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
3042 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
3043 | d951f6ff | balrog | if (slave && slave->receive)
|
3044 | d951f6ff | balrog | s->rxbuf = slave->receive(slave->opaque); |
3045 | d951f6ff | balrog | s->control |= 1 << 15; /* RDRB */ |
3046 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3047 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
3048 | d951f6ff | balrog | } |
3049 | d951f6ff | balrog | } |
3050 | d951f6ff | balrog | |
3051 | d951f6ff | balrog | static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
3052 | d951f6ff | balrog | { |
3053 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3054 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3055 | d951f6ff | balrog | |
3056 | d951f6ff | balrog | switch (offset) {
|
3057 | d951f6ff | balrog | case 0x00: /* RDR */ |
3058 | d951f6ff | balrog | s->control &= ~(1 << 15); /* RDRB */ |
3059 | d951f6ff | balrog | return s->rxbuf;
|
3060 | d951f6ff | balrog | |
3061 | d951f6ff | balrog | case 0x04: /* CSR */ |
3062 | d951f6ff | balrog | return s->control;
|
3063 | d951f6ff | balrog | |
3064 | d951f6ff | balrog | case 0x08: /* SR1 */ |
3065 | d951f6ff | balrog | return s->setup[0]; |
3066 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
3067 | d951f6ff | balrog | return s->setup[1]; |
3068 | d951f6ff | balrog | case 0x10: /* SR3 */ |
3069 | d951f6ff | balrog | return s->setup[2]; |
3070 | d951f6ff | balrog | case 0x14: /* SR4 */ |
3071 | d951f6ff | balrog | return s->setup[3]; |
3072 | d951f6ff | balrog | case 0x18: /* SR5 */ |
3073 | d951f6ff | balrog | return s->setup[4]; |
3074 | d951f6ff | balrog | } |
3075 | d951f6ff | balrog | |
3076 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
3077 | d951f6ff | balrog | return 0; |
3078 | d951f6ff | balrog | } |
3079 | d951f6ff | balrog | |
3080 | d951f6ff | balrog | static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
3081 | d951f6ff | balrog | uint32_t value) |
3082 | d951f6ff | balrog | { |
3083 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3084 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3085 | d951f6ff | balrog | |
3086 | d951f6ff | balrog | switch (offset) {
|
3087 | d951f6ff | balrog | case 0x00: /* TDR */ |
3088 | d951f6ff | balrog | s->txbuf = value; /* TD */
|
3089 | d951f6ff | balrog | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
3090 | d951f6ff | balrog | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
3091 | cf965d24 | balrog | (s->control & (1 << 12)))) { /* CS_CMD */ |
3092 | cf965d24 | balrog | s->control |= 1 << 14; /* CSRB */ |
3093 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
3094 | cf965d24 | balrog | } |
3095 | d951f6ff | balrog | break;
|
3096 | d951f6ff | balrog | |
3097 | d951f6ff | balrog | case 0x04: /* CSR */ |
3098 | d951f6ff | balrog | s->control = value & 0x1fff;
|
3099 | d951f6ff | balrog | if (value & (1 << 13)) /* START */ |
3100 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
3101 | d951f6ff | balrog | break;
|
3102 | d951f6ff | balrog | |
3103 | d951f6ff | balrog | case 0x08: /* SR1 */ |
3104 | d951f6ff | balrog | s->setup[0] = value & 0x003f; |
3105 | d951f6ff | balrog | break;
|
3106 | d951f6ff | balrog | |
3107 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
3108 | d951f6ff | balrog | s->setup[1] = value & 0x0fc0; |
3109 | d951f6ff | balrog | break;
|
3110 | d951f6ff | balrog | |
3111 | d951f6ff | balrog | case 0x10: /* SR3 */ |
3112 | d951f6ff | balrog | s->setup[2] = value & 0x0003; |
3113 | d951f6ff | balrog | break;
|
3114 | d951f6ff | balrog | |
3115 | d951f6ff | balrog | case 0x14: /* SR4 */ |
3116 | d951f6ff | balrog | s->setup[3] = value & 0x0001; |
3117 | d951f6ff | balrog | break;
|
3118 | d951f6ff | balrog | |
3119 | d951f6ff | balrog | case 0x18: /* SR5 */ |
3120 | d951f6ff | balrog | s->setup[4] = value & 0x000f; |
3121 | d951f6ff | balrog | break;
|
3122 | d951f6ff | balrog | |
3123 | d951f6ff | balrog | default:
|
3124 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
3125 | d951f6ff | balrog | return;
|
3126 | d951f6ff | balrog | } |
3127 | d951f6ff | balrog | } |
3128 | d951f6ff | balrog | |
3129 | d951f6ff | balrog | static CPUReadMemoryFunc *omap_uwire_readfn[] = {
|
3130 | d951f6ff | balrog | omap_badwidth_read16, |
3131 | d951f6ff | balrog | omap_uwire_read, |
3132 | d951f6ff | balrog | omap_badwidth_read16, |
3133 | d951f6ff | balrog | }; |
3134 | d951f6ff | balrog | |
3135 | d951f6ff | balrog | static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
|
3136 | d951f6ff | balrog | omap_badwidth_write16, |
3137 | d951f6ff | balrog | omap_uwire_write, |
3138 | d951f6ff | balrog | omap_badwidth_write16, |
3139 | d951f6ff | balrog | }; |
3140 | d951f6ff | balrog | |
3141 | 9596ebb7 | pbrook | static void omap_uwire_reset(struct omap_uwire_s *s) |
3142 | d951f6ff | balrog | { |
3143 | 66450b15 | balrog | s->control = 0;
|
3144 | d951f6ff | balrog | s->setup[0] = 0; |
3145 | d951f6ff | balrog | s->setup[1] = 0; |
3146 | d951f6ff | balrog | s->setup[2] = 0; |
3147 | d951f6ff | balrog | s->setup[3] = 0; |
3148 | d951f6ff | balrog | s->setup[4] = 0; |
3149 | d951f6ff | balrog | } |
3150 | d951f6ff | balrog | |
3151 | d951f6ff | balrog | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
3152 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk) |
3153 | d951f6ff | balrog | { |
3154 | d951f6ff | balrog | int iomemtype;
|
3155 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) |
3156 | d951f6ff | balrog | qemu_mallocz(sizeof(struct omap_uwire_s)); |
3157 | d951f6ff | balrog | |
3158 | d951f6ff | balrog | s->base = base; |
3159 | d951f6ff | balrog | s->txirq = irq[0];
|
3160 | d951f6ff | balrog | s->rxirq = irq[1];
|
3161 | d951f6ff | balrog | s->txdrq = dma; |
3162 | d951f6ff | balrog | omap_uwire_reset(s); |
3163 | d951f6ff | balrog | |
3164 | d951f6ff | balrog | iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
|
3165 | d951f6ff | balrog | omap_uwire_writefn, s); |
3166 | d951f6ff | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3167 | d951f6ff | balrog | |
3168 | d951f6ff | balrog | return s;
|
3169 | d951f6ff | balrog | } |
3170 | d951f6ff | balrog | |
3171 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
3172 | d951f6ff | balrog | struct uwire_slave_s *slave, int chipselect) |
3173 | d951f6ff | balrog | { |
3174 | 827df9f3 | balrog | if (chipselect < 0 || chipselect > 3) { |
3175 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
3176 | 827df9f3 | balrog | exit(-1);
|
3177 | 827df9f3 | balrog | } |
3178 | d951f6ff | balrog | |
3179 | d951f6ff | balrog | s->chip[chipselect] = slave; |
3180 | d951f6ff | balrog | } |
3181 | d951f6ff | balrog | |
3182 | 66450b15 | balrog | /* Pseudonoise Pulse-Width Light Modulator */
|
3183 | 9596ebb7 | pbrook | static void omap_pwl_update(struct omap_mpu_state_s *s) |
3184 | 66450b15 | balrog | { |
3185 | 66450b15 | balrog | int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
3186 | 66450b15 | balrog | |
3187 | 66450b15 | balrog | if (output != s->pwl.output) {
|
3188 | 66450b15 | balrog | s->pwl.output = output; |
3189 | 66450b15 | balrog | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
3190 | 66450b15 | balrog | } |
3191 | 66450b15 | balrog | } |
3192 | 66450b15 | balrog | |
3193 | 66450b15 | balrog | static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
3194 | 66450b15 | balrog | { |
3195 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3196 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3197 | 66450b15 | balrog | |
3198 | 66450b15 | balrog | switch (offset) {
|
3199 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
3200 | 66450b15 | balrog | return s->pwl.level;
|
3201 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
3202 | 66450b15 | balrog | return s->pwl.enable;
|
3203 | 66450b15 | balrog | } |
3204 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
3205 | 66450b15 | balrog | return 0; |
3206 | 66450b15 | balrog | } |
3207 | 66450b15 | balrog | |
3208 | 66450b15 | balrog | static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
3209 | 66450b15 | balrog | uint32_t value) |
3210 | 66450b15 | balrog | { |
3211 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3212 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3213 | 66450b15 | balrog | |
3214 | 66450b15 | balrog | switch (offset) {
|
3215 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
3216 | 66450b15 | balrog | s->pwl.level = value; |
3217 | 66450b15 | balrog | omap_pwl_update(s); |
3218 | 66450b15 | balrog | break;
|
3219 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
3220 | 66450b15 | balrog | s->pwl.enable = value & 1;
|
3221 | 66450b15 | balrog | omap_pwl_update(s); |
3222 | 66450b15 | balrog | break;
|
3223 | 66450b15 | balrog | default:
|
3224 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
3225 | 66450b15 | balrog | return;
|
3226 | 66450b15 | balrog | } |
3227 | 66450b15 | balrog | } |
3228 | 66450b15 | balrog | |
3229 | 66450b15 | balrog | static CPUReadMemoryFunc *omap_pwl_readfn[] = {
|
3230 | 02645926 | balrog | omap_pwl_read, |
3231 | 66450b15 | balrog | omap_badwidth_read8, |
3232 | 66450b15 | balrog | omap_badwidth_read8, |
3233 | 66450b15 | balrog | }; |
3234 | 66450b15 | balrog | |
3235 | 66450b15 | balrog | static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
|
3236 | 02645926 | balrog | omap_pwl_write, |
3237 | 66450b15 | balrog | omap_badwidth_write8, |
3238 | 66450b15 | balrog | omap_badwidth_write8, |
3239 | 66450b15 | balrog | }; |
3240 | 66450b15 | balrog | |
3241 | 9596ebb7 | pbrook | static void omap_pwl_reset(struct omap_mpu_state_s *s) |
3242 | 66450b15 | balrog | { |
3243 | 66450b15 | balrog | s->pwl.output = 0;
|
3244 | 66450b15 | balrog | s->pwl.level = 0;
|
3245 | 66450b15 | balrog | s->pwl.enable = 0;
|
3246 | 66450b15 | balrog | s->pwl.clk = 1;
|
3247 | 66450b15 | balrog | omap_pwl_update(s); |
3248 | 66450b15 | balrog | } |
3249 | 66450b15 | balrog | |
3250 | 66450b15 | balrog | static void omap_pwl_clk_update(void *opaque, int line, int on) |
3251 | 66450b15 | balrog | { |
3252 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3253 | 66450b15 | balrog | |
3254 | 66450b15 | balrog | s->pwl.clk = on; |
3255 | 66450b15 | balrog | omap_pwl_update(s); |
3256 | 66450b15 | balrog | } |
3257 | 66450b15 | balrog | |
3258 | 66450b15 | balrog | static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3259 | 66450b15 | balrog | omap_clk clk) |
3260 | 66450b15 | balrog | { |
3261 | 66450b15 | balrog | int iomemtype;
|
3262 | 66450b15 | balrog | |
3263 | 66450b15 | balrog | omap_pwl_reset(s); |
3264 | 66450b15 | balrog | |
3265 | 66450b15 | balrog | iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
|
3266 | 66450b15 | balrog | omap_pwl_writefn, s); |
3267 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3268 | 66450b15 | balrog | |
3269 | 66450b15 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
3270 | 66450b15 | balrog | } |
3271 | 66450b15 | balrog | |
3272 | f34c417b | balrog | /* Pulse-Width Tone module */
|
3273 | f34c417b | balrog | static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
3274 | f34c417b | balrog | { |
3275 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3276 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3277 | f34c417b | balrog | |
3278 | f34c417b | balrog | switch (offset) {
|
3279 | f34c417b | balrog | case 0x00: /* FRC */ |
3280 | f34c417b | balrog | return s->pwt.frc;
|
3281 | f34c417b | balrog | case 0x04: /* VCR */ |
3282 | f34c417b | balrog | return s->pwt.vrc;
|
3283 | f34c417b | balrog | case 0x08: /* GCR */ |
3284 | f34c417b | balrog | return s->pwt.gcr;
|
3285 | f34c417b | balrog | } |
3286 | f34c417b | balrog | OMAP_BAD_REG(addr); |
3287 | f34c417b | balrog | return 0; |
3288 | f34c417b | balrog | } |
3289 | f34c417b | balrog | |
3290 | f34c417b | balrog | static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
3291 | f34c417b | balrog | uint32_t value) |
3292 | f34c417b | balrog | { |
3293 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3294 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3295 | f34c417b | balrog | |
3296 | f34c417b | balrog | switch (offset) {
|
3297 | f34c417b | balrog | case 0x00: /* FRC */ |
3298 | f34c417b | balrog | s->pwt.frc = value & 0x3f;
|
3299 | f34c417b | balrog | break;
|
3300 | f34c417b | balrog | case 0x04: /* VRC */ |
3301 | f34c417b | balrog | if ((value ^ s->pwt.vrc) & 1) { |
3302 | f34c417b | balrog | if (value & 1) |
3303 | f34c417b | balrog | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
3304 | f34c417b | balrog | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
3305 | f34c417b | balrog | ((omap_clk_getrate(s->pwt.clk) >> 3) /
|
3306 | f34c417b | balrog | /* Pre-multiplexer divider */
|
3307 | f34c417b | balrog | ((s->pwt.gcr & 2) ? 1 : 154) / |
3308 | f34c417b | balrog | /* Octave multiplexer */
|
3309 | f34c417b | balrog | (2 << (value & 3)) * |
3310 | f34c417b | balrog | /* 101/107 divider */
|
3311 | f34c417b | balrog | ((value & (1 << 2)) ? 101 : 107) * |
3312 | f34c417b | balrog | /* 49/55 divider */
|
3313 | f34c417b | balrog | ((value & (1 << 3)) ? 49 : 55) * |
3314 | f34c417b | balrog | /* 50/63 divider */
|
3315 | f34c417b | balrog | ((value & (1 << 4)) ? 50 : 63) * |
3316 | f34c417b | balrog | /* 80/127 divider */
|
3317 | f34c417b | balrog | ((value & (1 << 5)) ? 80 : 127) / |
3318 | f34c417b | balrog | (107 * 55 * 63 * 127))); |
3319 | f34c417b | balrog | else
|
3320 | f34c417b | balrog | printf("%s: silence!\n", __FUNCTION__);
|
3321 | f34c417b | balrog | } |
3322 | f34c417b | balrog | s->pwt.vrc = value & 0x7f;
|
3323 | f34c417b | balrog | break;
|
3324 | f34c417b | balrog | case 0x08: /* GCR */ |
3325 | f34c417b | balrog | s->pwt.gcr = value & 3;
|
3326 | f34c417b | balrog | break;
|
3327 | f34c417b | balrog | default:
|
3328 | f34c417b | balrog | OMAP_BAD_REG(addr); |
3329 | f34c417b | balrog | return;
|
3330 | f34c417b | balrog | } |
3331 | f34c417b | balrog | } |
3332 | f34c417b | balrog | |
3333 | f34c417b | balrog | static CPUReadMemoryFunc *omap_pwt_readfn[] = {
|
3334 | 02645926 | balrog | omap_pwt_read, |
3335 | f34c417b | balrog | omap_badwidth_read8, |
3336 | f34c417b | balrog | omap_badwidth_read8, |
3337 | f34c417b | balrog | }; |
3338 | f34c417b | balrog | |
3339 | f34c417b | balrog | static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
|
3340 | 02645926 | balrog | omap_pwt_write, |
3341 | f34c417b | balrog | omap_badwidth_write8, |
3342 | f34c417b | balrog | omap_badwidth_write8, |
3343 | f34c417b | balrog | }; |
3344 | f34c417b | balrog | |
3345 | 9596ebb7 | pbrook | static void omap_pwt_reset(struct omap_mpu_state_s *s) |
3346 | f34c417b | balrog | { |
3347 | f34c417b | balrog | s->pwt.frc = 0;
|
3348 | f34c417b | balrog | s->pwt.vrc = 0;
|
3349 | f34c417b | balrog | s->pwt.gcr = 0;
|
3350 | f34c417b | balrog | } |
3351 | f34c417b | balrog | |
3352 | f34c417b | balrog | static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3353 | f34c417b | balrog | omap_clk clk) |
3354 | f34c417b | balrog | { |
3355 | f34c417b | balrog | int iomemtype;
|
3356 | f34c417b | balrog | |
3357 | f34c417b | balrog | s->pwt.clk = clk; |
3358 | f34c417b | balrog | omap_pwt_reset(s); |
3359 | f34c417b | balrog | |
3360 | f34c417b | balrog | iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
|
3361 | f34c417b | balrog | omap_pwt_writefn, s); |
3362 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3363 | f34c417b | balrog | } |
3364 | f34c417b | balrog | |
3365 | 5c1c390f | balrog | /* Real-time Clock module */
|
3366 | 5c1c390f | balrog | struct omap_rtc_s {
|
3367 | 5c1c390f | balrog | target_phys_addr_t base; |
3368 | 5c1c390f | balrog | qemu_irq irq; |
3369 | 5c1c390f | balrog | qemu_irq alarm; |
3370 | 5c1c390f | balrog | QEMUTimer *clk; |
3371 | 5c1c390f | balrog | |
3372 | 5c1c390f | balrog | uint8_t interrupts; |
3373 | 5c1c390f | balrog | uint8_t status; |
3374 | 5c1c390f | balrog | int16_t comp_reg; |
3375 | 5c1c390f | balrog | int running;
|
3376 | 5c1c390f | balrog | int pm_am;
|
3377 | 5c1c390f | balrog | int auto_comp;
|
3378 | 5c1c390f | balrog | int round;
|
3379 | 5c1c390f | balrog | struct tm alarm_tm;
|
3380 | 5c1c390f | balrog | time_t alarm_ti; |
3381 | 5c1c390f | balrog | |
3382 | 5c1c390f | balrog | struct tm current_tm;
|
3383 | 5c1c390f | balrog | time_t ti; |
3384 | 5c1c390f | balrog | uint64_t tick; |
3385 | 5c1c390f | balrog | }; |
3386 | 5c1c390f | balrog | |
3387 | 5c1c390f | balrog | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
3388 | 5c1c390f | balrog | { |
3389 | 106627d0 | balrog | /* s->alarm is level-triggered */
|
3390 | 5c1c390f | balrog | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
3391 | 5c1c390f | balrog | } |
3392 | 5c1c390f | balrog | |
3393 | 5c1c390f | balrog | static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
3394 | 5c1c390f | balrog | { |
3395 | 5c1c390f | balrog | s->alarm_ti = mktime(&s->alarm_tm); |
3396 | 5c1c390f | balrog | if (s->alarm_ti == -1) |
3397 | 5c1c390f | balrog | printf("%s: conversion failed\n", __FUNCTION__);
|
3398 | 5c1c390f | balrog | } |
3399 | 5c1c390f | balrog | |
3400 | 5c1c390f | balrog | static inline uint8_t omap_rtc_bcd(int num) |
3401 | 5c1c390f | balrog | { |
3402 | 5c1c390f | balrog | return ((num / 10) << 4) | (num % 10); |
3403 | 5c1c390f | balrog | } |
3404 | 5c1c390f | balrog | |
3405 | 5c1c390f | balrog | static inline int omap_rtc_bin(uint8_t num) |
3406 | 5c1c390f | balrog | { |
3407 | 5c1c390f | balrog | return (num & 15) + 10 * (num >> 4); |
3408 | 5c1c390f | balrog | } |
3409 | 5c1c390f | balrog | |
3410 | 5c1c390f | balrog | static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
3411 | 5c1c390f | balrog | { |
3412 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3413 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3414 | 5c1c390f | balrog | uint8_t i; |
3415 | 5c1c390f | balrog | |
3416 | 5c1c390f | balrog | switch (offset) {
|
3417 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3418 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_sec);
|
3419 | 5c1c390f | balrog | |
3420 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3421 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_min);
|
3422 | 5c1c390f | balrog | |
3423 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3424 | 5c1c390f | balrog | if (s->pm_am)
|
3425 | 5c1c390f | balrog | return ((s->current_tm.tm_hour > 11) << 7) | |
3426 | 5c1c390f | balrog | omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
3427 | 5c1c390f | balrog | else
|
3428 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_hour);
|
3429 | 5c1c390f | balrog | |
3430 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3431 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mday);
|
3432 | 5c1c390f | balrog | |
3433 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3434 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_mon + 1); |
3435 | 5c1c390f | balrog | |
3436 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3437 | 5c1c390f | balrog | return omap_rtc_bcd(s->current_tm.tm_year % 100); |
3438 | 5c1c390f | balrog | |
3439 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3440 | 5c1c390f | balrog | return s->current_tm.tm_wday;
|
3441 | 5c1c390f | balrog | |
3442 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3443 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_sec);
|
3444 | 5c1c390f | balrog | |
3445 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3446 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_min);
|
3447 | 5c1c390f | balrog | |
3448 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3449 | 5c1c390f | balrog | if (s->pm_am)
|
3450 | 5c1c390f | balrog | return ((s->alarm_tm.tm_hour > 11) << 7) | |
3451 | 5c1c390f | balrog | omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
3452 | 5c1c390f | balrog | else
|
3453 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_hour);
|
3454 | 5c1c390f | balrog | |
3455 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3456 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mday);
|
3457 | 5c1c390f | balrog | |
3458 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3459 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); |
3460 | 5c1c390f | balrog | |
3461 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3462 | 5c1c390f | balrog | return omap_rtc_bcd(s->alarm_tm.tm_year % 100); |
3463 | 5c1c390f | balrog | |
3464 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3465 | 5c1c390f | balrog | return (s->pm_am << 3) | (s->auto_comp << 2) | |
3466 | 5c1c390f | balrog | (s->round << 1) | s->running;
|
3467 | 5c1c390f | balrog | |
3468 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3469 | 5c1c390f | balrog | i = s->status; |
3470 | 5c1c390f | balrog | s->status &= ~0x3d;
|
3471 | 5c1c390f | balrog | return i;
|
3472 | 5c1c390f | balrog | |
3473 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3474 | 5c1c390f | balrog | return s->interrupts;
|
3475 | 5c1c390f | balrog | |
3476 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3477 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) & 0xff; |
3478 | 5c1c390f | balrog | |
3479 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3480 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) >> 8; |
3481 | 5c1c390f | balrog | } |
3482 | 5c1c390f | balrog | |
3483 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3484 | 5c1c390f | balrog | return 0; |
3485 | 5c1c390f | balrog | } |
3486 | 5c1c390f | balrog | |
3487 | 5c1c390f | balrog | static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
3488 | 5c1c390f | balrog | uint32_t value) |
3489 | 5c1c390f | balrog | { |
3490 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
3491 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3492 | 5c1c390f | balrog | struct tm new_tm;
|
3493 | 5c1c390f | balrog | time_t ti[2];
|
3494 | 5c1c390f | balrog | |
3495 | 5c1c390f | balrog | switch (offset) {
|
3496 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
3497 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3498 | 5c1c390f | balrog | printf("RTC SEC_REG <-- %02x\n", value);
|
3499 | 5c1c390f | balrog | #endif
|
3500 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3501 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value); |
3502 | 5c1c390f | balrog | return;
|
3503 | 5c1c390f | balrog | |
3504 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
3505 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3506 | 5c1c390f | balrog | printf("RTC MIN_REG <-- %02x\n", value);
|
3507 | 5c1c390f | balrog | #endif
|
3508 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_min * 60;
|
3509 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 60;
|
3510 | 5c1c390f | balrog | return;
|
3511 | 5c1c390f | balrog | |
3512 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
3513 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3514 | 5c1c390f | balrog | printf("RTC HRS_REG <-- %02x\n", value);
|
3515 | 5c1c390f | balrog | #endif
|
3516 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_hour * 3600;
|
3517 | 5c1c390f | balrog | if (s->pm_am) {
|
3518 | 5c1c390f | balrog | s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; |
3519 | 5c1c390f | balrog | s->ti += ((value >> 7) & 1) * 43200; |
3520 | 5c1c390f | balrog | } else
|
3521 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value & 0x3f) * 3600; |
3522 | 5c1c390f | balrog | return;
|
3523 | 5c1c390f | balrog | |
3524 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
3525 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3526 | 5c1c390f | balrog | printf("RTC DAY_REG <-- %02x\n", value);
|
3527 | 5c1c390f | balrog | #endif
|
3528 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mday * 86400;
|
3529 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 86400;
|
3530 | 5c1c390f | balrog | return;
|
3531 | 5c1c390f | balrog | |
3532 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
3533 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3534 | 5c1c390f | balrog | printf("RTC MTH_REG <-- %02x\n", value);
|
3535 | 5c1c390f | balrog | #endif
|
3536 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3537 | 5c1c390f | balrog | new_tm.tm_mon = omap_rtc_bin(value); |
3538 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3539 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3540 | 5c1c390f | balrog | |
3541 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3542 | 5c1c390f | balrog | s->ti -= ti[0];
|
3543 | 5c1c390f | balrog | s->ti += ti[1];
|
3544 | 5c1c390f | balrog | } else {
|
3545 | 5c1c390f | balrog | /* A less accurate version */
|
3546 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mon * 2592000;
|
3547 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 2592000;
|
3548 | 5c1c390f | balrog | } |
3549 | 5c1c390f | balrog | return;
|
3550 | 5c1c390f | balrog | |
3551 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
3552 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3553 | 5c1c390f | balrog | printf("RTC YRS_REG <-- %02x\n", value);
|
3554 | 5c1c390f | balrog | #endif
|
3555 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
3556 | 5c1c390f | balrog | new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
|
3557 | 5c1c390f | balrog | ti[0] = mktime(&s->current_tm);
|
3558 | 5c1c390f | balrog | ti[1] = mktime(&new_tm);
|
3559 | 5c1c390f | balrog | |
3560 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
3561 | 5c1c390f | balrog | s->ti -= ti[0];
|
3562 | 5c1c390f | balrog | s->ti += ti[1];
|
3563 | 5c1c390f | balrog | } else {
|
3564 | 5c1c390f | balrog | /* A less accurate version */
|
3565 | 5c1c390f | balrog | s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
3566 | 5c1c390f | balrog | s->ti += omap_rtc_bin(value) * 31536000;
|
3567 | 5c1c390f | balrog | } |
3568 | 5c1c390f | balrog | return;
|
3569 | 5c1c390f | balrog | |
3570 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
3571 | 5c1c390f | balrog | return; /* Ignored */ |
3572 | 5c1c390f | balrog | |
3573 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
3574 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3575 | 5c1c390f | balrog | printf("ALM SEC_REG <-- %02x\n", value);
|
3576 | 5c1c390f | balrog | #endif
|
3577 | 5c1c390f | balrog | s->alarm_tm.tm_sec = omap_rtc_bin(value); |
3578 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3579 | 5c1c390f | balrog | return;
|
3580 | 5c1c390f | balrog | |
3581 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
3582 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3583 | 5c1c390f | balrog | printf("ALM MIN_REG <-- %02x\n", value);
|
3584 | 5c1c390f | balrog | #endif
|
3585 | 5c1c390f | balrog | s->alarm_tm.tm_min = omap_rtc_bin(value); |
3586 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3587 | 5c1c390f | balrog | return;
|
3588 | 5c1c390f | balrog | |
3589 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
3590 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3591 | 5c1c390f | balrog | printf("ALM HRS_REG <-- %02x\n", value);
|
3592 | 5c1c390f | balrog | #endif
|
3593 | 5c1c390f | balrog | if (s->pm_am)
|
3594 | 5c1c390f | balrog | s->alarm_tm.tm_hour = |
3595 | 5c1c390f | balrog | ((omap_rtc_bin(value & 0x3f)) % 12) + |
3596 | 5c1c390f | balrog | ((value >> 7) & 1) * 12; |
3597 | 5c1c390f | balrog | else
|
3598 | 5c1c390f | balrog | s->alarm_tm.tm_hour = omap_rtc_bin(value); |
3599 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3600 | 5c1c390f | balrog | return;
|
3601 | 5c1c390f | balrog | |
3602 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
3603 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3604 | 5c1c390f | balrog | printf("ALM DAY_REG <-- %02x\n", value);
|
3605 | 5c1c390f | balrog | #endif
|
3606 | 5c1c390f | balrog | s->alarm_tm.tm_mday = omap_rtc_bin(value); |
3607 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3608 | 5c1c390f | balrog | return;
|
3609 | 5c1c390f | balrog | |
3610 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
3611 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3612 | 5c1c390f | balrog | printf("ALM MON_REG <-- %02x\n", value);
|
3613 | 5c1c390f | balrog | #endif
|
3614 | 5c1c390f | balrog | s->alarm_tm.tm_mon = omap_rtc_bin(value); |
3615 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3616 | 5c1c390f | balrog | return;
|
3617 | 5c1c390f | balrog | |
3618 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
3619 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3620 | 5c1c390f | balrog | printf("ALM YRS_REG <-- %02x\n", value);
|
3621 | 5c1c390f | balrog | #endif
|
3622 | 5c1c390f | balrog | s->alarm_tm.tm_year = omap_rtc_bin(value); |
3623 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3624 | 5c1c390f | balrog | return;
|
3625 | 5c1c390f | balrog | |
3626 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
3627 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3628 | 5c1c390f | balrog | printf("RTC CONTROL <-- %02x\n", value);
|
3629 | 5c1c390f | balrog | #endif
|
3630 | 5c1c390f | balrog | s->pm_am = (value >> 3) & 1; |
3631 | 5c1c390f | balrog | s->auto_comp = (value >> 2) & 1; |
3632 | 5c1c390f | balrog | s->round = (value >> 1) & 1; |
3633 | 5c1c390f | balrog | s->running = value & 1;
|
3634 | 5c1c390f | balrog | s->status &= 0xfd;
|
3635 | 5c1c390f | balrog | s->status |= s->running << 1;
|
3636 | 5c1c390f | balrog | return;
|
3637 | 5c1c390f | balrog | |
3638 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
3639 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3640 | 5c1c390f | balrog | printf("RTC STATUSL <-- %02x\n", value);
|
3641 | 5c1c390f | balrog | #endif
|
3642 | 5c1c390f | balrog | s->status &= ~((value & 0xc0) ^ 0x80); |
3643 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3644 | 5c1c390f | balrog | return;
|
3645 | 5c1c390f | balrog | |
3646 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
3647 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3648 | 5c1c390f | balrog | printf("RTC INTRS <-- %02x\n", value);
|
3649 | 5c1c390f | balrog | #endif
|
3650 | 5c1c390f | balrog | s->interrupts = value; |
3651 | 5c1c390f | balrog | return;
|
3652 | 5c1c390f | balrog | |
3653 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
3654 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3655 | 5c1c390f | balrog | printf("RTC COMPLSB <-- %02x\n", value);
|
3656 | 5c1c390f | balrog | #endif
|
3657 | 5c1c390f | balrog | s->comp_reg &= 0xff00;
|
3658 | 5c1c390f | balrog | s->comp_reg |= 0x00ff & value;
|
3659 | 5c1c390f | balrog | return;
|
3660 | 5c1c390f | balrog | |
3661 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
3662 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
3663 | 5c1c390f | balrog | printf("RTC COMPMSB <-- %02x\n", value);
|
3664 | 5c1c390f | balrog | #endif
|
3665 | 5c1c390f | balrog | s->comp_reg &= 0x00ff;
|
3666 | 5c1c390f | balrog | s->comp_reg |= 0xff00 & (value << 8); |
3667 | 5c1c390f | balrog | return;
|
3668 | 5c1c390f | balrog | |
3669 | 5c1c390f | balrog | default:
|
3670 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
3671 | 5c1c390f | balrog | return;
|
3672 | 5c1c390f | balrog | } |
3673 | 5c1c390f | balrog | } |
3674 | 5c1c390f | balrog | |
3675 | 5c1c390f | balrog | static CPUReadMemoryFunc *omap_rtc_readfn[] = {
|
3676 | 5c1c390f | balrog | omap_rtc_read, |
3677 | 5c1c390f | balrog | omap_badwidth_read8, |
3678 | 5c1c390f | balrog | omap_badwidth_read8, |
3679 | 5c1c390f | balrog | }; |
3680 | 5c1c390f | balrog | |
3681 | 5c1c390f | balrog | static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
|
3682 | 5c1c390f | balrog | omap_rtc_write, |
3683 | 5c1c390f | balrog | omap_badwidth_write8, |
3684 | 5c1c390f | balrog | omap_badwidth_write8, |
3685 | 5c1c390f | balrog | }; |
3686 | 5c1c390f | balrog | |
3687 | 5c1c390f | balrog | static void omap_rtc_tick(void *opaque) |
3688 | 5c1c390f | balrog | { |
3689 | 5c1c390f | balrog | struct omap_rtc_s *s = opaque;
|
3690 | 5c1c390f | balrog | |
3691 | 5c1c390f | balrog | if (s->round) {
|
3692 | 5c1c390f | balrog | /* Round to nearest full minute. */
|
3693 | 5c1c390f | balrog | if (s->current_tm.tm_sec < 30) |
3694 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
3695 | 5c1c390f | balrog | else
|
3696 | 5c1c390f | balrog | s->ti += 60 - s->current_tm.tm_sec;
|
3697 | 5c1c390f | balrog | |
3698 | 5c1c390f | balrog | s->round = 0;
|
3699 | 5c1c390f | balrog | } |
3700 | 5c1c390f | balrog | |
3701 | f6503059 | balrog | memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
|
3702 | 5c1c390f | balrog | |
3703 | 5c1c390f | balrog | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
3704 | 5c1c390f | balrog | s->status |= 0x40;
|
3705 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
3706 | 5c1c390f | balrog | } |
3707 | 5c1c390f | balrog | |
3708 | 5c1c390f | balrog | if (s->interrupts & 0x04) |
3709 | 5c1c390f | balrog | switch (s->interrupts & 3) { |
3710 | 5c1c390f | balrog | case 0: |
3711 | 5c1c390f | balrog | s->status |= 0x04;
|
3712 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3713 | 5c1c390f | balrog | break;
|
3714 | 5c1c390f | balrog | case 1: |
3715 | 5c1c390f | balrog | if (s->current_tm.tm_sec)
|
3716 | 5c1c390f | balrog | break;
|
3717 | 5c1c390f | balrog | s->status |= 0x08;
|
3718 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3719 | 5c1c390f | balrog | break;
|
3720 | 5c1c390f | balrog | case 2: |
3721 | 5c1c390f | balrog | if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
3722 | 5c1c390f | balrog | break;
|
3723 | 5c1c390f | balrog | s->status |= 0x10;
|
3724 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3725 | 5c1c390f | balrog | break;
|
3726 | 5c1c390f | balrog | case 3: |
3727 | 5c1c390f | balrog | if (s->current_tm.tm_sec ||
|
3728 | 5c1c390f | balrog | s->current_tm.tm_min || s->current_tm.tm_hour) |
3729 | 5c1c390f | balrog | break;
|
3730 | 5c1c390f | balrog | s->status |= 0x20;
|
3731 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
3732 | 5c1c390f | balrog | break;
|
3733 | 5c1c390f | balrog | } |
3734 | 5c1c390f | balrog | |
3735 | 5c1c390f | balrog | /* Move on */
|
3736 | 5c1c390f | balrog | if (s->running)
|
3737 | 5c1c390f | balrog | s->ti ++; |
3738 | 5c1c390f | balrog | s->tick += 1000;
|
3739 | 5c1c390f | balrog | |
3740 | 5c1c390f | balrog | /*
|
3741 | 5c1c390f | balrog | * Every full hour add a rough approximation of the compensation
|
3742 | 5c1c390f | balrog | * register to the 32kHz Timer (which drives the RTC) value.
|
3743 | 5c1c390f | balrog | */
|
3744 | 5c1c390f | balrog | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
3745 | 5c1c390f | balrog | s->tick += s->comp_reg * 1000 / 32768; |
3746 | 5c1c390f | balrog | |
3747 | 5c1c390f | balrog | qemu_mod_timer(s->clk, s->tick); |
3748 | 5c1c390f | balrog | } |
3749 | 5c1c390f | balrog | |
3750 | 9596ebb7 | pbrook | static void omap_rtc_reset(struct omap_rtc_s *s) |
3751 | 5c1c390f | balrog | { |
3752 | f6503059 | balrog | struct tm tm;
|
3753 | f6503059 | balrog | |
3754 | 5c1c390f | balrog | s->interrupts = 0;
|
3755 | 5c1c390f | balrog | s->comp_reg = 0;
|
3756 | 5c1c390f | balrog | s->running = 0;
|
3757 | 5c1c390f | balrog | s->pm_am = 0;
|
3758 | 5c1c390f | balrog | s->auto_comp = 0;
|
3759 | 5c1c390f | balrog | s->round = 0;
|
3760 | 5c1c390f | balrog | s->tick = qemu_get_clock(rt_clock); |
3761 | 5c1c390f | balrog | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
3762 | 5c1c390f | balrog | s->alarm_tm.tm_mday = 0x01;
|
3763 | 5c1c390f | balrog | s->status = 1 << 7; |
3764 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
3765 | f6503059 | balrog | s->ti = mktime(&tm); |
3766 | 5c1c390f | balrog | |
3767 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
3768 | 5c1c390f | balrog | omap_rtc_tick(s); |
3769 | 5c1c390f | balrog | } |
3770 | 5c1c390f | balrog | |
3771 | 5c1c390f | balrog | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
3772 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk) |
3773 | 5c1c390f | balrog | { |
3774 | 5c1c390f | balrog | int iomemtype;
|
3775 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) |
3776 | 5c1c390f | balrog | qemu_mallocz(sizeof(struct omap_rtc_s)); |
3777 | 5c1c390f | balrog | |
3778 | 5c1c390f | balrog | s->base = base; |
3779 | 5c1c390f | balrog | s->irq = irq[0];
|
3780 | 5c1c390f | balrog | s->alarm = irq[1];
|
3781 | 5c1c390f | balrog | s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
3782 | 5c1c390f | balrog | |
3783 | 5c1c390f | balrog | omap_rtc_reset(s); |
3784 | 5c1c390f | balrog | |
3785 | 5c1c390f | balrog | iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
|
3786 | 5c1c390f | balrog | omap_rtc_writefn, s); |
3787 | 5c1c390f | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3788 | 5c1c390f | balrog | |
3789 | 5c1c390f | balrog | return s;
|
3790 | 5c1c390f | balrog | } |
3791 | 5c1c390f | balrog | |
3792 | d8f699cb | balrog | /* Multi-channel Buffered Serial Port interfaces */
|
3793 | d8f699cb | balrog | struct omap_mcbsp_s {
|
3794 | d8f699cb | balrog | target_phys_addr_t base; |
3795 | d8f699cb | balrog | qemu_irq txirq; |
3796 | d8f699cb | balrog | qemu_irq rxirq; |
3797 | d8f699cb | balrog | qemu_irq txdrq; |
3798 | d8f699cb | balrog | qemu_irq rxdrq; |
3799 | d8f699cb | balrog | |
3800 | d8f699cb | balrog | uint16_t spcr[2];
|
3801 | d8f699cb | balrog | uint16_t rcr[2];
|
3802 | d8f699cb | balrog | uint16_t xcr[2];
|
3803 | d8f699cb | balrog | uint16_t srgr[2];
|
3804 | d8f699cb | balrog | uint16_t mcr[2];
|
3805 | d8f699cb | balrog | uint16_t pcr; |
3806 | d8f699cb | balrog | uint16_t rcer[8];
|
3807 | d8f699cb | balrog | uint16_t xcer[8];
|
3808 | d8f699cb | balrog | int tx_rate;
|
3809 | d8f699cb | balrog | int rx_rate;
|
3810 | d8f699cb | balrog | int tx_req;
|
3811 | 73560bc8 | balrog | int rx_req;
|
3812 | d8f699cb | balrog | |
3813 | d8f699cb | balrog | struct i2s_codec_s *codec;
|
3814 | 73560bc8 | balrog | QEMUTimer *source_timer; |
3815 | 73560bc8 | balrog | QEMUTimer *sink_timer; |
3816 | d8f699cb | balrog | }; |
3817 | d8f699cb | balrog | |
3818 | d8f699cb | balrog | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
3819 | d8f699cb | balrog | { |
3820 | d8f699cb | balrog | int irq;
|
3821 | d8f699cb | balrog | |
3822 | d8f699cb | balrog | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
3823 | d8f699cb | balrog | case 0: |
3824 | d8f699cb | balrog | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
3825 | d8f699cb | balrog | break;
|
3826 | d8f699cb | balrog | case 3: |
3827 | d8f699cb | balrog | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
3828 | d8f699cb | balrog | break;
|
3829 | d8f699cb | balrog | default:
|
3830 | d8f699cb | balrog | irq = 0;
|
3831 | d8f699cb | balrog | break;
|
3832 | d8f699cb | balrog | } |
3833 | d8f699cb | balrog | |
3834 | 106627d0 | balrog | if (irq)
|
3835 | 106627d0 | balrog | qemu_irq_pulse(s->rxirq); |
3836 | d8f699cb | balrog | |
3837 | d8f699cb | balrog | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
3838 | d8f699cb | balrog | case 0: |
3839 | d8f699cb | balrog | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
3840 | d8f699cb | balrog | break;
|
3841 | d8f699cb | balrog | case 3: |
3842 | d8f699cb | balrog | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
3843 | d8f699cb | balrog | break;
|
3844 | d8f699cb | balrog | default:
|
3845 | d8f699cb | balrog | irq = 0;
|
3846 | d8f699cb | balrog | break;
|
3847 | d8f699cb | balrog | } |
3848 | d8f699cb | balrog | |
3849 | 106627d0 | balrog | if (irq)
|
3850 | 106627d0 | balrog | qemu_irq_pulse(s->txirq); |
3851 | d8f699cb | balrog | } |
3852 | d8f699cb | balrog | |
3853 | 73560bc8 | balrog | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
3854 | d8f699cb | balrog | { |
3855 | 73560bc8 | balrog | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
3856 | 73560bc8 | balrog | s->spcr[0] |= 1 << 2; /* RFULL */ |
3857 | 73560bc8 | balrog | s->spcr[0] |= 1 << 1; /* RRDY */ |
3858 | 73560bc8 | balrog | qemu_irq_raise(s->rxdrq); |
3859 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3860 | d8f699cb | balrog | } |
3861 | d8f699cb | balrog | |
3862 | 73560bc8 | balrog | static void omap_mcbsp_source_tick(void *opaque) |
3863 | d8f699cb | balrog | { |
3864 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3865 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
3866 | 73560bc8 | balrog | |
3867 | 73560bc8 | balrog | if (!s->rx_rate)
|
3868 | d8f699cb | balrog | return;
|
3869 | 73560bc8 | balrog | if (s->rx_req)
|
3870 | 73560bc8 | balrog | printf("%s: Rx FIFO overrun\n", __FUNCTION__);
|
3871 | d8f699cb | balrog | |
3872 | 73560bc8 | balrog | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
3873 | d8f699cb | balrog | |
3874 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3875 | 73560bc8 | balrog | qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
3876 | d8f699cb | balrog | } |
3877 | d8f699cb | balrog | |
3878 | d8f699cb | balrog | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
3879 | d8f699cb | balrog | { |
3880 | 73560bc8 | balrog | if (!s->codec || !s->codec->rts)
|
3881 | 73560bc8 | balrog | omap_mcbsp_source_tick(s); |
3882 | 73560bc8 | balrog | else if (s->codec->in.len) { |
3883 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3884 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3885 | d8f699cb | balrog | } |
3886 | d8f699cb | balrog | } |
3887 | d8f699cb | balrog | |
3888 | d8f699cb | balrog | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
3889 | d8f699cb | balrog | { |
3890 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3891 | 73560bc8 | balrog | } |
3892 | 73560bc8 | balrog | |
3893 | 73560bc8 | balrog | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) |
3894 | 73560bc8 | balrog | { |
3895 | d8f699cb | balrog | s->spcr[0] &= ~(1 << 1); /* RRDY */ |
3896 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
3897 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
3898 | d8f699cb | balrog | } |
3899 | d8f699cb | balrog | |
3900 | 73560bc8 | balrog | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
3901 | 73560bc8 | balrog | { |
3902 | 73560bc8 | balrog | s->spcr[1] |= 1 << 1; /* XRDY */ |
3903 | 73560bc8 | balrog | qemu_irq_raise(s->txdrq); |
3904 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3905 | 73560bc8 | balrog | } |
3906 | 73560bc8 | balrog | |
3907 | 73560bc8 | balrog | static void omap_mcbsp_sink_tick(void *opaque) |
3908 | d8f699cb | balrog | { |
3909 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3910 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
3911 | 73560bc8 | balrog | |
3912 | 73560bc8 | balrog | if (!s->tx_rate)
|
3913 | d8f699cb | balrog | return;
|
3914 | 73560bc8 | balrog | if (s->tx_req)
|
3915 | 73560bc8 | balrog | printf("%s: Tx FIFO underrun\n", __FUNCTION__);
|
3916 | 73560bc8 | balrog | |
3917 | 73560bc8 | balrog | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
3918 | 73560bc8 | balrog | |
3919 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3920 | 73560bc8 | balrog | qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
3921 | 73560bc8 | balrog | } |
3922 | 73560bc8 | balrog | |
3923 | 73560bc8 | balrog | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
3924 | 73560bc8 | balrog | { |
3925 | 73560bc8 | balrog | if (!s->codec || !s->codec->cts)
|
3926 | 73560bc8 | balrog | omap_mcbsp_sink_tick(s); |
3927 | 73560bc8 | balrog | else if (s->codec->out.size) { |
3928 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3929 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3930 | 73560bc8 | balrog | } |
3931 | 73560bc8 | balrog | } |
3932 | 73560bc8 | balrog | |
3933 | 73560bc8 | balrog | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) |
3934 | 73560bc8 | balrog | { |
3935 | 73560bc8 | balrog | s->spcr[1] &= ~(1 << 1); /* XRDY */ |
3936 | 73560bc8 | balrog | qemu_irq_lower(s->txdrq); |
3937 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
3938 | 73560bc8 | balrog | if (s->codec && s->codec->cts)
|
3939 | 73560bc8 | balrog | s->codec->tx_swallow(s->codec->opaque); |
3940 | d8f699cb | balrog | } |
3941 | d8f699cb | balrog | |
3942 | d8f699cb | balrog | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
3943 | d8f699cb | balrog | { |
3944 | 73560bc8 | balrog | s->tx_req = 0;
|
3945 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3946 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3947 | 73560bc8 | balrog | } |
3948 | 73560bc8 | balrog | |
3949 | 73560bc8 | balrog | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
3950 | 73560bc8 | balrog | { |
3951 | 73560bc8 | balrog | int prev_rx_rate, prev_tx_rate;
|
3952 | 73560bc8 | balrog | int rx_rate = 0, tx_rate = 0; |
3953 | 73560bc8 | balrog | int cpu_rate = 1500000; /* XXX */ |
3954 | 73560bc8 | balrog | |
3955 | 73560bc8 | balrog | /* TODO: check CLKSTP bit */
|
3956 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 6)) { /* GRST */ |
3957 | 73560bc8 | balrog | if (s->spcr[0] & (1 << 0)) { /* RRST */ |
3958 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3959 | 73560bc8 | balrog | (s->pcr & (1 << 8))) { /* CLKRM */ |
3960 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3961 | 73560bc8 | balrog | rx_rate = cpu_rate / |
3962 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3963 | 73560bc8 | balrog | } else
|
3964 | 73560bc8 | balrog | if (s->codec)
|
3965 | 73560bc8 | balrog | rx_rate = s->codec->rx_rate; |
3966 | 73560bc8 | balrog | } |
3967 | 73560bc8 | balrog | |
3968 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 0)) { /* XRST */ |
3969 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3970 | 73560bc8 | balrog | (s->pcr & (1 << 9))) { /* CLKXM */ |
3971 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3972 | 73560bc8 | balrog | tx_rate = cpu_rate / |
3973 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3974 | 73560bc8 | balrog | } else
|
3975 | 73560bc8 | balrog | if (s->codec)
|
3976 | 73560bc8 | balrog | tx_rate = s->codec->tx_rate; |
3977 | 73560bc8 | balrog | } |
3978 | 73560bc8 | balrog | } |
3979 | 73560bc8 | balrog | prev_tx_rate = s->tx_rate; |
3980 | 73560bc8 | balrog | prev_rx_rate = s->rx_rate; |
3981 | 73560bc8 | balrog | s->tx_rate = tx_rate; |
3982 | 73560bc8 | balrog | s->rx_rate = rx_rate; |
3983 | 73560bc8 | balrog | |
3984 | 73560bc8 | balrog | if (s->codec)
|
3985 | 73560bc8 | balrog | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); |
3986 | 73560bc8 | balrog | |
3987 | 73560bc8 | balrog | if (!prev_tx_rate && tx_rate)
|
3988 | 73560bc8 | balrog | omap_mcbsp_tx_start(s); |
3989 | 73560bc8 | balrog | else if (s->tx_rate && !tx_rate) |
3990 | 73560bc8 | balrog | omap_mcbsp_tx_stop(s); |
3991 | 73560bc8 | balrog | |
3992 | 73560bc8 | balrog | if (!prev_rx_rate && rx_rate)
|
3993 | 73560bc8 | balrog | omap_mcbsp_rx_start(s); |
3994 | 73560bc8 | balrog | else if (prev_tx_rate && !tx_rate) |
3995 | 73560bc8 | balrog | omap_mcbsp_rx_stop(s); |
3996 | d8f699cb | balrog | } |
3997 | d8f699cb | balrog | |
3998 | d8f699cb | balrog | static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) |
3999 | d8f699cb | balrog | { |
4000 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4001 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4002 | d8f699cb | balrog | uint16_t ret; |
4003 | d8f699cb | balrog | |
4004 | d8f699cb | balrog | switch (offset) {
|
4005 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
4006 | d8f699cb | balrog | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
4007 | d8f699cb | balrog | return 0x0000; |
4008 | d8f699cb | balrog | /* Fall through. */
|
4009 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
4010 | 73560bc8 | balrog | if (s->rx_req < 2) { |
4011 | d8f699cb | balrog | printf("%s: Rx FIFO underrun\n", __FUNCTION__);
|
4012 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
4013 | d8f699cb | balrog | } else {
|
4014 | 73560bc8 | balrog | s->tx_req -= 2;
|
4015 | 73560bc8 | balrog | if (s->codec && s->codec->in.len >= 2) { |
4016 | 73560bc8 | balrog | ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
|
4017 | 73560bc8 | balrog | ret |= s->codec->in.fifo[s->codec->in.start ++]; |
4018 | 73560bc8 | balrog | s->codec->in.len -= 2;
|
4019 | 73560bc8 | balrog | } else
|
4020 | 73560bc8 | balrog | ret = 0x0000;
|
4021 | 73560bc8 | balrog | if (!s->tx_req)
|
4022 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
4023 | d8f699cb | balrog | return ret;
|
4024 | d8f699cb | balrog | } |
4025 | d8f699cb | balrog | return 0x0000; |
4026 | d8f699cb | balrog | |
4027 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
4028 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
4029 | d8f699cb | balrog | return 0x0000; |
4030 | d8f699cb | balrog | |
4031 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
4032 | d8f699cb | balrog | return s->spcr[1]; |
4033 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
4034 | d8f699cb | balrog | return s->spcr[0]; |
4035 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
4036 | d8f699cb | balrog | return s->rcr[1]; |
4037 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
4038 | d8f699cb | balrog | return s->rcr[0]; |
4039 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
4040 | d8f699cb | balrog | return s->xcr[1]; |
4041 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
4042 | d8f699cb | balrog | return s->xcr[0]; |
4043 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
4044 | d8f699cb | balrog | return s->srgr[1]; |
4045 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
4046 | d8f699cb | balrog | return s->srgr[0]; |
4047 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
4048 | d8f699cb | balrog | return s->mcr[1]; |
4049 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
4050 | d8f699cb | balrog | return s->mcr[0]; |
4051 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
4052 | d8f699cb | balrog | return s->rcer[0]; |
4053 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
4054 | d8f699cb | balrog | return s->rcer[1]; |
4055 | d8f699cb | balrog | case 0x20: /* XCERA */ |
4056 | d8f699cb | balrog | return s->xcer[0]; |
4057 | d8f699cb | balrog | case 0x22: /* XCERB */ |
4058 | d8f699cb | balrog | return s->xcer[1]; |
4059 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
4060 | d8f699cb | balrog | return s->pcr;
|
4061 | d8f699cb | balrog | case 0x26: /* RCERC */ |
4062 | d8f699cb | balrog | return s->rcer[2]; |
4063 | d8f699cb | balrog | case 0x28: /* RCERD */ |
4064 | d8f699cb | balrog | return s->rcer[3]; |
4065 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
4066 | d8f699cb | balrog | return s->xcer[2]; |
4067 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
4068 | d8f699cb | balrog | return s->xcer[3]; |
4069 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
4070 | d8f699cb | balrog | return s->rcer[4]; |
4071 | d8f699cb | balrog | case 0x30: /* RCERF */ |
4072 | d8f699cb | balrog | return s->rcer[5]; |
4073 | d8f699cb | balrog | case 0x32: /* XCERE */ |
4074 | d8f699cb | balrog | return s->xcer[4]; |
4075 | d8f699cb | balrog | case 0x34: /* XCERF */ |
4076 | d8f699cb | balrog | return s->xcer[5]; |
4077 | d8f699cb | balrog | case 0x36: /* RCERG */ |
4078 | d8f699cb | balrog | return s->rcer[6]; |
4079 | d8f699cb | balrog | case 0x38: /* RCERH */ |
4080 | d8f699cb | balrog | return s->rcer[7]; |
4081 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
4082 | d8f699cb | balrog | return s->xcer[6]; |
4083 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
4084 | d8f699cb | balrog | return s->xcer[7]; |
4085 | d8f699cb | balrog | } |
4086 | d8f699cb | balrog | |
4087 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
4088 | d8f699cb | balrog | return 0; |
4089 | d8f699cb | balrog | } |
4090 | d8f699cb | balrog | |
4091 | 73560bc8 | balrog | static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, |
4092 | d8f699cb | balrog | uint32_t value) |
4093 | d8f699cb | balrog | { |
4094 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4095 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4096 | d8f699cb | balrog | |
4097 | d8f699cb | balrog | switch (offset) {
|
4098 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
4099 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
4100 | d8f699cb | balrog | OMAP_RO_REG(addr); |
4101 | d8f699cb | balrog | return;
|
4102 | d8f699cb | balrog | |
4103 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
4104 | d8f699cb | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
4105 | d8f699cb | balrog | return;
|
4106 | d8f699cb | balrog | /* Fall through. */
|
4107 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
4108 | 73560bc8 | balrog | if (s->tx_req > 1) { |
4109 | 73560bc8 | balrog | s->tx_req -= 2;
|
4110 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
4111 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
4112 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
4113 | d8f699cb | balrog | } |
4114 | 73560bc8 | balrog | if (s->tx_req < 2) |
4115 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
4116 | d8f699cb | balrog | } else
|
4117 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
4118 | d8f699cb | balrog | return;
|
4119 | d8f699cb | balrog | |
4120 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
4121 | d8f699cb | balrog | s->spcr[1] &= 0x0002; |
4122 | d8f699cb | balrog | s->spcr[1] |= 0x03f9 & value; |
4123 | d8f699cb | balrog | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
4124 | 73560bc8 | balrog | if (~value & 1) /* XRST */ |
4125 | d8f699cb | balrog | s->spcr[1] &= ~6; |
4126 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4127 | d8f699cb | balrog | return;
|
4128 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
4129 | d8f699cb | balrog | s->spcr[0] &= 0x0006; |
4130 | d8f699cb | balrog | s->spcr[0] |= 0xf8f9 & value; |
4131 | d8f699cb | balrog | if (value & (1 << 15)) /* DLB */ |
4132 | d8f699cb | balrog | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
|
4133 | d8f699cb | balrog | if (~value & 1) { /* RRST */ |
4134 | d8f699cb | balrog | s->spcr[0] &= ~6; |
4135 | 73560bc8 | balrog | s->rx_req = 0;
|
4136 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
4137 | d8f699cb | balrog | } |
4138 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
4139 | d8f699cb | balrog | return;
|
4140 | d8f699cb | balrog | |
4141 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
4142 | d8f699cb | balrog | s->rcr[1] = value & 0xffff; |
4143 | d8f699cb | balrog | return;
|
4144 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
4145 | d8f699cb | balrog | s->rcr[0] = value & 0x7fe0; |
4146 | d8f699cb | balrog | return;
|
4147 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
4148 | d8f699cb | balrog | s->xcr[1] = value & 0xffff; |
4149 | d8f699cb | balrog | return;
|
4150 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
4151 | d8f699cb | balrog | s->xcr[0] = value & 0x7fe0; |
4152 | d8f699cb | balrog | return;
|
4153 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
4154 | d8f699cb | balrog | s->srgr[1] = value & 0xffff; |
4155 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
4156 | d8f699cb | balrog | return;
|
4157 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
4158 | d8f699cb | balrog | s->srgr[0] = value & 0xffff; |
4159 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
4160 | d8f699cb | balrog | return;
|
4161 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
4162 | d8f699cb | balrog | s->mcr[1] = value & 0x03e3; |
4163 | d8f699cb | balrog | if (value & 3) /* XMCM */ |
4164 | d8f699cb | balrog | printf("%s: Tx channel selection mode enable attempt\n",
|
4165 | d8f699cb | balrog | __FUNCTION__); |
4166 | d8f699cb | balrog | return;
|
4167 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
4168 | d8f699cb | balrog | s->mcr[0] = value & 0x03e1; |
4169 | d8f699cb | balrog | if (value & 1) /* RMCM */ |
4170 | d8f699cb | balrog | printf("%s: Rx channel selection mode enable attempt\n",
|
4171 | d8f699cb | balrog | __FUNCTION__); |
4172 | d8f699cb | balrog | return;
|
4173 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
4174 | d8f699cb | balrog | s->rcer[0] = value & 0xffff; |
4175 | d8f699cb | balrog | return;
|
4176 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
4177 | d8f699cb | balrog | s->rcer[1] = value & 0xffff; |
4178 | d8f699cb | balrog | return;
|
4179 | d8f699cb | balrog | case 0x20: /* XCERA */ |
4180 | d8f699cb | balrog | s->xcer[0] = value & 0xffff; |
4181 | d8f699cb | balrog | return;
|
4182 | d8f699cb | balrog | case 0x22: /* XCERB */ |
4183 | d8f699cb | balrog | s->xcer[1] = value & 0xffff; |
4184 | d8f699cb | balrog | return;
|
4185 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
4186 | d8f699cb | balrog | s->pcr = value & 0x7faf;
|
4187 | d8f699cb | balrog | return;
|
4188 | d8f699cb | balrog | case 0x26: /* RCERC */ |
4189 | d8f699cb | balrog | s->rcer[2] = value & 0xffff; |
4190 | d8f699cb | balrog | return;
|
4191 | d8f699cb | balrog | case 0x28: /* RCERD */ |
4192 | d8f699cb | balrog | s->rcer[3] = value & 0xffff; |
4193 | d8f699cb | balrog | return;
|
4194 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
4195 | d8f699cb | balrog | s->xcer[2] = value & 0xffff; |
4196 | d8f699cb | balrog | return;
|
4197 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
4198 | d8f699cb | balrog | s->xcer[3] = value & 0xffff; |
4199 | d8f699cb | balrog | return;
|
4200 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
4201 | d8f699cb | balrog | s->rcer[4] = value & 0xffff; |
4202 | d8f699cb | balrog | return;
|
4203 | d8f699cb | balrog | case 0x30: /* RCERF */ |
4204 | d8f699cb | balrog | s->rcer[5] = value & 0xffff; |
4205 | d8f699cb | balrog | return;
|
4206 | d8f699cb | balrog | case 0x32: /* XCERE */ |
4207 | d8f699cb | balrog | s->xcer[4] = value & 0xffff; |
4208 | d8f699cb | balrog | return;
|
4209 | d8f699cb | balrog | case 0x34: /* XCERF */ |
4210 | d8f699cb | balrog | s->xcer[5] = value & 0xffff; |
4211 | d8f699cb | balrog | return;
|
4212 | d8f699cb | balrog | case 0x36: /* RCERG */ |
4213 | d8f699cb | balrog | s->rcer[6] = value & 0xffff; |
4214 | d8f699cb | balrog | return;
|
4215 | d8f699cb | balrog | case 0x38: /* RCERH */ |
4216 | d8f699cb | balrog | s->rcer[7] = value & 0xffff; |
4217 | d8f699cb | balrog | return;
|
4218 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
4219 | d8f699cb | balrog | s->xcer[6] = value & 0xffff; |
4220 | d8f699cb | balrog | return;
|
4221 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
4222 | d8f699cb | balrog | s->xcer[7] = value & 0xffff; |
4223 | d8f699cb | balrog | return;
|
4224 | d8f699cb | balrog | } |
4225 | d8f699cb | balrog | |
4226 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
4227 | d8f699cb | balrog | } |
4228 | d8f699cb | balrog | |
4229 | 73560bc8 | balrog | static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, |
4230 | 73560bc8 | balrog | uint32_t value) |
4231 | 73560bc8 | balrog | { |
4232 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4233 | 73560bc8 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4234 | 73560bc8 | balrog | |
4235 | 73560bc8 | balrog | if (offset == 0x04) { /* DXR */ |
4236 | 73560bc8 | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
4237 | 73560bc8 | balrog | return;
|
4238 | 73560bc8 | balrog | if (s->tx_req > 3) { |
4239 | 73560bc8 | balrog | s->tx_req -= 4;
|
4240 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
4241 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
4242 | 73560bc8 | balrog | (value >> 24) & 0xff; |
4243 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
4244 | 73560bc8 | balrog | (value >> 16) & 0xff; |
4245 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
4246 | 73560bc8 | balrog | (value >> 8) & 0xff; |
4247 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
4248 | 73560bc8 | balrog | (value >> 0) & 0xff; |
4249 | 73560bc8 | balrog | } |
4250 | 73560bc8 | balrog | if (s->tx_req < 4) |
4251 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
4252 | 73560bc8 | balrog | } else
|
4253 | 73560bc8 | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
4254 | 73560bc8 | balrog | return;
|
4255 | 73560bc8 | balrog | } |
4256 | 73560bc8 | balrog | |
4257 | 73560bc8 | balrog | omap_badwidth_write16(opaque, addr, value); |
4258 | 73560bc8 | balrog | } |
4259 | 73560bc8 | balrog | |
4260 | d8f699cb | balrog | static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
|
4261 | d8f699cb | balrog | omap_badwidth_read16, |
4262 | d8f699cb | balrog | omap_mcbsp_read, |
4263 | d8f699cb | balrog | omap_badwidth_read16, |
4264 | d8f699cb | balrog | }; |
4265 | d8f699cb | balrog | |
4266 | d8f699cb | balrog | static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
|
4267 | d8f699cb | balrog | omap_badwidth_write16, |
4268 | 73560bc8 | balrog | omap_mcbsp_writeh, |
4269 | 73560bc8 | balrog | omap_mcbsp_writew, |
4270 | d8f699cb | balrog | }; |
4271 | d8f699cb | balrog | |
4272 | d8f699cb | balrog | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
4273 | d8f699cb | balrog | { |
4274 | d8f699cb | balrog | memset(&s->spcr, 0, sizeof(s->spcr)); |
4275 | d8f699cb | balrog | memset(&s->rcr, 0, sizeof(s->rcr)); |
4276 | d8f699cb | balrog | memset(&s->xcr, 0, sizeof(s->xcr)); |
4277 | d8f699cb | balrog | s->srgr[0] = 0x0001; |
4278 | d8f699cb | balrog | s->srgr[1] = 0x2000; |
4279 | d8f699cb | balrog | memset(&s->mcr, 0, sizeof(s->mcr)); |
4280 | d8f699cb | balrog | memset(&s->pcr, 0, sizeof(s->pcr)); |
4281 | d8f699cb | balrog | memset(&s->rcer, 0, sizeof(s->rcer)); |
4282 | d8f699cb | balrog | memset(&s->xcer, 0, sizeof(s->xcer)); |
4283 | d8f699cb | balrog | s->tx_req = 0;
|
4284 | 73560bc8 | balrog | s->rx_req = 0;
|
4285 | d8f699cb | balrog | s->tx_rate = 0;
|
4286 | d8f699cb | balrog | s->rx_rate = 0;
|
4287 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
4288 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
4289 | d8f699cb | balrog | } |
4290 | d8f699cb | balrog | |
4291 | d8f699cb | balrog | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
4292 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk) |
4293 | d8f699cb | balrog | { |
4294 | d8f699cb | balrog | int iomemtype;
|
4295 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
4296 | d8f699cb | balrog | qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
4297 | d8f699cb | balrog | |
4298 | d8f699cb | balrog | s->base = base; |
4299 | d8f699cb | balrog | s->txirq = irq[0];
|
4300 | d8f699cb | balrog | s->rxirq = irq[1];
|
4301 | d8f699cb | balrog | s->txdrq = dma[0];
|
4302 | d8f699cb | balrog | s->rxdrq = dma[1];
|
4303 | 73560bc8 | balrog | s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); |
4304 | 73560bc8 | balrog | s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); |
4305 | d8f699cb | balrog | omap_mcbsp_reset(s); |
4306 | d8f699cb | balrog | |
4307 | d8f699cb | balrog | iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
|
4308 | d8f699cb | balrog | omap_mcbsp_writefn, s); |
4309 | d8f699cb | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4310 | d8f699cb | balrog | |
4311 | d8f699cb | balrog | return s;
|
4312 | d8f699cb | balrog | } |
4313 | d8f699cb | balrog | |
4314 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
4315 | d8f699cb | balrog | { |
4316 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4317 | d8f699cb | balrog | |
4318 | 73560bc8 | balrog | if (s->rx_rate) {
|
4319 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
4320 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
4321 | 73560bc8 | balrog | } |
4322 | d8f699cb | balrog | } |
4323 | d8f699cb | balrog | |
4324 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
4325 | d8f699cb | balrog | { |
4326 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
4327 | d8f699cb | balrog | |
4328 | 73560bc8 | balrog | if (s->tx_rate) {
|
4329 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
4330 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
4331 | 73560bc8 | balrog | } |
4332 | d8f699cb | balrog | } |
4333 | d8f699cb | balrog | |
4334 | d8f699cb | balrog | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) |
4335 | d8f699cb | balrog | { |
4336 | d8f699cb | balrog | s->codec = slave; |
4337 | d8f699cb | balrog | slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
4338 | d8f699cb | balrog | slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
4339 | d8f699cb | balrog | } |
4340 | d8f699cb | balrog | |
4341 | f9d43072 | balrog | /* LED Pulse Generators */
|
4342 | f9d43072 | balrog | struct omap_lpg_s {
|
4343 | f9d43072 | balrog | target_phys_addr_t base; |
4344 | f9d43072 | balrog | QEMUTimer *tm; |
4345 | f9d43072 | balrog | |
4346 | f9d43072 | balrog | uint8_t control; |
4347 | f9d43072 | balrog | uint8_t power; |
4348 | f9d43072 | balrog | int64_t on; |
4349 | f9d43072 | balrog | int64_t period; |
4350 | f9d43072 | balrog | int clk;
|
4351 | f9d43072 | balrog | int cycle;
|
4352 | f9d43072 | balrog | }; |
4353 | f9d43072 | balrog | |
4354 | f9d43072 | balrog | static void omap_lpg_tick(void *opaque) |
4355 | f9d43072 | balrog | { |
4356 | f9d43072 | balrog | struct omap_lpg_s *s = opaque;
|
4357 | f9d43072 | balrog | |
4358 | f9d43072 | balrog | if (s->cycle)
|
4359 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); |
4360 | f9d43072 | balrog | else
|
4361 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); |
4362 | f9d43072 | balrog | |
4363 | f9d43072 | balrog | s->cycle = !s->cycle; |
4364 | f9d43072 | balrog | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); |
4365 | f9d43072 | balrog | } |
4366 | f9d43072 | balrog | |
4367 | f9d43072 | balrog | static void omap_lpg_update(struct omap_lpg_s *s) |
4368 | f9d43072 | balrog | { |
4369 | f9d43072 | balrog | int64_t on, period = 1, ticks = 1000; |
4370 | f9d43072 | balrog | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; |
4371 | f9d43072 | balrog | |
4372 | f9d43072 | balrog | if (~s->control & (1 << 6)) /* LPGRES */ |
4373 | f9d43072 | balrog | on = 0;
|
4374 | f9d43072 | balrog | else if (s->control & (1 << 7)) /* PERM_ON */ |
4375 | f9d43072 | balrog | on = period; |
4376 | f9d43072 | balrog | else {
|
4377 | f9d43072 | balrog | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ |
4378 | f9d43072 | balrog | 256 / 32); |
4379 | f9d43072 | balrog | on = (s->clk && s->power) ? muldiv64(ticks, |
4380 | f9d43072 | balrog | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ |
4381 | f9d43072 | balrog | } |
4382 | f9d43072 | balrog | |
4383 | f9d43072 | balrog | qemu_del_timer(s->tm); |
4384 | f9d43072 | balrog | if (on == period && s->on < s->period)
|
4385 | f9d43072 | balrog | printf("%s: LED is on\n", __FUNCTION__);
|
4386 | f9d43072 | balrog | else if (on == 0 && s->on) |
4387 | f9d43072 | balrog | printf("%s: LED is off\n", __FUNCTION__);
|
4388 | f9d43072 | balrog | else if (on && (on != s->on || period != s->period)) { |
4389 | f9d43072 | balrog | s->cycle = 0;
|
4390 | f9d43072 | balrog | s->on = on; |
4391 | f9d43072 | balrog | s->period = period; |
4392 | f9d43072 | balrog | omap_lpg_tick(s); |
4393 | f9d43072 | balrog | return;
|
4394 | f9d43072 | balrog | } |
4395 | f9d43072 | balrog | |
4396 | f9d43072 | balrog | s->on = on; |
4397 | f9d43072 | balrog | s->period = period; |
4398 | f9d43072 | balrog | } |
4399 | f9d43072 | balrog | |
4400 | f9d43072 | balrog | static void omap_lpg_reset(struct omap_lpg_s *s) |
4401 | f9d43072 | balrog | { |
4402 | f9d43072 | balrog | s->control = 0x00;
|
4403 | f9d43072 | balrog | s->power = 0x00;
|
4404 | f9d43072 | balrog | s->clk = 1;
|
4405 | f9d43072 | balrog | omap_lpg_update(s); |
4406 | f9d43072 | balrog | } |
4407 | f9d43072 | balrog | |
4408 | f9d43072 | balrog | static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) |
4409 | f9d43072 | balrog | { |
4410 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4411 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4412 | f9d43072 | balrog | |
4413 | f9d43072 | balrog | switch (offset) {
|
4414 | f9d43072 | balrog | case 0x00: /* LCR */ |
4415 | f9d43072 | balrog | return s->control;
|
4416 | f9d43072 | balrog | |
4417 | f9d43072 | balrog | case 0x04: /* PMR */ |
4418 | f9d43072 | balrog | return s->power;
|
4419 | f9d43072 | balrog | } |
4420 | f9d43072 | balrog | |
4421 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4422 | f9d43072 | balrog | return 0; |
4423 | f9d43072 | balrog | } |
4424 | f9d43072 | balrog | |
4425 | f9d43072 | balrog | static void omap_lpg_write(void *opaque, target_phys_addr_t addr, |
4426 | f9d43072 | balrog | uint32_t value) |
4427 | f9d43072 | balrog | { |
4428 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4429 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
4430 | f9d43072 | balrog | |
4431 | f9d43072 | balrog | switch (offset) {
|
4432 | f9d43072 | balrog | case 0x00: /* LCR */ |
4433 | f9d43072 | balrog | if (~value & (1 << 6)) /* LPGRES */ |
4434 | f9d43072 | balrog | omap_lpg_reset(s); |
4435 | f9d43072 | balrog | s->control = value & 0xff;
|
4436 | f9d43072 | balrog | omap_lpg_update(s); |
4437 | f9d43072 | balrog | return;
|
4438 | f9d43072 | balrog | |
4439 | f9d43072 | balrog | case 0x04: /* PMR */ |
4440 | f9d43072 | balrog | s->power = value & 0x01;
|
4441 | f9d43072 | balrog | omap_lpg_update(s); |
4442 | f9d43072 | balrog | return;
|
4443 | f9d43072 | balrog | |
4444 | f9d43072 | balrog | default:
|
4445 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4446 | f9d43072 | balrog | return;
|
4447 | f9d43072 | balrog | } |
4448 | f9d43072 | balrog | } |
4449 | f9d43072 | balrog | |
4450 | f9d43072 | balrog | static CPUReadMemoryFunc *omap_lpg_readfn[] = {
|
4451 | f9d43072 | balrog | omap_lpg_read, |
4452 | f9d43072 | balrog | omap_badwidth_read8, |
4453 | f9d43072 | balrog | omap_badwidth_read8, |
4454 | f9d43072 | balrog | }; |
4455 | f9d43072 | balrog | |
4456 | f9d43072 | balrog | static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
|
4457 | f9d43072 | balrog | omap_lpg_write, |
4458 | f9d43072 | balrog | omap_badwidth_write8, |
4459 | f9d43072 | balrog | omap_badwidth_write8, |
4460 | f9d43072 | balrog | }; |
4461 | f9d43072 | balrog | |
4462 | f9d43072 | balrog | static void omap_lpg_clk_update(void *opaque, int line, int on) |
4463 | f9d43072 | balrog | { |
4464 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
4465 | f9d43072 | balrog | |
4466 | f9d43072 | balrog | s->clk = on; |
4467 | f9d43072 | balrog | omap_lpg_update(s); |
4468 | f9d43072 | balrog | } |
4469 | f9d43072 | balrog | |
4470 | f9d43072 | balrog | struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
|
4471 | f9d43072 | balrog | { |
4472 | f9d43072 | balrog | int iomemtype;
|
4473 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) |
4474 | f9d43072 | balrog | qemu_mallocz(sizeof(struct omap_lpg_s)); |
4475 | f9d43072 | balrog | |
4476 | f9d43072 | balrog | s->base = base; |
4477 | f9d43072 | balrog | s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); |
4478 | f9d43072 | balrog | |
4479 | f9d43072 | balrog | omap_lpg_reset(s); |
4480 | f9d43072 | balrog | |
4481 | f9d43072 | balrog | iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
|
4482 | f9d43072 | balrog | omap_lpg_writefn, s); |
4483 | f9d43072 | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4484 | f9d43072 | balrog | |
4485 | f9d43072 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
4486 | f9d43072 | balrog | |
4487 | f9d43072 | balrog | return s;
|
4488 | f9d43072 | balrog | } |
4489 | f9d43072 | balrog | |
4490 | f9d43072 | balrog | /* MPUI Peripheral Bridge configuration */
|
4491 | f9d43072 | balrog | static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) |
4492 | f9d43072 | balrog | { |
4493 | f9d43072 | balrog | if (addr == OMAP_MPUI_BASE) /* CMR */ |
4494 | f9d43072 | balrog | return 0xfe4d; |
4495 | f9d43072 | balrog | |
4496 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
4497 | f9d43072 | balrog | return 0; |
4498 | f9d43072 | balrog | } |
4499 | f9d43072 | balrog | |
4500 | f9d43072 | balrog | static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
|
4501 | f9d43072 | balrog | omap_badwidth_read16, |
4502 | f9d43072 | balrog | omap_mpui_io_read, |
4503 | f9d43072 | balrog | omap_badwidth_read16, |
4504 | f9d43072 | balrog | }; |
4505 | f9d43072 | balrog | |
4506 | f9d43072 | balrog | static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
|
4507 | f9d43072 | balrog | omap_badwidth_write16, |
4508 | f9d43072 | balrog | omap_badwidth_write16, |
4509 | f9d43072 | balrog | omap_badwidth_write16, |
4510 | f9d43072 | balrog | }; |
4511 | f9d43072 | balrog | |
4512 | f9d43072 | balrog | static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) |
4513 | f9d43072 | balrog | { |
4514 | f9d43072 | balrog | int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn, |
4515 | f9d43072 | balrog | omap_mpui_io_writefn, mpu); |
4516 | f9d43072 | balrog | cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
|
4517 | f9d43072 | balrog | } |
4518 | f9d43072 | balrog | |
4519 | c3d2689d | balrog | /* General chip reset */
|
4520 | 827df9f3 | balrog | static void omap1_mpu_reset(void *opaque) |
4521 | c3d2689d | balrog | { |
4522 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4523 | c3d2689d | balrog | |
4524 | c3d2689d | balrog | omap_inth_reset(mpu->ih[0]);
|
4525 | c3d2689d | balrog | omap_inth_reset(mpu->ih[1]);
|
4526 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
4527 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
4528 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
4529 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
4530 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
4531 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
4532 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
4533 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
4534 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
4535 | c3d2689d | balrog | omap_mpui_reset(mpu); |
4536 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
4537 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
4538 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[0]);
|
4539 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[1]);
|
4540 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[2]);
|
4541 | d951f6ff | balrog | omap_uart_reset(mpu->uart[0]);
|
4542 | d951f6ff | balrog | omap_uart_reset(mpu->uart[1]);
|
4543 | d951f6ff | balrog | omap_uart_reset(mpu->uart[2]);
|
4544 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
4545 | fe71e81a | balrog | omap_mpuio_reset(mpu->mpuio); |
4546 | 64330148 | balrog | omap_gpio_reset(mpu->gpio); |
4547 | d951f6ff | balrog | omap_uwire_reset(mpu->microwire); |
4548 | 66450b15 | balrog | omap_pwl_reset(mpu); |
4549 | 4a2c8ac2 | balrog | omap_pwt_reset(mpu); |
4550 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[0]);
|
4551 | 5c1c390f | balrog | omap_rtc_reset(mpu->rtc); |
4552 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp1); |
4553 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp2); |
4554 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp3); |
4555 | f9d43072 | balrog | omap_lpg_reset(mpu->led[0]);
|
4556 | f9d43072 | balrog | omap_lpg_reset(mpu->led[1]);
|
4557 | 8ef6367e | balrog | omap_clkm_reset(mpu); |
4558 | c3d2689d | balrog | cpu_reset(mpu->env); |
4559 | c3d2689d | balrog | } |
4560 | c3d2689d | balrog | |
4561 | cf965d24 | balrog | static const struct omap_map_s { |
4562 | cf965d24 | balrog | target_phys_addr_t phys_dsp; |
4563 | cf965d24 | balrog | target_phys_addr_t phys_mpu; |
4564 | cf965d24 | balrog | uint32_t size; |
4565 | cf965d24 | balrog | const char *name; |
4566 | cf965d24 | balrog | } omap15xx_dsp_mm[] = { |
4567 | cf965d24 | balrog | /* Strobe 0 */
|
4568 | cf965d24 | balrog | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
4569 | cf965d24 | balrog | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
4570 | cf965d24 | balrog | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
4571 | cf965d24 | balrog | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
4572 | cf965d24 | balrog | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
4573 | cf965d24 | balrog | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
4574 | cf965d24 | balrog | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
4575 | cf965d24 | balrog | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
4576 | cf965d24 | balrog | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
4577 | cf965d24 | balrog | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
4578 | cf965d24 | balrog | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
4579 | cf965d24 | balrog | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
4580 | cf965d24 | balrog | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
4581 | cf965d24 | balrog | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
4582 | cf965d24 | balrog | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
4583 | cf965d24 | balrog | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
4584 | cf965d24 | balrog | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
4585 | cf965d24 | balrog | /* Strobe 1 */
|
4586 | cf965d24 | balrog | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
4587 | cf965d24 | balrog | |
4588 | cf965d24 | balrog | { 0 }
|
4589 | cf965d24 | balrog | }; |
4590 | cf965d24 | balrog | |
4591 | cf965d24 | balrog | static void omap_setup_dsp_mapping(const struct omap_map_s *map) |
4592 | cf965d24 | balrog | { |
4593 | cf965d24 | balrog | int io;
|
4594 | cf965d24 | balrog | |
4595 | cf965d24 | balrog | for (; map->phys_dsp; map ++) {
|
4596 | cf965d24 | balrog | io = cpu_get_physical_page_desc(map->phys_mpu); |
4597 | cf965d24 | balrog | |
4598 | cf965d24 | balrog | cpu_register_physical_memory(map->phys_dsp, map->size, io); |
4599 | cf965d24 | balrog | } |
4600 | cf965d24 | balrog | } |
4601 | cf965d24 | balrog | |
4602 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req) |
4603 | c3d2689d | balrog | { |
4604 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4605 | c3d2689d | balrog | |
4606 | fe71e81a | balrog | if (mpu->env->halted)
|
4607 | fe71e81a | balrog | cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
4608 | c3d2689d | balrog | } |
4609 | c3d2689d | balrog | |
4610 | 827df9f3 | balrog | static const struct dma_irq_map omap1_dma_irq_map[] = { |
4611 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH0_6 },
|
4612 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH1_7 },
|
4613 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH2_8 },
|
4614 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH3 },
|
4615 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH4 },
|
4616 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH5 },
|
4617 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH6 },
|
4618 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH7 },
|
4619 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH8 },
|
4620 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH9 },
|
4621 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH10 },
|
4622 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH11 },
|
4623 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH12 },
|
4624 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH13 },
|
4625 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH14 },
|
4626 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH15 }
|
4627 | 089b7c0a | balrog | }; |
4628 | 089b7c0a | balrog | |
4629 | b4e3104b | balrog | /* DMA ports for OMAP1 */
|
4630 | b4e3104b | balrog | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
4631 | b4e3104b | balrog | target_phys_addr_t addr) |
4632 | b4e3104b | balrog | { |
4633 | b4e3104b | balrog | return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
4634 | b4e3104b | balrog | } |
4635 | b4e3104b | balrog | |
4636 | b4e3104b | balrog | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
4637 | b4e3104b | balrog | target_phys_addr_t addr) |
4638 | b4e3104b | balrog | { |
4639 | b4e3104b | balrog | return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
4640 | b4e3104b | balrog | } |
4641 | b4e3104b | balrog | |
4642 | b4e3104b | balrog | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
4643 | b4e3104b | balrog | target_phys_addr_t addr) |
4644 | b4e3104b | balrog | { |
4645 | b4e3104b | balrog | return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
4646 | b4e3104b | balrog | } |
4647 | b4e3104b | balrog | |
4648 | b4e3104b | balrog | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
4649 | b4e3104b | balrog | target_phys_addr_t addr) |
4650 | b4e3104b | balrog | { |
4651 | b4e3104b | balrog | return addr >= 0xfffb0000 && addr < 0xffff0000; |
4652 | b4e3104b | balrog | } |
4653 | b4e3104b | balrog | |
4654 | b4e3104b | balrog | static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
4655 | b4e3104b | balrog | target_phys_addr_t addr) |
4656 | b4e3104b | balrog | { |
4657 | b4e3104b | balrog | return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
4658 | b4e3104b | balrog | } |
4659 | b4e3104b | balrog | |
4660 | b4e3104b | balrog | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
4661 | b4e3104b | balrog | target_phys_addr_t addr) |
4662 | b4e3104b | balrog | { |
4663 | b4e3104b | balrog | return addr >= 0xe1010000 && addr < 0xe1020004; |
4664 | b4e3104b | balrog | } |
4665 | b4e3104b | balrog | |
4666 | c3d2689d | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
4667 | c3d2689d | balrog | DisplayState *ds, const char *core) |
4668 | c3d2689d | balrog | { |
4669 | 089b7c0a | balrog | int i;
|
4670 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
4671 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
4672 | c3d2689d | balrog | ram_addr_t imif_base, emiff_base; |
4673 | 106627d0 | balrog | qemu_irq *cpu_irq; |
4674 | 089b7c0a | balrog | qemu_irq dma_irqs[6];
|
4675 | 9d413d1d | balrog | int sdindex;
|
4676 | 106627d0 | balrog | |
4677 | aaed909a | bellard | if (!core)
|
4678 | aaed909a | bellard | core = "ti925t";
|
4679 | c3d2689d | balrog | |
4680 | c3d2689d | balrog | /* Core */
|
4681 | c3d2689d | balrog | s->mpu_model = omap310; |
4682 | aaed909a | bellard | s->env = cpu_init(core); |
4683 | aaed909a | bellard | if (!s->env) {
|
4684 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
4685 | aaed909a | bellard | exit(1);
|
4686 | aaed909a | bellard | } |
4687 | c3d2689d | balrog | s->sdram_size = sdram_size; |
4688 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
4689 | c3d2689d | balrog | |
4690 | fe71e81a | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
4691 | fe71e81a | balrog | |
4692 | c3d2689d | balrog | /* Clocks */
|
4693 | c3d2689d | balrog | omap_clk_init(s); |
4694 | c3d2689d | balrog | |
4695 | c3d2689d | balrog | /* Memory-mapped stuff */
|
4696 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
4697 | c3d2689d | balrog | (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
4698 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
4699 | c3d2689d | balrog | (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
4700 | c3d2689d | balrog | |
4701 | c3d2689d | balrog | omap_clkm_init(0xfffece00, 0xe1008000, s); |
4702 | c3d2689d | balrog | |
4703 | 106627d0 | balrog | cpu_irq = arm_pic_init_cpu(s->env); |
4704 | 827df9f3 | balrog | s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0], |
4705 | 106627d0 | balrog | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
4706 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4707 | 827df9f3 | balrog | s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1], |
4708 | 106627d0 | balrog | s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL, |
4709 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
4710 | c3d2689d | balrog | |
4711 | 089b7c0a | balrog | for (i = 0; i < 6; i ++) |
4712 | 827df9f3 | balrog | dma_irqs[i] = |
4713 | 827df9f3 | balrog | s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr]; |
4714 | 089b7c0a | balrog | s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD], |
4715 | 089b7c0a | balrog | s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
|
4716 | 089b7c0a | balrog | |
4717 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
4718 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
4719 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
4720 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
4721 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
4722 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
4723 | c3d2689d | balrog | |
4724 | afbb5194 | balrog | /* Register SDRAM and SRAM DMA ports for fast transfers. */
|
4725 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, |
4726 | afbb5194 | balrog | emiff_base, OMAP_EMIFF_BASE, s->sdram_size); |
4727 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, |
4728 | afbb5194 | balrog | imif_base, OMAP_IMIF_BASE, s->sram_size); |
4729 | afbb5194 | balrog | |
4730 | c3d2689d | balrog | s->timer[0] = omap_mpu_timer_init(0xfffec500, |
4731 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER1],
|
4732 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4733 | c3d2689d | balrog | s->timer[1] = omap_mpu_timer_init(0xfffec600, |
4734 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER2],
|
4735 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4736 | c3d2689d | balrog | s->timer[2] = omap_mpu_timer_init(0xfffec700, |
4737 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER3],
|
4738 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
4739 | c3d2689d | balrog | |
4740 | c3d2689d | balrog | s->wdt = omap_wd_timer_init(0xfffec800,
|
4741 | c3d2689d | balrog | s->irq[0][OMAP_INT_WD_TIMER],
|
4742 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
4743 | c3d2689d | balrog | |
4744 | c3d2689d | balrog | s->os_timer = omap_os_timer_init(0xfffb9000,
|
4745 | c3d2689d | balrog | s->irq[1][OMAP_INT_OS_TIMER],
|
4746 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
4747 | c3d2689d | balrog | |
4748 | c3d2689d | balrog | s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
4749 | b4e3104b | balrog | omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base, |
4750 | c3d2689d | balrog | omap_findclk(s, "lcd_ck"));
|
4751 | c3d2689d | balrog | |
4752 | c3d2689d | balrog | omap_ulpd_pm_init(0xfffe0800, s);
|
4753 | c3d2689d | balrog | omap_pin_cfg_init(0xfffe1000, s);
|
4754 | c3d2689d | balrog | omap_id_init(s); |
4755 | c3d2689d | balrog | |
4756 | c3d2689d | balrog | omap_mpui_init(0xfffec900, s);
|
4757 | c3d2689d | balrog | |
4758 | c3d2689d | balrog | s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
4759 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
4760 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4761 | c3d2689d | balrog | s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
4762 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PUB],
|
4763 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
4764 | c3d2689d | balrog | |
4765 | c3d2689d | balrog | omap_tcmi_init(0xfffecc00, s);
|
4766 | c3d2689d | balrog | |
4767 | d951f6ff | balrog | s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
4768 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
4769 | 827df9f3 | balrog | omap_findclk(s, "uart1_ck"),
|
4770 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], |
4771 | c3d2689d | balrog | serial_hds[0]);
|
4772 | d951f6ff | balrog | s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
4773 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
4774 | 827df9f3 | balrog | omap_findclk(s, "uart2_ck"),
|
4775 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
4776 | c3d2689d | balrog | serial_hds[0] ? serial_hds[1] : 0); |
4777 | d951f6ff | balrog | s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
4778 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
4779 | 827df9f3 | balrog | omap_findclk(s, "uart3_ck"),
|
4780 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
4781 | c3d2689d | balrog | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
4782 | c3d2689d | balrog | |
4783 | c3d2689d | balrog | omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
4784 | c3d2689d | balrog | omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
4785 | c3d2689d | balrog | omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
4786 | c3d2689d | balrog | |
4787 | 9d413d1d | balrog | sdindex = drive_get_index(IF_SD, 0, 0); |
4788 | 9d413d1d | balrog | if (sdindex == -1) { |
4789 | e4bcb14c | ths | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
4790 | e4bcb14c | ths | exit(1);
|
4791 | e4bcb14c | ths | } |
4792 | 9d413d1d | balrog | s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
|
4793 | 9d413d1d | balrog | s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
|
4794 | 9d413d1d | balrog | omap_findclk(s, "mmc_ck"));
|
4795 | b30bb3a2 | balrog | |
4796 | fe71e81a | balrog | s->mpuio = omap_mpuio_init(0xfffb5000,
|
4797 | fe71e81a | balrog | s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
4798 | fe71e81a | balrog | s->wakeup, omap_findclk(s, "clk32-kHz"));
|
4799 | fe71e81a | balrog | |
4800 | 3efda49d | balrog | s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
4801 | 66450b15 | balrog | omap_findclk(s, "arm_gpio_ck"));
|
4802 | 64330148 | balrog | |
4803 | d951f6ff | balrog | s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
4804 | d951f6ff | balrog | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
4805 | d951f6ff | balrog | |
4806 | d8f699cb | balrog | omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); |
4807 | d8f699cb | balrog | omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); |
4808 | 66450b15 | balrog | |
4809 | 827df9f3 | balrog | s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
4810 | 4a2c8ac2 | balrog | &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
|
4811 | 4a2c8ac2 | balrog | |
4812 | 5c1c390f | balrog | s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
4813 | 5c1c390f | balrog | omap_findclk(s, "clk32-kHz"));
|
4814 | 02645926 | balrog | |
4815 | d8f699cb | balrog | s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], |
4816 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
|
4817 | d8f699cb | balrog | s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], |
4818 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
|
4819 | d8f699cb | balrog | s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], |
4820 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
|
4821 | d8f699cb | balrog | |
4822 | f9d43072 | balrog | s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz")); |
4823 | f9d43072 | balrog | s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz")); |
4824 | f9d43072 | balrog | |
4825 | 02645926 | balrog | /* Register mappings not currenlty implemented:
|
4826 | 02645926 | balrog | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
|
4827 | 02645926 | balrog | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
|
4828 | 02645926 | balrog | * USB W2FC fffb4000 - fffb47ff
|
4829 | 02645926 | balrog | * Camera Interface fffb6800 - fffb6fff
|
4830 | 02645926 | balrog | * USB Host fffba000 - fffba7ff
|
4831 | 02645926 | balrog | * FAC fffba800 - fffbafff
|
4832 | 02645926 | balrog | * HDQ/1-Wire fffbc000 - fffbc7ff
|
4833 | b854bc19 | balrog | * TIPB switches fffbc800 - fffbcfff
|
4834 | 02645926 | balrog | * Mailbox fffcf000 - fffcf7ff
|
4835 | 02645926 | balrog | * Local bus IF fffec100 - fffec1ff
|
4836 | 02645926 | balrog | * Local bus MMU fffec200 - fffec2ff
|
4837 | 02645926 | balrog | * DSP MMU fffed200 - fffed2ff
|
4838 | 02645926 | balrog | */
|
4839 | 02645926 | balrog | |
4840 | cf965d24 | balrog | omap_setup_dsp_mapping(omap15xx_dsp_mm); |
4841 | f9d43072 | balrog | omap_setup_mpui_io(s); |
4842 | cf965d24 | balrog | |
4843 | 827df9f3 | balrog | qemu_register_reset(omap1_mpu_reset, s); |
4844 | c3d2689d | balrog | |
4845 | c3d2689d | balrog | return s;
|
4846 | c3d2689d | balrog | } |