| 197 |
197 |
.access = PL0_W, .type = ARM_CP_NOP },
|
| 198 |
198 |
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
|
| 199 |
199 |
.access = PL0_W, .type = ARM_CP_NOP },
|
|
200 |
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
|
|
201 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
|
|
202 |
.resetvalue = 0, },
|
|
203 |
/* Watchpoint Fault Address Register : should actually only be present
|
|
204 |
* for 1136, 1176, 11MPCore.
|
|
205 |
*/
|
|
206 |
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
|
|
207 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
|
| 200 |
208 |
REGINFO_SENTINEL
|
| 201 |
209 |
};
|
| 202 |
210 |
|
| ... | ... | |
| 540 |
548 |
return 0;
|
| 541 |
549 |
}
|
| 542 |
550 |
|
|
551 |
static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
552 |
uint64_t *value)
|
|
553 |
{
|
|
554 |
if (ri->crm > 8) {
|
|
555 |
return EXCP_UDEF;
|
|
556 |
}
|
|
557 |
*value = env->cp15.c6_region[ri->crm];
|
|
558 |
return 0;
|
|
559 |
}
|
|
560 |
|
|
561 |
static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
562 |
uint64_t value)
|
|
563 |
{
|
|
564 |
if (ri->crm > 8) {
|
|
565 |
return EXCP_UDEF;
|
|
566 |
}
|
|
567 |
env->cp15.c6_region[ri->crm] = value;
|
|
568 |
return 0;
|
|
569 |
}
|
|
570 |
|
| 543 |
571 |
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
|
| 544 |
572 |
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 545 |
573 |
.access = PL1_RW,
|
| ... | ... | |
| 561 |
589 |
{ .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 562 |
590 |
.access = PL1_RW,
|
| 563 |
591 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
|
|
592 |
/* Protection region base and size registers */
|
|
593 |
{ .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
|
|
594 |
.opc2 = CP_ANY, .access = PL1_RW,
|
|
595 |
.readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
|
| 564 |
596 |
REGINFO_SENTINEL
|
| 565 |
597 |
};
|
| 566 |
598 |
|
| ... | ... | |
| 598 |
630 |
.access = PL1_RW, .writefn = vmsa_ttbcr_write,
|
| 599 |
631 |
.resetfn = vmsa_ttbcr_reset,
|
| 600 |
632 |
.fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
|
|
633 |
{ .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
|
|
634 |
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
|
|
635 |
.resetvalue = 0, },
|
| 601 |
636 |
REGINFO_SENTINEL
|
| 602 |
637 |
};
|
| 603 |
638 |
|
| ... | ... | |
| 1927 |
1962 |
break;
|
| 1928 |
1963 |
case 4: /* Reserved. */
|
| 1929 |
1964 |
goto bad_reg;
|
| 1930 |
|
case 6: /* MMU Fault address / MPU base/size. */
|
| 1931 |
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
| 1932 |
|
if (crm >= 8)
|
| 1933 |
|
goto bad_reg;
|
| 1934 |
|
env->cp15.c6_region[crm] = val;
|
| 1935 |
|
} else {
|
| 1936 |
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
| 1937 |
|
op2 = 0;
|
| 1938 |
|
switch (op2) {
|
| 1939 |
|
case 0:
|
| 1940 |
|
env->cp15.c6_data = val;
|
| 1941 |
|
break;
|
| 1942 |
|
case 1: /* ??? This is WFAR on armv6 */
|
| 1943 |
|
case 2:
|
| 1944 |
|
env->cp15.c6_insn = val;
|
| 1945 |
|
break;
|
| 1946 |
|
default:
|
| 1947 |
|
goto bad_reg;
|
| 1948 |
|
}
|
| 1949 |
|
}
|
| 1950 |
|
break;
|
| 1951 |
1965 |
case 9:
|
| 1952 |
1966 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
| 1953 |
1967 |
break;
|
| ... | ... | |
| 2121 |
2135 |
}
|
| 2122 |
2136 |
case 4: /* Reserved. */
|
| 2123 |
2137 |
goto bad_reg;
|
| 2124 |
|
case 6: /* MMU Fault address. */
|
| 2125 |
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
| 2126 |
|
if (crm >= 8)
|
| 2127 |
|
goto bad_reg;
|
| 2128 |
|
return env->cp15.c6_region[crm];
|
| 2129 |
|
} else {
|
| 2130 |
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
| 2131 |
|
op2 = 0;
|
| 2132 |
|
switch (op2) {
|
| 2133 |
|
case 0:
|
| 2134 |
|
return env->cp15.c6_data;
|
| 2135 |
|
case 1:
|
| 2136 |
|
if (arm_feature(env, ARM_FEATURE_V6)) {
|
| 2137 |
|
/* Watchpoint Fault Adrress. */
|
| 2138 |
|
return 0; /* Not implemented. */
|
| 2139 |
|
} else {
|
| 2140 |
|
/* Instruction Fault Adrress. */
|
| 2141 |
|
/* Arm9 doesn't have an IFAR, but implementing it anyway
|
| 2142 |
|
shouldn't do any harm. */
|
| 2143 |
|
return env->cp15.c6_insn;
|
| 2144 |
|
}
|
| 2145 |
|
case 2:
|
| 2146 |
|
if (arm_feature(env, ARM_FEATURE_V6)) {
|
| 2147 |
|
/* Instruction Fault Adrress. */
|
| 2148 |
|
return env->cp15.c6_insn;
|
| 2149 |
|
} else {
|
| 2150 |
|
goto bad_reg;
|
| 2151 |
|
}
|
| 2152 |
|
default:
|
| 2153 |
|
goto bad_reg;
|
| 2154 |
|
}
|
| 2155 |
|
}
|
| 2156 |
2138 |
case 9:
|
| 2157 |
2139 |
switch (crm) {
|
| 2158 |
2140 |
case 0: /* Cache lockdown */
|