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1 | ad96090a | Blue Swirl | /*
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2 | ad96090a | Blue Swirl | * QEMU System Emulator
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3 | ad96090a | Blue Swirl | *
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4 | ad96090a | Blue Swirl | * Copyright (c) 2003-2008 Fabrice Bellard
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5 | ad96090a | Blue Swirl | *
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6 | ad96090a | Blue Swirl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | ad96090a | Blue Swirl | * of this software and associated documentation files (the "Software"), to deal
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8 | ad96090a | Blue Swirl | * in the Software without restriction, including without limitation the rights
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9 | ad96090a | Blue Swirl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | ad96090a | Blue Swirl | * copies of the Software, and to permit persons to whom the Software is
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11 | ad96090a | Blue Swirl | * furnished to do so, subject to the following conditions:
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12 | ad96090a | Blue Swirl | *
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13 | ad96090a | Blue Swirl | * The above copyright notice and this permission notice shall be included in
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14 | ad96090a | Blue Swirl | * all copies or substantial portions of the Software.
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15 | ad96090a | Blue Swirl | *
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16 | ad96090a | Blue Swirl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | ad96090a | Blue Swirl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | ad96090a | Blue Swirl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | ad96090a | Blue Swirl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | ad96090a | Blue Swirl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | ad96090a | Blue Swirl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | ad96090a | Blue Swirl | * THE SOFTWARE.
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23 | ad96090a | Blue Swirl | */
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24 | ad96090a | Blue Swirl | #include <stdint.h> |
25 | ad96090a | Blue Swirl | #include <stdarg.h> |
26 | b2e0a138 | Michael S. Tsirkin | #include <stdlib.h> |
27 | ad96090a | Blue Swirl | #ifndef _WIN32
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28 | 1c47cb16 | Blue Swirl | #include <sys/types.h> |
29 | ad96090a | Blue Swirl | #include <sys/mman.h> |
30 | ad96090a | Blue Swirl | #endif
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31 | ad96090a | Blue Swirl | #include "config.h" |
32 | ad96090a | Blue Swirl | #include "monitor.h" |
33 | ad96090a | Blue Swirl | #include "sysemu.h" |
34 | ad96090a | Blue Swirl | #include "arch_init.h" |
35 | ad96090a | Blue Swirl | #include "audio/audio.h" |
36 | ad96090a | Blue Swirl | #include "hw/pc.h" |
37 | ad96090a | Blue Swirl | #include "hw/pci.h" |
38 | ad96090a | Blue Swirl | #include "hw/audiodev.h" |
39 | ad96090a | Blue Swirl | #include "kvm.h" |
40 | ad96090a | Blue Swirl | #include "migration.h" |
41 | ad96090a | Blue Swirl | #include "net.h" |
42 | ad96090a | Blue Swirl | #include "gdbstub.h" |
43 | ad96090a | Blue Swirl | #include "hw/smbios.h" |
44 | ad96090a | Blue Swirl | |
45 | ad96090a | Blue Swirl | #ifdef TARGET_SPARC
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46 | ad96090a | Blue Swirl | int graphic_width = 1024; |
47 | ad96090a | Blue Swirl | int graphic_height = 768; |
48 | ad96090a | Blue Swirl | int graphic_depth = 8; |
49 | ad96090a | Blue Swirl | #else
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50 | ad96090a | Blue Swirl | int graphic_width = 800; |
51 | ad96090a | Blue Swirl | int graphic_height = 600; |
52 | ad96090a | Blue Swirl | int graphic_depth = 15; |
53 | ad96090a | Blue Swirl | #endif
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54 | ad96090a | Blue Swirl | |
55 | ad96090a | Blue Swirl | const char arch_config_name[] = CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf"; |
56 | ad96090a | Blue Swirl | |
57 | ad96090a | Blue Swirl | #if defined(TARGET_ALPHA)
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58 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_ALPHA
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59 | ad96090a | Blue Swirl | #elif defined(TARGET_ARM)
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60 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_ARM
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61 | ad96090a | Blue Swirl | #elif defined(TARGET_CRIS)
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62 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_CRIS
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63 | ad96090a | Blue Swirl | #elif defined(TARGET_I386)
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64 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_I386
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65 | ad96090a | Blue Swirl | #elif defined(TARGET_M68K)
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66 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_M68K
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67 | 81ea0e13 | Michael Walle | #elif defined(TARGET_LM32)
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68 | 81ea0e13 | Michael Walle | #define QEMU_ARCH QEMU_ARCH_LM32
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69 | ad96090a | Blue Swirl | #elif defined(TARGET_MICROBLAZE)
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70 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_MICROBLAZE
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71 | ad96090a | Blue Swirl | #elif defined(TARGET_MIPS)
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72 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_MIPS
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73 | ad96090a | Blue Swirl | #elif defined(TARGET_PPC)
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74 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_PPC
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75 | ad96090a | Blue Swirl | #elif defined(TARGET_S390X)
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76 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_S390X
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77 | ad96090a | Blue Swirl | #elif defined(TARGET_SH4)
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78 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_SH4
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79 | ad96090a | Blue Swirl | #elif defined(TARGET_SPARC)
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80 | ad96090a | Blue Swirl | #define QEMU_ARCH QEMU_ARCH_SPARC
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81 | ad96090a | Blue Swirl | #endif
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82 | ad96090a | Blue Swirl | |
83 | ad96090a | Blue Swirl | const uint32_t arch_type = QEMU_ARCH;
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84 | ad96090a | Blue Swirl | |
85 | ad96090a | Blue Swirl | /***********************************************************/
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86 | ad96090a | Blue Swirl | /* ram save/restore */
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87 | ad96090a | Blue Swirl | |
88 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_FULL 0x01 /* Obsolete, not used anymore */ |
89 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_COMPRESS 0x02 |
90 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_MEM_SIZE 0x04 |
91 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_PAGE 0x08 |
92 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_EOS 0x10 |
93 | d20878d2 | Yoshiaki Tamura | #define RAM_SAVE_FLAG_CONTINUE 0x20 |
94 | ad96090a | Blue Swirl | |
95 | ad96090a | Blue Swirl | static int is_dup_page(uint8_t *page, uint8_t ch) |
96 | ad96090a | Blue Swirl | { |
97 | ad96090a | Blue Swirl | uint32_t val = ch << 24 | ch << 16 | ch << 8 | ch; |
98 | ad96090a | Blue Swirl | uint32_t *array = (uint32_t *)page; |
99 | ad96090a | Blue Swirl | int i;
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100 | ad96090a | Blue Swirl | |
101 | ad96090a | Blue Swirl | for (i = 0; i < (TARGET_PAGE_SIZE / 4); i++) { |
102 | ad96090a | Blue Swirl | if (array[i] != val) {
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103 | ad96090a | Blue Swirl | return 0; |
104 | ad96090a | Blue Swirl | } |
105 | ad96090a | Blue Swirl | } |
106 | ad96090a | Blue Swirl | |
107 | ad96090a | Blue Swirl | return 1; |
108 | ad96090a | Blue Swirl | } |
109 | ad96090a | Blue Swirl | |
110 | 760e77ea | Alex Williamson | static RAMBlock *last_block;
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111 | 760e77ea | Alex Williamson | static ram_addr_t last_offset;
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112 | 760e77ea | Alex Williamson | |
113 | ad96090a | Blue Swirl | static int ram_save_block(QEMUFile *f) |
114 | ad96090a | Blue Swirl | { |
115 | e44359c3 | Alex Williamson | RAMBlock *block = last_block; |
116 | e44359c3 | Alex Williamson | ram_addr_t offset = last_offset; |
117 | e44359c3 | Alex Williamson | ram_addr_t current_addr; |
118 | 3fc250b4 | Pierre Riteau | int bytes_sent = 0; |
119 | ad96090a | Blue Swirl | |
120 | e44359c3 | Alex Williamson | if (!block)
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121 | e44359c3 | Alex Williamson | block = QLIST_FIRST(&ram_list.blocks); |
122 | e44359c3 | Alex Williamson | |
123 | e44359c3 | Alex Williamson | current_addr = block->offset + offset; |
124 | e44359c3 | Alex Williamson | |
125 | e44359c3 | Alex Williamson | do {
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126 | ad96090a | Blue Swirl | if (cpu_physical_memory_get_dirty(current_addr, MIGRATION_DIRTY_FLAG)) {
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127 | ad96090a | Blue Swirl | uint8_t *p; |
128 | a55bbe31 | Alex Williamson | int cont = (block == last_block) ? RAM_SAVE_FLAG_CONTINUE : 0; |
129 | ad96090a | Blue Swirl | |
130 | ad96090a | Blue Swirl | cpu_physical_memory_reset_dirty(current_addr, |
131 | ad96090a | Blue Swirl | current_addr + TARGET_PAGE_SIZE, |
132 | ad96090a | Blue Swirl | MIGRATION_DIRTY_FLAG); |
133 | ad96090a | Blue Swirl | |
134 | 97ab12d4 | Alex Williamson | p = block->host + offset; |
135 | ad96090a | Blue Swirl | |
136 | ad96090a | Blue Swirl | if (is_dup_page(p, *p)) {
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137 | a55bbe31 | Alex Williamson | qemu_put_be64(f, offset | cont | RAM_SAVE_FLAG_COMPRESS); |
138 | a55bbe31 | Alex Williamson | if (!cont) {
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139 | a55bbe31 | Alex Williamson | qemu_put_byte(f, strlen(block->idstr)); |
140 | a55bbe31 | Alex Williamson | qemu_put_buffer(f, (uint8_t *)block->idstr, |
141 | a55bbe31 | Alex Williamson | strlen(block->idstr)); |
142 | a55bbe31 | Alex Williamson | } |
143 | ad96090a | Blue Swirl | qemu_put_byte(f, *p); |
144 | 3fc250b4 | Pierre Riteau | bytes_sent = 1;
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145 | ad96090a | Blue Swirl | } else {
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146 | a55bbe31 | Alex Williamson | qemu_put_be64(f, offset | cont | RAM_SAVE_FLAG_PAGE); |
147 | a55bbe31 | Alex Williamson | if (!cont) {
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148 | a55bbe31 | Alex Williamson | qemu_put_byte(f, strlen(block->idstr)); |
149 | a55bbe31 | Alex Williamson | qemu_put_buffer(f, (uint8_t *)block->idstr, |
150 | a55bbe31 | Alex Williamson | strlen(block->idstr)); |
151 | a55bbe31 | Alex Williamson | } |
152 | ad96090a | Blue Swirl | qemu_put_buffer(f, p, TARGET_PAGE_SIZE); |
153 | 3fc250b4 | Pierre Riteau | bytes_sent = TARGET_PAGE_SIZE; |
154 | ad96090a | Blue Swirl | } |
155 | ad96090a | Blue Swirl | |
156 | ad96090a | Blue Swirl | break;
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157 | ad96090a | Blue Swirl | } |
158 | e44359c3 | Alex Williamson | |
159 | e44359c3 | Alex Williamson | offset += TARGET_PAGE_SIZE; |
160 | e44359c3 | Alex Williamson | if (offset >= block->length) {
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161 | e44359c3 | Alex Williamson | offset = 0;
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162 | e44359c3 | Alex Williamson | block = QLIST_NEXT(block, next); |
163 | e44359c3 | Alex Williamson | if (!block)
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164 | e44359c3 | Alex Williamson | block = QLIST_FIRST(&ram_list.blocks); |
165 | e44359c3 | Alex Williamson | } |
166 | e44359c3 | Alex Williamson | |
167 | e44359c3 | Alex Williamson | current_addr = block->offset + offset; |
168 | e44359c3 | Alex Williamson | |
169 | e44359c3 | Alex Williamson | } while (current_addr != last_block->offset + last_offset);
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170 | e44359c3 | Alex Williamson | |
171 | e44359c3 | Alex Williamson | last_block = block; |
172 | e44359c3 | Alex Williamson | last_offset = offset; |
173 | ad96090a | Blue Swirl | |
174 | 3fc250b4 | Pierre Riteau | return bytes_sent;
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175 | ad96090a | Blue Swirl | } |
176 | ad96090a | Blue Swirl | |
177 | ad96090a | Blue Swirl | static uint64_t bytes_transferred;
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178 | ad96090a | Blue Swirl | |
179 | ad96090a | Blue Swirl | static ram_addr_t ram_save_remaining(void) |
180 | ad96090a | Blue Swirl | { |
181 | e44359c3 | Alex Williamson | RAMBlock *block; |
182 | ad96090a | Blue Swirl | ram_addr_t count = 0;
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183 | ad96090a | Blue Swirl | |
184 | e44359c3 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) { |
185 | e44359c3 | Alex Williamson | ram_addr_t addr; |
186 | e44359c3 | Alex Williamson | for (addr = block->offset; addr < block->offset + block->length;
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187 | e44359c3 | Alex Williamson | addr += TARGET_PAGE_SIZE) { |
188 | e44359c3 | Alex Williamson | if (cpu_physical_memory_get_dirty(addr, MIGRATION_DIRTY_FLAG)) {
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189 | e44359c3 | Alex Williamson | count++; |
190 | e44359c3 | Alex Williamson | } |
191 | ad96090a | Blue Swirl | } |
192 | ad96090a | Blue Swirl | } |
193 | ad96090a | Blue Swirl | |
194 | ad96090a | Blue Swirl | return count;
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195 | ad96090a | Blue Swirl | } |
196 | ad96090a | Blue Swirl | |
197 | ad96090a | Blue Swirl | uint64_t ram_bytes_remaining(void)
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198 | ad96090a | Blue Swirl | { |
199 | ad96090a | Blue Swirl | return ram_save_remaining() * TARGET_PAGE_SIZE;
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200 | ad96090a | Blue Swirl | } |
201 | ad96090a | Blue Swirl | |
202 | ad96090a | Blue Swirl | uint64_t ram_bytes_transferred(void)
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203 | ad96090a | Blue Swirl | { |
204 | ad96090a | Blue Swirl | return bytes_transferred;
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205 | ad96090a | Blue Swirl | } |
206 | ad96090a | Blue Swirl | |
207 | ad96090a | Blue Swirl | uint64_t ram_bytes_total(void)
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208 | ad96090a | Blue Swirl | { |
209 | d17b5288 | Alex Williamson | RAMBlock *block; |
210 | d17b5288 | Alex Williamson | uint64_t total = 0;
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211 | d17b5288 | Alex Williamson | |
212 | d17b5288 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) |
213 | d17b5288 | Alex Williamson | total += block->length; |
214 | d17b5288 | Alex Williamson | |
215 | d17b5288 | Alex Williamson | return total;
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216 | ad96090a | Blue Swirl | } |
217 | ad96090a | Blue Swirl | |
218 | b2e0a138 | Michael S. Tsirkin | static int block_compar(const void *a, const void *b) |
219 | b2e0a138 | Michael S. Tsirkin | { |
220 | b2e0a138 | Michael S. Tsirkin | RAMBlock * const *ablock = a;
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221 | b2e0a138 | Michael S. Tsirkin | RAMBlock * const *bblock = b;
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222 | b2e0a138 | Michael S. Tsirkin | if ((*ablock)->offset < (*bblock)->offset) {
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223 | b2e0a138 | Michael S. Tsirkin | return -1; |
224 | b2e0a138 | Michael S. Tsirkin | } else if ((*ablock)->offset > (*bblock)->offset) { |
225 | b2e0a138 | Michael S. Tsirkin | return 1; |
226 | b2e0a138 | Michael S. Tsirkin | } |
227 | b2e0a138 | Michael S. Tsirkin | return 0; |
228 | b2e0a138 | Michael S. Tsirkin | } |
229 | b2e0a138 | Michael S. Tsirkin | |
230 | b2e0a138 | Michael S. Tsirkin | static void sort_ram_list(void) |
231 | b2e0a138 | Michael S. Tsirkin | { |
232 | b2e0a138 | Michael S. Tsirkin | RAMBlock *block, *nblock, **blocks; |
233 | b2e0a138 | Michael S. Tsirkin | int n;
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234 | b2e0a138 | Michael S. Tsirkin | n = 0;
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235 | b2e0a138 | Michael S. Tsirkin | QLIST_FOREACH(block, &ram_list.blocks, next) { |
236 | b2e0a138 | Michael S. Tsirkin | ++n; |
237 | b2e0a138 | Michael S. Tsirkin | } |
238 | b2e0a138 | Michael S. Tsirkin | blocks = qemu_malloc(n * sizeof *blocks);
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239 | b2e0a138 | Michael S. Tsirkin | n = 0;
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240 | b2e0a138 | Michael S. Tsirkin | QLIST_FOREACH_SAFE(block, &ram_list.blocks, next, nblock) { |
241 | b2e0a138 | Michael S. Tsirkin | blocks[n++] = block; |
242 | b2e0a138 | Michael S. Tsirkin | QLIST_REMOVE(block, next); |
243 | b2e0a138 | Michael S. Tsirkin | } |
244 | b2e0a138 | Michael S. Tsirkin | qsort(blocks, n, sizeof *blocks, block_compar);
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245 | b2e0a138 | Michael S. Tsirkin | while (--n >= 0) { |
246 | b2e0a138 | Michael S. Tsirkin | QLIST_INSERT_HEAD(&ram_list.blocks, blocks[n], next); |
247 | b2e0a138 | Michael S. Tsirkin | } |
248 | b2e0a138 | Michael S. Tsirkin | qemu_free(blocks); |
249 | b2e0a138 | Michael S. Tsirkin | } |
250 | b2e0a138 | Michael S. Tsirkin | |
251 | ad96090a | Blue Swirl | int ram_save_live(Monitor *mon, QEMUFile *f, int stage, void *opaque) |
252 | ad96090a | Blue Swirl | { |
253 | ad96090a | Blue Swirl | ram_addr_t addr; |
254 | ad96090a | Blue Swirl | uint64_t bytes_transferred_last; |
255 | ad96090a | Blue Swirl | double bwidth = 0; |
256 | ad96090a | Blue Swirl | uint64_t expected_time = 0;
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257 | ad96090a | Blue Swirl | |
258 | ad96090a | Blue Swirl | if (stage < 0) { |
259 | ad96090a | Blue Swirl | cpu_physical_memory_set_dirty_tracking(0);
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260 | ad96090a | Blue Swirl | return 0; |
261 | ad96090a | Blue Swirl | } |
262 | ad96090a | Blue Swirl | |
263 | ad96090a | Blue Swirl | if (cpu_physical_sync_dirty_bitmap(0, TARGET_PHYS_ADDR_MAX) != 0) { |
264 | ad96090a | Blue Swirl | qemu_file_set_error(f); |
265 | ad96090a | Blue Swirl | return 0; |
266 | ad96090a | Blue Swirl | } |
267 | ad96090a | Blue Swirl | |
268 | ad96090a | Blue Swirl | if (stage == 1) { |
269 | 97ab12d4 | Alex Williamson | RAMBlock *block; |
270 | ad96090a | Blue Swirl | bytes_transferred = 0;
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271 | 760e77ea | Alex Williamson | last_block = NULL;
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272 | 760e77ea | Alex Williamson | last_offset = 0;
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273 | b2e0a138 | Michael S. Tsirkin | sort_ram_list(); |
274 | ad96090a | Blue Swirl | |
275 | ad96090a | Blue Swirl | /* Make sure all dirty bits are set */
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276 | e44359c3 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) { |
277 | e44359c3 | Alex Williamson | for (addr = block->offset; addr < block->offset + block->length;
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278 | e44359c3 | Alex Williamson | addr += TARGET_PAGE_SIZE) { |
279 | e44359c3 | Alex Williamson | if (!cpu_physical_memory_get_dirty(addr,
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280 | e44359c3 | Alex Williamson | MIGRATION_DIRTY_FLAG)) { |
281 | e44359c3 | Alex Williamson | cpu_physical_memory_set_dirty(addr); |
282 | e44359c3 | Alex Williamson | } |
283 | ad96090a | Blue Swirl | } |
284 | ad96090a | Blue Swirl | } |
285 | ad96090a | Blue Swirl | |
286 | ad96090a | Blue Swirl | /* Enable dirty memory tracking */
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287 | ad96090a | Blue Swirl | cpu_physical_memory_set_dirty_tracking(1);
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288 | ad96090a | Blue Swirl | |
289 | e44359c3 | Alex Williamson | qemu_put_be64(f, ram_bytes_total() | RAM_SAVE_FLAG_MEM_SIZE); |
290 | 97ab12d4 | Alex Williamson | |
291 | 97ab12d4 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) { |
292 | 97ab12d4 | Alex Williamson | qemu_put_byte(f, strlen(block->idstr)); |
293 | 97ab12d4 | Alex Williamson | qemu_put_buffer(f, (uint8_t *)block->idstr, strlen(block->idstr)); |
294 | 97ab12d4 | Alex Williamson | qemu_put_be64(f, block->length); |
295 | 97ab12d4 | Alex Williamson | } |
296 | ad96090a | Blue Swirl | } |
297 | ad96090a | Blue Swirl | |
298 | ad96090a | Blue Swirl | bytes_transferred_last = bytes_transferred; |
299 | ad96090a | Blue Swirl | bwidth = qemu_get_clock_ns(rt_clock); |
300 | ad96090a | Blue Swirl | |
301 | ad96090a | Blue Swirl | while (!qemu_file_rate_limit(f)) {
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302 | 3fc250b4 | Pierre Riteau | int bytes_sent;
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303 | ad96090a | Blue Swirl | |
304 | 3fc250b4 | Pierre Riteau | bytes_sent = ram_save_block(f); |
305 | 3fc250b4 | Pierre Riteau | bytes_transferred += bytes_sent; |
306 | 3fc250b4 | Pierre Riteau | if (bytes_sent == 0) { /* no more blocks */ |
307 | ad96090a | Blue Swirl | break;
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308 | ad96090a | Blue Swirl | } |
309 | ad96090a | Blue Swirl | } |
310 | ad96090a | Blue Swirl | |
311 | ad96090a | Blue Swirl | bwidth = qemu_get_clock_ns(rt_clock) - bwidth; |
312 | ad96090a | Blue Swirl | bwidth = (bytes_transferred - bytes_transferred_last) / bwidth; |
313 | ad96090a | Blue Swirl | |
314 | ad96090a | Blue Swirl | /* if we haven't transferred anything this round, force expected_time to a
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315 | ad96090a | Blue Swirl | * a very high value, but without crashing */
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316 | ad96090a | Blue Swirl | if (bwidth == 0) { |
317 | ad96090a | Blue Swirl | bwidth = 0.000001; |
318 | ad96090a | Blue Swirl | } |
319 | ad96090a | Blue Swirl | |
320 | ad96090a | Blue Swirl | /* try transferring iterative blocks of memory */
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321 | ad96090a | Blue Swirl | if (stage == 3) { |
322 | 3fc250b4 | Pierre Riteau | int bytes_sent;
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323 | 3fc250b4 | Pierre Riteau | |
324 | ad96090a | Blue Swirl | /* flush all remaining blocks regardless of rate limiting */
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325 | 3fc250b4 | Pierre Riteau | while ((bytes_sent = ram_save_block(f)) != 0) { |
326 | 3fc250b4 | Pierre Riteau | bytes_transferred += bytes_sent; |
327 | ad96090a | Blue Swirl | } |
328 | ad96090a | Blue Swirl | cpu_physical_memory_set_dirty_tracking(0);
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329 | ad96090a | Blue Swirl | } |
330 | ad96090a | Blue Swirl | |
331 | ad96090a | Blue Swirl | qemu_put_be64(f, RAM_SAVE_FLAG_EOS); |
332 | ad96090a | Blue Swirl | |
333 | ad96090a | Blue Swirl | expected_time = ram_save_remaining() * TARGET_PAGE_SIZE / bwidth; |
334 | ad96090a | Blue Swirl | |
335 | ad96090a | Blue Swirl | return (stage == 2) && (expected_time <= migrate_max_downtime()); |
336 | ad96090a | Blue Swirl | } |
337 | ad96090a | Blue Swirl | |
338 | a55bbe31 | Alex Williamson | static inline void *host_from_stream_offset(QEMUFile *f, |
339 | a55bbe31 | Alex Williamson | ram_addr_t offset, |
340 | a55bbe31 | Alex Williamson | int flags)
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341 | a55bbe31 | Alex Williamson | { |
342 | a55bbe31 | Alex Williamson | static RAMBlock *block = NULL; |
343 | a55bbe31 | Alex Williamson | char id[256]; |
344 | a55bbe31 | Alex Williamson | uint8_t len; |
345 | a55bbe31 | Alex Williamson | |
346 | a55bbe31 | Alex Williamson | if (flags & RAM_SAVE_FLAG_CONTINUE) {
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347 | a55bbe31 | Alex Williamson | if (!block) {
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348 | a55bbe31 | Alex Williamson | fprintf(stderr, "Ack, bad migration stream!\n");
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349 | a55bbe31 | Alex Williamson | return NULL; |
350 | a55bbe31 | Alex Williamson | } |
351 | a55bbe31 | Alex Williamson | |
352 | a55bbe31 | Alex Williamson | return block->host + offset;
|
353 | a55bbe31 | Alex Williamson | } |
354 | a55bbe31 | Alex Williamson | |
355 | a55bbe31 | Alex Williamson | len = qemu_get_byte(f); |
356 | a55bbe31 | Alex Williamson | qemu_get_buffer(f, (uint8_t *)id, len); |
357 | a55bbe31 | Alex Williamson | id[len] = 0;
|
358 | a55bbe31 | Alex Williamson | |
359 | a55bbe31 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) { |
360 | a55bbe31 | Alex Williamson | if (!strncmp(id, block->idstr, sizeof(id))) |
361 | a55bbe31 | Alex Williamson | return block->host + offset;
|
362 | a55bbe31 | Alex Williamson | } |
363 | a55bbe31 | Alex Williamson | |
364 | a55bbe31 | Alex Williamson | fprintf(stderr, "Can't find block %s!\n", id);
|
365 | a55bbe31 | Alex Williamson | return NULL; |
366 | a55bbe31 | Alex Williamson | } |
367 | a55bbe31 | Alex Williamson | |
368 | ad96090a | Blue Swirl | int ram_load(QEMUFile *f, void *opaque, int version_id) |
369 | ad96090a | Blue Swirl | { |
370 | ad96090a | Blue Swirl | ram_addr_t addr; |
371 | ad96090a | Blue Swirl | int flags;
|
372 | ad96090a | Blue Swirl | |
373 | 97ab12d4 | Alex Williamson | if (version_id < 3 || version_id > 4) { |
374 | ad96090a | Blue Swirl | return -EINVAL;
|
375 | ad96090a | Blue Swirl | } |
376 | ad96090a | Blue Swirl | |
377 | ad96090a | Blue Swirl | do {
|
378 | ad96090a | Blue Swirl | addr = qemu_get_be64(f); |
379 | ad96090a | Blue Swirl | |
380 | ad96090a | Blue Swirl | flags = addr & ~TARGET_PAGE_MASK; |
381 | ad96090a | Blue Swirl | addr &= TARGET_PAGE_MASK; |
382 | ad96090a | Blue Swirl | |
383 | ad96090a | Blue Swirl | if (flags & RAM_SAVE_FLAG_MEM_SIZE) {
|
384 | 97ab12d4 | Alex Williamson | if (version_id == 3) { |
385 | 97ab12d4 | Alex Williamson | if (addr != ram_bytes_total()) {
|
386 | 97ab12d4 | Alex Williamson | return -EINVAL;
|
387 | 97ab12d4 | Alex Williamson | } |
388 | 97ab12d4 | Alex Williamson | } else {
|
389 | 97ab12d4 | Alex Williamson | /* Synchronize RAM block list */
|
390 | 97ab12d4 | Alex Williamson | char id[256]; |
391 | 97ab12d4 | Alex Williamson | ram_addr_t length; |
392 | 97ab12d4 | Alex Williamson | ram_addr_t total_ram_bytes = addr; |
393 | 97ab12d4 | Alex Williamson | |
394 | 97ab12d4 | Alex Williamson | while (total_ram_bytes) {
|
395 | 97ab12d4 | Alex Williamson | RAMBlock *block; |
396 | 97ab12d4 | Alex Williamson | uint8_t len; |
397 | 97ab12d4 | Alex Williamson | |
398 | 97ab12d4 | Alex Williamson | len = qemu_get_byte(f); |
399 | 97ab12d4 | Alex Williamson | qemu_get_buffer(f, (uint8_t *)id, len); |
400 | 97ab12d4 | Alex Williamson | id[len] = 0;
|
401 | 97ab12d4 | Alex Williamson | length = qemu_get_be64(f); |
402 | 97ab12d4 | Alex Williamson | |
403 | 97ab12d4 | Alex Williamson | QLIST_FOREACH(block, &ram_list.blocks, next) { |
404 | 97ab12d4 | Alex Williamson | if (!strncmp(id, block->idstr, sizeof(id))) { |
405 | 97ab12d4 | Alex Williamson | if (block->length != length)
|
406 | 97ab12d4 | Alex Williamson | return -EINVAL;
|
407 | 97ab12d4 | Alex Williamson | break;
|
408 | 97ab12d4 | Alex Williamson | } |
409 | 97ab12d4 | Alex Williamson | } |
410 | 97ab12d4 | Alex Williamson | |
411 | 97ab12d4 | Alex Williamson | if (!block) {
|
412 | fb787f81 | Alex Williamson | fprintf(stderr, "Unknown ramblock \"%s\", cannot "
|
413 | fb787f81 | Alex Williamson | "accept migration\n", id);
|
414 | fb787f81 | Alex Williamson | return -EINVAL;
|
415 | 97ab12d4 | Alex Williamson | } |
416 | 97ab12d4 | Alex Williamson | |
417 | 97ab12d4 | Alex Williamson | total_ram_bytes -= length; |
418 | 97ab12d4 | Alex Williamson | } |
419 | ad96090a | Blue Swirl | } |
420 | ad96090a | Blue Swirl | } |
421 | ad96090a | Blue Swirl | |
422 | ad96090a | Blue Swirl | if (flags & RAM_SAVE_FLAG_COMPRESS) {
|
423 | 97ab12d4 | Alex Williamson | void *host;
|
424 | 97ab12d4 | Alex Williamson | uint8_t ch; |
425 | 97ab12d4 | Alex Williamson | |
426 | a55bbe31 | Alex Williamson | if (version_id == 3) |
427 | 97ab12d4 | Alex Williamson | host = qemu_get_ram_ptr(addr); |
428 | a55bbe31 | Alex Williamson | else
|
429 | a55bbe31 | Alex Williamson | host = host_from_stream_offset(f, addr, flags); |
430 | 492fb99c | Michael S. Tsirkin | if (!host) {
|
431 | 492fb99c | Michael S. Tsirkin | return -EINVAL;
|
432 | 492fb99c | Michael S. Tsirkin | } |
433 | 97ab12d4 | Alex Williamson | |
434 | 97ab12d4 | Alex Williamson | ch = qemu_get_byte(f); |
435 | 97ab12d4 | Alex Williamson | memset(host, ch, TARGET_PAGE_SIZE); |
436 | ad96090a | Blue Swirl | #ifndef _WIN32
|
437 | ad96090a | Blue Swirl | if (ch == 0 && |
438 | ad96090a | Blue Swirl | (!kvm_enabled() || kvm_has_sync_mmu())) { |
439 | e78815a5 | Andreas Fรคrber | qemu_madvise(host, TARGET_PAGE_SIZE, QEMU_MADV_DONTNEED); |
440 | ad96090a | Blue Swirl | } |
441 | ad96090a | Blue Swirl | #endif
|
442 | ad96090a | Blue Swirl | } else if (flags & RAM_SAVE_FLAG_PAGE) { |
443 | 97ab12d4 | Alex Williamson | void *host;
|
444 | 97ab12d4 | Alex Williamson | |
445 | a55bbe31 | Alex Williamson | if (version_id == 3) |
446 | 97ab12d4 | Alex Williamson | host = qemu_get_ram_ptr(addr); |
447 | a55bbe31 | Alex Williamson | else
|
448 | a55bbe31 | Alex Williamson | host = host_from_stream_offset(f, addr, flags); |
449 | 97ab12d4 | Alex Williamson | |
450 | 97ab12d4 | Alex Williamson | qemu_get_buffer(f, host, TARGET_PAGE_SIZE); |
451 | ad96090a | Blue Swirl | } |
452 | ad96090a | Blue Swirl | if (qemu_file_has_error(f)) {
|
453 | ad96090a | Blue Swirl | return -EIO;
|
454 | ad96090a | Blue Swirl | } |
455 | ad96090a | Blue Swirl | } while (!(flags & RAM_SAVE_FLAG_EOS));
|
456 | ad96090a | Blue Swirl | |
457 | ad96090a | Blue Swirl | return 0; |
458 | ad96090a | Blue Swirl | } |
459 | ad96090a | Blue Swirl | |
460 | ad96090a | Blue Swirl | void qemu_service_io(void) |
461 | ad96090a | Blue Swirl | { |
462 | ad96090a | Blue Swirl | qemu_notify_event(); |
463 | ad96090a | Blue Swirl | } |
464 | ad96090a | Blue Swirl | |
465 | ad96090a | Blue Swirl | #ifdef HAS_AUDIO
|
466 | 0dfa5ef9 | Isaku Yamahata | struct soundhw {
|
467 | 0dfa5ef9 | Isaku Yamahata | const char *name; |
468 | 0dfa5ef9 | Isaku Yamahata | const char *descr; |
469 | 0dfa5ef9 | Isaku Yamahata | int enabled;
|
470 | 0dfa5ef9 | Isaku Yamahata | int isa;
|
471 | 0dfa5ef9 | Isaku Yamahata | union {
|
472 | 0dfa5ef9 | Isaku Yamahata | int (*init_isa) (qemu_irq *pic);
|
473 | 0dfa5ef9 | Isaku Yamahata | int (*init_pci) (PCIBus *bus);
|
474 | 0dfa5ef9 | Isaku Yamahata | } init; |
475 | 0dfa5ef9 | Isaku Yamahata | }; |
476 | 0dfa5ef9 | Isaku Yamahata | |
477 | 0dfa5ef9 | Isaku Yamahata | static struct soundhw soundhw[] = { |
478 | ad96090a | Blue Swirl | #ifdef HAS_AUDIO_CHOICE
|
479 | ad96090a | Blue Swirl | #if defined(TARGET_I386) || defined(TARGET_MIPS)
|
480 | ad96090a | Blue Swirl | { |
481 | ad96090a | Blue Swirl | "pcspk",
|
482 | ad96090a | Blue Swirl | "PC speaker",
|
483 | ad96090a | Blue Swirl | 0,
|
484 | ad96090a | Blue Swirl | 1,
|
485 | ad96090a | Blue Swirl | { .init_isa = pcspk_audio_init } |
486 | ad96090a | Blue Swirl | }, |
487 | ad96090a | Blue Swirl | #endif
|
488 | ad96090a | Blue Swirl | |
489 | ad96090a | Blue Swirl | #ifdef CONFIG_SB16
|
490 | ad96090a | Blue Swirl | { |
491 | ad96090a | Blue Swirl | "sb16",
|
492 | ad96090a | Blue Swirl | "Creative Sound Blaster 16",
|
493 | ad96090a | Blue Swirl | 0,
|
494 | ad96090a | Blue Swirl | 1,
|
495 | ad96090a | Blue Swirl | { .init_isa = SB16_init } |
496 | ad96090a | Blue Swirl | }, |
497 | ad96090a | Blue Swirl | #endif
|
498 | ad96090a | Blue Swirl | |
499 | ad96090a | Blue Swirl | #ifdef CONFIG_CS4231A
|
500 | ad96090a | Blue Swirl | { |
501 | ad96090a | Blue Swirl | "cs4231a",
|
502 | ad96090a | Blue Swirl | "CS4231A",
|
503 | ad96090a | Blue Swirl | 0,
|
504 | ad96090a | Blue Swirl | 1,
|
505 | ad96090a | Blue Swirl | { .init_isa = cs4231a_init } |
506 | ad96090a | Blue Swirl | }, |
507 | ad96090a | Blue Swirl | #endif
|
508 | ad96090a | Blue Swirl | |
509 | ad96090a | Blue Swirl | #ifdef CONFIG_ADLIB
|
510 | ad96090a | Blue Swirl | { |
511 | ad96090a | Blue Swirl | "adlib",
|
512 | ad96090a | Blue Swirl | #ifdef HAS_YMF262
|
513 | ad96090a | Blue Swirl | "Yamaha YMF262 (OPL3)",
|
514 | ad96090a | Blue Swirl | #else
|
515 | ad96090a | Blue Swirl | "Yamaha YM3812 (OPL2)",
|
516 | ad96090a | Blue Swirl | #endif
|
517 | ad96090a | Blue Swirl | 0,
|
518 | ad96090a | Blue Swirl | 1,
|
519 | ad96090a | Blue Swirl | { .init_isa = Adlib_init } |
520 | ad96090a | Blue Swirl | }, |
521 | ad96090a | Blue Swirl | #endif
|
522 | ad96090a | Blue Swirl | |
523 | ad96090a | Blue Swirl | #ifdef CONFIG_GUS
|
524 | ad96090a | Blue Swirl | { |
525 | ad96090a | Blue Swirl | "gus",
|
526 | ad96090a | Blue Swirl | "Gravis Ultrasound GF1",
|
527 | ad96090a | Blue Swirl | 0,
|
528 | ad96090a | Blue Swirl | 1,
|
529 | ad96090a | Blue Swirl | { .init_isa = GUS_init } |
530 | ad96090a | Blue Swirl | }, |
531 | ad96090a | Blue Swirl | #endif
|
532 | ad96090a | Blue Swirl | |
533 | ad96090a | Blue Swirl | #ifdef CONFIG_AC97
|
534 | ad96090a | Blue Swirl | { |
535 | ad96090a | Blue Swirl | "ac97",
|
536 | ad96090a | Blue Swirl | "Intel 82801AA AC97 Audio",
|
537 | ad96090a | Blue Swirl | 0,
|
538 | ad96090a | Blue Swirl | 0,
|
539 | ad96090a | Blue Swirl | { .init_pci = ac97_init } |
540 | ad96090a | Blue Swirl | }, |
541 | ad96090a | Blue Swirl | #endif
|
542 | ad96090a | Blue Swirl | |
543 | ad96090a | Blue Swirl | #ifdef CONFIG_ES1370
|
544 | ad96090a | Blue Swirl | { |
545 | ad96090a | Blue Swirl | "es1370",
|
546 | ad96090a | Blue Swirl | "ENSONIQ AudioPCI ES1370",
|
547 | ad96090a | Blue Swirl | 0,
|
548 | ad96090a | Blue Swirl | 0,
|
549 | ad96090a | Blue Swirl | { .init_pci = es1370_init } |
550 | ad96090a | Blue Swirl | }, |
551 | ad96090a | Blue Swirl | #endif
|
552 | ad96090a | Blue Swirl | |
553 | d61a4ce8 | Gerd Hoffmann | #ifdef CONFIG_HDA
|
554 | d61a4ce8 | Gerd Hoffmann | { |
555 | d61a4ce8 | Gerd Hoffmann | "hda",
|
556 | d61a4ce8 | Gerd Hoffmann | "Intel HD Audio",
|
557 | d61a4ce8 | Gerd Hoffmann | 0,
|
558 | d61a4ce8 | Gerd Hoffmann | 0,
|
559 | d61a4ce8 | Gerd Hoffmann | { .init_pci = intel_hda_and_codec_init } |
560 | d61a4ce8 | Gerd Hoffmann | }, |
561 | d61a4ce8 | Gerd Hoffmann | #endif
|
562 | d61a4ce8 | Gerd Hoffmann | |
563 | ad96090a | Blue Swirl | #endif /* HAS_AUDIO_CHOICE */ |
564 | ad96090a | Blue Swirl | |
565 | ad96090a | Blue Swirl | { NULL, NULL, 0, 0, { NULL } } |
566 | ad96090a | Blue Swirl | }; |
567 | ad96090a | Blue Swirl | |
568 | ad96090a | Blue Swirl | void select_soundhw(const char *optarg) |
569 | ad96090a | Blue Swirl | { |
570 | ad96090a | Blue Swirl | struct soundhw *c;
|
571 | ad96090a | Blue Swirl | |
572 | ad96090a | Blue Swirl | if (*optarg == '?') { |
573 | ad96090a | Blue Swirl | show_valid_cards:
|
574 | ad96090a | Blue Swirl | |
575 | ad96090a | Blue Swirl | printf("Valid sound card names (comma separated):\n");
|
576 | ad96090a | Blue Swirl | for (c = soundhw; c->name; ++c) {
|
577 | ad96090a | Blue Swirl | printf ("%-11s %s\n", c->name, c->descr);
|
578 | ad96090a | Blue Swirl | } |
579 | ad96090a | Blue Swirl | printf("\n-soundhw all will enable all of the above\n");
|
580 | ad96090a | Blue Swirl | exit(*optarg != '?');
|
581 | ad96090a | Blue Swirl | } |
582 | ad96090a | Blue Swirl | else {
|
583 | ad96090a | Blue Swirl | size_t l; |
584 | ad96090a | Blue Swirl | const char *p; |
585 | ad96090a | Blue Swirl | char *e;
|
586 | ad96090a | Blue Swirl | int bad_card = 0; |
587 | ad96090a | Blue Swirl | |
588 | ad96090a | Blue Swirl | if (!strcmp(optarg, "all")) { |
589 | ad96090a | Blue Swirl | for (c = soundhw; c->name; ++c) {
|
590 | ad96090a | Blue Swirl | c->enabled = 1;
|
591 | ad96090a | Blue Swirl | } |
592 | ad96090a | Blue Swirl | return;
|
593 | ad96090a | Blue Swirl | } |
594 | ad96090a | Blue Swirl | |
595 | ad96090a | Blue Swirl | p = optarg; |
596 | ad96090a | Blue Swirl | while (*p) {
|
597 | ad96090a | Blue Swirl | e = strchr(p, ',');
|
598 | ad96090a | Blue Swirl | l = !e ? strlen(p) : (size_t) (e - p); |
599 | ad96090a | Blue Swirl | |
600 | ad96090a | Blue Swirl | for (c = soundhw; c->name; ++c) {
|
601 | ad96090a | Blue Swirl | if (!strncmp(c->name, p, l) && !c->name[l]) {
|
602 | ad96090a | Blue Swirl | c->enabled = 1;
|
603 | ad96090a | Blue Swirl | break;
|
604 | ad96090a | Blue Swirl | } |
605 | ad96090a | Blue Swirl | } |
606 | ad96090a | Blue Swirl | |
607 | ad96090a | Blue Swirl | if (!c->name) {
|
608 | ad96090a | Blue Swirl | if (l > 80) { |
609 | ad96090a | Blue Swirl | fprintf(stderr, |
610 | ad96090a | Blue Swirl | "Unknown sound card name (too big to show)\n");
|
611 | ad96090a | Blue Swirl | } |
612 | ad96090a | Blue Swirl | else {
|
613 | ad96090a | Blue Swirl | fprintf(stderr, "Unknown sound card name `%.*s'\n",
|
614 | ad96090a | Blue Swirl | (int) l, p);
|
615 | ad96090a | Blue Swirl | } |
616 | ad96090a | Blue Swirl | bad_card = 1;
|
617 | ad96090a | Blue Swirl | } |
618 | ad96090a | Blue Swirl | p += l + (e != NULL);
|
619 | ad96090a | Blue Swirl | } |
620 | ad96090a | Blue Swirl | |
621 | ad96090a | Blue Swirl | if (bad_card) {
|
622 | ad96090a | Blue Swirl | goto show_valid_cards;
|
623 | ad96090a | Blue Swirl | } |
624 | ad96090a | Blue Swirl | } |
625 | ad96090a | Blue Swirl | } |
626 | 0dfa5ef9 | Isaku Yamahata | |
627 | 0dfa5ef9 | Isaku Yamahata | void audio_init(qemu_irq *isa_pic, PCIBus *pci_bus)
|
628 | 0dfa5ef9 | Isaku Yamahata | { |
629 | 0dfa5ef9 | Isaku Yamahata | struct soundhw *c;
|
630 | 0dfa5ef9 | Isaku Yamahata | |
631 | 0dfa5ef9 | Isaku Yamahata | for (c = soundhw; c->name; ++c) {
|
632 | 0dfa5ef9 | Isaku Yamahata | if (c->enabled) {
|
633 | 0dfa5ef9 | Isaku Yamahata | if (c->isa) {
|
634 | 0dfa5ef9 | Isaku Yamahata | if (isa_pic) {
|
635 | 0dfa5ef9 | Isaku Yamahata | c->init.init_isa(isa_pic); |
636 | 0dfa5ef9 | Isaku Yamahata | } |
637 | 0dfa5ef9 | Isaku Yamahata | } else {
|
638 | 0dfa5ef9 | Isaku Yamahata | if (pci_bus) {
|
639 | 0dfa5ef9 | Isaku Yamahata | c->init.init_pci(pci_bus); |
640 | 0dfa5ef9 | Isaku Yamahata | } |
641 | 0dfa5ef9 | Isaku Yamahata | } |
642 | 0dfa5ef9 | Isaku Yamahata | } |
643 | 0dfa5ef9 | Isaku Yamahata | } |
644 | 0dfa5ef9 | Isaku Yamahata | } |
645 | ad96090a | Blue Swirl | #else
|
646 | ad96090a | Blue Swirl | void select_soundhw(const char *optarg) |
647 | ad96090a | Blue Swirl | { |
648 | ad96090a | Blue Swirl | } |
649 | 0dfa5ef9 | Isaku Yamahata | void audio_init(qemu_irq *isa_pic, PCIBus *pci_bus)
|
650 | 0dfa5ef9 | Isaku Yamahata | { |
651 | 0dfa5ef9 | Isaku Yamahata | } |
652 | ad96090a | Blue Swirl | #endif
|
653 | ad96090a | Blue Swirl | |
654 | ad96090a | Blue Swirl | int qemu_uuid_parse(const char *str, uint8_t *uuid) |
655 | ad96090a | Blue Swirl | { |
656 | ad96090a | Blue Swirl | int ret;
|
657 | ad96090a | Blue Swirl | |
658 | ad96090a | Blue Swirl | if (strlen(str) != 36) { |
659 | ad96090a | Blue Swirl | return -1; |
660 | ad96090a | Blue Swirl | } |
661 | ad96090a | Blue Swirl | |
662 | ad96090a | Blue Swirl | ret = sscanf(str, UUID_FMT, &uuid[0], &uuid[1], &uuid[2], &uuid[3], |
663 | ad96090a | Blue Swirl | &uuid[4], &uuid[5], &uuid[6], &uuid[7], &uuid[8], &uuid[9], |
664 | ad96090a | Blue Swirl | &uuid[10], &uuid[11], &uuid[12], &uuid[13], &uuid[14], |
665 | ad96090a | Blue Swirl | &uuid[15]);
|
666 | ad96090a | Blue Swirl | |
667 | ad96090a | Blue Swirl | if (ret != 16) { |
668 | ad96090a | Blue Swirl | return -1; |
669 | ad96090a | Blue Swirl | } |
670 | ad96090a | Blue Swirl | #ifdef TARGET_I386
|
671 | ad96090a | Blue Swirl | smbios_add_field(1, offsetof(struct smbios_type_1, uuid), 16, uuid); |
672 | ad96090a | Blue Swirl | #endif
|
673 | ad96090a | Blue Swirl | return 0; |
674 | ad96090a | Blue Swirl | } |
675 | ad96090a | Blue Swirl | |
676 | ad96090a | Blue Swirl | void do_acpitable_option(const char *optarg) |
677 | ad96090a | Blue Swirl | { |
678 | ad96090a | Blue Swirl | #ifdef TARGET_I386
|
679 | ad96090a | Blue Swirl | if (acpi_table_add(optarg) < 0) { |
680 | ad96090a | Blue Swirl | fprintf(stderr, "Wrong acpi table provided\n");
|
681 | ad96090a | Blue Swirl | exit(1);
|
682 | ad96090a | Blue Swirl | } |
683 | ad96090a | Blue Swirl | #endif
|
684 | ad96090a | Blue Swirl | } |
685 | ad96090a | Blue Swirl | |
686 | ad96090a | Blue Swirl | void do_smbios_option(const char *optarg) |
687 | ad96090a | Blue Swirl | { |
688 | ad96090a | Blue Swirl | #ifdef TARGET_I386
|
689 | ad96090a | Blue Swirl | if (smbios_entry_add(optarg) < 0) { |
690 | ad96090a | Blue Swirl | fprintf(stderr, "Wrong smbios provided\n");
|
691 | ad96090a | Blue Swirl | exit(1);
|
692 | ad96090a | Blue Swirl | } |
693 | ad96090a | Blue Swirl | #endif
|
694 | ad96090a | Blue Swirl | } |
695 | ad96090a | Blue Swirl | |
696 | ad96090a | Blue Swirl | void cpudef_init(void) |
697 | ad96090a | Blue Swirl | { |
698 | ad96090a | Blue Swirl | #if defined(cpudef_setup)
|
699 | ad96090a | Blue Swirl | cpudef_setup(); /* parse cpu definitions in target config file */
|
700 | ad96090a | Blue Swirl | #endif
|
701 | ad96090a | Blue Swirl | } |
702 | ad96090a | Blue Swirl | |
703 | ad96090a | Blue Swirl | int audio_available(void) |
704 | ad96090a | Blue Swirl | { |
705 | ad96090a | Blue Swirl | #ifdef HAS_AUDIO
|
706 | ad96090a | Blue Swirl | return 1; |
707 | ad96090a | Blue Swirl | #else
|
708 | ad96090a | Blue Swirl | return 0; |
709 | ad96090a | Blue Swirl | #endif
|
710 | ad96090a | Blue Swirl | } |
711 | ad96090a | Blue Swirl | |
712 | 303d4e86 | Anthony PERARD | int tcg_available(void) |
713 | 303d4e86 | Anthony PERARD | { |
714 | 303d4e86 | Anthony PERARD | return 1; |
715 | 303d4e86 | Anthony PERARD | } |
716 | 303d4e86 | Anthony PERARD | |
717 | ad96090a | Blue Swirl | int kvm_available(void) |
718 | ad96090a | Blue Swirl | { |
719 | ad96090a | Blue Swirl | #ifdef CONFIG_KVM
|
720 | ad96090a | Blue Swirl | return 1; |
721 | ad96090a | Blue Swirl | #else
|
722 | ad96090a | Blue Swirl | return 0; |
723 | ad96090a | Blue Swirl | #endif
|
724 | ad96090a | Blue Swirl | } |
725 | ad96090a | Blue Swirl | |
726 | ad96090a | Blue Swirl | int xen_available(void) |
727 | ad96090a | Blue Swirl | { |
728 | ad96090a | Blue Swirl | #ifdef CONFIG_XEN
|
729 | ad96090a | Blue Swirl | return 1; |
730 | ad96090a | Blue Swirl | #else
|
731 | ad96090a | Blue Swirl | return 0; |
732 | ad96090a | Blue Swirl | #endif
|
733 | ad96090a | Blue Swirl | } |