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1 | 770ae571 | Michael Walle | /*
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2 | 770ae571 | Michael Walle | * QEMU model of the LatticeMico32 UART block.
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3 | 770ae571 | Michael Walle | *
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4 | 770ae571 | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | 770ae571 | Michael Walle | *
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6 | 770ae571 | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | 770ae571 | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | 770ae571 | Michael Walle | * License as published by the Free Software Foundation; either
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9 | 770ae571 | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | 770ae571 | Michael Walle | *
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11 | 770ae571 | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | 770ae571 | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 770ae571 | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 770ae571 | Michael Walle | * Lesser General Public License for more details.
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15 | 770ae571 | Michael Walle | *
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16 | 770ae571 | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | 770ae571 | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 770ae571 | Michael Walle | *
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19 | 770ae571 | Michael Walle | *
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20 | 770ae571 | Michael Walle | * Specification available at:
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21 | 770ae571 | Michael Walle | * http://www.latticesemi.com/documents/mico32uart.pdf
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22 | 770ae571 | Michael Walle | */
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23 | 770ae571 | Michael Walle | |
24 | 770ae571 | Michael Walle | |
25 | 770ae571 | Michael Walle | #include "hw.h" |
26 | 770ae571 | Michael Walle | #include "sysbus.h" |
27 | 770ae571 | Michael Walle | #include "trace.h" |
28 | 770ae571 | Michael Walle | #include "qemu-char.h" |
29 | 770ae571 | Michael Walle | #include "qemu-error.h" |
30 | 770ae571 | Michael Walle | |
31 | 770ae571 | Michael Walle | enum {
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32 | 770ae571 | Michael Walle | R_RXTX = 0,
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33 | 770ae571 | Michael Walle | R_IER, |
34 | 770ae571 | Michael Walle | R_IIR, |
35 | 770ae571 | Michael Walle | R_LCR, |
36 | 770ae571 | Michael Walle | R_MCR, |
37 | 770ae571 | Michael Walle | R_LSR, |
38 | 770ae571 | Michael Walle | R_MSR, |
39 | 770ae571 | Michael Walle | R_DIV, |
40 | 770ae571 | Michael Walle | R_MAX |
41 | 770ae571 | Michael Walle | }; |
42 | 770ae571 | Michael Walle | |
43 | 770ae571 | Michael Walle | enum {
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44 | 770ae571 | Michael Walle | IER_RBRI = (1<<0), |
45 | 770ae571 | Michael Walle | IER_THRI = (1<<1), |
46 | 770ae571 | Michael Walle | IER_RLSI = (1<<2), |
47 | 770ae571 | Michael Walle | IER_MSI = (1<<3), |
48 | 770ae571 | Michael Walle | }; |
49 | 770ae571 | Michael Walle | |
50 | 770ae571 | Michael Walle | enum {
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51 | 770ae571 | Michael Walle | IIR_STAT = (1<<0), |
52 | 770ae571 | Michael Walle | IIR_ID0 = (1<<1), |
53 | 770ae571 | Michael Walle | IIR_ID1 = (1<<2), |
54 | 770ae571 | Michael Walle | }; |
55 | 770ae571 | Michael Walle | |
56 | 770ae571 | Michael Walle | enum {
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57 | 770ae571 | Michael Walle | LCR_WLS0 = (1<<0), |
58 | 770ae571 | Michael Walle | LCR_WLS1 = (1<<1), |
59 | 770ae571 | Michael Walle | LCR_STB = (1<<2), |
60 | 770ae571 | Michael Walle | LCR_PEN = (1<<3), |
61 | 770ae571 | Michael Walle | LCR_EPS = (1<<4), |
62 | 770ae571 | Michael Walle | LCR_SP = (1<<5), |
63 | 770ae571 | Michael Walle | LCR_SB = (1<<6), |
64 | 770ae571 | Michael Walle | }; |
65 | 770ae571 | Michael Walle | |
66 | 770ae571 | Michael Walle | enum {
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67 | 770ae571 | Michael Walle | MCR_DTR = (1<<0), |
68 | 770ae571 | Michael Walle | MCR_RTS = (1<<1), |
69 | 770ae571 | Michael Walle | }; |
70 | 770ae571 | Michael Walle | |
71 | 770ae571 | Michael Walle | enum {
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72 | 770ae571 | Michael Walle | LSR_DR = (1<<0), |
73 | 770ae571 | Michael Walle | LSR_OE = (1<<1), |
74 | 770ae571 | Michael Walle | LSR_PE = (1<<2), |
75 | 770ae571 | Michael Walle | LSR_FE = (1<<3), |
76 | 770ae571 | Michael Walle | LSR_BI = (1<<4), |
77 | 770ae571 | Michael Walle | LSR_THRE = (1<<5), |
78 | 770ae571 | Michael Walle | LSR_TEMT = (1<<6), |
79 | 770ae571 | Michael Walle | }; |
80 | 770ae571 | Michael Walle | |
81 | 770ae571 | Michael Walle | enum {
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82 | 770ae571 | Michael Walle | MSR_DCTS = (1<<0), |
83 | 770ae571 | Michael Walle | MSR_DDSR = (1<<1), |
84 | 770ae571 | Michael Walle | MSR_TERI = (1<<2), |
85 | 770ae571 | Michael Walle | MSR_DDCD = (1<<3), |
86 | 770ae571 | Michael Walle | MSR_CTS = (1<<4), |
87 | 770ae571 | Michael Walle | MSR_DSR = (1<<5), |
88 | 770ae571 | Michael Walle | MSR_RI = (1<<6), |
89 | 770ae571 | Michael Walle | MSR_DCD = (1<<7), |
90 | 770ae571 | Michael Walle | }; |
91 | 770ae571 | Michael Walle | |
92 | 770ae571 | Michael Walle | struct LM32UartState {
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93 | 770ae571 | Michael Walle | SysBusDevice busdev; |
94 | 5f2be17a | Benoît Canet | MemoryRegion iomem; |
95 | 770ae571 | Michael Walle | CharDriverState *chr; |
96 | 770ae571 | Michael Walle | qemu_irq irq; |
97 | 770ae571 | Michael Walle | |
98 | 770ae571 | Michael Walle | uint32_t regs[R_MAX]; |
99 | 770ae571 | Michael Walle | }; |
100 | 770ae571 | Michael Walle | typedef struct LM32UartState LM32UartState; |
101 | 770ae571 | Michael Walle | |
102 | 770ae571 | Michael Walle | static void uart_update_irq(LM32UartState *s) |
103 | 770ae571 | Michael Walle | { |
104 | 770ae571 | Michael Walle | unsigned int irq; |
105 | 770ae571 | Michael Walle | |
106 | 770ae571 | Michael Walle | if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
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107 | 770ae571 | Michael Walle | && (s->regs[R_IER] & IER_RLSI)) { |
108 | 770ae571 | Michael Walle | irq = 1;
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109 | 770ae571 | Michael Walle | s->regs[R_IIR] = IIR_ID1 | IIR_ID0; |
110 | 770ae571 | Michael Walle | } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) { |
111 | 770ae571 | Michael Walle | irq = 1;
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112 | 770ae571 | Michael Walle | s->regs[R_IIR] = IIR_ID1; |
113 | 770ae571 | Michael Walle | } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) { |
114 | 770ae571 | Michael Walle | irq = 1;
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115 | 770ae571 | Michael Walle | s->regs[R_IIR] = IIR_ID0; |
116 | 770ae571 | Michael Walle | } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) { |
117 | 770ae571 | Michael Walle | irq = 1;
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118 | 770ae571 | Michael Walle | s->regs[R_IIR] = 0;
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119 | 770ae571 | Michael Walle | } else {
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120 | 770ae571 | Michael Walle | irq = 0;
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121 | 770ae571 | Michael Walle | s->regs[R_IIR] = IIR_STAT; |
122 | 770ae571 | Michael Walle | } |
123 | 770ae571 | Michael Walle | |
124 | 770ae571 | Michael Walle | trace_lm32_uart_irq_state(irq); |
125 | 770ae571 | Michael Walle | qemu_set_irq(s->irq, irq); |
126 | 770ae571 | Michael Walle | } |
127 | 770ae571 | Michael Walle | |
128 | 5f2be17a | Benoît Canet | static uint64_t uart_read(void *opaque, target_phys_addr_t addr, |
129 | 5f2be17a | Benoît Canet | unsigned size)
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130 | 770ae571 | Michael Walle | { |
131 | 770ae571 | Michael Walle | LM32UartState *s = opaque; |
132 | 770ae571 | Michael Walle | uint32_t r = 0;
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133 | 770ae571 | Michael Walle | |
134 | 770ae571 | Michael Walle | addr >>= 2;
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135 | 770ae571 | Michael Walle | switch (addr) {
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136 | 770ae571 | Michael Walle | case R_RXTX:
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137 | 770ae571 | Michael Walle | r = s->regs[R_RXTX]; |
138 | 770ae571 | Michael Walle | s->regs[R_LSR] &= ~LSR_DR; |
139 | 770ae571 | Michael Walle | uart_update_irq(s); |
140 | 770ae571 | Michael Walle | break;
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141 | 770ae571 | Michael Walle | case R_IIR:
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142 | 770ae571 | Michael Walle | case R_LSR:
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143 | 770ae571 | Michael Walle | case R_MSR:
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144 | 770ae571 | Michael Walle | r = s->regs[addr]; |
145 | 770ae571 | Michael Walle | break;
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146 | 770ae571 | Michael Walle | case R_IER:
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147 | 770ae571 | Michael Walle | case R_LCR:
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148 | 770ae571 | Michael Walle | case R_MCR:
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149 | 770ae571 | Michael Walle | case R_DIV:
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150 | 770ae571 | Michael Walle | error_report("lm32_uart: read access to write only register 0x"
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151 | 770ae571 | Michael Walle | TARGET_FMT_plx, addr << 2);
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152 | 770ae571 | Michael Walle | break;
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153 | 770ae571 | Michael Walle | default:
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154 | dd3d6775 | Markus Armbruster | error_report("lm32_uart: read access to unknown register 0x"
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155 | 770ae571 | Michael Walle | TARGET_FMT_plx, addr << 2);
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156 | 770ae571 | Michael Walle | break;
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157 | 770ae571 | Michael Walle | } |
158 | 770ae571 | Michael Walle | |
159 | 770ae571 | Michael Walle | trace_lm32_uart_memory_read(addr << 2, r);
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160 | 770ae571 | Michael Walle | return r;
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161 | 770ae571 | Michael Walle | } |
162 | 770ae571 | Michael Walle | |
163 | 5f2be17a | Benoît Canet | static void uart_write(void *opaque, target_phys_addr_t addr, |
164 | 5f2be17a | Benoît Canet | uint64_t value, unsigned size)
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165 | 770ae571 | Michael Walle | { |
166 | 770ae571 | Michael Walle | LM32UartState *s = opaque; |
167 | 770ae571 | Michael Walle | unsigned char ch = value; |
168 | 770ae571 | Michael Walle | |
169 | 770ae571 | Michael Walle | trace_lm32_uart_memory_write(addr, value); |
170 | 770ae571 | Michael Walle | |
171 | 770ae571 | Michael Walle | addr >>= 2;
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172 | 770ae571 | Michael Walle | switch (addr) {
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173 | 770ae571 | Michael Walle | case R_RXTX:
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174 | 770ae571 | Michael Walle | if (s->chr) {
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175 | 2cc6e0a1 | Anthony Liguori | qemu_chr_fe_write(s->chr, &ch, 1);
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176 | 770ae571 | Michael Walle | } |
177 | 770ae571 | Michael Walle | break;
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178 | 770ae571 | Michael Walle | case R_IER:
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179 | 770ae571 | Michael Walle | case R_LCR:
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180 | 770ae571 | Michael Walle | case R_MCR:
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181 | 770ae571 | Michael Walle | case R_DIV:
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182 | 770ae571 | Michael Walle | s->regs[addr] = value; |
183 | 770ae571 | Michael Walle | break;
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184 | 770ae571 | Michael Walle | case R_IIR:
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185 | 770ae571 | Michael Walle | case R_LSR:
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186 | 770ae571 | Michael Walle | case R_MSR:
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187 | 770ae571 | Michael Walle | error_report("lm32_uart: write access to read only register 0x"
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188 | 770ae571 | Michael Walle | TARGET_FMT_plx, addr << 2);
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189 | 770ae571 | Michael Walle | break;
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190 | 770ae571 | Michael Walle | default:
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191 | dd3d6775 | Markus Armbruster | error_report("lm32_uart: write access to unknown register 0x"
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192 | 770ae571 | Michael Walle | TARGET_FMT_plx, addr << 2);
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193 | 770ae571 | Michael Walle | break;
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194 | 770ae571 | Michael Walle | } |
195 | 770ae571 | Michael Walle | uart_update_irq(s); |
196 | 770ae571 | Michael Walle | } |
197 | 770ae571 | Michael Walle | |
198 | 5f2be17a | Benoît Canet | static const MemoryRegionOps uart_ops = { |
199 | 5f2be17a | Benoît Canet | .read = uart_read, |
200 | 5f2be17a | Benoît Canet | .write = uart_write, |
201 | 5f2be17a | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
202 | 5f2be17a | Benoît Canet | .valid = { |
203 | 5f2be17a | Benoît Canet | .min_access_size = 4,
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204 | 5f2be17a | Benoît Canet | .max_access_size = 4,
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205 | 5f2be17a | Benoît Canet | }, |
206 | 770ae571 | Michael Walle | }; |
207 | 770ae571 | Michael Walle | |
208 | 770ae571 | Michael Walle | static void uart_rx(void *opaque, const uint8_t *buf, int size) |
209 | 770ae571 | Michael Walle | { |
210 | 770ae571 | Michael Walle | LM32UartState *s = opaque; |
211 | 770ae571 | Michael Walle | |
212 | 770ae571 | Michael Walle | if (s->regs[R_LSR] & LSR_DR) {
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213 | 770ae571 | Michael Walle | s->regs[R_LSR] |= LSR_OE; |
214 | 770ae571 | Michael Walle | } |
215 | 770ae571 | Michael Walle | |
216 | 770ae571 | Michael Walle | s->regs[R_LSR] |= LSR_DR; |
217 | 770ae571 | Michael Walle | s->regs[R_RXTX] = *buf; |
218 | 770ae571 | Michael Walle | |
219 | 770ae571 | Michael Walle | uart_update_irq(s); |
220 | 770ae571 | Michael Walle | } |
221 | 770ae571 | Michael Walle | |
222 | 770ae571 | Michael Walle | static int uart_can_rx(void *opaque) |
223 | 770ae571 | Michael Walle | { |
224 | 770ae571 | Michael Walle | LM32UartState *s = opaque; |
225 | 770ae571 | Michael Walle | |
226 | 770ae571 | Michael Walle | return !(s->regs[R_LSR] & LSR_DR);
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227 | 770ae571 | Michael Walle | } |
228 | 770ae571 | Michael Walle | |
229 | 770ae571 | Michael Walle | static void uart_event(void *opaque, int event) |
230 | 770ae571 | Michael Walle | { |
231 | 770ae571 | Michael Walle | } |
232 | 770ae571 | Michael Walle | |
233 | 770ae571 | Michael Walle | static void uart_reset(DeviceState *d) |
234 | 770ae571 | Michael Walle | { |
235 | 770ae571 | Michael Walle | LM32UartState *s = container_of(d, LM32UartState, busdev.qdev); |
236 | 770ae571 | Michael Walle | int i;
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237 | 770ae571 | Michael Walle | |
238 | 770ae571 | Michael Walle | for (i = 0; i < R_MAX; i++) { |
239 | 770ae571 | Michael Walle | s->regs[i] = 0;
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240 | 770ae571 | Michael Walle | } |
241 | 770ae571 | Michael Walle | |
242 | 770ae571 | Michael Walle | /* defaults */
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243 | 770ae571 | Michael Walle | s->regs[R_LSR] = LSR_THRE | LSR_TEMT; |
244 | 770ae571 | Michael Walle | } |
245 | 770ae571 | Michael Walle | |
246 | 770ae571 | Michael Walle | static int lm32_uart_init(SysBusDevice *dev) |
247 | 770ae571 | Michael Walle | { |
248 | 770ae571 | Michael Walle | LM32UartState *s = FROM_SYSBUS(typeof(*s), dev); |
249 | 770ae571 | Michael Walle | |
250 | 770ae571 | Michael Walle | sysbus_init_irq(dev, &s->irq); |
251 | 770ae571 | Michael Walle | |
252 | 5f2be17a | Benoît Canet | memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4); |
253 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
254 | 770ae571 | Michael Walle | |
255 | 0beb4942 | Anthony Liguori | s->chr = qemu_char_get_next_serial(); |
256 | 770ae571 | Michael Walle | if (s->chr) {
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257 | 770ae571 | Michael Walle | qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); |
258 | 770ae571 | Michael Walle | } |
259 | 770ae571 | Michael Walle | |
260 | 770ae571 | Michael Walle | return 0; |
261 | 770ae571 | Michael Walle | } |
262 | 770ae571 | Michael Walle | |
263 | 770ae571 | Michael Walle | static const VMStateDescription vmstate_lm32_uart = { |
264 | 770ae571 | Michael Walle | .name = "lm32-uart",
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265 | 770ae571 | Michael Walle | .version_id = 1,
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266 | 770ae571 | Michael Walle | .minimum_version_id = 1,
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267 | 770ae571 | Michael Walle | .minimum_version_id_old = 1,
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268 | 770ae571 | Michael Walle | .fields = (VMStateField[]) { |
269 | 770ae571 | Michael Walle | VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX), |
270 | 770ae571 | Michael Walle | VMSTATE_END_OF_LIST() |
271 | 770ae571 | Michael Walle | } |
272 | 770ae571 | Michael Walle | }; |
273 | 770ae571 | Michael Walle | |
274 | 999e12bb | Anthony Liguori | static void lm32_uart_class_init(ObjectClass *klass, void *data) |
275 | 999e12bb | Anthony Liguori | { |
276 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
277 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
278 | 999e12bb | Anthony Liguori | |
279 | 999e12bb | Anthony Liguori | k->init = lm32_uart_init; |
280 | 39bffca2 | Anthony Liguori | dc->reset = uart_reset; |
281 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_lm32_uart; |
282 | 999e12bb | Anthony Liguori | } |
283 | 999e12bb | Anthony Liguori | |
284 | 39bffca2 | Anthony Liguori | static TypeInfo lm32_uart_info = {
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285 | 39bffca2 | Anthony Liguori | .name = "lm32-uart",
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286 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
287 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(LM32UartState),
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288 | 39bffca2 | Anthony Liguori | .class_init = lm32_uart_class_init, |
289 | 770ae571 | Michael Walle | }; |
290 | 770ae571 | Michael Walle | |
291 | 770ae571 | Michael Walle | static void lm32_uart_register(void) |
292 | 770ae571 | Michael Walle | { |
293 | 39bffca2 | Anthony Liguori | type_register_static(&lm32_uart_info); |
294 | 770ae571 | Michael Walle | } |
295 | 770ae571 | Michael Walle | |
296 | 770ae571 | Michael Walle | device_init(lm32_uart_register) |