root / hw / slavio_intctl.c @ 07a8de35
History | View | Annotate | Download (13.4 kB)
1 | e80cfcfc | bellard | /*
|
---|---|---|---|
2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO interrupt controller emulation
|
3 | 5fafdf24 | ths | *
|
4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
|
9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
|
12 | e80cfcfc | bellard | *
|
13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
|
15 | e80cfcfc | bellard | *
|
16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | e80cfcfc | bellard | * THE SOFTWARE.
|
23 | e80cfcfc | bellard | */
|
24 | a1961a4b | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 376253ec | aliguori | #include "monitor.h" |
27 | a1961a4b | Blue Swirl | #include "sysbus.h" |
28 | 87ecb68b | pbrook | |
29 | e80cfcfc | bellard | //#define DEBUG_IRQ_COUNT
|
30 | 66321a11 | bellard | //#define DEBUG_IRQ
|
31 | 66321a11 | bellard | |
32 | 66321a11 | bellard | #ifdef DEBUG_IRQ
|
33 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
|
34 | 001faf32 | Blue Swirl | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
35 | 66321a11 | bellard | #else
|
36 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
|
37 | 66321a11 | bellard | #endif
|
38 | e80cfcfc | bellard | |
39 | e80cfcfc | bellard | /*
|
40 | e80cfcfc | bellard | * Registers of interrupt controller in sun4m.
|
41 | e80cfcfc | bellard | *
|
42 | e80cfcfc | bellard | * This is the interrupt controller part of chip STP2001 (Slave I/O), also
|
43 | e80cfcfc | bellard | * produced as NCR89C105. See
|
44 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
45 | e80cfcfc | bellard | *
|
46 | e80cfcfc | bellard | * There is a system master controller and one for each cpu.
|
47 | 5fafdf24 | ths | *
|
48 | e80cfcfc | bellard | */
|
49 | e80cfcfc | bellard | |
50 | e80cfcfc | bellard | #define MAX_CPUS 16 |
51 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
52 | e80cfcfc | bellard | |
53 | a1961a4b | Blue Swirl | struct SLAVIO_INTCTLState;
|
54 | a1961a4b | Blue Swirl | |
55 | a1961a4b | Blue Swirl | typedef struct SLAVIO_CPUINTCTLState { |
56 | a1961a4b | Blue Swirl | uint32_t intreg_pending; |
57 | a1961a4b | Blue Swirl | struct SLAVIO_INTCTLState *master;
|
58 | a1961a4b | Blue Swirl | uint32_t cpu; |
59 | 462eda24 | Blue Swirl | uint32_t irl_out; |
60 | a1961a4b | Blue Swirl | } SLAVIO_CPUINTCTLState; |
61 | a8f48dcc | blueswir1 | |
62 | e80cfcfc | bellard | typedef struct SLAVIO_INTCTLState { |
63 | a1961a4b | Blue Swirl | SysBusDevice busdev; |
64 | e80cfcfc | bellard | uint32_t intregm_pending; |
65 | e80cfcfc | bellard | uint32_t intregm_disabled; |
66 | e80cfcfc | bellard | uint32_t target_cpu; |
67 | e80cfcfc | bellard | #ifdef DEBUG_IRQ_COUNT
|
68 | e80cfcfc | bellard | uint64_t irq_count[32];
|
69 | e80cfcfc | bellard | #endif
|
70 | a1961a4b | Blue Swirl | qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; |
71 | a1961a4b | Blue Swirl | SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; |
72 | e80cfcfc | bellard | } SLAVIO_INTCTLState; |
73 | e80cfcfc | bellard | |
74 | e80cfcfc | bellard | #define INTCTL_MAXADDR 0xf |
75 | 5aca8c3b | blueswir1 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) |
76 | a8f48dcc | blueswir1 | #define INTCTLM_SIZE 0x14 |
77 | 80be36b8 | blueswir1 | #define MASTER_IRQ_MASK ~0x0fa2007f |
78 | 9a87ce9b | blueswir1 | #define MASTER_DISABLE 0x80000000 |
79 | 6341fdcb | blueswir1 | #define CPU_SOFTIRQ_MASK 0xfffe0000 |
80 | 462eda24 | Blue Swirl | #define CPU_IRQ_INT15_IN (1 << 15) |
81 | 462eda24 | Blue Swirl | #define CPU_IRQ_TIMER_IN (1 << 14) |
82 | 9a87ce9b | blueswir1 | |
83 | 0d0a7e69 | Blue Swirl | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); |
84 | e80cfcfc | bellard | |
85 | e80cfcfc | bellard | // per-cpu interrupt controller
|
86 | c227f099 | Anthony Liguori | static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) |
87 | e80cfcfc | bellard | { |
88 | a8f48dcc | blueswir1 | SLAVIO_CPUINTCTLState *s = opaque; |
89 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
90 | e80cfcfc | bellard | |
91 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
92 | e80cfcfc | bellard | switch (saddr) {
|
93 | e80cfcfc | bellard | case 0: |
94 | a8f48dcc | blueswir1 | ret = s->intreg_pending; |
95 | dd4131b3 | blueswir1 | break;
|
96 | e80cfcfc | bellard | default:
|
97 | dd4131b3 | blueswir1 | ret = 0;
|
98 | dd4131b3 | blueswir1 | break;
|
99 | e80cfcfc | bellard | } |
100 | 3c4cf535 | blueswir1 | DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret); |
101 | dd4131b3 | blueswir1 | |
102 | dd4131b3 | blueswir1 | return ret;
|
103 | e80cfcfc | bellard | } |
104 | e80cfcfc | bellard | |
105 | c227f099 | Anthony Liguori | static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, |
106 | 77f193da | blueswir1 | uint32_t val) |
107 | e80cfcfc | bellard | { |
108 | a8f48dcc | blueswir1 | SLAVIO_CPUINTCTLState *s = opaque; |
109 | e80cfcfc | bellard | uint32_t saddr; |
110 | e80cfcfc | bellard | |
111 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
112 | 3c4cf535 | blueswir1 | DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val); |
113 | e80cfcfc | bellard | switch (saddr) {
|
114 | e80cfcfc | bellard | case 1: // clear pending softints |
115 | 462eda24 | Blue Swirl | val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; |
116 | a8f48dcc | blueswir1 | s->intreg_pending &= ~val; |
117 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s->master, 1);
|
118 | a8f48dcc | blueswir1 | DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
|
119 | a8f48dcc | blueswir1 | s->intreg_pending); |
120 | f930d07e | blueswir1 | break;
|
121 | e80cfcfc | bellard | case 2: // set softint |
122 | 6341fdcb | blueswir1 | val &= CPU_SOFTIRQ_MASK; |
123 | a8f48dcc | blueswir1 | s->intreg_pending |= val; |
124 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s->master, 1);
|
125 | a8f48dcc | blueswir1 | DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
|
126 | a8f48dcc | blueswir1 | s->intreg_pending); |
127 | f930d07e | blueswir1 | break;
|
128 | e80cfcfc | bellard | default:
|
129 | f930d07e | blueswir1 | break;
|
130 | e80cfcfc | bellard | } |
131 | e80cfcfc | bellard | } |
132 | e80cfcfc | bellard | |
133 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = { |
134 | 7c560456 | blueswir1 | NULL,
|
135 | 7c560456 | blueswir1 | NULL,
|
136 | e80cfcfc | bellard | slavio_intctl_mem_readl, |
137 | e80cfcfc | bellard | }; |
138 | e80cfcfc | bellard | |
139 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = { |
140 | 7c560456 | blueswir1 | NULL,
|
141 | 7c560456 | blueswir1 | NULL,
|
142 | e80cfcfc | bellard | slavio_intctl_mem_writel, |
143 | e80cfcfc | bellard | }; |
144 | e80cfcfc | bellard | |
145 | e80cfcfc | bellard | // master system interrupt controller
|
146 | c227f099 | Anthony Liguori | static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) |
147 | e80cfcfc | bellard | { |
148 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
149 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
150 | e80cfcfc | bellard | |
151 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
152 | e80cfcfc | bellard | switch (saddr) {
|
153 | e80cfcfc | bellard | case 0: |
154 | 9a87ce9b | blueswir1 | ret = s->intregm_pending & ~MASTER_DISABLE; |
155 | dd4131b3 | blueswir1 | break;
|
156 | e80cfcfc | bellard | case 1: |
157 | 80be36b8 | blueswir1 | ret = s->intregm_disabled & MASTER_IRQ_MASK; |
158 | dd4131b3 | blueswir1 | break;
|
159 | e80cfcfc | bellard | case 4: |
160 | dd4131b3 | blueswir1 | ret = s->target_cpu; |
161 | dd4131b3 | blueswir1 | break;
|
162 | e80cfcfc | bellard | default:
|
163 | dd4131b3 | blueswir1 | ret = 0;
|
164 | dd4131b3 | blueswir1 | break;
|
165 | e80cfcfc | bellard | } |
166 | 1569fc29 | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
167 | dd4131b3 | blueswir1 | |
168 | dd4131b3 | blueswir1 | return ret;
|
169 | e80cfcfc | bellard | } |
170 | e80cfcfc | bellard | |
171 | c227f099 | Anthony Liguori | static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, |
172 | 77f193da | blueswir1 | uint32_t val) |
173 | e80cfcfc | bellard | { |
174 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
175 | e80cfcfc | bellard | uint32_t saddr; |
176 | e80cfcfc | bellard | |
177 | a8f48dcc | blueswir1 | saddr = addr >> 2;
|
178 | 1569fc29 | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
179 | e80cfcfc | bellard | switch (saddr) {
|
180 | e80cfcfc | bellard | case 2: // clear (enable) |
181 | f930d07e | blueswir1 | // Force clear unused bits
|
182 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
183 | f930d07e | blueswir1 | s->intregm_disabled &= ~val; |
184 | 77f193da | blueswir1 | DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
|
185 | 77f193da | blueswir1 | s->intregm_disabled); |
186 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
187 | f930d07e | blueswir1 | break;
|
188 | e80cfcfc | bellard | case 3: // set (disable, clear pending) |
189 | f930d07e | blueswir1 | // Force clear unused bits
|
190 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
191 | f930d07e | blueswir1 | s->intregm_disabled |= val; |
192 | f930d07e | blueswir1 | s->intregm_pending &= ~val; |
193 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
194 | 77f193da | blueswir1 | DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
|
195 | 77f193da | blueswir1 | s->intregm_disabled); |
196 | f930d07e | blueswir1 | break;
|
197 | e80cfcfc | bellard | case 4: |
198 | f930d07e | blueswir1 | s->target_cpu = val & (MAX_CPUS - 1);
|
199 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
200 | f930d07e | blueswir1 | DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
201 | f930d07e | blueswir1 | break;
|
202 | e80cfcfc | bellard | default:
|
203 | f930d07e | blueswir1 | break;
|
204 | e80cfcfc | bellard | } |
205 | e80cfcfc | bellard | } |
206 | e80cfcfc | bellard | |
207 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = { |
208 | 7c560456 | blueswir1 | NULL,
|
209 | 7c560456 | blueswir1 | NULL,
|
210 | e80cfcfc | bellard | slavio_intctlm_mem_readl, |
211 | e80cfcfc | bellard | }; |
212 | e80cfcfc | bellard | |
213 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = { |
214 | 7c560456 | blueswir1 | NULL,
|
215 | 7c560456 | blueswir1 | NULL,
|
216 | e80cfcfc | bellard | slavio_intctlm_mem_writel, |
217 | e80cfcfc | bellard | }; |
218 | e80cfcfc | bellard | |
219 | d453c2c3 | Blue Swirl | void slavio_pic_info(Monitor *mon, DeviceState *dev)
|
220 | e80cfcfc | bellard | { |
221 | d453c2c3 | Blue Swirl | SysBusDevice *sd; |
222 | d453c2c3 | Blue Swirl | SLAVIO_INTCTLState *s; |
223 | e80cfcfc | bellard | int i;
|
224 | e80cfcfc | bellard | |
225 | d453c2c3 | Blue Swirl | sd = sysbus_from_qdev(dev); |
226 | d453c2c3 | Blue Swirl | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
227 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
228 | 376253ec | aliguori | monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
|
229 | a1961a4b | Blue Swirl | s->slaves[i].intreg_pending); |
230 | e80cfcfc | bellard | } |
231 | 376253ec | aliguori | monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
|
232 | 376253ec | aliguori | s->intregm_pending, s->intregm_disabled); |
233 | e80cfcfc | bellard | } |
234 | e80cfcfc | bellard | |
235 | d453c2c3 | Blue Swirl | void slavio_irq_info(Monitor *mon, DeviceState *dev)
|
236 | e80cfcfc | bellard | { |
237 | e80cfcfc | bellard | #ifndef DEBUG_IRQ_COUNT
|
238 | 376253ec | aliguori | monitor_printf(mon, "irq statistic code not compiled.\n");
|
239 | e80cfcfc | bellard | #else
|
240 | d453c2c3 | Blue Swirl | SysBusDevice *sd; |
241 | d453c2c3 | Blue Swirl | SLAVIO_INTCTLState *s; |
242 | e80cfcfc | bellard | int i;
|
243 | e80cfcfc | bellard | int64_t count; |
244 | e80cfcfc | bellard | |
245 | d453c2c3 | Blue Swirl | sd = sysbus_from_qdev(dev); |
246 | d453c2c3 | Blue Swirl | s = FROM_SYSBUS(SLAVIO_INTCTLState, sd); |
247 | 376253ec | aliguori | monitor_printf(mon, "IRQ statistics:\n");
|
248 | e80cfcfc | bellard | for (i = 0; i < 32; i++) { |
249 | e80cfcfc | bellard | count = s->irq_count[i]; |
250 | e80cfcfc | bellard | if (count > 0) |
251 | 376253ec | aliguori | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); |
252 | e80cfcfc | bellard | } |
253 | e80cfcfc | bellard | #endif
|
254 | e80cfcfc | bellard | } |
255 | e80cfcfc | bellard | |
256 | 68556e2e | Blue Swirl | static const uint32_t intbit_to_level[] = { |
257 | 462eda24 | Blue Swirl | 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, |
258 | 462eda24 | Blue Swirl | 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, |
259 | 68556e2e | Blue Swirl | }; |
260 | 68556e2e | Blue Swirl | |
261 | 0d0a7e69 | Blue Swirl | static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) |
262 | 66321a11 | bellard | { |
263 | 327ac2e7 | blueswir1 | uint32_t pending = s->intregm_pending, pil_pending; |
264 | 327ac2e7 | blueswir1 | unsigned int i, j; |
265 | 66321a11 | bellard | |
266 | 66321a11 | bellard | pending &= ~s->intregm_disabled; |
267 | 66321a11 | bellard | |
268 | b3a23197 | blueswir1 | DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
|
269 | ba3c64fb | bellard | for (i = 0; i < MAX_CPUS; i++) { |
270 | 327ac2e7 | blueswir1 | pil_pending = 0;
|
271 | 462eda24 | Blue Swirl | |
272 | 462eda24 | Blue Swirl | /* If we are the current interrupt target, get hard interrupts */
|
273 | 9a87ce9b | blueswir1 | if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
|
274 | b3a23197 | blueswir1 | (i == s->target_cpu)) { |
275 | b3a23197 | blueswir1 | for (j = 0; j < 32; j++) { |
276 | 462eda24 | Blue Swirl | if ((pending & (1 << j)) && intbit_to_level[j]) { |
277 | 68556e2e | Blue Swirl | pil_pending |= 1 << intbit_to_level[j];
|
278 | 462eda24 | Blue Swirl | } |
279 | 462eda24 | Blue Swirl | } |
280 | 462eda24 | Blue Swirl | } |
281 | 462eda24 | Blue Swirl | |
282 | 462eda24 | Blue Swirl | /* Calculate current pending hard interrupts for display */
|
283 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | |
284 | 462eda24 | Blue Swirl | CPU_IRQ_TIMER_IN; |
285 | 462eda24 | Blue Swirl | if (i == s->target_cpu) {
|
286 | 462eda24 | Blue Swirl | for (j = 0; j < 32; j++) { |
287 | 462eda24 | Blue Swirl | if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) { |
288 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
|
289 | 462eda24 | Blue Swirl | } |
290 | b3a23197 | blueswir1 | } |
291 | b3a23197 | blueswir1 | } |
292 | 462eda24 | Blue Swirl | |
293 | 462eda24 | Blue Swirl | /* Level 15 and CPU timer interrupts are not maskable */
|
294 | 462eda24 | Blue Swirl | pil_pending |= s->slaves[i].intreg_pending & |
295 | 462eda24 | Blue Swirl | (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); |
296 | 462eda24 | Blue Swirl | |
297 | 462eda24 | Blue Swirl | /* Add soft interrupts */
|
298 | a1961a4b | Blue Swirl | pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
|
299 | 327ac2e7 | blueswir1 | |
300 | 0d0a7e69 | Blue Swirl | if (set_irqs) {
|
301 | 462eda24 | Blue Swirl | for (j = MAX_PILS; j > 0; j--) { |
302 | 0d0a7e69 | Blue Swirl | if (pil_pending & (1 << j)) { |
303 | 462eda24 | Blue Swirl | if (!(s->slaves[i].irl_out & (1 << j))) { |
304 | 0d0a7e69 | Blue Swirl | qemu_irq_raise(s->cpu_irqs[i][j]); |
305 | 0d0a7e69 | Blue Swirl | } |
306 | 0d0a7e69 | Blue Swirl | } else {
|
307 | 462eda24 | Blue Swirl | if (s->slaves[i].irl_out & (1 << j)) { |
308 | 0d0a7e69 | Blue Swirl | qemu_irq_lower(s->cpu_irqs[i][j]); |
309 | 0d0a7e69 | Blue Swirl | } |
310 | 0d0a7e69 | Blue Swirl | } |
311 | ba3c64fb | bellard | } |
312 | ba3c64fb | bellard | } |
313 | 462eda24 | Blue Swirl | s->slaves[i].irl_out = pil_pending; |
314 | ba3c64fb | bellard | } |
315 | 66321a11 | bellard | } |
316 | 66321a11 | bellard | |
317 | e80cfcfc | bellard | /*
|
318 | e80cfcfc | bellard | * "irq" here is the bit number in the system interrupt register to
|
319 | e80cfcfc | bellard | * separate serial and keyboard interrupts sharing a level.
|
320 | e80cfcfc | bellard | */
|
321 | d7edfd27 | blueswir1 | static void slavio_set_irq(void *opaque, int irq, int level) |
322 | e80cfcfc | bellard | { |
323 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
324 | b3a23197 | blueswir1 | uint32_t mask = 1 << irq;
|
325 | 68556e2e | Blue Swirl | uint32_t pil = intbit_to_level[irq]; |
326 | 462eda24 | Blue Swirl | unsigned int i; |
327 | b3a23197 | blueswir1 | |
328 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
|
329 | b3a23197 | blueswir1 | level); |
330 | b3a23197 | blueswir1 | if (pil > 0) { |
331 | b3a23197 | blueswir1 | if (level) {
|
332 | 327ac2e7 | blueswir1 | #ifdef DEBUG_IRQ_COUNT
|
333 | 327ac2e7 | blueswir1 | s->irq_count[pil]++; |
334 | 327ac2e7 | blueswir1 | #endif
|
335 | b3a23197 | blueswir1 | s->intregm_pending |= mask; |
336 | 462eda24 | Blue Swirl | if (pil == 15) { |
337 | 462eda24 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
338 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending |= 1 << pil;
|
339 | 462eda24 | Blue Swirl | } |
340 | 462eda24 | Blue Swirl | } |
341 | b3a23197 | blueswir1 | } else {
|
342 | b3a23197 | blueswir1 | s->intregm_pending &= ~mask; |
343 | 462eda24 | Blue Swirl | if (pil == 15) { |
344 | 462eda24 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
345 | 462eda24 | Blue Swirl | s->slaves[i].intreg_pending &= ~(1 << pil);
|
346 | 462eda24 | Blue Swirl | } |
347 | 462eda24 | Blue Swirl | } |
348 | b3a23197 | blueswir1 | } |
349 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
350 | e80cfcfc | bellard | } |
351 | e80cfcfc | bellard | } |
352 | e80cfcfc | bellard | |
353 | d7edfd27 | blueswir1 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) |
354 | ba3c64fb | bellard | { |
355 | ba3c64fb | bellard | SLAVIO_INTCTLState *s = opaque; |
356 | ba3c64fb | bellard | |
357 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
|
358 | d7edfd27 | blueswir1 | |
359 | e3a79bca | blueswir1 | if (level) {
|
360 | 462eda24 | Blue Swirl | s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; |
361 | e3a79bca | blueswir1 | } else {
|
362 | 462eda24 | Blue Swirl | s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; |
363 | e3a79bca | blueswir1 | } |
364 | d7edfd27 | blueswir1 | |
365 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 1);
|
366 | ba3c64fb | bellard | } |
367 | ba3c64fb | bellard | |
368 | a1961a4b | Blue Swirl | static void slavio_set_irq_all(void *opaque, int irq, int level) |
369 | a1961a4b | Blue Swirl | { |
370 | a1961a4b | Blue Swirl | if (irq < 32) { |
371 | a1961a4b | Blue Swirl | slavio_set_irq(opaque, irq, level); |
372 | a1961a4b | Blue Swirl | } else {
|
373 | a1961a4b | Blue Swirl | slavio_set_timer_irq_cpu(opaque, irq - 32, level);
|
374 | a1961a4b | Blue Swirl | } |
375 | a1961a4b | Blue Swirl | } |
376 | a1961a4b | Blue Swirl | |
377 | e59fb374 | Juan Quintela | static int vmstate_intctl_post_load(void *opaque, int version_id) |
378 | e80cfcfc | bellard | { |
379 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
380 | 3b46e624 | ths | |
381 | c9e95029 | Blue Swirl | slavio_check_interrupts(s, 0);
|
382 | c9e95029 | Blue Swirl | return 0; |
383 | e80cfcfc | bellard | } |
384 | e80cfcfc | bellard | |
385 | c9e95029 | Blue Swirl | static const VMStateDescription vmstate_intctl_cpu = { |
386 | c9e95029 | Blue Swirl | .name ="slavio_intctl_cpu",
|
387 | c9e95029 | Blue Swirl | .version_id = 1,
|
388 | c9e95029 | Blue Swirl | .minimum_version_id = 1,
|
389 | c9e95029 | Blue Swirl | .minimum_version_id_old = 1,
|
390 | c9e95029 | Blue Swirl | .fields = (VMStateField []) { |
391 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), |
392 | c9e95029 | Blue Swirl | VMSTATE_END_OF_LIST() |
393 | c9e95029 | Blue Swirl | } |
394 | c9e95029 | Blue Swirl | }; |
395 | e80cfcfc | bellard | |
396 | c9e95029 | Blue Swirl | static const VMStateDescription vmstate_intctl = { |
397 | c9e95029 | Blue Swirl | .name ="slavio_intctl",
|
398 | c9e95029 | Blue Swirl | .version_id = 1,
|
399 | c9e95029 | Blue Swirl | .minimum_version_id = 1,
|
400 | c9e95029 | Blue Swirl | .minimum_version_id_old = 1,
|
401 | 752ff2fa | Juan Quintela | .post_load = vmstate_intctl_post_load, |
402 | c9e95029 | Blue Swirl | .fields = (VMStateField []) { |
403 | c9e95029 | Blue Swirl | VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
|
404 | c9e95029 | Blue Swirl | vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), |
405 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), |
406 | c9e95029 | Blue Swirl | VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), |
407 | c9e95029 | Blue Swirl | VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), |
408 | c9e95029 | Blue Swirl | VMSTATE_END_OF_LIST() |
409 | e80cfcfc | bellard | } |
410 | c9e95029 | Blue Swirl | }; |
411 | e80cfcfc | bellard | |
412 | 78971d57 | Blue Swirl | static void slavio_intctl_reset(DeviceState *d) |
413 | e80cfcfc | bellard | { |
414 | 78971d57 | Blue Swirl | SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev); |
415 | e80cfcfc | bellard | int i;
|
416 | e80cfcfc | bellard | |
417 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
418 | a1961a4b | Blue Swirl | s->slaves[i].intreg_pending = 0;
|
419 | 462eda24 | Blue Swirl | s->slaves[i].irl_out = 0;
|
420 | e80cfcfc | bellard | } |
421 | 9a87ce9b | blueswir1 | s->intregm_disabled = ~MASTER_IRQ_MASK; |
422 | e80cfcfc | bellard | s->intregm_pending = 0;
|
423 | e80cfcfc | bellard | s->target_cpu = 0;
|
424 | 0d0a7e69 | Blue Swirl | slavio_check_interrupts(s, 0);
|
425 | e80cfcfc | bellard | } |
426 | e80cfcfc | bellard | |
427 | 81a322d4 | Gerd Hoffmann | static int slavio_intctl_init1(SysBusDevice *dev) |
428 | e80cfcfc | bellard | { |
429 | a1961a4b | Blue Swirl | SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); |
430 | ee6847d1 | Gerd Hoffmann | int io_memory;
|
431 | a1961a4b | Blue Swirl | unsigned int i, j; |
432 | e80cfcfc | bellard | |
433 | a1961a4b | Blue Swirl | qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
|
434 | a1961a4b | Blue Swirl | io_memory = cpu_register_io_memory(slavio_intctlm_mem_read, |
435 | a1961a4b | Blue Swirl | slavio_intctlm_mem_write, s); |
436 | a1961a4b | Blue Swirl | sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); |
437 | e80cfcfc | bellard | |
438 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
439 | a1961a4b | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
440 | a1961a4b | Blue Swirl | sysbus_init_irq(dev, &s->cpu_irqs[i][j]); |
441 | a1961a4b | Blue Swirl | } |
442 | a1961a4b | Blue Swirl | io_memory = cpu_register_io_memory(slavio_intctl_mem_read, |
443 | a1961a4b | Blue Swirl | slavio_intctl_mem_write, |
444 | a1961a4b | Blue Swirl | &s->slaves[i]); |
445 | a1961a4b | Blue Swirl | sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); |
446 | a1961a4b | Blue Swirl | s->slaves[i].cpu = i; |
447 | a1961a4b | Blue Swirl | s->slaves[i].master = s; |
448 | a1961a4b | Blue Swirl | } |
449 | 78971d57 | Blue Swirl | |
450 | 81a322d4 | Gerd Hoffmann | return 0; |
451 | a1961a4b | Blue Swirl | } |
452 | a1961a4b | Blue Swirl | |
453 | a1961a4b | Blue Swirl | static SysBusDeviceInfo slavio_intctl_info = {
|
454 | a1961a4b | Blue Swirl | .init = slavio_intctl_init1, |
455 | a1961a4b | Blue Swirl | .qdev.name = "slavio_intctl",
|
456 | a1961a4b | Blue Swirl | .qdev.size = sizeof(SLAVIO_INTCTLState),
|
457 | 78971d57 | Blue Swirl | .qdev.vmsd = &vmstate_intctl, |
458 | 78971d57 | Blue Swirl | .qdev.reset = slavio_intctl_reset, |
459 | a1961a4b | Blue Swirl | }; |
460 | d7edfd27 | blueswir1 | |
461 | a1961a4b | Blue Swirl | static void slavio_intctl_register_devices(void) |
462 | a1961a4b | Blue Swirl | { |
463 | a1961a4b | Blue Swirl | sysbus_register_withprop(&slavio_intctl_info); |
464 | e80cfcfc | bellard | } |
465 | a1961a4b | Blue Swirl | |
466 | a1961a4b | Blue Swirl | device_init(slavio_intctl_register_devices) |