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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation cpu definitions for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 79aceca5 | bellard | #include <endian.h> |
24 | 79aceca5 | bellard | #include <asm/byteorder.h> |
25 | 79aceca5 | bellard | |
26 | 79aceca5 | bellard | #include "cpu-defs.h" |
27 | 79aceca5 | bellard | |
28 | 79aceca5 | bellard | /*** Sign extend constants ***/
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29 | 79aceca5 | bellard | /* 8 to 32 bits */
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30 | 79aceca5 | bellard | static inline int32_t s_ext8 (uint8_t value) |
31 | 79aceca5 | bellard | { |
32 | 79aceca5 | bellard | int8_t *tmp = &value; |
33 | 79aceca5 | bellard | |
34 | 79aceca5 | bellard | return *tmp;
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35 | 79aceca5 | bellard | } |
36 | 79aceca5 | bellard | |
37 | 79aceca5 | bellard | /* 16 to 32 bits */
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38 | 79aceca5 | bellard | static inline int32_t s_ext16 (uint16_t value) |
39 | 79aceca5 | bellard | { |
40 | 79aceca5 | bellard | int16_t *tmp = &value; |
41 | 79aceca5 | bellard | |
42 | 79aceca5 | bellard | return *tmp;
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43 | 79aceca5 | bellard | } |
44 | 79aceca5 | bellard | |
45 | 79aceca5 | bellard | /* 24 to 32 bits */
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46 | 79aceca5 | bellard | static inline int32_t s_ext24 (uint32_t value) |
47 | 79aceca5 | bellard | { |
48 | 79aceca5 | bellard | uint16_t utmp = (value >> 8) & 0xFFFF; |
49 | 79aceca5 | bellard | int16_t *tmp = &utmp; |
50 | 79aceca5 | bellard | |
51 | 79aceca5 | bellard | return (*tmp << 8) | (value & 0xFF); |
52 | 79aceca5 | bellard | } |
53 | 79aceca5 | bellard | |
54 | 79aceca5 | bellard | #include "config.h" |
55 | 79aceca5 | bellard | #include <setjmp.h> |
56 | 79aceca5 | bellard | |
57 | 79aceca5 | bellard | /* Floting point status and control register */
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58 | 79aceca5 | bellard | #define FPSCR_FX 31 |
59 | 79aceca5 | bellard | #define FPSCR_FEX 30 |
60 | 79aceca5 | bellard | #define FPSCR_VX 29 |
61 | 79aceca5 | bellard | #define FPSCR_OX 28 |
62 | 79aceca5 | bellard | #define FPSCR_UX 27 |
63 | 79aceca5 | bellard | #define FPSCR_ZX 26 |
64 | 79aceca5 | bellard | #define FPSCR_XX 25 |
65 | 79aceca5 | bellard | #define FPSCR_VXSNAN 24 |
66 | 79aceca5 | bellard | #define FPSCR_VXISI 26 |
67 | 79aceca5 | bellard | #define FPSCR_VXIDI 25 |
68 | 79aceca5 | bellard | #define FPSCR_VXZDZ 21 |
69 | 79aceca5 | bellard | #define FPSCR_VXIMZ 20 |
70 | 79aceca5 | bellard | |
71 | 79aceca5 | bellard | #define FPSCR_VXVC 18 |
72 | 79aceca5 | bellard | #define FPSCR_FR 17 |
73 | 79aceca5 | bellard | #define FPSCR_FI 16 |
74 | 79aceca5 | bellard | #define FPSCR_FPRF 11 |
75 | 79aceca5 | bellard | #define FPSCR_VXSOFT 9 |
76 | 79aceca5 | bellard | #define FPSCR_VXSQRT 8 |
77 | 79aceca5 | bellard | #define FPSCR_VXCVI 7 |
78 | 79aceca5 | bellard | #define FPSCR_OE 6 |
79 | 79aceca5 | bellard | #define FPSCR_UE 5 |
80 | 79aceca5 | bellard | #define FPSCR_ZE 4 |
81 | 79aceca5 | bellard | #define FPSCR_XE 3 |
82 | 79aceca5 | bellard | #define FPSCR_NI 2 |
83 | 79aceca5 | bellard | #define FPSCR_RN 0 |
84 | 79aceca5 | bellard | #define fpscr_fx env->fpscr[FPSCR_FX]
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85 | 79aceca5 | bellard | #define fpscr_fex env->fpscr[FPSCR_FEX]
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86 | 79aceca5 | bellard | #define fpscr_vx env->fpscr[FPSCR_VX]
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87 | 79aceca5 | bellard | #define fpscr_ox env->fpscr[FPSCR_OX]
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88 | 79aceca5 | bellard | #define fpscr_ux env->fpscr[FPSCR_UX]
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89 | 79aceca5 | bellard | #define fpscr_zx env->fpscr[FPSCR_ZX]
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90 | 79aceca5 | bellard | #define fpscr_xx env->fpscr[FPSCR_XX]
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91 | 79aceca5 | bellard | #define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN]
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92 | 79aceca5 | bellard | #define fpscr_vxisi env->fpscr[FPSCR_VXISI]
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93 | 79aceca5 | bellard | #define fpscr_vxidi env->fpscr[FPSCR_VXIDI]
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94 | 79aceca5 | bellard | #define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ]
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95 | 79aceca5 | bellard | #define fpscr_vximz env->fpscr[FPSCR_VXIMZ]
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96 | 79aceca5 | bellard | #define fpscr_fr env->fpscr[FPSCR_FR]
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97 | 79aceca5 | bellard | #define fpscr_fi env->fpscr[FPSCR_FI]
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98 | 79aceca5 | bellard | #define fpscr_fprf env->fpscr[FPSCR_FPRF]
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99 | 79aceca5 | bellard | #define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT]
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100 | 79aceca5 | bellard | #define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT]
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101 | 79aceca5 | bellard | #define fpscr_oe env->fpscr[FPSCR_OE]
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102 | 79aceca5 | bellard | #define fpscr_ue env->fpscr[FPSCR_UE]
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103 | 79aceca5 | bellard | #define fpscr_ze env->fpscr[FPSCR_ZE]
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104 | 79aceca5 | bellard | #define fpscr_xe env->fpscr[FPSCR_XE]
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105 | 79aceca5 | bellard | #define fpscr_ni env->fpscr[FPSCR_NI]
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106 | 79aceca5 | bellard | #define fpscr_rn env->fpscr[FPSCR_RN]
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107 | 79aceca5 | bellard | |
108 | 79aceca5 | bellard | /* Supervisor mode registers */
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109 | 79aceca5 | bellard | /* Machine state register */
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110 | 79aceca5 | bellard | #define MSR_POW 18 |
111 | 79aceca5 | bellard | #define MSR_ILE 16 |
112 | 79aceca5 | bellard | #define MSR_EE 15 |
113 | 79aceca5 | bellard | #define MSR_PR 14 |
114 | 79aceca5 | bellard | #define MSR_FP 13 |
115 | 79aceca5 | bellard | #define MSR_ME 12 |
116 | 79aceca5 | bellard | #define MSR_FE0 11 |
117 | 79aceca5 | bellard | #define MSR_SE 10 |
118 | 79aceca5 | bellard | #define MSR_BE 9 |
119 | 79aceca5 | bellard | #define MSR_FE1 8 |
120 | 79aceca5 | bellard | #define MSR_IP 6 |
121 | 79aceca5 | bellard | #define MSR_IR 5 |
122 | 79aceca5 | bellard | #define MSR_DR 4 |
123 | 79aceca5 | bellard | #define MSR_RI 1 |
124 | 79aceca5 | bellard | #define MSR_LE 0 |
125 | 79aceca5 | bellard | #define msr_pow env->msr[MSR_POW]
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126 | 79aceca5 | bellard | #define msr_ile env->msr[MSR_ILE]
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127 | 79aceca5 | bellard | #define msr_ee env->msr[MSR_EE]
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128 | 79aceca5 | bellard | #define msr_pr env->msr[MSR_PR]
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129 | 79aceca5 | bellard | #define msr_fp env->msr[MSR_FP]
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130 | 79aceca5 | bellard | #define msr_me env->msr[MSR_ME]
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131 | 79aceca5 | bellard | #define msr_fe0 env->msr[MSR_FE0]
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132 | 79aceca5 | bellard | #define msr_se env->msr[MSR_SE]
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133 | 79aceca5 | bellard | #define msr_be env->msr[MSR_BE]
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134 | 79aceca5 | bellard | #define msr_fe1 env->msr[MSR_FE1]
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135 | 79aceca5 | bellard | #define msr_ip env->msr[MSR_IP]
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136 | 79aceca5 | bellard | #define msr_ir env->msr[MSR_IR]
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137 | 79aceca5 | bellard | #define msr_dr env->msr[MSR_DR]
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138 | 79aceca5 | bellard | #define msr_ri env->msr[MSR_RI]
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139 | 79aceca5 | bellard | #define msr_le env->msr[MSR_LE]
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140 | 79aceca5 | bellard | |
141 | 79aceca5 | bellard | /* Segment registers */
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142 | 79aceca5 | bellard | typedef struct ppc_sr_t { |
143 | 79aceca5 | bellard | uint32_t t:1;
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144 | 79aceca5 | bellard | uint32_t ks:1;
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145 | 79aceca5 | bellard | uint32_t kp:1;
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146 | 79aceca5 | bellard | uint32_t n:1;
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147 | 79aceca5 | bellard | uint32_t res:4;
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148 | 79aceca5 | bellard | uint32_t vsid:24;
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149 | 79aceca5 | bellard | } ppc_sr_t; |
150 | 79aceca5 | bellard | |
151 | 79aceca5 | bellard | typedef struct CPUPPCState { |
152 | 79aceca5 | bellard | /* general purpose registers */
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153 | 79aceca5 | bellard | uint32_t gpr[32];
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154 | 79aceca5 | bellard | /* floating point registers */
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155 | 79aceca5 | bellard | uint64_t fpr[32];
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156 | 79aceca5 | bellard | /* segment registers */
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157 | 79aceca5 | bellard | ppc_sr_t sr[16];
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158 | 79aceca5 | bellard | /* special purpose registers */
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159 | 79aceca5 | bellard | uint32_t spr[1024];
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160 | 79aceca5 | bellard | /* XER */
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161 | 79aceca5 | bellard | uint8_t xer[32];
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162 | 79aceca5 | bellard | /* Reservation address */
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163 | 79aceca5 | bellard | uint32_t reserve; |
164 | 79aceca5 | bellard | /* machine state register */
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165 | 79aceca5 | bellard | uint8_t msr[32];
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166 | 79aceca5 | bellard | /* condition register */
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167 | 79aceca5 | bellard | uint8_t crf[8];
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168 | 79aceca5 | bellard | /* floating point status and control register */
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169 | 79aceca5 | bellard | uint8_t fpscr[32];
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170 | 79aceca5 | bellard | uint32_t nip; |
171 | 79aceca5 | bellard | /* CPU exception code */
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172 | 79aceca5 | bellard | uint32_t exception; |
173 | 79aceca5 | bellard | |
174 | 79aceca5 | bellard | /* qemu dedicated */
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175 | 28b6751f | bellard | uint64_t ft0; /* temporary float register */
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176 | 79aceca5 | bellard | int interrupt_request;
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177 | 79aceca5 | bellard | jmp_buf jmp_env; |
178 | 79aceca5 | bellard | int exception_index;
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179 | 79aceca5 | bellard | int error_code;
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180 | 79aceca5 | bellard | int user_mode_only; /* user mode only simulation */ |
181 | 79aceca5 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
182 | 79aceca5 | bellard | |
183 | 79aceca5 | bellard | /* user data */
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184 | 79aceca5 | bellard | void *opaque;
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185 | 79aceca5 | bellard | } CPUPPCState; |
186 | 79aceca5 | bellard | |
187 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
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188 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
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189 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
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190 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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191 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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192 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
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193 | 79aceca5 | bellard | struct siginfo;
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194 | 79aceca5 | bellard | int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
195 | 79aceca5 | bellard | void *puc);
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196 | 79aceca5 | bellard | |
197 | 79aceca5 | bellard | void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
198 | 79aceca5 | bellard | |
199 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
200 | 79aceca5 | bellard | #include "cpu-all.h" |
201 | 79aceca5 | bellard | |
202 | 79aceca5 | bellard | #define ugpr(n) (env->gpr[n])
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203 | 79aceca5 | bellard | #define fpr(n) (env->fpr[n])
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204 | 79aceca5 | bellard | |
205 | 79aceca5 | bellard | #define SPR_ENCODE(sprn) \
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206 | 79aceca5 | bellard | (((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
207 | 79aceca5 | bellard | |
208 | 79aceca5 | bellard | /* User mode SPR */
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209 | 79aceca5 | bellard | #define spr(n) env->spr[n]
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210 | 79aceca5 | bellard | //#define XER spr[1]
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211 | 79aceca5 | bellard | #define XER env->xer
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212 | 79aceca5 | bellard | #define XER_SO 31 |
213 | 79aceca5 | bellard | #define XER_OV 30 |
214 | 79aceca5 | bellard | #define XER_CA 29 |
215 | 79aceca5 | bellard | #define XER_BC 0 |
216 | 79aceca5 | bellard | #define xer_so env->xer[XER_SO]
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217 | 79aceca5 | bellard | #define xer_ov env->xer[XER_OV]
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218 | 79aceca5 | bellard | #define xer_ca env->xer[XER_CA]
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219 | 79aceca5 | bellard | #define xer_bc env->xer[XER_BC]
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220 | 79aceca5 | bellard | |
221 | 79aceca5 | bellard | #define LR spr[SPR_ENCODE(8)] |
222 | 79aceca5 | bellard | #define CTR spr[SPR_ENCODE(9)] |
223 | 79aceca5 | bellard | /* VEA mode SPR */
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224 | 79aceca5 | bellard | #define V_TBL spr[SPR_ENCODE(268)] |
225 | 79aceca5 | bellard | #define V_TBU spr[SPR_ENCODE(269)] |
226 | 79aceca5 | bellard | /* supervisor mode SPR */
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227 | 79aceca5 | bellard | #define DSISR spr[SPR_ENCODE(18)] |
228 | 79aceca5 | bellard | #define DAR spr[SPR_ENCODE(19)] |
229 | 79aceca5 | bellard | #define DEC spr[SPR_ENCODE(22)] |
230 | 79aceca5 | bellard | #define SDR1 spr[SPR_ENCODE(25)] |
231 | 79aceca5 | bellard | typedef struct ppc_sdr1_t { |
232 | 79aceca5 | bellard | uint32_t htaborg:16;
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233 | 79aceca5 | bellard | uint32_t res:7;
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234 | 79aceca5 | bellard | uint32_t htabmask:9;
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235 | 79aceca5 | bellard | } ppc_sdr1_t; |
236 | 79aceca5 | bellard | #define SRR0 spr[SPR_ENCODE(26)] |
237 | 79aceca5 | bellard | #define SRR0_MASK 0xFFFFFFFC |
238 | 79aceca5 | bellard | #define SRR1 spr[SPR_ENCODE(27)] |
239 | 79aceca5 | bellard | #define SPRG0 spr[SPR_ENCODE(272)] |
240 | 79aceca5 | bellard | #define SPRG1 spr[SPR_ENCODE(273)] |
241 | 79aceca5 | bellard | #define SPRG2 spr[SPR_ENCODE(274)] |
242 | 79aceca5 | bellard | #define SPRG3 spr[SPR_ENCODE(275)] |
243 | 79aceca5 | bellard | #define EAR spr[SPR_ENCODE(282)] |
244 | 79aceca5 | bellard | typedef struct ppc_ear_t { |
245 | 79aceca5 | bellard | uint32_t e:1;
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246 | 79aceca5 | bellard | uint32_t res:25;
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247 | 79aceca5 | bellard | uint32_t rid:6;
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248 | 79aceca5 | bellard | } ppc_ear_t; |
249 | 79aceca5 | bellard | #define TBL spr[SPR_ENCODE(284)] |
250 | 79aceca5 | bellard | #define TBU spr[SPR_ENCODE(285)] |
251 | 79aceca5 | bellard | #define PVR spr[SPR_ENCODE(287)] |
252 | 79aceca5 | bellard | typedef struct ppc_pvr_t { |
253 | 79aceca5 | bellard | uint32_t version:16;
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254 | 79aceca5 | bellard | uint32_t revision:16;
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255 | 79aceca5 | bellard | } ppc_pvr_t; |
256 | 79aceca5 | bellard | #define IBAT0U spr[SPR_ENCODE(528)] |
257 | 79aceca5 | bellard | #define IBAT0L spr[SPR_ENCODE(529)] |
258 | 79aceca5 | bellard | #define IBAT1U spr[SPR_ENCODE(530)] |
259 | 79aceca5 | bellard | #define IBAT1L spr[SPR_ENCODE(531)] |
260 | 79aceca5 | bellard | #define IBAT2U spr[SPR_ENCODE(532)] |
261 | 79aceca5 | bellard | #define IBAT2L spr[SPR_ENCODE(533)] |
262 | 79aceca5 | bellard | #define IBAT3U spr[SPR_ENCODE(534)] |
263 | 79aceca5 | bellard | #define IBAT3L spr[SPR_ENCODE(535)] |
264 | 79aceca5 | bellard | #define DBAT0U spr[SPR_ENCODE(536)] |
265 | 79aceca5 | bellard | #define DBAT0L spr[SPR_ENCODE(537)] |
266 | 79aceca5 | bellard | #define DBAT1U spr[SPR_ENCODE(538)] |
267 | 79aceca5 | bellard | #define DBAT1L spr[SPR_ENCODE(539)] |
268 | 79aceca5 | bellard | #define DBAT2U spr[SPR_ENCODE(540)] |
269 | 79aceca5 | bellard | #define DBAT2L spr[SPR_ENCODE(541)] |
270 | 79aceca5 | bellard | #define DBAT3U spr[SPR_ENCODE(542)] |
271 | 79aceca5 | bellard | #define DBAT3L spr[SPR_ENCODE(543)] |
272 | 79aceca5 | bellard | typedef struct ppc_ubat_t { |
273 | 79aceca5 | bellard | uint32_t bepi:15;
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274 | 79aceca5 | bellard | uint32_t res:4;
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275 | 79aceca5 | bellard | uint32_t bl:11;
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276 | 79aceca5 | bellard | uint32_t vs:1;
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277 | 79aceca5 | bellard | uint32_t vp:1;
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278 | 79aceca5 | bellard | } ppc_ubat_t; |
279 | 79aceca5 | bellard | typedef struct ppc_lbat_t { |
280 | 79aceca5 | bellard | uint32_t brpn:15;
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281 | 79aceca5 | bellard | uint32_t res0:10;
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282 | 79aceca5 | bellard | uint32_t w:1;
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283 | 79aceca5 | bellard | uint32_t i:1;
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284 | 79aceca5 | bellard | uint32_t m:1;
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285 | 79aceca5 | bellard | uint32_t g:1;
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286 | 79aceca5 | bellard | uint32_t res1:1;
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287 | 79aceca5 | bellard | uint32_t pp:2;
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288 | 79aceca5 | bellard | } ppc_lbat_t; |
289 | 79aceca5 | bellard | #define DABR spr[SPR_ENCODE(1013)] |
290 | 79aceca5 | bellard | #define DABR_MASK 0xFFFFFFF8 |
291 | 79aceca5 | bellard | typedef struct ppc_dabr_t { |
292 | 79aceca5 | bellard | uint32_t dab:29;
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293 | 79aceca5 | bellard | uint32_t bt:1;
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294 | 79aceca5 | bellard | uint32_t dw:1;
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295 | 79aceca5 | bellard | uint32_t dr:1;
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296 | 79aceca5 | bellard | } ppc_dabr_t; |
297 | 79aceca5 | bellard | #define FPECR spr[SPR_ENCODE(1022)] |
298 | 79aceca5 | bellard | #define PIR spr[SPR_ENCODE(1023)] |
299 | 79aceca5 | bellard | |
300 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
301 | 79aceca5 | bellard | #include "cpu-all.h" |
302 | 79aceca5 | bellard | |
303 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
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304 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
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305 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
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306 | 79aceca5 | bellard | void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
307 | 79aceca5 | bellard | |
308 | 79aceca5 | bellard | /* Exeptions */
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309 | 79aceca5 | bellard | enum {
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310 | 79aceca5 | bellard | EXCP_NONE = 0x00,
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311 | 79aceca5 | bellard | /* PPC hardware exceptions : exception vector / 0x100 */
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312 | 79aceca5 | bellard | EXCP_RESET = 0x01, /* System reset */ |
313 | 79aceca5 | bellard | EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
314 | 79aceca5 | bellard | EXCP_DSI = 0x03, /* Impossible memory access */ |
315 | 79aceca5 | bellard | EXCP_ISI = 0x04, /* Impossible instruction fetch */ |
316 | 79aceca5 | bellard | EXCP_EXTERNAL = 0x05, /* External interruption */ |
317 | 79aceca5 | bellard | EXCP_ALIGN = 0x06, /* Alignment exception */ |
318 | 79aceca5 | bellard | EXCP_PROGRAM = 0x07, /* Program exception */ |
319 | 79aceca5 | bellard | EXCP_NO_FP = 0x08, /* No floating point */ |
320 | 79aceca5 | bellard | EXCP_DECR = 0x09, /* Decrementer exception */ |
321 | 79aceca5 | bellard | EXCP_RESA = 0x0A, /* Implementation specific */ |
322 | 79aceca5 | bellard | EXCP_RESB = 0x0B, /* Implementation specific */ |
323 | 79aceca5 | bellard | EXCP_SYSCALL = 0x0C, /* System call */ |
324 | 79aceca5 | bellard | EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
325 | 79aceca5 | bellard | EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
326 | 79aceca5 | bellard | #if 0
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327 | 79aceca5 | bellard | /* Exeption subtypes for EXCP_DSI */
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328 | 79aceca5 | bellard | EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */
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329 | 79aceca5 | bellard | EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */
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330 | 79aceca5 | bellard | EXCP_DSI_PROT = 0x10303, /* Memory protection violation */
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331 | 79aceca5 | bellard | EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */
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332 | 79aceca5 | bellard | EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */
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333 | 79aceca5 | bellard | /* Exeption subtypes for EXCP_ISI */
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334 | 79aceca5 | bellard | EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */
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335 | 79aceca5 | bellard | EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */
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336 | 79aceca5 | bellard | EXCP_ISI_PROT = 0x10403, /* Memory protection violation */
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337 | 79aceca5 | bellard | EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */
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338 | 79aceca5 | bellard | /* Exeption subtypes for EXCP_ALIGN */
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339 | 79aceca5 | bellard | EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */
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340 | 79aceca5 | bellard | EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */
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341 | 79aceca5 | bellard | EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */
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342 | 79aceca5 | bellard | EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */
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343 | 79aceca5 | bellard | EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */
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344 | 79aceca5 | bellard | EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */
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345 | 79aceca5 | bellard | /* Exeption subtypes for EXCP_PROGRAM */
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346 | 79aceca5 | bellard | /* FP exceptions */
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347 | 79aceca5 | bellard | EXCP_FP_OX = 0x10701, /* FP overflow */
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348 | 79aceca5 | bellard | EXCP_FP_UX = 0x10702, /* FP underflow */
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349 | 79aceca5 | bellard | EXCP_FP_ZX = 0x10703, /* FP divide by zero */
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350 | 79aceca5 | bellard | EXCP_FP_XX = 0x10704, /* FP inexact */
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351 | 79aceca5 | bellard | EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */
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352 | 79aceca5 | bellard | EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */
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353 | 79aceca5 | bellard | EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */
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354 | 79aceca5 | bellard | EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */
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355 | 79aceca5 | bellard | EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */
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356 | 79aceca5 | bellard | EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */
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357 | 79aceca5 | bellard | EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */
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358 | 79aceca5 | bellard | EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */
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359 | 79aceca5 | bellard | EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */
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360 | 79aceca5 | bellard | /* Invalid instruction */
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361 | 79aceca5 | bellard | EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */
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362 | 79aceca5 | bellard | EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */
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363 | 79aceca5 | bellard | EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */
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364 | 79aceca5 | bellard | EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */
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365 | 79aceca5 | bellard | #endif
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366 | 79aceca5 | bellard | EXCP_INVAL = 0x70, /* Invalid instruction */ |
367 | 79aceca5 | bellard | /* Privileged instruction */
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368 | 79aceca5 | bellard | EXCP_PRIV = 0x71, /* Privileged instruction */ |
369 | 79aceca5 | bellard | /* Trap */
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370 | 79aceca5 | bellard | EXCP_TRAP = 0x72, /* Trap */ |
371 | 79aceca5 | bellard | /* Special cases where we want to stop translation */
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372 | 79aceca5 | bellard | EXCP_MTMSR = 0x103, /* mtmsr instruction: */ |
373 | 79aceca5 | bellard | /* may change privilege level */
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374 | 79aceca5 | bellard | EXCP_BRANCH = 0x104, /* branch instruction */ |
375 | 79aceca5 | bellard | }; |
376 | 79aceca5 | bellard | |
377 | 79aceca5 | bellard | /*
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378 | 79aceca5 | bellard | * We need to put in some extra aux table entries to tell glibc what
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379 | 79aceca5 | bellard | * the cache block size is, so it can use the dcbz instruction safely.
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380 | 79aceca5 | bellard | */
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381 | 79aceca5 | bellard | #define AT_DCACHEBSIZE 19 |
382 | 79aceca5 | bellard | #define AT_ICACHEBSIZE 20 |
383 | 79aceca5 | bellard | #define AT_UCACHEBSIZE 21 |
384 | 79aceca5 | bellard | /* A special ignored type value for PPC, for glibc compatibility. */
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385 | 79aceca5 | bellard | #define AT_IGNOREPPC 22 |
386 | 79aceca5 | bellard | /*
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387 | 79aceca5 | bellard | * The requirements here are:
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388 | 79aceca5 | bellard | * - keep the final alignment of sp (sp & 0xf)
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389 | 79aceca5 | bellard | * - make sure the 32-bit value at the first 16 byte aligned position of
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390 | 79aceca5 | bellard | * AUXV is greater than 16 for glibc compatibility.
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391 | 79aceca5 | bellard | * AT_IGNOREPPC is used for that.
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392 | 79aceca5 | bellard | * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
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393 | 79aceca5 | bellard | * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
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394 | 79aceca5 | bellard | */
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395 | 79aceca5 | bellard | #define DLINFO_ARCH_ITEMS 3 |
396 | 79aceca5 | bellard | #define ARCH_DLINFO \
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397 | 79aceca5 | bellard | do { \
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398 | 79aceca5 | bellard | /* \
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399 | 79aceca5 | bellard | * Now handle glibc compatibility. \
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400 | 79aceca5 | bellard | */ \
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401 | 79aceca5 | bellard | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ |
402 | 79aceca5 | bellard | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ |
403 | 79aceca5 | bellard | \ |
404 | 79aceca5 | bellard | NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \
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405 | 79aceca5 | bellard | NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \
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406 | 79aceca5 | bellard | NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \
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407 | 79aceca5 | bellard | } while (0) |
408 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |