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1 | 0824d6fc | bellard | /*
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2 | 1df912cf | bellard | * QEMU PC System Emulator
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3 | 0824d6fc | bellard | *
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4 | 1df912cf | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 0824d6fc | bellard | *
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6 | 1df912cf | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1df912cf | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 1df912cf | bellard | * in the Software without restriction, including without limitation the rights
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9 | 1df912cf | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1df912cf | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 1df912cf | bellard | * furnished to do so, subject to the following conditions:
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12 | 1df912cf | bellard | *
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13 | 1df912cf | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 1df912cf | bellard | * all copies or substantial portions of the Software.
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15 | 1df912cf | bellard | *
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16 | 1df912cf | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1df912cf | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1df912cf | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1df912cf | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1df912cf | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1df912cf | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1df912cf | bellard | * THE SOFTWARE.
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23 | 0824d6fc | bellard | */
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24 | 0824d6fc | bellard | #include <stdlib.h> |
25 | 0824d6fc | bellard | #include <stdio.h> |
26 | 1df912cf | bellard | #include <stdarg.h> |
27 | 0824d6fc | bellard | #include <string.h> |
28 | 0824d6fc | bellard | #include <getopt.h> |
29 | 0824d6fc | bellard | #include <inttypes.h> |
30 | 0824d6fc | bellard | #include <unistd.h> |
31 | 0824d6fc | bellard | #include <sys/mman.h> |
32 | 0824d6fc | bellard | #include <fcntl.h> |
33 | 0824d6fc | bellard | #include <signal.h> |
34 | 0824d6fc | bellard | #include <time.h> |
35 | 0824d6fc | bellard | #include <sys/time.h> |
36 | 0824d6fc | bellard | #include <malloc.h> |
37 | 0824d6fc | bellard | #include <termios.h> |
38 | 0824d6fc | bellard | #include <sys/poll.h> |
39 | 0824d6fc | bellard | #include <errno.h> |
40 | f1510b2c | bellard | #include <sys/wait.h> |
41 | f1510b2c | bellard | |
42 | f1510b2c | bellard | #include <sys/ioctl.h> |
43 | f1510b2c | bellard | #include <sys/socket.h> |
44 | f1510b2c | bellard | #include <linux/if.h> |
45 | f1510b2c | bellard | #include <linux/if_tun.h> |
46 | 0824d6fc | bellard | |
47 | a20dd508 | bellard | #include "cpu.h" |
48 | 0824d6fc | bellard | #include "disas.h" |
49 | fc01f7e7 | bellard | #include "thunk.h" |
50 | fc01f7e7 | bellard | |
51 | fc01f7e7 | bellard | #include "vl.h" |
52 | 0824d6fc | bellard | |
53 | 5a67135a | bellard | #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup" |
54 | 330d0414 | bellard | #define BIOS_FILENAME "bios.bin" |
55 | 330d0414 | bellard | #define VGABIOS_FILENAME "vgabios.bin" |
56 | f1510b2c | bellard | |
57 | 0824d6fc | bellard | //#define DEBUG_UNUSED_IOPORT
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58 | 330d0414 | bellard | |
59 | c9159e53 | bellard | //#define DEBUG_IRQ_LATENCY
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60 | 0824d6fc | bellard | |
61 | 330d0414 | bellard | /* output Bochs bios info messages */
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62 | 330d0414 | bellard | //#define DEBUG_BIOS
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63 | 330d0414 | bellard | |
64 | 7dea1da4 | bellard | //#define DEBUG_CMOS
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65 | 7dea1da4 | bellard | |
66 | 330d0414 | bellard | /* debug PIC */
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67 | 330d0414 | bellard | //#define DEBUG_PIC
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68 | 330d0414 | bellard | |
69 | 330d0414 | bellard | /* debug NE2000 card */
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70 | 330d0414 | bellard | //#define DEBUG_NE2000
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71 | 330d0414 | bellard | |
72 | 330d0414 | bellard | /* debug PC keyboard */
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73 | 330d0414 | bellard | //#define DEBUG_KBD
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74 | 330d0414 | bellard | |
75 | 313aa567 | bellard | /* debug PC keyboard : only mouse */
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76 | 313aa567 | bellard | //#define DEBUG_MOUSE
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77 | 313aa567 | bellard | |
78 | 7dea1da4 | bellard | //#define DEBUG_SERIAL
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79 | 7dea1da4 | bellard | |
80 | 7916e224 | bellard | #define PHYS_RAM_BASE 0xac000000 |
81 | 7916e224 | bellard | #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) |
82 | 7916e224 | bellard | |
83 | 0824d6fc | bellard | #define KERNEL_LOAD_ADDR 0x00100000 |
84 | 0824d6fc | bellard | #define INITRD_LOAD_ADDR 0x00400000 |
85 | 0824d6fc | bellard | #define KERNEL_PARAMS_ADDR 0x00090000 |
86 | 0824d6fc | bellard | |
87 | 313aa567 | bellard | #define GUI_REFRESH_INTERVAL 30 |
88 | 313aa567 | bellard | |
89 | 0824d6fc | bellard | /* from plex86 (BSD license) */
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90 | 0824d6fc | bellard | struct __attribute__ ((packed)) linux_params {
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91 | 0824d6fc | bellard | // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
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92 | 0824d6fc | bellard | // I just padded out the VESA parts, rather than define them.
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93 | 0824d6fc | bellard | |
94 | 0824d6fc | bellard | /* 0x000 */ uint8_t orig_x;
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95 | 0824d6fc | bellard | /* 0x001 */ uint8_t orig_y;
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96 | 0824d6fc | bellard | /* 0x002 */ uint16_t ext_mem_k;
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97 | 0824d6fc | bellard | /* 0x004 */ uint16_t orig_video_page;
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98 | 0824d6fc | bellard | /* 0x006 */ uint8_t orig_video_mode;
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99 | 0824d6fc | bellard | /* 0x007 */ uint8_t orig_video_cols;
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100 | 0824d6fc | bellard | /* 0x008 */ uint16_t unused1;
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101 | 0824d6fc | bellard | /* 0x00a */ uint16_t orig_video_ega_bx;
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102 | 0824d6fc | bellard | /* 0x00c */ uint16_t unused2;
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103 | 0824d6fc | bellard | /* 0x00e */ uint8_t orig_video_lines;
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104 | 0824d6fc | bellard | /* 0x00f */ uint8_t orig_video_isVGA;
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105 | 0824d6fc | bellard | /* 0x010 */ uint16_t orig_video_points;
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106 | 0824d6fc | bellard | /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. |
107 | 0824d6fc | bellard | /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) |
108 | 0824d6fc | bellard | /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline |
109 | 0824d6fc | bellard | // is calculated as 0x90000 + cl_offset, bu
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110 | 0824d6fc | bellard | // only if cl_magic == 0xA33F.
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111 | 0824d6fc | bellard | /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. |
112 | 0824d6fc | bellard | |
113 | 0824d6fc | bellard | /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info |
114 | 0824d6fc | bellard | /* 0x054 */ uint8_t pad2[0x80 - 0x54]; |
115 | 0824d6fc | bellard | |
116 | 0824d6fc | bellard | // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
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117 | 0824d6fc | bellard | // Might be truncated?
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118 | 0824d6fc | bellard | /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 |
119 | 0824d6fc | bellard | /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 |
120 | 0824d6fc | bellard | |
121 | 0824d6fc | bellard | // System description table truncated to 16 bytes
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122 | 0824d6fc | bellard | // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
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123 | 0824d6fc | bellard | /* 0x0a0 */ uint16_t sys_description_len;
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124 | 0824d6fc | bellard | /* 0x0a2 */ uint8_t sys_description_table[14]; |
125 | 0824d6fc | bellard | // [0] machine id
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126 | 0824d6fc | bellard | // [1] machine submodel id
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127 | 0824d6fc | bellard | // [2] BIOS revision
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128 | 0824d6fc | bellard | // [3] bit1: MCA bus
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129 | 0824d6fc | bellard | |
130 | 0824d6fc | bellard | /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; |
131 | 0824d6fc | bellard | /* 0x1e0 */ uint32_t alt_mem_k;
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132 | 0824d6fc | bellard | /* 0x1e4 */ uint8_t pad4[4]; |
133 | 0824d6fc | bellard | /* 0x1e8 */ uint8_t e820map_entries;
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134 | 0824d6fc | bellard | /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR |
135 | 0824d6fc | bellard | /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; |
136 | 0824d6fc | bellard | /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors |
137 | 0824d6fc | bellard | /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) |
138 | 0824d6fc | bellard | /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the |
139 | 0824d6fc | bellard | // (b)zImage-file (in 16 byte units, rounded up)
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140 | 0824d6fc | bellard | /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) |
141 | 0824d6fc | bellard | /* 0x1f8 */ uint16_t ramdisk_flags;
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142 | 0824d6fc | bellard | /* 0x1fa */ uint16_t vga_mode; // (old one) |
143 | 0824d6fc | bellard | /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) |
144 | 0824d6fc | bellard | /* 0x1fe */ uint8_t pad6[1]; |
145 | 0824d6fc | bellard | /* 0x1ff */ uint8_t aux_device_info;
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146 | 0824d6fc | bellard | /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, |
147 | 0824d6fc | bellard | // aka "reserved" field.
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148 | 0824d6fc | bellard | /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" |
149 | 0824d6fc | bellard | /* 0x206 */ uint16_t header_format_version; // Version number of header format; |
150 | 0824d6fc | bellard | /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with |
151 | 0824d6fc | bellard | // boot loaders, look there.
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152 | 0824d6fc | bellard | /* 0x210 */ uint8_t loader_type;
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153 | 0824d6fc | bellard | // 0 for old one.
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154 | 0824d6fc | bellard | // else 0xTV:
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155 | 0824d6fc | bellard | // T=0: LILO
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156 | 0824d6fc | bellard | // T=1: Loadlin
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157 | 0824d6fc | bellard | // T=2: bootsect-loader
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158 | 0824d6fc | bellard | // T=3: SYSLINUX
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159 | 0824d6fc | bellard | // T=4: ETHERBOOT
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160 | 0824d6fc | bellard | // V=version
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161 | 0824d6fc | bellard | /* 0x211 */ uint8_t loadflags;
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162 | 0824d6fc | bellard | // bit0 = 1: kernel is loaded high (bzImage)
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163 | 0824d6fc | bellard | // bit7 = 1: Heap and pointer (see below) set by boot
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164 | 0824d6fc | bellard | // loader.
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165 | 0824d6fc | bellard | /* 0x212 */ uint16_t setup_S_temp1;
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166 | 0824d6fc | bellard | /* 0x214 */ uint32_t kernel_start;
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167 | 0824d6fc | bellard | /* 0x218 */ uint32_t initrd_start;
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168 | 0824d6fc | bellard | /* 0x21c */ uint32_t initrd_size;
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169 | 0824d6fc | bellard | /* 0x220 */ uint8_t setup_S_temp2[4]; |
170 | 0824d6fc | bellard | /* 0x224 */ uint16_t setup_S_heap_end_pointer;
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171 | 0824d6fc | bellard | /* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; |
172 | 0824d6fc | bellard | |
173 | 0824d6fc | bellard | /* 0x2d0 : Int 15, ax=e820 memory map. */
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174 | 0824d6fc | bellard | // (linux/include/asm-i386/e820.h, 'struct e820entry')
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175 | 0824d6fc | bellard | #define E820MAX 32 |
176 | 0824d6fc | bellard | #define E820_RAM 1 |
177 | 0824d6fc | bellard | #define E820_RESERVED 2 |
178 | 0824d6fc | bellard | #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ |
179 | 0824d6fc | bellard | #define E820_NVS 4 |
180 | 0824d6fc | bellard | struct {
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181 | 0824d6fc | bellard | uint64_t addr; |
182 | 0824d6fc | bellard | uint64_t size; |
183 | 0824d6fc | bellard | uint32_t type; |
184 | 0824d6fc | bellard | } e820map[E820MAX]; |
185 | 0824d6fc | bellard | |
186 | 0824d6fc | bellard | /* 0x550 */ uint8_t pad8[0x600 - 0x550]; |
187 | 0824d6fc | bellard | |
188 | 0824d6fc | bellard | // BIOS Enhanced Disk Drive Services.
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189 | 0824d6fc | bellard | // (From linux/include/asm-i386/edd.h, 'struct edd_info')
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190 | 0824d6fc | bellard | // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
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191 | 0824d6fc | bellard | /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; |
192 | 0824d6fc | bellard | |
193 | 0824d6fc | bellard | /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; |
194 | 0824d6fc | bellard | /* 0x800 */ uint8_t commandline[0x800]; |
195 | 0824d6fc | bellard | |
196 | 0824d6fc | bellard | /* 0x1000 */
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197 | 0824d6fc | bellard | uint64_t gdt_table[256];
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198 | 0824d6fc | bellard | uint64_t idt_table[48];
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199 | 0824d6fc | bellard | }; |
200 | 0824d6fc | bellard | |
201 | 0824d6fc | bellard | #define KERNEL_CS 0x10 |
202 | 0824d6fc | bellard | #define KERNEL_DS 0x18 |
203 | 0824d6fc | bellard | |
204 | 7dea1da4 | bellard | /* XXX: use a two level table to limit memory usage */
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205 | 7dea1da4 | bellard | #define MAX_IOPORTS 65536 |
206 | 0824d6fc | bellard | |
207 | 5a67135a | bellard | static const char *bios_dir = CONFIG_QEMU_SHAREDIR; |
208 | 0824d6fc | bellard | char phys_ram_file[1024]; |
209 | 0824d6fc | bellard | CPUX86State *global_env; |
210 | 1df912cf | bellard | CPUX86State *cpu_single_env; |
211 | fc01f7e7 | bellard | IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
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212 | fc01f7e7 | bellard | IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
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213 | 33e3963e | bellard | BlockDriverState *bs_table[MAX_DISKS]; |
214 | 313aa567 | bellard | int vga_ram_size;
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215 | 313aa567 | bellard | static DisplayState display_state;
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216 | a20dd508 | bellard | int nographic;
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217 | 313aa567 | bellard | int term_inited;
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218 | 313aa567 | bellard | int64_t ticks_per_sec; |
219 | 36b486bb | bellard | int boot_device = 'c'; |
220 | 0824d6fc | bellard | |
221 | 0824d6fc | bellard | /***********************************************************/
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222 | 0824d6fc | bellard | /* x86 io ports */
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223 | 0824d6fc | bellard | |
224 | 0824d6fc | bellard | uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) |
225 | 0824d6fc | bellard | { |
226 | 0824d6fc | bellard | #ifdef DEBUG_UNUSED_IOPORT
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227 | 0824d6fc | bellard | fprintf(stderr, "inb: port=0x%04x\n", address);
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228 | 0824d6fc | bellard | #endif
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229 | fc01f7e7 | bellard | return 0xff; |
230 | 0824d6fc | bellard | } |
231 | 0824d6fc | bellard | |
232 | 0824d6fc | bellard | void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
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233 | 0824d6fc | bellard | { |
234 | 0824d6fc | bellard | #ifdef DEBUG_UNUSED_IOPORT
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235 | 0824d6fc | bellard | fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
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236 | 0824d6fc | bellard | #endif
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237 | 0824d6fc | bellard | } |
238 | 0824d6fc | bellard | |
239 | 0824d6fc | bellard | /* default is to make two byte accesses */
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240 | 0824d6fc | bellard | uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) |
241 | 0824d6fc | bellard | { |
242 | 0824d6fc | bellard | uint32_t data; |
243 | 330d0414 | bellard | data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address); |
244 | 330d0414 | bellard | data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8; |
245 | 0824d6fc | bellard | return data;
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246 | 0824d6fc | bellard | } |
247 | 0824d6fc | bellard | |
248 | 0824d6fc | bellard | void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
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249 | 0824d6fc | bellard | { |
250 | 330d0414 | bellard | ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff); |
251 | 330d0414 | bellard | ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff); |
252 | 0824d6fc | bellard | } |
253 | 0824d6fc | bellard | |
254 | fc01f7e7 | bellard | uint32_t default_ioport_readl(CPUX86State *env, uint32_t address) |
255 | 0824d6fc | bellard | { |
256 | fc01f7e7 | bellard | #ifdef DEBUG_UNUSED_IOPORT
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257 | fc01f7e7 | bellard | fprintf(stderr, "inl: port=0x%04x\n", address);
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258 | fc01f7e7 | bellard | #endif
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259 | fc01f7e7 | bellard | return 0xffffffff; |
260 | 0824d6fc | bellard | } |
261 | 0824d6fc | bellard | |
262 | fc01f7e7 | bellard | void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
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263 | 0824d6fc | bellard | { |
264 | fc01f7e7 | bellard | #ifdef DEBUG_UNUSED_IOPORT
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265 | fc01f7e7 | bellard | fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
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266 | fc01f7e7 | bellard | #endif
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267 | 0824d6fc | bellard | } |
268 | 0824d6fc | bellard | |
269 | fc01f7e7 | bellard | void init_ioports(void) |
270 | 0824d6fc | bellard | { |
271 | 0824d6fc | bellard | int i;
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272 | 0824d6fc | bellard | |
273 | fc01f7e7 | bellard | for(i = 0; i < MAX_IOPORTS; i++) { |
274 | fc01f7e7 | bellard | ioport_read_table[0][i] = default_ioport_readb;
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275 | fc01f7e7 | bellard | ioport_write_table[0][i] = default_ioport_writeb;
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276 | fc01f7e7 | bellard | ioport_read_table[1][i] = default_ioport_readw;
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277 | fc01f7e7 | bellard | ioport_write_table[1][i] = default_ioport_writew;
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278 | fc01f7e7 | bellard | ioport_read_table[2][i] = default_ioport_readl;
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279 | fc01f7e7 | bellard | ioport_write_table[2][i] = default_ioport_writel;
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280 | fc01f7e7 | bellard | } |
281 | 0824d6fc | bellard | } |
282 | 0824d6fc | bellard | |
283 | fc01f7e7 | bellard | /* size is the word size in byte */
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284 | fc01f7e7 | bellard | int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) |
285 | f1510b2c | bellard | { |
286 | fc01f7e7 | bellard | int i, bsize;
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287 | f1510b2c | bellard | |
288 | fc01f7e7 | bellard | if (size == 1) |
289 | fc01f7e7 | bellard | bsize = 0;
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290 | fc01f7e7 | bellard | else if (size == 2) |
291 | fc01f7e7 | bellard | bsize = 1;
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292 | fc01f7e7 | bellard | else if (size == 4) |
293 | fc01f7e7 | bellard | bsize = 2;
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294 | fc01f7e7 | bellard | else
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295 | fc01f7e7 | bellard | return -1; |
296 | fc01f7e7 | bellard | for(i = start; i < start + length; i += size)
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297 | fc01f7e7 | bellard | ioport_read_table[bsize][i] = func; |
298 | f1510b2c | bellard | return 0; |
299 | f1510b2c | bellard | } |
300 | f1510b2c | bellard | |
301 | fc01f7e7 | bellard | /* size is the word size in byte */
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302 | fc01f7e7 | bellard | int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) |
303 | f1510b2c | bellard | { |
304 | fc01f7e7 | bellard | int i, bsize;
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305 | f1510b2c | bellard | |
306 | fc01f7e7 | bellard | if (size == 1) |
307 | fc01f7e7 | bellard | bsize = 0;
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308 | fc01f7e7 | bellard | else if (size == 2) |
309 | fc01f7e7 | bellard | bsize = 1;
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310 | fc01f7e7 | bellard | else if (size == 4) |
311 | fc01f7e7 | bellard | bsize = 2;
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312 | fc01f7e7 | bellard | else
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313 | fc01f7e7 | bellard | return -1; |
314 | fc01f7e7 | bellard | for(i = start; i < start + length; i += size)
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315 | fc01f7e7 | bellard | ioport_write_table[bsize][i] = func; |
316 | f1510b2c | bellard | return 0; |
317 | f1510b2c | bellard | } |
318 | f1510b2c | bellard | |
319 | 0824d6fc | bellard | void pstrcpy(char *buf, int buf_size, const char *str) |
320 | 0824d6fc | bellard | { |
321 | 0824d6fc | bellard | int c;
|
322 | 0824d6fc | bellard | char *q = buf;
|
323 | 0824d6fc | bellard | |
324 | 0824d6fc | bellard | if (buf_size <= 0) |
325 | 0824d6fc | bellard | return;
|
326 | 0824d6fc | bellard | |
327 | 0824d6fc | bellard | for(;;) {
|
328 | 0824d6fc | bellard | c = *str++; |
329 | 0824d6fc | bellard | if (c == 0 || q >= buf + buf_size - 1) |
330 | 0824d6fc | bellard | break;
|
331 | 0824d6fc | bellard | *q++ = c; |
332 | 0824d6fc | bellard | } |
333 | 0824d6fc | bellard | *q = '\0';
|
334 | 0824d6fc | bellard | } |
335 | 0824d6fc | bellard | |
336 | 0824d6fc | bellard | /* strcat and truncate. */
|
337 | 0824d6fc | bellard | char *pstrcat(char *buf, int buf_size, const char *s) |
338 | 0824d6fc | bellard | { |
339 | 0824d6fc | bellard | int len;
|
340 | 0824d6fc | bellard | len = strlen(buf); |
341 | 0824d6fc | bellard | if (len < buf_size)
|
342 | 0824d6fc | bellard | pstrcpy(buf + len, buf_size - len, s); |
343 | 0824d6fc | bellard | return buf;
|
344 | 0824d6fc | bellard | } |
345 | 0824d6fc | bellard | |
346 | 0824d6fc | bellard | int load_kernel(const char *filename, uint8_t *addr) |
347 | 0824d6fc | bellard | { |
348 | 0824d6fc | bellard | int fd, size, setup_sects;
|
349 | 0824d6fc | bellard | uint8_t bootsect[512];
|
350 | 0824d6fc | bellard | |
351 | 0824d6fc | bellard | fd = open(filename, O_RDONLY); |
352 | 0824d6fc | bellard | if (fd < 0) |
353 | 0824d6fc | bellard | return -1; |
354 | 0824d6fc | bellard | if (read(fd, bootsect, 512) != 512) |
355 | 0824d6fc | bellard | goto fail;
|
356 | 0824d6fc | bellard | setup_sects = bootsect[0x1F1];
|
357 | 0824d6fc | bellard | if (!setup_sects)
|
358 | 0824d6fc | bellard | setup_sects = 4;
|
359 | 0824d6fc | bellard | /* skip 16 bit setup code */
|
360 | 0824d6fc | bellard | lseek(fd, (setup_sects + 1) * 512, SEEK_SET); |
361 | 0824d6fc | bellard | size = read(fd, addr, 16 * 1024 * 1024); |
362 | 0824d6fc | bellard | if (size < 0) |
363 | 0824d6fc | bellard | goto fail;
|
364 | 0824d6fc | bellard | close(fd); |
365 | 0824d6fc | bellard | return size;
|
366 | 0824d6fc | bellard | fail:
|
367 | 0824d6fc | bellard | close(fd); |
368 | 0824d6fc | bellard | return -1; |
369 | 0824d6fc | bellard | } |
370 | 0824d6fc | bellard | |
371 | 0824d6fc | bellard | /* return the size or -1 if error */
|
372 | 0824d6fc | bellard | int load_image(const char *filename, uint8_t *addr) |
373 | 0824d6fc | bellard | { |
374 | 0824d6fc | bellard | int fd, size;
|
375 | 0824d6fc | bellard | fd = open(filename, O_RDONLY); |
376 | 0824d6fc | bellard | if (fd < 0) |
377 | 0824d6fc | bellard | return -1; |
378 | 0824d6fc | bellard | size = lseek(fd, 0, SEEK_END);
|
379 | 0824d6fc | bellard | lseek(fd, 0, SEEK_SET);
|
380 | 0824d6fc | bellard | if (read(fd, addr, size) != size) {
|
381 | 0824d6fc | bellard | close(fd); |
382 | 0824d6fc | bellard | return -1; |
383 | 0824d6fc | bellard | } |
384 | 0824d6fc | bellard | close(fd); |
385 | 0824d6fc | bellard | return size;
|
386 | 0824d6fc | bellard | } |
387 | 0824d6fc | bellard | |
388 | 0824d6fc | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val) |
389 | 0824d6fc | bellard | { |
390 | fc01f7e7 | bellard | ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
391 | 0824d6fc | bellard | } |
392 | 0824d6fc | bellard | |
393 | 0824d6fc | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val) |
394 | 0824d6fc | bellard | { |
395 | fc01f7e7 | bellard | ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
396 | 0824d6fc | bellard | } |
397 | 0824d6fc | bellard | |
398 | 0824d6fc | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val) |
399 | 0824d6fc | bellard | { |
400 | fc01f7e7 | bellard | ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
401 | 0824d6fc | bellard | } |
402 | 0824d6fc | bellard | |
403 | 0824d6fc | bellard | int cpu_x86_inb(CPUX86State *env, int addr) |
404 | 0824d6fc | bellard | { |
405 | fc01f7e7 | bellard | return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
406 | 0824d6fc | bellard | } |
407 | 0824d6fc | bellard | |
408 | 0824d6fc | bellard | int cpu_x86_inw(CPUX86State *env, int addr) |
409 | 0824d6fc | bellard | { |
410 | fc01f7e7 | bellard | return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
411 | 0824d6fc | bellard | } |
412 | 0824d6fc | bellard | |
413 | 0824d6fc | bellard | int cpu_x86_inl(CPUX86State *env, int addr) |
414 | 0824d6fc | bellard | { |
415 | fc01f7e7 | bellard | return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
416 | 0824d6fc | bellard | } |
417 | 0824d6fc | bellard | |
418 | 0824d6fc | bellard | /***********************************************************/
|
419 | 0824d6fc | bellard | void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
420 | 0824d6fc | bellard | { |
421 | 0824d6fc | bellard | } |
422 | 0824d6fc | bellard | |
423 | 0824d6fc | bellard | void hw_error(const char *fmt, ...) |
424 | 0824d6fc | bellard | { |
425 | 0824d6fc | bellard | va_list ap; |
426 | 0824d6fc | bellard | |
427 | 0824d6fc | bellard | va_start(ap, fmt); |
428 | 0824d6fc | bellard | fprintf(stderr, "qemu: hardware error: ");
|
429 | 0824d6fc | bellard | vfprintf(stderr, fmt, ap); |
430 | 0824d6fc | bellard | fprintf(stderr, "\n");
|
431 | 0824d6fc | bellard | #ifdef TARGET_I386
|
432 | 0824d6fc | bellard | cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); |
433 | 0824d6fc | bellard | #endif
|
434 | 0824d6fc | bellard | va_end(ap); |
435 | 0824d6fc | bellard | abort(); |
436 | 0824d6fc | bellard | } |
437 | 0824d6fc | bellard | |
438 | 0824d6fc | bellard | /***********************************************************/
|
439 | 0824d6fc | bellard | /* cmos emulation */
|
440 | 0824d6fc | bellard | |
441 | 0824d6fc | bellard | #define RTC_SECONDS 0 |
442 | 0824d6fc | bellard | #define RTC_SECONDS_ALARM 1 |
443 | 0824d6fc | bellard | #define RTC_MINUTES 2 |
444 | 0824d6fc | bellard | #define RTC_MINUTES_ALARM 3 |
445 | 0824d6fc | bellard | #define RTC_HOURS 4 |
446 | 0824d6fc | bellard | #define RTC_HOURS_ALARM 5 |
447 | 0824d6fc | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
448 | 0824d6fc | bellard | |
449 | 0824d6fc | bellard | #define RTC_DAY_OF_WEEK 6 |
450 | 0824d6fc | bellard | #define RTC_DAY_OF_MONTH 7 |
451 | 0824d6fc | bellard | #define RTC_MONTH 8 |
452 | 0824d6fc | bellard | #define RTC_YEAR 9 |
453 | 0824d6fc | bellard | |
454 | 0824d6fc | bellard | #define RTC_REG_A 10 |
455 | 0824d6fc | bellard | #define RTC_REG_B 11 |
456 | 0824d6fc | bellard | #define RTC_REG_C 12 |
457 | 0824d6fc | bellard | #define RTC_REG_D 13 |
458 | 0824d6fc | bellard | |
459 | 0824d6fc | bellard | /* PC cmos mappings */
|
460 | 0824d6fc | bellard | #define REG_EQUIPMENT_BYTE 0x14 |
461 | 0824d6fc | bellard | |
462 | 0824d6fc | bellard | uint8_t cmos_data[128];
|
463 | 0824d6fc | bellard | uint8_t cmos_index; |
464 | 0824d6fc | bellard | |
465 | 0824d6fc | bellard | void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
466 | 0824d6fc | bellard | { |
467 | 0824d6fc | bellard | if (addr == 0x70) { |
468 | 0824d6fc | bellard | cmos_index = data & 0x7f;
|
469 | 7dea1da4 | bellard | } else {
|
470 | 7dea1da4 | bellard | #ifdef DEBUG_CMOS
|
471 | 7dea1da4 | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
|
472 | 7dea1da4 | bellard | cmos_index, data); |
473 | 7dea1da4 | bellard | #endif
|
474 | 7dea1da4 | bellard | switch(addr) {
|
475 | 7dea1da4 | bellard | case RTC_SECONDS_ALARM:
|
476 | 7dea1da4 | bellard | case RTC_MINUTES_ALARM:
|
477 | 7dea1da4 | bellard | case RTC_HOURS_ALARM:
|
478 | 7dea1da4 | bellard | /* XXX: not supported */
|
479 | 7dea1da4 | bellard | cmos_data[cmos_index] = data; |
480 | 7dea1da4 | bellard | break;
|
481 | 7dea1da4 | bellard | case RTC_SECONDS:
|
482 | 7dea1da4 | bellard | case RTC_MINUTES:
|
483 | 7dea1da4 | bellard | case RTC_HOURS:
|
484 | 7dea1da4 | bellard | case RTC_DAY_OF_WEEK:
|
485 | 7dea1da4 | bellard | case RTC_DAY_OF_MONTH:
|
486 | 7dea1da4 | bellard | case RTC_MONTH:
|
487 | 7dea1da4 | bellard | case RTC_YEAR:
|
488 | 7dea1da4 | bellard | cmos_data[cmos_index] = data; |
489 | 7dea1da4 | bellard | break;
|
490 | 7dea1da4 | bellard | case RTC_REG_A:
|
491 | 7dea1da4 | bellard | case RTC_REG_B:
|
492 | 7dea1da4 | bellard | cmos_data[cmos_index] = data; |
493 | 7dea1da4 | bellard | break;
|
494 | 7dea1da4 | bellard | case RTC_REG_C:
|
495 | 7dea1da4 | bellard | case RTC_REG_D:
|
496 | 7dea1da4 | bellard | /* cannot write to them */
|
497 | 7dea1da4 | bellard | break;
|
498 | 7dea1da4 | bellard | default:
|
499 | 7dea1da4 | bellard | cmos_data[cmos_index] = data; |
500 | 7dea1da4 | bellard | break;
|
501 | 7dea1da4 | bellard | } |
502 | 0824d6fc | bellard | } |
503 | 0824d6fc | bellard | } |
504 | 0824d6fc | bellard | |
505 | 0824d6fc | bellard | uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) |
506 | 0824d6fc | bellard | { |
507 | 0824d6fc | bellard | int ret;
|
508 | 0824d6fc | bellard | |
509 | 0824d6fc | bellard | if (addr == 0x70) { |
510 | 0824d6fc | bellard | return 0xff; |
511 | 0824d6fc | bellard | } else {
|
512 | 0824d6fc | bellard | ret = cmos_data[cmos_index]; |
513 | 7dea1da4 | bellard | switch(cmos_index) {
|
514 | 7dea1da4 | bellard | case RTC_REG_A:
|
515 | 7dea1da4 | bellard | /* toggle update-in-progress bit for Linux (same hack as
|
516 | 7dea1da4 | bellard | plex86) */
|
517 | 0824d6fc | bellard | cmos_data[RTC_REG_A] ^= 0x80;
|
518 | 7dea1da4 | bellard | break;
|
519 | 7dea1da4 | bellard | case RTC_REG_C:
|
520 | 7dea1da4 | bellard | pic_set_irq(8, 0); |
521 | 0824d6fc | bellard | cmos_data[RTC_REG_C] = 0x00;
|
522 | 7dea1da4 | bellard | break;
|
523 | 7dea1da4 | bellard | } |
524 | 7dea1da4 | bellard | #ifdef DEBUG_CMOS
|
525 | 7dea1da4 | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
526 | 7dea1da4 | bellard | cmos_index, ret); |
527 | 7dea1da4 | bellard | #endif
|
528 | 0824d6fc | bellard | return ret;
|
529 | 0824d6fc | bellard | } |
530 | 0824d6fc | bellard | } |
531 | 0824d6fc | bellard | |
532 | 0824d6fc | bellard | |
533 | 0824d6fc | bellard | static inline int to_bcd(int a) |
534 | 0824d6fc | bellard | { |
535 | 0824d6fc | bellard | return ((a / 10) << 4) | (a % 10); |
536 | 0824d6fc | bellard | } |
537 | 0824d6fc | bellard | |
538 | 0824d6fc | bellard | void cmos_init(void) |
539 | 0824d6fc | bellard | { |
540 | 0824d6fc | bellard | struct tm *tm;
|
541 | 0824d6fc | bellard | time_t ti; |
542 | 330d0414 | bellard | int val;
|
543 | 0824d6fc | bellard | |
544 | 0824d6fc | bellard | ti = time(NULL);
|
545 | 0824d6fc | bellard | tm = gmtime(&ti); |
546 | 0824d6fc | bellard | cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); |
547 | 0824d6fc | bellard | cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); |
548 | 0824d6fc | bellard | cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); |
549 | 0824d6fc | bellard | cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); |
550 | 0824d6fc | bellard | cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); |
551 | abd0aaff | bellard | cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
|
552 | 0824d6fc | bellard | cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
|
553 | 0824d6fc | bellard | |
554 | 0824d6fc | bellard | cmos_data[RTC_REG_A] = 0x26;
|
555 | 0824d6fc | bellard | cmos_data[RTC_REG_B] = 0x02;
|
556 | 0824d6fc | bellard | cmos_data[RTC_REG_C] = 0x00;
|
557 | 0824d6fc | bellard | cmos_data[RTC_REG_D] = 0x80;
|
558 | 0824d6fc | bellard | |
559 | 330d0414 | bellard | /* various important CMOS locations needed by PC/Bochs bios */
|
560 | 330d0414 | bellard | |
561 | 0824d6fc | bellard | cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
562 | 313aa567 | bellard | cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */ |
563 | 0824d6fc | bellard | |
564 | 330d0414 | bellard | /* memory size */
|
565 | 330d0414 | bellard | val = (phys_ram_size / 1024) - 1024; |
566 | 330d0414 | bellard | if (val > 65535) |
567 | 330d0414 | bellard | val = 65535;
|
568 | 330d0414 | bellard | cmos_data[0x17] = val;
|
569 | 330d0414 | bellard | cmos_data[0x18] = val >> 8; |
570 | 330d0414 | bellard | cmos_data[0x30] = val;
|
571 | 330d0414 | bellard | cmos_data[0x31] = val >> 8; |
572 | 330d0414 | bellard | |
573 | 330d0414 | bellard | val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
574 | 330d0414 | bellard | if (val > 65535) |
575 | 330d0414 | bellard | val = 65535;
|
576 | 330d0414 | bellard | cmos_data[0x34] = val;
|
577 | 330d0414 | bellard | cmos_data[0x35] = val >> 8; |
578 | 330d0414 | bellard | |
579 | 36b486bb | bellard | switch(boot_device) {
|
580 | 36b486bb | bellard | case 'a': |
581 | 36b486bb | bellard | cmos_data[0x3d] = 0x01; /* floppy boot */ |
582 | 36b486bb | bellard | break;
|
583 | 36b486bb | bellard | default:
|
584 | 36b486bb | bellard | case 'c': |
585 | 36b486bb | bellard | cmos_data[0x3d] = 0x02; /* hard drive boot */ |
586 | 36b486bb | bellard | break;
|
587 | 36b486bb | bellard | case 'd': |
588 | 36b486bb | bellard | cmos_data[0x3d] = 0x03; /* CD-ROM boot */ |
589 | 36b486bb | bellard | break;
|
590 | 36b486bb | bellard | } |
591 | 36b486bb | bellard | |
592 | fc01f7e7 | bellard | register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
593 | fc01f7e7 | bellard | register_ioport_read(0x70, 2, cmos_ioport_read, 1); |
594 | 0824d6fc | bellard | } |
595 | 0824d6fc | bellard | |
596 | 0824d6fc | bellard | /***********************************************************/
|
597 | 0824d6fc | bellard | /* 8259 pic emulation */
|
598 | 0824d6fc | bellard | |
599 | 0824d6fc | bellard | typedef struct PicState { |
600 | 0824d6fc | bellard | uint8_t last_irr; /* edge detection */
|
601 | 0824d6fc | bellard | uint8_t irr; /* interrupt request register */
|
602 | 0824d6fc | bellard | uint8_t imr; /* interrupt mask register */
|
603 | 0824d6fc | bellard | uint8_t isr; /* interrupt service register */
|
604 | 0824d6fc | bellard | uint8_t priority_add; /* used to compute irq priority */
|
605 | 0824d6fc | bellard | uint8_t irq_base; |
606 | 0824d6fc | bellard | uint8_t read_reg_select; |
607 | 0824d6fc | bellard | uint8_t special_mask; |
608 | 0824d6fc | bellard | uint8_t init_state; |
609 | 0824d6fc | bellard | uint8_t auto_eoi; |
610 | 0824d6fc | bellard | uint8_t rotate_on_autoeoi; |
611 | 0824d6fc | bellard | uint8_t init4; /* true if 4 byte init */
|
612 | 0824d6fc | bellard | } PicState; |
613 | 0824d6fc | bellard | |
614 | 0824d6fc | bellard | /* 0 is master pic, 1 is slave pic */
|
615 | 0824d6fc | bellard | PicState pics[2];
|
616 | 0824d6fc | bellard | int pic_irq_requested;
|
617 | 0824d6fc | bellard | |
618 | 0824d6fc | bellard | /* set irq level. If an edge is detected, then the IRR is set to 1 */
|
619 | 0824d6fc | bellard | static inline void pic_set_irq1(PicState *s, int irq, int level) |
620 | 0824d6fc | bellard | { |
621 | 0824d6fc | bellard | int mask;
|
622 | 0824d6fc | bellard | mask = 1 << irq;
|
623 | 0824d6fc | bellard | if (level) {
|
624 | 0824d6fc | bellard | if ((s->last_irr & mask) == 0) |
625 | 0824d6fc | bellard | s->irr |= mask; |
626 | 0824d6fc | bellard | s->last_irr |= mask; |
627 | 0824d6fc | bellard | } else {
|
628 | 0824d6fc | bellard | s->last_irr &= ~mask; |
629 | 0824d6fc | bellard | } |
630 | 0824d6fc | bellard | } |
631 | 0824d6fc | bellard | |
632 | 0824d6fc | bellard | static inline int get_priority(PicState *s, int mask) |
633 | 0824d6fc | bellard | { |
634 | 0824d6fc | bellard | int priority;
|
635 | 0824d6fc | bellard | if (mask == 0) |
636 | 0824d6fc | bellard | return -1; |
637 | 0824d6fc | bellard | priority = 7;
|
638 | 0824d6fc | bellard | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
639 | 0824d6fc | bellard | priority--; |
640 | 0824d6fc | bellard | return priority;
|
641 | 0824d6fc | bellard | } |
642 | 0824d6fc | bellard | |
643 | 0824d6fc | bellard | /* return the pic wanted interrupt. return -1 if none */
|
644 | 0824d6fc | bellard | static int pic_get_irq(PicState *s) |
645 | 0824d6fc | bellard | { |
646 | 0824d6fc | bellard | int mask, cur_priority, priority;
|
647 | 0824d6fc | bellard | |
648 | 0824d6fc | bellard | mask = s->irr & ~s->imr; |
649 | 0824d6fc | bellard | priority = get_priority(s, mask); |
650 | 0824d6fc | bellard | if (priority < 0) |
651 | 0824d6fc | bellard | return -1; |
652 | 0824d6fc | bellard | /* compute current priority */
|
653 | 0824d6fc | bellard | cur_priority = get_priority(s, s->isr); |
654 | 0824d6fc | bellard | if (priority > cur_priority) {
|
655 | 0824d6fc | bellard | /* higher priority found: an irq should be generated */
|
656 | 0824d6fc | bellard | return priority;
|
657 | 0824d6fc | bellard | } else {
|
658 | 0824d6fc | bellard | return -1; |
659 | 0824d6fc | bellard | } |
660 | 0824d6fc | bellard | } |
661 | 0824d6fc | bellard | |
662 | c9159e53 | bellard | /* raise irq to CPU if necessary. must be called every time the active
|
663 | c9159e53 | bellard | irq may change */
|
664 | c9159e53 | bellard | static void pic_update_irq(void) |
665 | 0824d6fc | bellard | { |
666 | 0824d6fc | bellard | int irq2, irq;
|
667 | 0824d6fc | bellard | |
668 | 0824d6fc | bellard | /* first look at slave pic */
|
669 | 0824d6fc | bellard | irq2 = pic_get_irq(&pics[1]);
|
670 | 0824d6fc | bellard | if (irq2 >= 0) { |
671 | 0824d6fc | bellard | /* if irq request by slave pic, signal master PIC */
|
672 | 0824d6fc | bellard | pic_set_irq1(&pics[0], 2, 1); |
673 | 0824d6fc | bellard | pic_set_irq1(&pics[0], 2, 0); |
674 | 0824d6fc | bellard | } |
675 | 0824d6fc | bellard | /* look at requested irq */
|
676 | 0824d6fc | bellard | irq = pic_get_irq(&pics[0]);
|
677 | 0824d6fc | bellard | if (irq >= 0) { |
678 | 0824d6fc | bellard | if (irq == 2) { |
679 | 0824d6fc | bellard | /* from slave pic */
|
680 | 0824d6fc | bellard | pic_irq_requested = 8 + irq2;
|
681 | 0824d6fc | bellard | } else {
|
682 | 0824d6fc | bellard | /* from master pic */
|
683 | 0824d6fc | bellard | pic_irq_requested = irq; |
684 | 0824d6fc | bellard | } |
685 | c9159e53 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD); |
686 | 0824d6fc | bellard | } |
687 | 0824d6fc | bellard | } |
688 | 0824d6fc | bellard | |
689 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
690 | c9159e53 | bellard | int64_t irq_time[16];
|
691 | c9159e53 | bellard | int64_t cpu_get_ticks(void);
|
692 | c9159e53 | bellard | #endif
|
693 | 313aa567 | bellard | #if defined(DEBUG_PIC)
|
694 | b118d61e | bellard | int irq_level[16]; |
695 | b118d61e | bellard | #endif
|
696 | c9159e53 | bellard | |
697 | c9159e53 | bellard | void pic_set_irq(int irq, int level) |
698 | c9159e53 | bellard | { |
699 | 313aa567 | bellard | #if defined(DEBUG_PIC)
|
700 | b118d61e | bellard | if (level != irq_level[irq]) {
|
701 | b118d61e | bellard | printf("pic_set_irq: irq=%d level=%d\n", irq, level);
|
702 | b118d61e | bellard | irq_level[irq] = level; |
703 | b118d61e | bellard | } |
704 | b118d61e | bellard | #endif
|
705 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
706 | c9159e53 | bellard | if (level) {
|
707 | c9159e53 | bellard | irq_time[irq] = cpu_get_ticks(); |
708 | c9159e53 | bellard | } |
709 | c9159e53 | bellard | #endif
|
710 | c9159e53 | bellard | pic_set_irq1(&pics[irq >> 3], irq & 7, level); |
711 | c9159e53 | bellard | pic_update_irq(); |
712 | c9159e53 | bellard | } |
713 | c9159e53 | bellard | |
714 | 0824d6fc | bellard | int cpu_x86_get_pic_interrupt(CPUX86State *env)
|
715 | 0824d6fc | bellard | { |
716 | 0824d6fc | bellard | int irq, irq2, intno;
|
717 | 0824d6fc | bellard | |
718 | 0824d6fc | bellard | /* signal the pic that the irq was acked by the CPU */
|
719 | 0824d6fc | bellard | irq = pic_irq_requested; |
720 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
721 | 313aa567 | bellard | printf("IRQ%d latency=%0.3fus\n",
|
722 | 313aa567 | bellard | irq, |
723 | 313aa567 | bellard | (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec); |
724 | c9159e53 | bellard | #endif
|
725 | 7dea1da4 | bellard | #if defined(DEBUG_PIC)
|
726 | b118d61e | bellard | printf("pic_interrupt: irq=%d\n", irq);
|
727 | b118d61e | bellard | #endif
|
728 | c9159e53 | bellard | |
729 | 0824d6fc | bellard | if (irq >= 8) { |
730 | 0824d6fc | bellard | irq2 = irq & 7;
|
731 | 0824d6fc | bellard | pics[1].isr |= (1 << irq2); |
732 | 0824d6fc | bellard | pics[1].irr &= ~(1 << irq2); |
733 | 0824d6fc | bellard | irq = 2;
|
734 | 0824d6fc | bellard | intno = pics[1].irq_base + irq2;
|
735 | 0824d6fc | bellard | } else {
|
736 | 0824d6fc | bellard | intno = pics[0].irq_base + irq;
|
737 | 0824d6fc | bellard | } |
738 | 0824d6fc | bellard | pics[0].isr |= (1 << irq); |
739 | 0824d6fc | bellard | pics[0].irr &= ~(1 << irq); |
740 | 0824d6fc | bellard | return intno;
|
741 | 0824d6fc | bellard | } |
742 | 0824d6fc | bellard | |
743 | 0824d6fc | bellard | void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
744 | 0824d6fc | bellard | { |
745 | 0824d6fc | bellard | PicState *s; |
746 | 0824d6fc | bellard | int priority;
|
747 | 0824d6fc | bellard | |
748 | b118d61e | bellard | #ifdef DEBUG_PIC
|
749 | b118d61e | bellard | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
|
750 | b118d61e | bellard | #endif
|
751 | 0824d6fc | bellard | s = &pics[addr >> 7];
|
752 | 0824d6fc | bellard | addr &= 1;
|
753 | 0824d6fc | bellard | if (addr == 0) { |
754 | 0824d6fc | bellard | if (val & 0x10) { |
755 | 0824d6fc | bellard | /* init */
|
756 | 0824d6fc | bellard | memset(s, 0, sizeof(PicState)); |
757 | 0824d6fc | bellard | s->init_state = 1;
|
758 | 0824d6fc | bellard | s->init4 = val & 1;
|
759 | 0824d6fc | bellard | if (val & 0x02) |
760 | 0824d6fc | bellard | hw_error("single mode not supported");
|
761 | 0824d6fc | bellard | if (val & 0x08) |
762 | 0824d6fc | bellard | hw_error("level sensitive irq not supported");
|
763 | 0824d6fc | bellard | } else if (val & 0x08) { |
764 | 0824d6fc | bellard | if (val & 0x02) |
765 | 0824d6fc | bellard | s->read_reg_select = val & 1;
|
766 | 0824d6fc | bellard | if (val & 0x40) |
767 | 0824d6fc | bellard | s->special_mask = (val >> 5) & 1; |
768 | 0824d6fc | bellard | } else {
|
769 | 0824d6fc | bellard | switch(val) {
|
770 | 0824d6fc | bellard | case 0x00: |
771 | 0824d6fc | bellard | case 0x80: |
772 | 0824d6fc | bellard | s->rotate_on_autoeoi = val >> 7;
|
773 | 0824d6fc | bellard | break;
|
774 | 0824d6fc | bellard | case 0x20: /* end of interrupt */ |
775 | 0824d6fc | bellard | case 0xa0: |
776 | 0824d6fc | bellard | priority = get_priority(s, s->isr); |
777 | 0824d6fc | bellard | if (priority >= 0) { |
778 | 0824d6fc | bellard | s->isr &= ~(1 << ((priority + s->priority_add) & 7)); |
779 | 0824d6fc | bellard | } |
780 | 0824d6fc | bellard | if (val == 0xa0) |
781 | 0824d6fc | bellard | s->priority_add = (s->priority_add + 1) & 7; |
782 | 313aa567 | bellard | pic_update_irq(); |
783 | 0824d6fc | bellard | break;
|
784 | 0824d6fc | bellard | case 0x60 ... 0x67: |
785 | 0824d6fc | bellard | priority = val & 7;
|
786 | 0824d6fc | bellard | s->isr &= ~(1 << priority);
|
787 | 313aa567 | bellard | pic_update_irq(); |
788 | 0824d6fc | bellard | break;
|
789 | 0824d6fc | bellard | case 0xc0 ... 0xc7: |
790 | 0824d6fc | bellard | s->priority_add = (val + 1) & 7; |
791 | 313aa567 | bellard | pic_update_irq(); |
792 | 0824d6fc | bellard | break;
|
793 | 0824d6fc | bellard | case 0xe0 ... 0xe7: |
794 | 0824d6fc | bellard | priority = val & 7;
|
795 | 0824d6fc | bellard | s->isr &= ~(1 << priority);
|
796 | 0824d6fc | bellard | s->priority_add = (priority + 1) & 7; |
797 | 313aa567 | bellard | pic_update_irq(); |
798 | 0824d6fc | bellard | break;
|
799 | 0824d6fc | bellard | } |
800 | 0824d6fc | bellard | } |
801 | 0824d6fc | bellard | } else {
|
802 | 0824d6fc | bellard | switch(s->init_state) {
|
803 | 0824d6fc | bellard | case 0: |
804 | 0824d6fc | bellard | /* normal mode */
|
805 | 0824d6fc | bellard | s->imr = val; |
806 | c9159e53 | bellard | pic_update_irq(); |
807 | 0824d6fc | bellard | break;
|
808 | 0824d6fc | bellard | case 1: |
809 | 0824d6fc | bellard | s->irq_base = val & 0xf8;
|
810 | 0824d6fc | bellard | s->init_state = 2;
|
811 | 0824d6fc | bellard | break;
|
812 | 0824d6fc | bellard | case 2: |
813 | 0824d6fc | bellard | if (s->init4) {
|
814 | 0824d6fc | bellard | s->init_state = 3;
|
815 | 0824d6fc | bellard | } else {
|
816 | 0824d6fc | bellard | s->init_state = 0;
|
817 | 0824d6fc | bellard | } |
818 | 0824d6fc | bellard | break;
|
819 | 0824d6fc | bellard | case 3: |
820 | 0824d6fc | bellard | s->auto_eoi = (val >> 1) & 1; |
821 | 0824d6fc | bellard | s->init_state = 0;
|
822 | 0824d6fc | bellard | break;
|
823 | 0824d6fc | bellard | } |
824 | 0824d6fc | bellard | } |
825 | 0824d6fc | bellard | } |
826 | 0824d6fc | bellard | |
827 | b118d61e | bellard | uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1) |
828 | 0824d6fc | bellard | { |
829 | 0824d6fc | bellard | PicState *s; |
830 | b118d61e | bellard | unsigned int addr; |
831 | b118d61e | bellard | int ret;
|
832 | b118d61e | bellard | |
833 | b118d61e | bellard | addr = addr1; |
834 | 0824d6fc | bellard | s = &pics[addr >> 7];
|
835 | 0824d6fc | bellard | addr &= 1;
|
836 | 0824d6fc | bellard | if (addr == 0) { |
837 | 0824d6fc | bellard | if (s->read_reg_select)
|
838 | b118d61e | bellard | ret = s->isr; |
839 | 0824d6fc | bellard | else
|
840 | b118d61e | bellard | ret = s->irr; |
841 | 0824d6fc | bellard | } else {
|
842 | b118d61e | bellard | ret = s->imr; |
843 | 0824d6fc | bellard | } |
844 | b118d61e | bellard | #ifdef DEBUG_PIC
|
845 | b118d61e | bellard | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
|
846 | b118d61e | bellard | #endif
|
847 | b118d61e | bellard | return ret;
|
848 | 0824d6fc | bellard | } |
849 | 0824d6fc | bellard | |
850 | 0824d6fc | bellard | void pic_init(void) |
851 | 0824d6fc | bellard | { |
852 | fc01f7e7 | bellard | register_ioport_write(0x20, 2, pic_ioport_write, 1); |
853 | fc01f7e7 | bellard | register_ioport_read(0x20, 2, pic_ioport_read, 1); |
854 | fc01f7e7 | bellard | register_ioport_write(0xa0, 2, pic_ioport_write, 1); |
855 | fc01f7e7 | bellard | register_ioport_read(0xa0, 2, pic_ioport_read, 1); |
856 | 0824d6fc | bellard | } |
857 | 0824d6fc | bellard | |
858 | 0824d6fc | bellard | /***********************************************************/
|
859 | 0824d6fc | bellard | /* 8253 PIT emulation */
|
860 | 0824d6fc | bellard | |
861 | 0824d6fc | bellard | #define PIT_FREQ 1193182 |
862 | 0824d6fc | bellard | |
863 | 0824d6fc | bellard | #define RW_STATE_LSB 0 |
864 | 0824d6fc | bellard | #define RW_STATE_MSB 1 |
865 | 0824d6fc | bellard | #define RW_STATE_WORD0 2 |
866 | 0824d6fc | bellard | #define RW_STATE_WORD1 3 |
867 | 0824d6fc | bellard | #define RW_STATE_LATCHED_WORD0 4 |
868 | 0824d6fc | bellard | #define RW_STATE_LATCHED_WORD1 5 |
869 | 0824d6fc | bellard | |
870 | 0824d6fc | bellard | typedef struct PITChannelState { |
871 | 87858c89 | bellard | int count; /* can be 65536 */ |
872 | 0824d6fc | bellard | uint16_t latched_count; |
873 | 0824d6fc | bellard | uint8_t rw_state; |
874 | 0824d6fc | bellard | uint8_t mode; |
875 | 0824d6fc | bellard | uint8_t bcd; /* not supported */
|
876 | 0824d6fc | bellard | uint8_t gate; /* timer start */
|
877 | 0824d6fc | bellard | int64_t count_load_time; |
878 | 87858c89 | bellard | int64_t count_last_edge_check_time; |
879 | 0824d6fc | bellard | } PITChannelState; |
880 | 0824d6fc | bellard | |
881 | 0824d6fc | bellard | PITChannelState pit_channels[3];
|
882 | 0824d6fc | bellard | int speaker_data_on;
|
883 | 61a2ad53 | bellard | int dummy_refresh_clock;
|
884 | 87858c89 | bellard | int pit_min_timer_count = 0; |
885 | 0824d6fc | bellard | |
886 | 34865134 | bellard | |
887 | 34865134 | bellard | #if defined(__powerpc__)
|
888 | 34865134 | bellard | |
889 | 34865134 | bellard | static inline uint32_t get_tbl(void) |
890 | 0824d6fc | bellard | { |
891 | 34865134 | bellard | uint32_t tbl; |
892 | 34865134 | bellard | asm volatile("mftb %0" : "=r" (tbl)); |
893 | 34865134 | bellard | return tbl;
|
894 | 0824d6fc | bellard | } |
895 | 0824d6fc | bellard | |
896 | 34865134 | bellard | static inline uint32_t get_tbu(void) |
897 | 34865134 | bellard | { |
898 | 34865134 | bellard | uint32_t tbl; |
899 | 34865134 | bellard | asm volatile("mftbu %0" : "=r" (tbl)); |
900 | 34865134 | bellard | return tbl;
|
901 | 34865134 | bellard | } |
902 | 34865134 | bellard | |
903 | 34865134 | bellard | int64_t cpu_get_real_ticks(void)
|
904 | 34865134 | bellard | { |
905 | 34865134 | bellard | uint32_t l, h, h1; |
906 | 34865134 | bellard | /* NOTE: we test if wrapping has occurred */
|
907 | 34865134 | bellard | do {
|
908 | 34865134 | bellard | h = get_tbu(); |
909 | 34865134 | bellard | l = get_tbl(); |
910 | 34865134 | bellard | h1 = get_tbu(); |
911 | 34865134 | bellard | } while (h != h1);
|
912 | 34865134 | bellard | return ((int64_t)h << 32) | l; |
913 | 34865134 | bellard | } |
914 | 34865134 | bellard | |
915 | 34865134 | bellard | #elif defined(__i386__)
|
916 | 34865134 | bellard | |
917 | 34865134 | bellard | int64_t cpu_get_real_ticks(void)
|
918 | 0824d6fc | bellard | { |
919 | 0824d6fc | bellard | int64_t val; |
920 | 0824d6fc | bellard | asm("rdtsc" : "=A" (val)); |
921 | 0824d6fc | bellard | return val;
|
922 | 0824d6fc | bellard | } |
923 | 0824d6fc | bellard | |
924 | 34865134 | bellard | #else
|
925 | 34865134 | bellard | #error unsupported CPU
|
926 | 34865134 | bellard | #endif
|
927 | 34865134 | bellard | |
928 | 34865134 | bellard | static int64_t cpu_ticks_offset;
|
929 | 34865134 | bellard | static int64_t cpu_ticks_last;
|
930 | 34865134 | bellard | |
931 | 34865134 | bellard | int64_t cpu_get_ticks(void)
|
932 | 34865134 | bellard | { |
933 | 34865134 | bellard | return cpu_get_real_ticks() + cpu_ticks_offset;
|
934 | 34865134 | bellard | } |
935 | 34865134 | bellard | |
936 | 34865134 | bellard | /* enable cpu_get_ticks() */
|
937 | 34865134 | bellard | void cpu_enable_ticks(void) |
938 | 34865134 | bellard | { |
939 | 34865134 | bellard | cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks(); |
940 | 34865134 | bellard | } |
941 | 34865134 | bellard | |
942 | 34865134 | bellard | /* disable cpu_get_ticks() : the clock is stopped. You must not call
|
943 | 34865134 | bellard | cpu_get_ticks() after that. */
|
944 | 34865134 | bellard | void cpu_disable_ticks(void) |
945 | 34865134 | bellard | { |
946 | 34865134 | bellard | cpu_ticks_last = cpu_get_ticks(); |
947 | 34865134 | bellard | } |
948 | 34865134 | bellard | |
949 | 34865134 | bellard | int64_t get_clock(void)
|
950 | 34865134 | bellard | { |
951 | 34865134 | bellard | struct timeval tv;
|
952 | 34865134 | bellard | gettimeofday(&tv, NULL);
|
953 | 34865134 | bellard | return tv.tv_sec * 1000000LL + tv.tv_usec; |
954 | 34865134 | bellard | } |
955 | 34865134 | bellard | |
956 | 0824d6fc | bellard | void cpu_calibrate_ticks(void) |
957 | 0824d6fc | bellard | { |
958 | 0824d6fc | bellard | int64_t usec, ticks; |
959 | 0824d6fc | bellard | |
960 | 0824d6fc | bellard | usec = get_clock(); |
961 | 0824d6fc | bellard | ticks = cpu_get_ticks(); |
962 | 0824d6fc | bellard | usleep(50 * 1000); |
963 | 0824d6fc | bellard | usec = get_clock() - usec; |
964 | 0824d6fc | bellard | ticks = cpu_get_ticks() - ticks; |
965 | 0824d6fc | bellard | ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; |
966 | 0824d6fc | bellard | } |
967 | 0824d6fc | bellard | |
968 | 87858c89 | bellard | /* compute with 96 bit intermediate result: (a*b)/c */
|
969 | 87858c89 | bellard | static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
|
970 | 87858c89 | bellard | { |
971 | 87858c89 | bellard | union {
|
972 | 87858c89 | bellard | uint64_t ll; |
973 | 87858c89 | bellard | struct {
|
974 | 87858c89 | bellard | #ifdef WORDS_BIGENDIAN
|
975 | 87858c89 | bellard | uint32_t high, low; |
976 | 87858c89 | bellard | #else
|
977 | 87858c89 | bellard | uint32_t low, high; |
978 | 87858c89 | bellard | #endif
|
979 | 87858c89 | bellard | } l; |
980 | 87858c89 | bellard | } u, res; |
981 | 87858c89 | bellard | uint64_t rl, rh; |
982 | 87858c89 | bellard | |
983 | 87858c89 | bellard | u.ll = a; |
984 | 87858c89 | bellard | rl = (uint64_t)u.l.low * (uint64_t)b; |
985 | 87858c89 | bellard | rh = (uint64_t)u.l.high * (uint64_t)b; |
986 | 87858c89 | bellard | rh += (rl >> 32);
|
987 | 87858c89 | bellard | res.l.high = rh / c; |
988 | 87858c89 | bellard | res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; |
989 | 87858c89 | bellard | return res.ll;
|
990 | 87858c89 | bellard | } |
991 | 87858c89 | bellard | |
992 | 0824d6fc | bellard | static int pit_get_count(PITChannelState *s) |
993 | 0824d6fc | bellard | { |
994 | 87858c89 | bellard | uint64_t d; |
995 | 0824d6fc | bellard | int counter;
|
996 | 0824d6fc | bellard | |
997 | 87858c89 | bellard | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
998 | 0824d6fc | bellard | switch(s->mode) {
|
999 | 0824d6fc | bellard | case 0: |
1000 | 0824d6fc | bellard | case 1: |
1001 | 0824d6fc | bellard | case 4: |
1002 | 0824d6fc | bellard | case 5: |
1003 | 0824d6fc | bellard | counter = (s->count - d) & 0xffff;
|
1004 | 0824d6fc | bellard | break;
|
1005 | 0824d6fc | bellard | default:
|
1006 | 0824d6fc | bellard | counter = s->count - (d % s->count); |
1007 | 0824d6fc | bellard | break;
|
1008 | 0824d6fc | bellard | } |
1009 | 0824d6fc | bellard | return counter;
|
1010 | 0824d6fc | bellard | } |
1011 | 0824d6fc | bellard | |
1012 | 0824d6fc | bellard | /* get pit output bit */
|
1013 | 0824d6fc | bellard | static int pit_get_out(PITChannelState *s) |
1014 | 0824d6fc | bellard | { |
1015 | 87858c89 | bellard | uint64_t d; |
1016 | 0824d6fc | bellard | int out;
|
1017 | 0824d6fc | bellard | |
1018 | 87858c89 | bellard | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
1019 | 0824d6fc | bellard | switch(s->mode) {
|
1020 | 0824d6fc | bellard | default:
|
1021 | 0824d6fc | bellard | case 0: |
1022 | 0824d6fc | bellard | out = (d >= s->count); |
1023 | 0824d6fc | bellard | break;
|
1024 | 0824d6fc | bellard | case 1: |
1025 | 0824d6fc | bellard | out = (d < s->count); |
1026 | 0824d6fc | bellard | break;
|
1027 | 0824d6fc | bellard | case 2: |
1028 | 0824d6fc | bellard | if ((d % s->count) == 0 && d != 0) |
1029 | 0824d6fc | bellard | out = 1;
|
1030 | 0824d6fc | bellard | else
|
1031 | 0824d6fc | bellard | out = 0;
|
1032 | 0824d6fc | bellard | break;
|
1033 | 0824d6fc | bellard | case 3: |
1034 | 0824d6fc | bellard | out = (d % s->count) < (s->count >> 1);
|
1035 | 0824d6fc | bellard | break;
|
1036 | 0824d6fc | bellard | case 4: |
1037 | 0824d6fc | bellard | case 5: |
1038 | 0824d6fc | bellard | out = (d == s->count); |
1039 | 0824d6fc | bellard | break;
|
1040 | 0824d6fc | bellard | } |
1041 | 0824d6fc | bellard | return out;
|
1042 | 0824d6fc | bellard | } |
1043 | 0824d6fc | bellard | |
1044 | 87858c89 | bellard | /* get the number of 0 to 1 transitions we had since we call this
|
1045 | 87858c89 | bellard | function */
|
1046 | 87858c89 | bellard | /* XXX: maybe better to use ticks precision to avoid getting edges
|
1047 | 87858c89 | bellard | twice if checks are done at very small intervals */
|
1048 | 87858c89 | bellard | static int pit_get_out_edges(PITChannelState *s) |
1049 | 87858c89 | bellard | { |
1050 | 87858c89 | bellard | uint64_t d1, d2; |
1051 | 87858c89 | bellard | int64_t ticks; |
1052 | 87858c89 | bellard | int ret, v;
|
1053 | 87858c89 | bellard | |
1054 | 87858c89 | bellard | ticks = cpu_get_ticks(); |
1055 | 87858c89 | bellard | d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, |
1056 | 87858c89 | bellard | PIT_FREQ, ticks_per_sec); |
1057 | 87858c89 | bellard | d2 = muldiv64(ticks - s->count_load_time, |
1058 | 87858c89 | bellard | PIT_FREQ, ticks_per_sec); |
1059 | 87858c89 | bellard | s->count_last_edge_check_time = ticks; |
1060 | 87858c89 | bellard | switch(s->mode) {
|
1061 | 87858c89 | bellard | default:
|
1062 | 87858c89 | bellard | case 0: |
1063 | 87858c89 | bellard | if (d1 < s->count && d2 >= s->count)
|
1064 | 87858c89 | bellard | ret = 1;
|
1065 | 87858c89 | bellard | else
|
1066 | 87858c89 | bellard | ret = 0;
|
1067 | 87858c89 | bellard | break;
|
1068 | 87858c89 | bellard | case 1: |
1069 | 87858c89 | bellard | ret = 0;
|
1070 | 87858c89 | bellard | break;
|
1071 | 87858c89 | bellard | case 2: |
1072 | 87858c89 | bellard | d1 /= s->count; |
1073 | 87858c89 | bellard | d2 /= s->count; |
1074 | 87858c89 | bellard | ret = d2 - d1; |
1075 | 87858c89 | bellard | break;
|
1076 | 87858c89 | bellard | case 3: |
1077 | 87858c89 | bellard | v = s->count - (s->count >> 1);
|
1078 | 87858c89 | bellard | d1 = (d1 + v) / s->count; |
1079 | 87858c89 | bellard | d2 = (d2 + v) / s->count; |
1080 | 87858c89 | bellard | ret = d2 - d1; |
1081 | 87858c89 | bellard | break;
|
1082 | 87858c89 | bellard | case 4: |
1083 | 87858c89 | bellard | case 5: |
1084 | 87858c89 | bellard | if (d1 < s->count && d2 >= s->count)
|
1085 | 87858c89 | bellard | ret = 1;
|
1086 | 87858c89 | bellard | else
|
1087 | 87858c89 | bellard | ret = 0;
|
1088 | 87858c89 | bellard | break;
|
1089 | 87858c89 | bellard | } |
1090 | 87858c89 | bellard | return ret;
|
1091 | 87858c89 | bellard | } |
1092 | 87858c89 | bellard | |
1093 | 87858c89 | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
1094 | 87858c89 | bellard | { |
1095 | 87858c89 | bellard | if (val == 0) |
1096 | 87858c89 | bellard | val = 0x10000;
|
1097 | 87858c89 | bellard | s->count_load_time = cpu_get_ticks(); |
1098 | 87858c89 | bellard | s->count_last_edge_check_time = s->count_load_time; |
1099 | 87858c89 | bellard | s->count = val; |
1100 | 87858c89 | bellard | if (s == &pit_channels[0] && val <= pit_min_timer_count) { |
1101 | 87858c89 | bellard | fprintf(stderr, |
1102 | 36b486bb | bellard | "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
|
1103 | 87858c89 | bellard | PIT_FREQ / pit_min_timer_count); |
1104 | 87858c89 | bellard | } |
1105 | 87858c89 | bellard | } |
1106 | 87858c89 | bellard | |
1107 | 0824d6fc | bellard | void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1108 | 0824d6fc | bellard | { |
1109 | 0824d6fc | bellard | int channel, access;
|
1110 | 0824d6fc | bellard | PITChannelState *s; |
1111 | 87858c89 | bellard | |
1112 | 0824d6fc | bellard | addr &= 3;
|
1113 | 0824d6fc | bellard | if (addr == 3) { |
1114 | 0824d6fc | bellard | channel = val >> 6;
|
1115 | 0824d6fc | bellard | if (channel == 3) |
1116 | 0824d6fc | bellard | return;
|
1117 | 0824d6fc | bellard | s = &pit_channels[channel]; |
1118 | 0824d6fc | bellard | access = (val >> 4) & 3; |
1119 | 0824d6fc | bellard | switch(access) {
|
1120 | 0824d6fc | bellard | case 0: |
1121 | 0824d6fc | bellard | s->latched_count = pit_get_count(s); |
1122 | 0824d6fc | bellard | s->rw_state = RW_STATE_LATCHED_WORD0; |
1123 | 0824d6fc | bellard | break;
|
1124 | 0824d6fc | bellard | default:
|
1125 | 87858c89 | bellard | s->mode = (val >> 1) & 7; |
1126 | 87858c89 | bellard | s->bcd = val & 1;
|
1127 | 0824d6fc | bellard | s->rw_state = access - 1 + RW_STATE_LSB;
|
1128 | 0824d6fc | bellard | break;
|
1129 | 0824d6fc | bellard | } |
1130 | 0824d6fc | bellard | } else {
|
1131 | 0824d6fc | bellard | s = &pit_channels[addr]; |
1132 | 0824d6fc | bellard | switch(s->rw_state) {
|
1133 | 0824d6fc | bellard | case RW_STATE_LSB:
|
1134 | 87858c89 | bellard | pit_load_count(s, val); |
1135 | 0824d6fc | bellard | break;
|
1136 | 0824d6fc | bellard | case RW_STATE_MSB:
|
1137 | 87858c89 | bellard | pit_load_count(s, val << 8);
|
1138 | 0824d6fc | bellard | break;
|
1139 | 0824d6fc | bellard | case RW_STATE_WORD0:
|
1140 | 0824d6fc | bellard | case RW_STATE_WORD1:
|
1141 | 0824d6fc | bellard | if (s->rw_state & 1) { |
1142 | 87858c89 | bellard | pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
1143 | 0824d6fc | bellard | } else {
|
1144 | 0824d6fc | bellard | s->latched_count = val; |
1145 | 0824d6fc | bellard | } |
1146 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1147 | 0824d6fc | bellard | break;
|
1148 | 0824d6fc | bellard | } |
1149 | 0824d6fc | bellard | } |
1150 | 0824d6fc | bellard | } |
1151 | 0824d6fc | bellard | |
1152 | 0824d6fc | bellard | uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) |
1153 | 0824d6fc | bellard | { |
1154 | 0824d6fc | bellard | int ret, count;
|
1155 | 0824d6fc | bellard | PITChannelState *s; |
1156 | 0824d6fc | bellard | |
1157 | 0824d6fc | bellard | addr &= 3;
|
1158 | 0824d6fc | bellard | s = &pit_channels[addr]; |
1159 | 0824d6fc | bellard | switch(s->rw_state) {
|
1160 | 0824d6fc | bellard | case RW_STATE_LSB:
|
1161 | 0824d6fc | bellard | case RW_STATE_MSB:
|
1162 | 0824d6fc | bellard | case RW_STATE_WORD0:
|
1163 | 0824d6fc | bellard | case RW_STATE_WORD1:
|
1164 | 0824d6fc | bellard | count = pit_get_count(s); |
1165 | 0824d6fc | bellard | if (s->rw_state & 1) |
1166 | 0824d6fc | bellard | ret = (count >> 8) & 0xff; |
1167 | 0824d6fc | bellard | else
|
1168 | 0824d6fc | bellard | ret = count & 0xff;
|
1169 | 0824d6fc | bellard | if (s->rw_state & 2) |
1170 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1171 | 0824d6fc | bellard | break;
|
1172 | 0824d6fc | bellard | default:
|
1173 | 0824d6fc | bellard | case RW_STATE_LATCHED_WORD0:
|
1174 | 0824d6fc | bellard | case RW_STATE_LATCHED_WORD1:
|
1175 | 0824d6fc | bellard | if (s->rw_state & 1) |
1176 | 0824d6fc | bellard | ret = s->latched_count >> 8;
|
1177 | 0824d6fc | bellard | else
|
1178 | 0824d6fc | bellard | ret = s->latched_count & 0xff;
|
1179 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1180 | 0824d6fc | bellard | break;
|
1181 | 0824d6fc | bellard | } |
1182 | 0824d6fc | bellard | return ret;
|
1183 | 0824d6fc | bellard | } |
1184 | 0824d6fc | bellard | |
1185 | 0824d6fc | bellard | void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1186 | 0824d6fc | bellard | { |
1187 | 0824d6fc | bellard | speaker_data_on = (val >> 1) & 1; |
1188 | 0824d6fc | bellard | pit_channels[2].gate = val & 1; |
1189 | 0824d6fc | bellard | } |
1190 | 0824d6fc | bellard | |
1191 | 0824d6fc | bellard | uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) |
1192 | 0824d6fc | bellard | { |
1193 | 0824d6fc | bellard | int out;
|
1194 | 0824d6fc | bellard | out = pit_get_out(&pit_channels[2]);
|
1195 | 61a2ad53 | bellard | dummy_refresh_clock ^= 1;
|
1196 | 61a2ad53 | bellard | return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) | |
1197 | 61a2ad53 | bellard | (dummy_refresh_clock << 4);
|
1198 | 0824d6fc | bellard | } |
1199 | 0824d6fc | bellard | |
1200 | 0824d6fc | bellard | void pit_init(void) |
1201 | 0824d6fc | bellard | { |
1202 | 87858c89 | bellard | PITChannelState *s; |
1203 | 87858c89 | bellard | int i;
|
1204 | 87858c89 | bellard | |
1205 | 87858c89 | bellard | cpu_calibrate_ticks(); |
1206 | 87858c89 | bellard | |
1207 | 87858c89 | bellard | for(i = 0;i < 3; i++) { |
1208 | 87858c89 | bellard | s = &pit_channels[i]; |
1209 | 87858c89 | bellard | s->mode = 3;
|
1210 | 87858c89 | bellard | s->gate = (i != 2);
|
1211 | 87858c89 | bellard | pit_load_count(s, 0);
|
1212 | 87858c89 | bellard | } |
1213 | 87858c89 | bellard | |
1214 | fc01f7e7 | bellard | register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1215 | fc01f7e7 | bellard | register_ioport_read(0x40, 3, pit_ioport_read, 1); |
1216 | 0824d6fc | bellard | |
1217 | fc01f7e7 | bellard | register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1218 | fc01f7e7 | bellard | register_ioport_write(0x61, 1, speaker_ioport_write, 1); |
1219 | 0824d6fc | bellard | } |
1220 | 0824d6fc | bellard | |
1221 | 0824d6fc | bellard | /***********************************************************/
|
1222 | 0824d6fc | bellard | /* serial port emulation */
|
1223 | 0824d6fc | bellard | |
1224 | 0824d6fc | bellard | #define UART_IRQ 4 |
1225 | 0824d6fc | bellard | |
1226 | 0824d6fc | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
1227 | 0824d6fc | bellard | |
1228 | 0824d6fc | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
1229 | 0824d6fc | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
1230 | 0824d6fc | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
1231 | 0824d6fc | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
1232 | 0824d6fc | bellard | |
1233 | 0824d6fc | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
1234 | 0824d6fc | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
1235 | 0824d6fc | bellard | |
1236 | 0824d6fc | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
1237 | 0824d6fc | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
1238 | 0824d6fc | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
1239 | 0824d6fc | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
1240 | 0824d6fc | bellard | |
1241 | 7dea1da4 | bellard | /*
|
1242 | 7dea1da4 | bellard | * These are the definitions for the Modem Control Register
|
1243 | 7dea1da4 | bellard | */
|
1244 | 7dea1da4 | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
1245 | 7dea1da4 | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
1246 | 7dea1da4 | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
1247 | 7dea1da4 | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
1248 | 7dea1da4 | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
1249 | 7dea1da4 | bellard | |
1250 | 7dea1da4 | bellard | /*
|
1251 | 7dea1da4 | bellard | * These are the definitions for the Modem Status Register
|
1252 | 7dea1da4 | bellard | */
|
1253 | 7dea1da4 | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
1254 | 7dea1da4 | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
1255 | 7dea1da4 | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
1256 | 7dea1da4 | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
1257 | 7dea1da4 | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
1258 | 7dea1da4 | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
1259 | 7dea1da4 | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
1260 | 7dea1da4 | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
1261 | 7dea1da4 | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
1262 | 7dea1da4 | bellard | |
1263 | 0824d6fc | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1264 | 0824d6fc | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
1265 | 0824d6fc | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
1266 | 0824d6fc | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
1267 | 0824d6fc | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
1268 | 0824d6fc | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
1269 | 0824d6fc | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
1270 | 0824d6fc | bellard | |
1271 | 0824d6fc | bellard | typedef struct SerialState { |
1272 | 0824d6fc | bellard | uint8_t divider; |
1273 | 0824d6fc | bellard | uint8_t rbr; /* receive register */
|
1274 | 0824d6fc | bellard | uint8_t ier; |
1275 | 0824d6fc | bellard | uint8_t iir; /* read only */
|
1276 | 0824d6fc | bellard | uint8_t lcr; |
1277 | 0824d6fc | bellard | uint8_t mcr; |
1278 | 0824d6fc | bellard | uint8_t lsr; /* read only */
|
1279 | 0824d6fc | bellard | uint8_t msr; |
1280 | 0824d6fc | bellard | uint8_t scr; |
1281 | 7dea1da4 | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
|
1282 | 7dea1da4 | bellard | it can be reset while reading iir */
|
1283 | 7dea1da4 | bellard | int thr_ipending;
|
1284 | 0824d6fc | bellard | } SerialState; |
1285 | 0824d6fc | bellard | |
1286 | 0824d6fc | bellard | SerialState serial_ports[1];
|
1287 | 0824d6fc | bellard | |
1288 | 0824d6fc | bellard | void serial_update_irq(void) |
1289 | 0824d6fc | bellard | { |
1290 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1291 | 0824d6fc | bellard | |
1292 | 0824d6fc | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
1293 | 0824d6fc | bellard | s->iir = UART_IIR_RDI; |
1294 | 7dea1da4 | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
1295 | 0824d6fc | bellard | s->iir = UART_IIR_THRI; |
1296 | 0824d6fc | bellard | } else {
|
1297 | 0824d6fc | bellard | s->iir = UART_IIR_NO_INT; |
1298 | 0824d6fc | bellard | } |
1299 | 0824d6fc | bellard | if (s->iir != UART_IIR_NO_INT) {
|
1300 | 0824d6fc | bellard | pic_set_irq(UART_IRQ, 1);
|
1301 | 0824d6fc | bellard | } else {
|
1302 | 0824d6fc | bellard | pic_set_irq(UART_IRQ, 0);
|
1303 | 0824d6fc | bellard | } |
1304 | 0824d6fc | bellard | } |
1305 | 0824d6fc | bellard | |
1306 | 0824d6fc | bellard | void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1307 | 0824d6fc | bellard | { |
1308 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1309 | 0824d6fc | bellard | unsigned char ch; |
1310 | 0824d6fc | bellard | int ret;
|
1311 | 0824d6fc | bellard | |
1312 | 0824d6fc | bellard | addr &= 7;
|
1313 | 7dea1da4 | bellard | #ifdef DEBUG_SERIAL
|
1314 | 7dea1da4 | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
|
1315 | 7dea1da4 | bellard | #endif
|
1316 | 0824d6fc | bellard | switch(addr) {
|
1317 | 0824d6fc | bellard | default:
|
1318 | 0824d6fc | bellard | case 0: |
1319 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1320 | 0824d6fc | bellard | s->divider = (s->divider & 0xff00) | val;
|
1321 | 0824d6fc | bellard | } else {
|
1322 | 7dea1da4 | bellard | s->thr_ipending = 0;
|
1323 | 0824d6fc | bellard | s->lsr &= ~UART_LSR_THRE; |
1324 | 0824d6fc | bellard | serial_update_irq(); |
1325 | 0824d6fc | bellard | |
1326 | 0824d6fc | bellard | ch = val; |
1327 | 0824d6fc | bellard | do {
|
1328 | 0824d6fc | bellard | ret = write(1, &ch, 1); |
1329 | 0824d6fc | bellard | } while (ret != 1); |
1330 | 7dea1da4 | bellard | s->thr_ipending = 1;
|
1331 | 0824d6fc | bellard | s->lsr |= UART_LSR_THRE; |
1332 | 0824d6fc | bellard | s->lsr |= UART_LSR_TEMT; |
1333 | 0824d6fc | bellard | serial_update_irq(); |
1334 | 0824d6fc | bellard | } |
1335 | 0824d6fc | bellard | break;
|
1336 | 0824d6fc | bellard | case 1: |
1337 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1338 | 0824d6fc | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
1339 | 0824d6fc | bellard | } else {
|
1340 | 0824d6fc | bellard | s->ier = val; |
1341 | 0824d6fc | bellard | serial_update_irq(); |
1342 | 0824d6fc | bellard | } |
1343 | 0824d6fc | bellard | break;
|
1344 | 0824d6fc | bellard | case 2: |
1345 | 0824d6fc | bellard | break;
|
1346 | 0824d6fc | bellard | case 3: |
1347 | 0824d6fc | bellard | s->lcr = val; |
1348 | 0824d6fc | bellard | break;
|
1349 | 0824d6fc | bellard | case 4: |
1350 | 0824d6fc | bellard | s->mcr = val; |
1351 | 0824d6fc | bellard | break;
|
1352 | 0824d6fc | bellard | case 5: |
1353 | 0824d6fc | bellard | break;
|
1354 | 0824d6fc | bellard | case 6: |
1355 | 0824d6fc | bellard | s->msr = val; |
1356 | 0824d6fc | bellard | break;
|
1357 | 0824d6fc | bellard | case 7: |
1358 | 0824d6fc | bellard | s->scr = val; |
1359 | 0824d6fc | bellard | break;
|
1360 | 0824d6fc | bellard | } |
1361 | 0824d6fc | bellard | } |
1362 | 0824d6fc | bellard | |
1363 | 0824d6fc | bellard | uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) |
1364 | 0824d6fc | bellard | { |
1365 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1366 | 0824d6fc | bellard | uint32_t ret; |
1367 | 0824d6fc | bellard | |
1368 | 0824d6fc | bellard | addr &= 7;
|
1369 | 0824d6fc | bellard | switch(addr) {
|
1370 | 0824d6fc | bellard | default:
|
1371 | 0824d6fc | bellard | case 0: |
1372 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1373 | 0824d6fc | bellard | ret = s->divider & 0xff;
|
1374 | 0824d6fc | bellard | } else {
|
1375 | 0824d6fc | bellard | ret = s->rbr; |
1376 | 0824d6fc | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
1377 | 0824d6fc | bellard | serial_update_irq(); |
1378 | 0824d6fc | bellard | } |
1379 | 0824d6fc | bellard | break;
|
1380 | 0824d6fc | bellard | case 1: |
1381 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1382 | 0824d6fc | bellard | ret = (s->divider >> 8) & 0xff; |
1383 | 0824d6fc | bellard | } else {
|
1384 | 0824d6fc | bellard | ret = s->ier; |
1385 | 0824d6fc | bellard | } |
1386 | 0824d6fc | bellard | break;
|
1387 | 0824d6fc | bellard | case 2: |
1388 | 0824d6fc | bellard | ret = s->iir; |
1389 | 7dea1da4 | bellard | /* reset THR pending bit */
|
1390 | 7dea1da4 | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
1391 | 7dea1da4 | bellard | s->thr_ipending = 0;
|
1392 | 7dea1da4 | bellard | serial_update_irq(); |
1393 | 0824d6fc | bellard | break;
|
1394 | 0824d6fc | bellard | case 3: |
1395 | 0824d6fc | bellard | ret = s->lcr; |
1396 | 0824d6fc | bellard | break;
|
1397 | 0824d6fc | bellard | case 4: |
1398 | 0824d6fc | bellard | ret = s->mcr; |
1399 | 0824d6fc | bellard | break;
|
1400 | 0824d6fc | bellard | case 5: |
1401 | 0824d6fc | bellard | ret = s->lsr; |
1402 | 0824d6fc | bellard | break;
|
1403 | 0824d6fc | bellard | case 6: |
1404 | 7dea1da4 | bellard | if (s->mcr & UART_MCR_LOOP) {
|
1405 | 7dea1da4 | bellard | /* in loopback, the modem output pins are connected to the
|
1406 | 7dea1da4 | bellard | inputs */
|
1407 | 7dea1da4 | bellard | ret = (s->mcr & 0x0c) << 4; |
1408 | 7dea1da4 | bellard | ret |= (s->mcr & 0x02) << 3; |
1409 | 7dea1da4 | bellard | ret |= (s->mcr & 0x01) << 5; |
1410 | 7dea1da4 | bellard | } else {
|
1411 | 7dea1da4 | bellard | ret = s->msr; |
1412 | 7dea1da4 | bellard | } |
1413 | 0824d6fc | bellard | break;
|
1414 | 0824d6fc | bellard | case 7: |
1415 | 0824d6fc | bellard | ret = s->scr; |
1416 | 0824d6fc | bellard | break;
|
1417 | 0824d6fc | bellard | } |
1418 | 7dea1da4 | bellard | #ifdef DEBUG_SERIAL
|
1419 | 7dea1da4 | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
1420 | 7dea1da4 | bellard | #endif
|
1421 | 0824d6fc | bellard | return ret;
|
1422 | 0824d6fc | bellard | } |
1423 | 0824d6fc | bellard | |
1424 | 0824d6fc | bellard | #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ |
1425 | 0824d6fc | bellard | static int term_got_escape; |
1426 | 0824d6fc | bellard | |
1427 | 0824d6fc | bellard | void term_print_help(void) |
1428 | 0824d6fc | bellard | { |
1429 | 0824d6fc | bellard | printf("\n"
|
1430 | 0824d6fc | bellard | "C-a h print this help\n"
|
1431 | 0824d6fc | bellard | "C-a x exit emulatior\n"
|
1432 | 33e3963e | bellard | "C-a s save disk data back to file (if -snapshot)\n"
|
1433 | 0824d6fc | bellard | "C-a b send break (magic sysrq)\n"
|
1434 | 0824d6fc | bellard | "C-a C-a send C-a\n"
|
1435 | 0824d6fc | bellard | ); |
1436 | 0824d6fc | bellard | } |
1437 | 0824d6fc | bellard | |
1438 | 0824d6fc | bellard | /* called when a char is received */
|
1439 | 0824d6fc | bellard | void serial_received_byte(SerialState *s, int ch) |
1440 | 0824d6fc | bellard | { |
1441 | 0824d6fc | bellard | if (term_got_escape) {
|
1442 | 0824d6fc | bellard | term_got_escape = 0;
|
1443 | 0824d6fc | bellard | switch(ch) {
|
1444 | 0824d6fc | bellard | case 'h': |
1445 | 0824d6fc | bellard | term_print_help(); |
1446 | 0824d6fc | bellard | break;
|
1447 | 0824d6fc | bellard | case 'x': |
1448 | 0824d6fc | bellard | exit(0);
|
1449 | 0824d6fc | bellard | break;
|
1450 | 33e3963e | bellard | case 's': |
1451 | 33e3963e | bellard | { |
1452 | 33e3963e | bellard | int i;
|
1453 | 33e3963e | bellard | for (i = 0; i < MAX_DISKS; i++) { |
1454 | 33e3963e | bellard | if (bs_table[i])
|
1455 | 33e3963e | bellard | bdrv_commit(bs_table[i]); |
1456 | 33e3963e | bellard | } |
1457 | 33e3963e | bellard | } |
1458 | 33e3963e | bellard | break;
|
1459 | 0824d6fc | bellard | case 'b': |
1460 | 0824d6fc | bellard | /* send break */
|
1461 | 0824d6fc | bellard | s->rbr = 0;
|
1462 | 0824d6fc | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
1463 | 0824d6fc | bellard | serial_update_irq(); |
1464 | 0824d6fc | bellard | break;
|
1465 | 07ad1b93 | bellard | case 'd': |
1466 | 07ad1b93 | bellard | // tb_flush();
|
1467 | 07ad1b93 | bellard | cpu_set_log(CPU_LOG_ALL); |
1468 | 07ad1b93 | bellard | break;
|
1469 | 0824d6fc | bellard | case TERM_ESCAPE:
|
1470 | 0824d6fc | bellard | goto send_char;
|
1471 | 0824d6fc | bellard | } |
1472 | 0824d6fc | bellard | } else if (ch == TERM_ESCAPE) { |
1473 | 0824d6fc | bellard | term_got_escape = 1;
|
1474 | 0824d6fc | bellard | } else {
|
1475 | 0824d6fc | bellard | send_char:
|
1476 | 0824d6fc | bellard | s->rbr = ch; |
1477 | 0824d6fc | bellard | s->lsr |= UART_LSR_DR; |
1478 | 0824d6fc | bellard | serial_update_irq(); |
1479 | 0824d6fc | bellard | } |
1480 | 0824d6fc | bellard | } |
1481 | 0824d6fc | bellard | |
1482 | 0824d6fc | bellard | void serial_init(void) |
1483 | 0824d6fc | bellard | { |
1484 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1485 | 0824d6fc | bellard | |
1486 | 0824d6fc | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
1487 | 7dea1da4 | bellard | s->iir = UART_IIR_NO_INT; |
1488 | 7dea1da4 | bellard | |
1489 | fc01f7e7 | bellard | register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1490 | fc01f7e7 | bellard | register_ioport_read(0x3f8, 8, serial_ioport_read, 1); |
1491 | 0824d6fc | bellard | } |
1492 | 0824d6fc | bellard | |
1493 | f1510b2c | bellard | /***********************************************************/
|
1494 | f1510b2c | bellard | /* ne2000 emulation */
|
1495 | f1510b2c | bellard | |
1496 | f1510b2c | bellard | #define NE2000_IOPORT 0x300 |
1497 | f1510b2c | bellard | #define NE2000_IRQ 9 |
1498 | f1510b2c | bellard | |
1499 | f1510b2c | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
1500 | f1510b2c | bellard | |
1501 | f1510b2c | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
1502 | f1510b2c | bellard | /* Page 0 register offsets. */
|
1503 | f1510b2c | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
1504 | f1510b2c | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
1505 | f1510b2c | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
1506 | f1510b2c | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
1507 | f1510b2c | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
1508 | f1510b2c | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
1509 | f1510b2c | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
1510 | f1510b2c | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
1511 | f1510b2c | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
1512 | f1510b2c | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
1513 | f1510b2c | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
1514 | f1510b2c | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
1515 | f1510b2c | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
1516 | f1510b2c | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
1517 | f1510b2c | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
1518 | f1510b2c | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
1519 | f1510b2c | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
1520 | f1510b2c | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
1521 | f1510b2c | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
1522 | f1510b2c | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
1523 | f1510b2c | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
1524 | f1510b2c | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
1525 | f1510b2c | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
1526 | f1510b2c | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
1527 | f1510b2c | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
1528 | f1510b2c | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
1529 | f1510b2c | bellard | |
1530 | f1510b2c | bellard | #define EN1_PHYS 0x11 |
1531 | f1510b2c | bellard | #define EN1_CURPAG 0x17 |
1532 | f1510b2c | bellard | #define EN1_MULT 0x18 |
1533 | f1510b2c | bellard | |
1534 | f1510b2c | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
|
1535 | f1510b2c | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
1536 | f1510b2c | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
1537 | f1510b2c | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
1538 | f1510b2c | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
1539 | f1510b2c | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
1540 | f1510b2c | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
1541 | f1510b2c | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
1542 | f1510b2c | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
1543 | f1510b2c | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
1544 | f1510b2c | bellard | |
1545 | f1510b2c | bellard | /* Bits in EN0_ISR - Interrupt status register */
|
1546 | f1510b2c | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
1547 | f1510b2c | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
1548 | f1510b2c | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
1549 | f1510b2c | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
1550 | f1510b2c | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
1551 | f1510b2c | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
1552 | f1510b2c | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
1553 | f1510b2c | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
1554 | f1510b2c | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
1555 | f1510b2c | bellard | |
1556 | f1510b2c | bellard | /* Bits in received packet status byte and EN0_RSR*/
|
1557 | f1510b2c | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
1558 | f1510b2c | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
1559 | f1510b2c | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
1560 | f1510b2c | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
1561 | f1510b2c | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
1562 | f1510b2c | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
1563 | f1510b2c | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
1564 | f1510b2c | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
1565 | f1510b2c | bellard | |
1566 | f1510b2c | bellard | /* Transmitted packet status, EN0_TSR. */
|
1567 | f1510b2c | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
1568 | f1510b2c | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
1569 | f1510b2c | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
1570 | f1510b2c | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
1571 | f1510b2c | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
1572 | f1510b2c | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
1573 | f1510b2c | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
1574 | f1510b2c | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
1575 | f1510b2c | bellard | |
1576 | f1510b2c | bellard | #define NE2000_MEM_SIZE 32768 |
1577 | f1510b2c | bellard | |
1578 | f1510b2c | bellard | typedef struct NE2000State { |
1579 | f1510b2c | bellard | uint8_t cmd; |
1580 | f1510b2c | bellard | uint32_t start; |
1581 | f1510b2c | bellard | uint32_t stop; |
1582 | f1510b2c | bellard | uint8_t boundary; |
1583 | f1510b2c | bellard | uint8_t tsr; |
1584 | f1510b2c | bellard | uint8_t tpsr; |
1585 | f1510b2c | bellard | uint16_t tcnt; |
1586 | f1510b2c | bellard | uint16_t rcnt; |
1587 | f1510b2c | bellard | uint32_t rsar; |
1588 | f1510b2c | bellard | uint8_t isr; |
1589 | f1510b2c | bellard | uint8_t dcfg; |
1590 | f1510b2c | bellard | uint8_t imr; |
1591 | f1510b2c | bellard | uint8_t phys[6]; /* mac address */ |
1592 | f1510b2c | bellard | uint8_t curpag; |
1593 | f1510b2c | bellard | uint8_t mult[8]; /* multicast mask array */ |
1594 | f1510b2c | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
1595 | f1510b2c | bellard | } NE2000State; |
1596 | f1510b2c | bellard | |
1597 | f1510b2c | bellard | NE2000State ne2000_state; |
1598 | f1510b2c | bellard | int net_fd = -1; |
1599 | f1510b2c | bellard | char network_script[1024]; |
1600 | f1510b2c | bellard | |
1601 | f1510b2c | bellard | void ne2000_reset(void) |
1602 | f1510b2c | bellard | { |
1603 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1604 | f1510b2c | bellard | int i;
|
1605 | f1510b2c | bellard | |
1606 | f1510b2c | bellard | s->isr = ENISR_RESET; |
1607 | f1510b2c | bellard | s->mem[0] = 0x52; |
1608 | f1510b2c | bellard | s->mem[1] = 0x54; |
1609 | f1510b2c | bellard | s->mem[2] = 0x00; |
1610 | f1510b2c | bellard | s->mem[3] = 0x12; |
1611 | f1510b2c | bellard | s->mem[4] = 0x34; |
1612 | f1510b2c | bellard | s->mem[5] = 0x56; |
1613 | f1510b2c | bellard | s->mem[14] = 0x57; |
1614 | f1510b2c | bellard | s->mem[15] = 0x57; |
1615 | f1510b2c | bellard | |
1616 | f1510b2c | bellard | /* duplicate prom data */
|
1617 | f1510b2c | bellard | for(i = 15;i >= 0; i--) { |
1618 | f1510b2c | bellard | s->mem[2 * i] = s->mem[i];
|
1619 | f1510b2c | bellard | s->mem[2 * i + 1] = s->mem[i]; |
1620 | f1510b2c | bellard | } |
1621 | f1510b2c | bellard | } |
1622 | f1510b2c | bellard | |
1623 | f1510b2c | bellard | void ne2000_update_irq(NE2000State *s)
|
1624 | f1510b2c | bellard | { |
1625 | f1510b2c | bellard | int isr;
|
1626 | f1510b2c | bellard | isr = s->isr & s->imr; |
1627 | f1510b2c | bellard | if (isr)
|
1628 | f1510b2c | bellard | pic_set_irq(NE2000_IRQ, 1);
|
1629 | f1510b2c | bellard | else
|
1630 | f1510b2c | bellard | pic_set_irq(NE2000_IRQ, 0);
|
1631 | f1510b2c | bellard | } |
1632 | f1510b2c | bellard | |
1633 | f1510b2c | bellard | int net_init(void) |
1634 | f1510b2c | bellard | { |
1635 | f1510b2c | bellard | struct ifreq ifr;
|
1636 | f1510b2c | bellard | int fd, ret, pid, status;
|
1637 | f1510b2c | bellard | |
1638 | f1510b2c | bellard | fd = open("/dev/net/tun", O_RDWR);
|
1639 | f1510b2c | bellard | if (fd < 0) { |
1640 | f1510b2c | bellard | fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
|
1641 | f1510b2c | bellard | return -1; |
1642 | f1510b2c | bellard | } |
1643 | f1510b2c | bellard | memset(&ifr, 0, sizeof(ifr)); |
1644 | f1510b2c | bellard | ifr.ifr_flags = IFF_TAP | IFF_NO_PI; |
1645 | f1510b2c | bellard | pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
|
1646 | f1510b2c | bellard | ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
|
1647 | f1510b2c | bellard | if (ret != 0) { |
1648 | f1510b2c | bellard | fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
|
1649 | f1510b2c | bellard | close(fd); |
1650 | f1510b2c | bellard | return -1; |
1651 | f1510b2c | bellard | } |
1652 | fc01f7e7 | bellard | printf("Connected to host network interface: %s\n", ifr.ifr_name);
|
1653 | f1510b2c | bellard | fcntl(fd, F_SETFL, O_NONBLOCK); |
1654 | f1510b2c | bellard | net_fd = fd; |
1655 | f1510b2c | bellard | |
1656 | f1510b2c | bellard | /* try to launch network init script */
|
1657 | f1510b2c | bellard | pid = fork(); |
1658 | f1510b2c | bellard | if (pid >= 0) { |
1659 | f1510b2c | bellard | if (pid == 0) { |
1660 | f1510b2c | bellard | execl(network_script, network_script, ifr.ifr_name, NULL);
|
1661 | f1510b2c | bellard | exit(1);
|
1662 | f1510b2c | bellard | } |
1663 | f1510b2c | bellard | while (waitpid(pid, &status, 0) != pid); |
1664 | f1510b2c | bellard | if (!WIFEXITED(status) ||
|
1665 | f1510b2c | bellard | WEXITSTATUS(status) != 0) {
|
1666 | f1510b2c | bellard | fprintf(stderr, "%s: could not launch network script for '%s'\n",
|
1667 | f1510b2c | bellard | network_script, ifr.ifr_name); |
1668 | f1510b2c | bellard | } |
1669 | f1510b2c | bellard | } |
1670 | f1510b2c | bellard | return 0; |
1671 | f1510b2c | bellard | } |
1672 | f1510b2c | bellard | |
1673 | f1510b2c | bellard | void net_send_packet(NE2000State *s, const uint8_t *buf, int size) |
1674 | f1510b2c | bellard | { |
1675 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1676 | f1510b2c | bellard | printf("NE2000: sending packet size=%d\n", size);
|
1677 | f1510b2c | bellard | #endif
|
1678 | f1510b2c | bellard | write(net_fd, buf, size); |
1679 | f1510b2c | bellard | } |
1680 | f1510b2c | bellard | |
1681 | f1510b2c | bellard | /* return true if the NE2000 can receive more data */
|
1682 | f1510b2c | bellard | int ne2000_can_receive(NE2000State *s)
|
1683 | f1510b2c | bellard | { |
1684 | f1510b2c | bellard | int avail, index, boundary;
|
1685 | f1510b2c | bellard | |
1686 | f1510b2c | bellard | if (s->cmd & E8390_STOP)
|
1687 | f1510b2c | bellard | return 0; |
1688 | f1510b2c | bellard | index = s->curpag << 8;
|
1689 | f1510b2c | bellard | boundary = s->boundary << 8;
|
1690 | f1510b2c | bellard | if (index < boundary)
|
1691 | f1510b2c | bellard | avail = boundary - index; |
1692 | f1510b2c | bellard | else
|
1693 | f1510b2c | bellard | avail = (s->stop - s->start) - (index - boundary); |
1694 | f1510b2c | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
1695 | f1510b2c | bellard | return 0; |
1696 | f1510b2c | bellard | return 1; |
1697 | f1510b2c | bellard | } |
1698 | f1510b2c | bellard | |
1699 | f1510b2c | bellard | void ne2000_receive(NE2000State *s, uint8_t *buf, int size) |
1700 | f1510b2c | bellard | { |
1701 | f1510b2c | bellard | uint8_t *p; |
1702 | f1510b2c | bellard | int total_len, next, avail, len, index;
|
1703 | f1510b2c | bellard | |
1704 | f1510b2c | bellard | #if defined(DEBUG_NE2000)
|
1705 | f1510b2c | bellard | printf("NE2000: received len=%d\n", size);
|
1706 | f1510b2c | bellard | #endif
|
1707 | f1510b2c | bellard | |
1708 | f1510b2c | bellard | index = s->curpag << 8;
|
1709 | f1510b2c | bellard | /* 4 bytes for header */
|
1710 | f1510b2c | bellard | total_len = size + 4;
|
1711 | f1510b2c | bellard | /* address for next packet (4 bytes for CRC) */
|
1712 | f1510b2c | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
1713 | f1510b2c | bellard | if (next >= s->stop)
|
1714 | f1510b2c | bellard | next -= (s->stop - s->start); |
1715 | f1510b2c | bellard | /* prepare packet header */
|
1716 | f1510b2c | bellard | p = s->mem + index; |
1717 | f1510b2c | bellard | p[0] = ENRSR_RXOK; /* receive status */ |
1718 | f1510b2c | bellard | p[1] = next >> 8; |
1719 | f1510b2c | bellard | p[2] = total_len;
|
1720 | f1510b2c | bellard | p[3] = total_len >> 8; |
1721 | f1510b2c | bellard | index += 4;
|
1722 | f1510b2c | bellard | |
1723 | f1510b2c | bellard | /* write packet data */
|
1724 | f1510b2c | bellard | while (size > 0) { |
1725 | f1510b2c | bellard | avail = s->stop - index; |
1726 | f1510b2c | bellard | len = size; |
1727 | f1510b2c | bellard | if (len > avail)
|
1728 | f1510b2c | bellard | len = avail; |
1729 | f1510b2c | bellard | memcpy(s->mem + index, buf, len); |
1730 | f1510b2c | bellard | buf += len; |
1731 | f1510b2c | bellard | index += len; |
1732 | f1510b2c | bellard | if (index == s->stop)
|
1733 | f1510b2c | bellard | index = s->start; |
1734 | f1510b2c | bellard | size -= len; |
1735 | f1510b2c | bellard | } |
1736 | f1510b2c | bellard | s->curpag = next >> 8;
|
1737 | f1510b2c | bellard | |
1738 | f1510b2c | bellard | /* now we can signal we have receive something */
|
1739 | f1510b2c | bellard | s->isr |= ENISR_RX; |
1740 | f1510b2c | bellard | ne2000_update_irq(s); |
1741 | f1510b2c | bellard | } |
1742 | f1510b2c | bellard | |
1743 | f1510b2c | bellard | void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1744 | f1510b2c | bellard | { |
1745 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1746 | f1510b2c | bellard | int offset, page;
|
1747 | f1510b2c | bellard | |
1748 | f1510b2c | bellard | addr &= 0xf;
|
1749 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1750 | f1510b2c | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
1751 | f1510b2c | bellard | #endif
|
1752 | f1510b2c | bellard | if (addr == E8390_CMD) {
|
1753 | f1510b2c | bellard | /* control register */
|
1754 | f1510b2c | bellard | s->cmd = val; |
1755 | f1510b2c | bellard | if (val & E8390_START) {
|
1756 | f1510b2c | bellard | /* test specific case: zero length transfert */
|
1757 | f1510b2c | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
1758 | f1510b2c | bellard | s->rcnt == 0) {
|
1759 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1760 | f1510b2c | bellard | ne2000_update_irq(s); |
1761 | f1510b2c | bellard | } |
1762 | f1510b2c | bellard | if (val & E8390_TRANS) {
|
1763 | f1510b2c | bellard | net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
|
1764 | f1510b2c | bellard | /* signal end of transfert */
|
1765 | f1510b2c | bellard | s->tsr = ENTSR_PTX; |
1766 | f1510b2c | bellard | s->isr |= ENISR_TX; |
1767 | f1510b2c | bellard | ne2000_update_irq(s); |
1768 | f1510b2c | bellard | } |
1769 | f1510b2c | bellard | } |
1770 | f1510b2c | bellard | } else {
|
1771 | f1510b2c | bellard | page = s->cmd >> 6;
|
1772 | f1510b2c | bellard | offset = addr | (page << 4);
|
1773 | f1510b2c | bellard | switch(offset) {
|
1774 | f1510b2c | bellard | case EN0_STARTPG:
|
1775 | f1510b2c | bellard | s->start = val << 8;
|
1776 | f1510b2c | bellard | break;
|
1777 | f1510b2c | bellard | case EN0_STOPPG:
|
1778 | f1510b2c | bellard | s->stop = val << 8;
|
1779 | f1510b2c | bellard | break;
|
1780 | f1510b2c | bellard | case EN0_BOUNDARY:
|
1781 | f1510b2c | bellard | s->boundary = val; |
1782 | f1510b2c | bellard | break;
|
1783 | f1510b2c | bellard | case EN0_IMR:
|
1784 | f1510b2c | bellard | s->imr = val; |
1785 | f1510b2c | bellard | ne2000_update_irq(s); |
1786 | f1510b2c | bellard | break;
|
1787 | f1510b2c | bellard | case EN0_TPSR:
|
1788 | f1510b2c | bellard | s->tpsr = val; |
1789 | f1510b2c | bellard | break;
|
1790 | f1510b2c | bellard | case EN0_TCNTLO:
|
1791 | f1510b2c | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
1792 | f1510b2c | bellard | break;
|
1793 | f1510b2c | bellard | case EN0_TCNTHI:
|
1794 | f1510b2c | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
1795 | f1510b2c | bellard | break;
|
1796 | f1510b2c | bellard | case EN0_RSARLO:
|
1797 | f1510b2c | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
1798 | f1510b2c | bellard | break;
|
1799 | f1510b2c | bellard | case EN0_RSARHI:
|
1800 | f1510b2c | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
1801 | f1510b2c | bellard | break;
|
1802 | f1510b2c | bellard | case EN0_RCNTLO:
|
1803 | f1510b2c | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
1804 | f1510b2c | bellard | break;
|
1805 | f1510b2c | bellard | case EN0_RCNTHI:
|
1806 | f1510b2c | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
1807 | f1510b2c | bellard | break;
|
1808 | f1510b2c | bellard | case EN0_DCFG:
|
1809 | f1510b2c | bellard | s->dcfg = val; |
1810 | f1510b2c | bellard | break;
|
1811 | f1510b2c | bellard | case EN0_ISR:
|
1812 | f1510b2c | bellard | s->isr &= ~val; |
1813 | f1510b2c | bellard | ne2000_update_irq(s); |
1814 | f1510b2c | bellard | break;
|
1815 | f1510b2c | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
1816 | f1510b2c | bellard | s->phys[offset - EN1_PHYS] = val; |
1817 | f1510b2c | bellard | break;
|
1818 | f1510b2c | bellard | case EN1_CURPAG:
|
1819 | f1510b2c | bellard | s->curpag = val; |
1820 | f1510b2c | bellard | break;
|
1821 | f1510b2c | bellard | case EN1_MULT ... EN1_MULT + 7: |
1822 | f1510b2c | bellard | s->mult[offset - EN1_MULT] = val; |
1823 | f1510b2c | bellard | break;
|
1824 | f1510b2c | bellard | } |
1825 | f1510b2c | bellard | } |
1826 | f1510b2c | bellard | } |
1827 | f1510b2c | bellard | |
1828 | f1510b2c | bellard | uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) |
1829 | f1510b2c | bellard | { |
1830 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1831 | f1510b2c | bellard | int offset, page, ret;
|
1832 | f1510b2c | bellard | |
1833 | f1510b2c | bellard | addr &= 0xf;
|
1834 | f1510b2c | bellard | if (addr == E8390_CMD) {
|
1835 | f1510b2c | bellard | ret = s->cmd; |
1836 | f1510b2c | bellard | } else {
|
1837 | f1510b2c | bellard | page = s->cmd >> 6;
|
1838 | f1510b2c | bellard | offset = addr | (page << 4);
|
1839 | f1510b2c | bellard | switch(offset) {
|
1840 | f1510b2c | bellard | case EN0_TSR:
|
1841 | f1510b2c | bellard | ret = s->tsr; |
1842 | f1510b2c | bellard | break;
|
1843 | f1510b2c | bellard | case EN0_BOUNDARY:
|
1844 | f1510b2c | bellard | ret = s->boundary; |
1845 | f1510b2c | bellard | break;
|
1846 | f1510b2c | bellard | case EN0_ISR:
|
1847 | f1510b2c | bellard | ret = s->isr; |
1848 | f1510b2c | bellard | break;
|
1849 | f1510b2c | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
1850 | f1510b2c | bellard | ret = s->phys[offset - EN1_PHYS]; |
1851 | f1510b2c | bellard | break;
|
1852 | f1510b2c | bellard | case EN1_CURPAG:
|
1853 | f1510b2c | bellard | ret = s->curpag; |
1854 | f1510b2c | bellard | break;
|
1855 | f1510b2c | bellard | case EN1_MULT ... EN1_MULT + 7: |
1856 | f1510b2c | bellard | ret = s->mult[offset - EN1_MULT]; |
1857 | f1510b2c | bellard | break;
|
1858 | f1510b2c | bellard | default:
|
1859 | f1510b2c | bellard | ret = 0x00;
|
1860 | f1510b2c | bellard | break;
|
1861 | f1510b2c | bellard | } |
1862 | f1510b2c | bellard | } |
1863 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1864 | f1510b2c | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
1865 | f1510b2c | bellard | #endif
|
1866 | f1510b2c | bellard | return ret;
|
1867 | f1510b2c | bellard | } |
1868 | f1510b2c | bellard | |
1869 | f1510b2c | bellard | void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1870 | f1510b2c | bellard | { |
1871 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1872 | f1510b2c | bellard | uint8_t *p; |
1873 | f1510b2c | bellard | |
1874 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1875 | f1510b2c | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
1876 | f1510b2c | bellard | #endif
|
1877 | f1510b2c | bellard | p = s->mem + s->rsar; |
1878 | f1510b2c | bellard | if (s->dcfg & 0x01) { |
1879 | f1510b2c | bellard | /* 16 bit access */
|
1880 | f1510b2c | bellard | p[0] = val;
|
1881 | f1510b2c | bellard | p[1] = val >> 8; |
1882 | f1510b2c | bellard | s->rsar += 2;
|
1883 | f1510b2c | bellard | s->rcnt -= 2;
|
1884 | f1510b2c | bellard | } else {
|
1885 | f1510b2c | bellard | /* 8 bit access */
|
1886 | f1510b2c | bellard | p[0] = val;
|
1887 | f1510b2c | bellard | s->rsar++; |
1888 | f1510b2c | bellard | s->rcnt--; |
1889 | f1510b2c | bellard | } |
1890 | f1510b2c | bellard | /* wrap */
|
1891 | f1510b2c | bellard | if (s->rsar == s->stop)
|
1892 | f1510b2c | bellard | s->rsar = s->start; |
1893 | f1510b2c | bellard | if (s->rcnt == 0) { |
1894 | f1510b2c | bellard | /* signal end of transfert */
|
1895 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1896 | f1510b2c | bellard | ne2000_update_irq(s); |
1897 | f1510b2c | bellard | } |
1898 | f1510b2c | bellard | } |
1899 | f1510b2c | bellard | |
1900 | f1510b2c | bellard | uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) |
1901 | f1510b2c | bellard | { |
1902 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1903 | f1510b2c | bellard | uint8_t *p; |
1904 | f1510b2c | bellard | int ret;
|
1905 | f1510b2c | bellard | |
1906 | f1510b2c | bellard | p = s->mem + s->rsar; |
1907 | f1510b2c | bellard | if (s->dcfg & 0x01) { |
1908 | f1510b2c | bellard | /* 16 bit access */
|
1909 | f1510b2c | bellard | ret = p[0] | (p[1] << 8); |
1910 | f1510b2c | bellard | s->rsar += 2;
|
1911 | f1510b2c | bellard | s->rcnt -= 2;
|
1912 | f1510b2c | bellard | } else {
|
1913 | f1510b2c | bellard | /* 8 bit access */
|
1914 | f1510b2c | bellard | ret = p[0];
|
1915 | f1510b2c | bellard | s->rsar++; |
1916 | f1510b2c | bellard | s->rcnt--; |
1917 | f1510b2c | bellard | } |
1918 | f1510b2c | bellard | /* wrap */
|
1919 | f1510b2c | bellard | if (s->rsar == s->stop)
|
1920 | f1510b2c | bellard | s->rsar = s->start; |
1921 | f1510b2c | bellard | if (s->rcnt == 0) { |
1922 | f1510b2c | bellard | /* signal end of transfert */
|
1923 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1924 | f1510b2c | bellard | ne2000_update_irq(s); |
1925 | f1510b2c | bellard | } |
1926 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1927 | f1510b2c | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
1928 | f1510b2c | bellard | #endif
|
1929 | f1510b2c | bellard | return ret;
|
1930 | f1510b2c | bellard | } |
1931 | f1510b2c | bellard | |
1932 | f1510b2c | bellard | void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1933 | f1510b2c | bellard | { |
1934 | f1510b2c | bellard | /* nothing to do (end of reset pulse) */
|
1935 | f1510b2c | bellard | } |
1936 | f1510b2c | bellard | |
1937 | f1510b2c | bellard | uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) |
1938 | f1510b2c | bellard | { |
1939 | f1510b2c | bellard | ne2000_reset(); |
1940 | f1510b2c | bellard | return 0; |
1941 | f1510b2c | bellard | } |
1942 | f1510b2c | bellard | |
1943 | f1510b2c | bellard | void ne2000_init(void) |
1944 | f1510b2c | bellard | { |
1945 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
1946 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); |
1947 | f1510b2c | bellard | |
1948 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
1949 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); |
1950 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); |
1951 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); |
1952 | f1510b2c | bellard | |
1953 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
1954 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); |
1955 | f1510b2c | bellard | ne2000_reset(); |
1956 | f1510b2c | bellard | } |
1957 | f1510b2c | bellard | |
1958 | f1510b2c | bellard | /***********************************************************/
|
1959 | 330d0414 | bellard | /* keyboard emulation */
|
1960 | 330d0414 | bellard | |
1961 | 330d0414 | bellard | /* Keyboard Controller Commands */
|
1962 | 330d0414 | bellard | #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ |
1963 | 330d0414 | bellard | #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ |
1964 | 330d0414 | bellard | #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ |
1965 | 330d0414 | bellard | #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ |
1966 | 330d0414 | bellard | #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ |
1967 | 330d0414 | bellard | #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ |
1968 | 330d0414 | bellard | #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ |
1969 | 330d0414 | bellard | #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ |
1970 | 330d0414 | bellard | #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ |
1971 | 330d0414 | bellard | #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ |
1972 | 330d0414 | bellard | #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ |
1973 | 330d0414 | bellard | #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ |
1974 | 330d0414 | bellard | #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ |
1975 | 330d0414 | bellard | #define KBD_CCMD_WRITE_OBUF 0xD2 |
1976 | 330d0414 | bellard | #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if |
1977 | 330d0414 | bellard | initiated by the auxiliary device */
|
1978 | 330d0414 | bellard | #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ |
1979 | 1f5476fc | bellard | #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ |
1980 | 1f5476fc | bellard | #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ |
1981 | 330d0414 | bellard | #define KBD_CCMD_RESET 0xFE |
1982 | 330d0414 | bellard | |
1983 | 330d0414 | bellard | /* Keyboard Commands */
|
1984 | 330d0414 | bellard | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
1985 | 330d0414 | bellard | #define KBD_CMD_ECHO 0xEE |
1986 | 07ad1b93 | bellard | #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ |
1987 | 330d0414 | bellard | #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ |
1988 | 330d0414 | bellard | #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ |
1989 | 330d0414 | bellard | #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ |
1990 | 330d0414 | bellard | #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ |
1991 | 330d0414 | bellard | #define KBD_CMD_RESET 0xFF /* Reset */ |
1992 | 330d0414 | bellard | |
1993 | 330d0414 | bellard | /* Keyboard Replies */
|
1994 | 330d0414 | bellard | #define KBD_REPLY_POR 0xAA /* Power on reset */ |
1995 | 330d0414 | bellard | #define KBD_REPLY_ACK 0xFA /* Command ACK */ |
1996 | 330d0414 | bellard | #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ |
1997 | 330d0414 | bellard | |
1998 | 330d0414 | bellard | /* Status Register Bits */
|
1999 | 330d0414 | bellard | #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ |
2000 | 330d0414 | bellard | #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ |
2001 | 330d0414 | bellard | #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ |
2002 | 330d0414 | bellard | #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ |
2003 | 330d0414 | bellard | #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ |
2004 | 330d0414 | bellard | #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ |
2005 | 330d0414 | bellard | #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ |
2006 | 330d0414 | bellard | #define KBD_STAT_PERR 0x80 /* Parity error */ |
2007 | 330d0414 | bellard | |
2008 | 330d0414 | bellard | /* Controller Mode Register Bits */
|
2009 | 330d0414 | bellard | #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ |
2010 | 330d0414 | bellard | #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ |
2011 | 330d0414 | bellard | #define KBD_MODE_SYS 0x04 /* The system flag (?) */ |
2012 | 330d0414 | bellard | #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ |
2013 | 330d0414 | bellard | #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ |
2014 | 330d0414 | bellard | #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ |
2015 | 330d0414 | bellard | #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ |
2016 | 330d0414 | bellard | #define KBD_MODE_RFU 0x80 |
2017 | 330d0414 | bellard | |
2018 | 330d0414 | bellard | /* Mouse Commands */
|
2019 | 330d0414 | bellard | #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ |
2020 | 330d0414 | bellard | #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ |
2021 | 313aa567 | bellard | #define AUX_SET_RES 0xE8 /* Set resolution */ |
2022 | 330d0414 | bellard | #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ |
2023 | 330d0414 | bellard | #define AUX_SET_STREAM 0xEA /* Set stream mode */ |
2024 | 313aa567 | bellard | #define AUX_POLL 0xEB /* Poll */ |
2025 | 313aa567 | bellard | #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ |
2026 | 313aa567 | bellard | #define AUX_SET_WRAP 0xEE /* Set wrap mode */ |
2027 | 313aa567 | bellard | #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ |
2028 | 313aa567 | bellard | #define AUX_GET_TYPE 0xF2 /* Get type */ |
2029 | 330d0414 | bellard | #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ |
2030 | 330d0414 | bellard | #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ |
2031 | 330d0414 | bellard | #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ |
2032 | 313aa567 | bellard | #define AUX_SET_DEFAULT 0xF6 |
2033 | 330d0414 | bellard | #define AUX_RESET 0xFF /* Reset aux device */ |
2034 | 330d0414 | bellard | #define AUX_ACK 0xFA /* Command byte ACK. */ |
2035 | 330d0414 | bellard | |
2036 | 313aa567 | bellard | #define MOUSE_STATUS_REMOTE 0x40 |
2037 | 313aa567 | bellard | #define MOUSE_STATUS_ENABLED 0x20 |
2038 | 313aa567 | bellard | #define MOUSE_STATUS_SCALE21 0x10 |
2039 | 313aa567 | bellard | |
2040 | 313aa567 | bellard | #define KBD_QUEUE_SIZE 256 |
2041 | 330d0414 | bellard | |
2042 | 330d0414 | bellard | typedef struct { |
2043 | 330d0414 | bellard | uint8_t data[KBD_QUEUE_SIZE]; |
2044 | 330d0414 | bellard | int rptr, wptr, count;
|
2045 | 330d0414 | bellard | } KBDQueue; |
2046 | 330d0414 | bellard | |
2047 | 330d0414 | bellard | typedef struct KBDState { |
2048 | 330d0414 | bellard | KBDQueue queues[2];
|
2049 | 330d0414 | bellard | uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
|
2050 | 330d0414 | bellard | uint8_t status; |
2051 | 330d0414 | bellard | uint8_t mode; |
2052 | 313aa567 | bellard | /* keyboard state */
|
2053 | 330d0414 | bellard | int kbd_write_cmd;
|
2054 | 330d0414 | bellard | int scan_enabled;
|
2055 | 313aa567 | bellard | /* mouse state */
|
2056 | 313aa567 | bellard | int mouse_write_cmd;
|
2057 | 313aa567 | bellard | uint8_t mouse_status; |
2058 | 313aa567 | bellard | uint8_t mouse_resolution; |
2059 | 313aa567 | bellard | uint8_t mouse_sample_rate; |
2060 | 313aa567 | bellard | uint8_t mouse_wrap; |
2061 | 313aa567 | bellard | uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
|
2062 | 313aa567 | bellard | uint8_t mouse_detect_state; |
2063 | 313aa567 | bellard | int mouse_dx; /* current values, needed for 'poll' mode */ |
2064 | 313aa567 | bellard | int mouse_dy;
|
2065 | 313aa567 | bellard | int mouse_dz;
|
2066 | 313aa567 | bellard | uint8_t mouse_buttons; |
2067 | 330d0414 | bellard | } KBDState; |
2068 | 330d0414 | bellard | |
2069 | 330d0414 | bellard | KBDState kbd_state; |
2070 | cd4c3e88 | bellard | int reset_requested;
|
2071 | 330d0414 | bellard | |
2072 | 313aa567 | bellard | /* update irq and KBD_STAT_[MOUSE_]OBF */
|
2073 | 07ad1b93 | bellard | /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
|
2074 | 07ad1b93 | bellard | incorrect, but it avoids having to simulate exact delays */
|
2075 | 330d0414 | bellard | static void kbd_update_irq(KBDState *s) |
2076 | 330d0414 | bellard | { |
2077 | 313aa567 | bellard | int irq12_level, irq1_level;
|
2078 | 313aa567 | bellard | |
2079 | 313aa567 | bellard | irq1_level = 0;
|
2080 | 313aa567 | bellard | irq12_level = 0;
|
2081 | 313aa567 | bellard | s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); |
2082 | 313aa567 | bellard | if (s->queues[0].count != 0 || |
2083 | 313aa567 | bellard | s->queues[1].count != 0) { |
2084 | 313aa567 | bellard | s->status |= KBD_STAT_OBF; |
2085 | 313aa567 | bellard | if (s->queues[1].count != 0) { |
2086 | 313aa567 | bellard | s->status |= KBD_STAT_MOUSE_OBF; |
2087 | 313aa567 | bellard | if (s->mode & KBD_MODE_MOUSE_INT)
|
2088 | 313aa567 | bellard | irq12_level = 1;
|
2089 | 313aa567 | bellard | } else {
|
2090 | 07ad1b93 | bellard | if ((s->mode & KBD_MODE_KBD_INT) &&
|
2091 | 07ad1b93 | bellard | !(s->mode & KBD_MODE_DISABLE_KBD)) |
2092 | 313aa567 | bellard | irq1_level = 1;
|
2093 | 313aa567 | bellard | } |
2094 | 313aa567 | bellard | } |
2095 | 313aa567 | bellard | pic_set_irq(1, irq1_level);
|
2096 | 313aa567 | bellard | pic_set_irq(12, irq12_level);
|
2097 | 330d0414 | bellard | } |
2098 | 330d0414 | bellard | |
2099 | 330d0414 | bellard | static void kbd_queue(KBDState *s, int b, int aux) |
2100 | 330d0414 | bellard | { |
2101 | 330d0414 | bellard | KBDQueue *q = &kbd_state.queues[aux]; |
2102 | 330d0414 | bellard | |
2103 | 313aa567 | bellard | #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
|
2104 | 313aa567 | bellard | if (aux)
|
2105 | 313aa567 | bellard | printf("mouse event: 0x%02x\n", b);
|
2106 | 313aa567 | bellard | #ifdef DEBUG_KBD
|
2107 | 313aa567 | bellard | else
|
2108 | 313aa567 | bellard | printf("kbd event: 0x%02x\n", b);
|
2109 | 313aa567 | bellard | #endif
|
2110 | 313aa567 | bellard | #endif
|
2111 | 330d0414 | bellard | if (q->count >= KBD_QUEUE_SIZE)
|
2112 | 330d0414 | bellard | return;
|
2113 | 330d0414 | bellard | q->data[q->wptr] = b; |
2114 | 330d0414 | bellard | if (++q->wptr == KBD_QUEUE_SIZE)
|
2115 | 330d0414 | bellard | q->wptr = 0;
|
2116 | 330d0414 | bellard | q->count++; |
2117 | 330d0414 | bellard | kbd_update_irq(s); |
2118 | 330d0414 | bellard | } |
2119 | cd4c3e88 | bellard | |
2120 | 313aa567 | bellard | void kbd_put_keycode(int keycode) |
2121 | 313aa567 | bellard | { |
2122 | 313aa567 | bellard | KBDState *s = &kbd_state; |
2123 | 313aa567 | bellard | kbd_queue(s, keycode, 0);
|
2124 | 313aa567 | bellard | } |
2125 | 313aa567 | bellard | |
2126 | cd4c3e88 | bellard | uint32_t kbd_read_status(CPUX86State *env, uint32_t addr) |
2127 | cd4c3e88 | bellard | { |
2128 | 330d0414 | bellard | KBDState *s = &kbd_state; |
2129 | 330d0414 | bellard | int val;
|
2130 | 330d0414 | bellard | val = s->status; |
2131 | 07ad1b93 | bellard | #if defined(DEBUG_KBD)
|
2132 | 330d0414 | bellard | printf("kbd: read status=0x%02x\n", val);
|
2133 | 330d0414 | bellard | #endif
|
2134 | 330d0414 | bellard | return val;
|
2135 | cd4c3e88 | bellard | } |
2136 | cd4c3e88 | bellard | |
2137 | cd4c3e88 | bellard | void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
|
2138 | cd4c3e88 | bellard | { |
2139 | 330d0414 | bellard | KBDState *s = &kbd_state; |
2140 | 330d0414 | bellard | |
2141 | 330d0414 | bellard | #ifdef DEBUG_KBD
|
2142 | 330d0414 | bellard | printf("kbd: write cmd=0x%02x\n", val);
|
2143 | 330d0414 | bellard | #endif
|
2144 | cd4c3e88 | bellard | switch(val) {
|
2145 | 330d0414 | bellard | case KBD_CCMD_READ_MODE:
|
2146 | 330d0414 | bellard | kbd_queue(s, s->mode, 0);
|
2147 | 330d0414 | bellard | break;
|
2148 | 330d0414 | bellard | case KBD_CCMD_WRITE_MODE:
|
2149 | 330d0414 | bellard | case KBD_CCMD_WRITE_OBUF:
|
2150 | 330d0414 | bellard | case KBD_CCMD_WRITE_AUX_OBUF:
|
2151 | 330d0414 | bellard | case KBD_CCMD_WRITE_MOUSE:
|
2152 | 330d0414 | bellard | case KBD_CCMD_WRITE_OUTPORT:
|
2153 | 330d0414 | bellard | s->write_cmd = val; |
2154 | 330d0414 | bellard | break;
|
2155 | 330d0414 | bellard | case KBD_CCMD_MOUSE_DISABLE:
|
2156 | 330d0414 | bellard | s->mode |= KBD_MODE_DISABLE_MOUSE; |
2157 | 330d0414 | bellard | break;
|
2158 | 330d0414 | bellard | case KBD_CCMD_MOUSE_ENABLE:
|
2159 | 330d0414 | bellard | s->mode &= ~KBD_MODE_DISABLE_MOUSE; |
2160 | 330d0414 | bellard | break;
|
2161 | 330d0414 | bellard | case KBD_CCMD_TEST_MOUSE:
|
2162 | 330d0414 | bellard | kbd_queue(s, 0x00, 0); |
2163 | 330d0414 | bellard | break;
|
2164 | 330d0414 | bellard | case KBD_CCMD_SELF_TEST:
|
2165 | 330d0414 | bellard | s->status |= KBD_STAT_SELFTEST; |
2166 | 330d0414 | bellard | kbd_queue(s, 0x55, 0); |
2167 | 330d0414 | bellard | break;
|
2168 | 330d0414 | bellard | case KBD_CCMD_KBD_TEST:
|
2169 | 330d0414 | bellard | kbd_queue(s, 0x00, 0); |
2170 | 330d0414 | bellard | break;
|
2171 | 330d0414 | bellard | case KBD_CCMD_KBD_DISABLE:
|
2172 | 330d0414 | bellard | s->mode |= KBD_MODE_DISABLE_KBD; |
2173 | 07ad1b93 | bellard | kbd_update_irq(s); |
2174 | 330d0414 | bellard | break;
|
2175 | 330d0414 | bellard | case KBD_CCMD_KBD_ENABLE:
|
2176 | 330d0414 | bellard | s->mode &= ~KBD_MODE_DISABLE_KBD; |
2177 | 07ad1b93 | bellard | kbd_update_irq(s); |
2178 | 330d0414 | bellard | break;
|
2179 | 330d0414 | bellard | case KBD_CCMD_READ_INPORT:
|
2180 | 330d0414 | bellard | kbd_queue(s, 0x00, 0); |
2181 | 330d0414 | bellard | break;
|
2182 | 330d0414 | bellard | case KBD_CCMD_READ_OUTPORT:
|
2183 | 330d0414 | bellard | /* XXX: check that */
|
2184 | 330d0414 | bellard | val = 0x01 | (a20_enabled << 1); |
2185 | 330d0414 | bellard | if (s->status & KBD_STAT_OBF)
|
2186 | 330d0414 | bellard | val |= 0x10;
|
2187 | 330d0414 | bellard | if (s->status & KBD_STAT_MOUSE_OBF)
|
2188 | 330d0414 | bellard | val |= 0x20;
|
2189 | 330d0414 | bellard | kbd_queue(s, val, 0);
|
2190 | 330d0414 | bellard | break;
|
2191 | 330d0414 | bellard | case KBD_CCMD_ENABLE_A20:
|
2192 | 1f5476fc | bellard | cpu_x86_set_a20(env, 1);
|
2193 | 330d0414 | bellard | break;
|
2194 | 330d0414 | bellard | case KBD_CCMD_DISABLE_A20:
|
2195 | 1f5476fc | bellard | cpu_x86_set_a20(env, 0);
|
2196 | 330d0414 | bellard | break;
|
2197 | 330d0414 | bellard | case KBD_CCMD_RESET:
|
2198 | cd4c3e88 | bellard | reset_requested = 1;
|
2199 | cd4c3e88 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2200 | cd4c3e88 | bellard | break;
|
2201 | 27503323 | bellard | case 0xff: |
2202 | 27503323 | bellard | /* ignore that - I don't know what is its use */
|
2203 | 27503323 | bellard | break;
|
2204 | cd4c3e88 | bellard | default:
|
2205 | 36b486bb | bellard | fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
|
2206 | 330d0414 | bellard | break;
|
2207 | 330d0414 | bellard | } |
2208 | 330d0414 | bellard | } |
2209 | 330d0414 | bellard | |
2210 | 330d0414 | bellard | uint32_t kbd_read_data(CPUX86State *env, uint32_t addr) |
2211 | 330d0414 | bellard | { |
2212 | 330d0414 | bellard | KBDState *s = &kbd_state; |
2213 | 330d0414 | bellard | KBDQueue *q; |
2214 | 7dea1da4 | bellard | int val, index;
|
2215 | 330d0414 | bellard | |
2216 | 313aa567 | bellard | q = &s->queues[0]; /* first check KBD data */ |
2217 | 330d0414 | bellard | if (q->count == 0) |
2218 | 313aa567 | bellard | q = &s->queues[1]; /* then check AUX data */ |
2219 | 330d0414 | bellard | if (q->count == 0) { |
2220 | 7dea1da4 | bellard | /* NOTE: if no data left, we return the last keyboard one
|
2221 | 7dea1da4 | bellard | (needed for EMM386) */
|
2222 | 7dea1da4 | bellard | /* XXX: need a timer to do things correctly */
|
2223 | 7dea1da4 | bellard | q = &s->queues[0];
|
2224 | 7dea1da4 | bellard | index = q->rptr - 1;
|
2225 | 7dea1da4 | bellard | if (index < 0) |
2226 | 7dea1da4 | bellard | index = KBD_QUEUE_SIZE - 1;
|
2227 | 7dea1da4 | bellard | val = q->data[index]; |
2228 | 330d0414 | bellard | } else {
|
2229 | 330d0414 | bellard | val = q->data[q->rptr]; |
2230 | 330d0414 | bellard | if (++q->rptr == KBD_QUEUE_SIZE)
|
2231 | 330d0414 | bellard | q->rptr = 0;
|
2232 | 330d0414 | bellard | q->count--; |
2233 | 313aa567 | bellard | /* reading deasserts IRQ */
|
2234 | 313aa567 | bellard | if (q == &s->queues[0]) |
2235 | 313aa567 | bellard | pic_set_irq(1, 0); |
2236 | 313aa567 | bellard | else
|
2237 | 313aa567 | bellard | pic_set_irq(12, 0); |
2238 | 330d0414 | bellard | } |
2239 | 313aa567 | bellard | /* reassert IRQs if data left */
|
2240 | 313aa567 | bellard | kbd_update_irq(s); |
2241 | 330d0414 | bellard | #ifdef DEBUG_KBD
|
2242 | 330d0414 | bellard | printf("kbd: read data=0x%02x\n", val);
|
2243 | 330d0414 | bellard | #endif
|
2244 | 330d0414 | bellard | return val;
|
2245 | 330d0414 | bellard | } |
2246 | 330d0414 | bellard | |
2247 | 330d0414 | bellard | static void kbd_reset_keyboard(KBDState *s) |
2248 | 330d0414 | bellard | { |
2249 | 330d0414 | bellard | s->scan_enabled = 1;
|
2250 | 330d0414 | bellard | } |
2251 | 330d0414 | bellard | |
2252 | 330d0414 | bellard | static void kbd_write_keyboard(KBDState *s, int val) |
2253 | 330d0414 | bellard | { |
2254 | 330d0414 | bellard | switch(s->kbd_write_cmd) {
|
2255 | 330d0414 | bellard | default:
|
2256 | 330d0414 | bellard | case -1: |
2257 | 330d0414 | bellard | switch(val) {
|
2258 | 330d0414 | bellard | case 0x00: |
2259 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2260 | 330d0414 | bellard | break;
|
2261 | 330d0414 | bellard | case 0x05: |
2262 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_RESEND, 0);
|
2263 | 330d0414 | bellard | break;
|
2264 | 07ad1b93 | bellard | case KBD_CMD_GET_ID:
|
2265 | 07ad1b93 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2266 | 07ad1b93 | bellard | kbd_queue(s, 0xab, 0); |
2267 | 07ad1b93 | bellard | kbd_queue(s, 0x83, 0); |
2268 | 07ad1b93 | bellard | break;
|
2269 | 330d0414 | bellard | case KBD_CMD_ECHO:
|
2270 | 330d0414 | bellard | kbd_queue(s, KBD_CMD_ECHO, 0);
|
2271 | 330d0414 | bellard | break;
|
2272 | 330d0414 | bellard | case KBD_CMD_ENABLE:
|
2273 | 330d0414 | bellard | s->scan_enabled = 1;
|
2274 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2275 | 330d0414 | bellard | break;
|
2276 | 330d0414 | bellard | case KBD_CMD_SET_LEDS:
|
2277 | 330d0414 | bellard | case KBD_CMD_SET_RATE:
|
2278 | 330d0414 | bellard | s->kbd_write_cmd = val; |
2279 | 1f5476fc | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2280 | 330d0414 | bellard | break;
|
2281 | 330d0414 | bellard | case KBD_CMD_RESET_DISABLE:
|
2282 | 330d0414 | bellard | kbd_reset_keyboard(s); |
2283 | 330d0414 | bellard | s->scan_enabled = 0;
|
2284 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2285 | 330d0414 | bellard | break;
|
2286 | 330d0414 | bellard | case KBD_CMD_RESET_ENABLE:
|
2287 | 330d0414 | bellard | kbd_reset_keyboard(s); |
2288 | 330d0414 | bellard | s->scan_enabled = 1;
|
2289 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2290 | 330d0414 | bellard | break;
|
2291 | 330d0414 | bellard | case KBD_CMD_RESET:
|
2292 | 330d0414 | bellard | kbd_reset_keyboard(s); |
2293 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2294 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_POR, 0);
|
2295 | 330d0414 | bellard | break;
|
2296 | 330d0414 | bellard | default:
|
2297 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2298 | 330d0414 | bellard | break;
|
2299 | 330d0414 | bellard | } |
2300 | 330d0414 | bellard | break;
|
2301 | 330d0414 | bellard | case KBD_CMD_SET_LEDS:
|
2302 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2303 | 313aa567 | bellard | s->kbd_write_cmd = -1;
|
2304 | 330d0414 | bellard | break;
|
2305 | 330d0414 | bellard | case KBD_CMD_SET_RATE:
|
2306 | 330d0414 | bellard | kbd_queue(s, KBD_REPLY_ACK, 0);
|
2307 | 313aa567 | bellard | s->kbd_write_cmd = -1;
|
2308 | 313aa567 | bellard | break;
|
2309 | 313aa567 | bellard | } |
2310 | 313aa567 | bellard | } |
2311 | 313aa567 | bellard | |
2312 | 313aa567 | bellard | static void kbd_mouse_send_packet(KBDState *s) |
2313 | 313aa567 | bellard | { |
2314 | 313aa567 | bellard | unsigned int b; |
2315 | 313aa567 | bellard | int dx1, dy1, dz1;
|
2316 | 313aa567 | bellard | |
2317 | 313aa567 | bellard | dx1 = s->mouse_dx; |
2318 | 313aa567 | bellard | dy1 = s->mouse_dy; |
2319 | 313aa567 | bellard | dz1 = s->mouse_dz; |
2320 | 313aa567 | bellard | /* XXX: increase range to 8 bits ? */
|
2321 | 313aa567 | bellard | if (dx1 > 127) |
2322 | 313aa567 | bellard | dx1 = 127;
|
2323 | 313aa567 | bellard | else if (dx1 < -127) |
2324 | 313aa567 | bellard | dx1 = -127;
|
2325 | 313aa567 | bellard | if (dy1 > 127) |
2326 | 313aa567 | bellard | dy1 = 127;
|
2327 | 313aa567 | bellard | else if (dy1 < -127) |
2328 | 313aa567 | bellard | dy1 = -127;
|
2329 | 313aa567 | bellard | b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07); |
2330 | 313aa567 | bellard | kbd_queue(s, b, 1);
|
2331 | 313aa567 | bellard | kbd_queue(s, dx1 & 0xff, 1); |
2332 | 313aa567 | bellard | kbd_queue(s, dy1 & 0xff, 1); |
2333 | 313aa567 | bellard | /* extra byte for IMPS/2 or IMEX */
|
2334 | 313aa567 | bellard | switch(s->mouse_type) {
|
2335 | 313aa567 | bellard | default:
|
2336 | 313aa567 | bellard | break;
|
2337 | 313aa567 | bellard | case 3: |
2338 | 313aa567 | bellard | if (dz1 > 127) |
2339 | 313aa567 | bellard | dz1 = 127;
|
2340 | 313aa567 | bellard | else if (dz1 < -127) |
2341 | 313aa567 | bellard | dz1 = -127;
|
2342 | 313aa567 | bellard | kbd_queue(s, dz1 & 0xff, 1); |
2343 | 313aa567 | bellard | break;
|
2344 | 313aa567 | bellard | case 4: |
2345 | 313aa567 | bellard | if (dz1 > 7) |
2346 | 313aa567 | bellard | dz1 = 7;
|
2347 | 313aa567 | bellard | else if (dz1 < -7) |
2348 | 313aa567 | bellard | dz1 = -7;
|
2349 | 313aa567 | bellard | b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1); |
2350 | 313aa567 | bellard | kbd_queue(s, b, 1);
|
2351 | 313aa567 | bellard | break;
|
2352 | 313aa567 | bellard | } |
2353 | 313aa567 | bellard | |
2354 | 313aa567 | bellard | /* update deltas */
|
2355 | 313aa567 | bellard | s->mouse_dx -= dx1; |
2356 | 313aa567 | bellard | s->mouse_dy -= dy1; |
2357 | 313aa567 | bellard | s->mouse_dz -= dz1; |
2358 | 313aa567 | bellard | } |
2359 | 313aa567 | bellard | |
2360 | 313aa567 | bellard | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state) |
2361 | 313aa567 | bellard | { |
2362 | 313aa567 | bellard | KBDState *s = &kbd_state; |
2363 | 313aa567 | bellard | |
2364 | 313aa567 | bellard | /* check if deltas are recorded when disabled */
|
2365 | 313aa567 | bellard | if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
|
2366 | 313aa567 | bellard | return;
|
2367 | 313aa567 | bellard | |
2368 | 313aa567 | bellard | s->mouse_dx += dx; |
2369 | 313aa567 | bellard | s->mouse_dy -= dy; |
2370 | 313aa567 | bellard | s->mouse_dz += dz; |
2371 | 313aa567 | bellard | s->mouse_buttons = buttons_state; |
2372 | 313aa567 | bellard | |
2373 | 313aa567 | bellard | if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
|
2374 | 313aa567 | bellard | (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) { |
2375 | 313aa567 | bellard | for(;;) {
|
2376 | 313aa567 | bellard | /* if not remote, send event. Multiple events are sent if
|
2377 | 313aa567 | bellard | too big deltas */
|
2378 | 313aa567 | bellard | kbd_mouse_send_packet(s); |
2379 | 313aa567 | bellard | if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0) |
2380 | 313aa567 | bellard | break;
|
2381 | 313aa567 | bellard | } |
2382 | 313aa567 | bellard | } |
2383 | 313aa567 | bellard | } |
2384 | 313aa567 | bellard | |
2385 | 313aa567 | bellard | static void kbd_write_mouse(KBDState *s, int val) |
2386 | 313aa567 | bellard | { |
2387 | 313aa567 | bellard | #ifdef DEBUG_MOUSE
|
2388 | 313aa567 | bellard | printf("kbd: write mouse 0x%02x\n", val);
|
2389 | 313aa567 | bellard | #endif
|
2390 | 313aa567 | bellard | switch(s->mouse_write_cmd) {
|
2391 | 313aa567 | bellard | default:
|
2392 | 313aa567 | bellard | case -1: |
2393 | 313aa567 | bellard | /* mouse command */
|
2394 | 313aa567 | bellard | if (s->mouse_wrap) {
|
2395 | 313aa567 | bellard | if (val == AUX_RESET_WRAP) {
|
2396 | 313aa567 | bellard | s->mouse_wrap = 0;
|
2397 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2398 | 313aa567 | bellard | return;
|
2399 | 313aa567 | bellard | } else if (val != AUX_RESET) { |
2400 | 313aa567 | bellard | kbd_queue(s, val, 1);
|
2401 | 313aa567 | bellard | return;
|
2402 | 313aa567 | bellard | } |
2403 | 313aa567 | bellard | } |
2404 | 313aa567 | bellard | switch(val) {
|
2405 | 313aa567 | bellard | case AUX_SET_SCALE11:
|
2406 | 313aa567 | bellard | s->mouse_status &= ~MOUSE_STATUS_SCALE21; |
2407 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2408 | 313aa567 | bellard | break;
|
2409 | 313aa567 | bellard | case AUX_SET_SCALE21:
|
2410 | 313aa567 | bellard | s->mouse_status |= MOUSE_STATUS_SCALE21; |
2411 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2412 | 313aa567 | bellard | break;
|
2413 | 313aa567 | bellard | case AUX_SET_STREAM:
|
2414 | 313aa567 | bellard | s->mouse_status &= ~MOUSE_STATUS_REMOTE; |
2415 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2416 | 313aa567 | bellard | break;
|
2417 | 313aa567 | bellard | case AUX_SET_WRAP:
|
2418 | 313aa567 | bellard | s->mouse_wrap = 1;
|
2419 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2420 | 313aa567 | bellard | break;
|
2421 | 313aa567 | bellard | case AUX_SET_REMOTE:
|
2422 | 313aa567 | bellard | s->mouse_status |= MOUSE_STATUS_REMOTE; |
2423 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2424 | 313aa567 | bellard | break;
|
2425 | 313aa567 | bellard | case AUX_GET_TYPE:
|
2426 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2427 | 313aa567 | bellard | kbd_queue(s, s->mouse_type, 1);
|
2428 | 313aa567 | bellard | break;
|
2429 | 313aa567 | bellard | case AUX_SET_RES:
|
2430 | 313aa567 | bellard | case AUX_SET_SAMPLE:
|
2431 | 313aa567 | bellard | s->mouse_write_cmd = val; |
2432 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2433 | 313aa567 | bellard | break;
|
2434 | 313aa567 | bellard | case AUX_GET_SCALE:
|
2435 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2436 | 313aa567 | bellard | kbd_queue(s, s->mouse_status, 1);
|
2437 | 313aa567 | bellard | kbd_queue(s, s->mouse_resolution, 1);
|
2438 | 313aa567 | bellard | kbd_queue(s, s->mouse_sample_rate, 1);
|
2439 | 313aa567 | bellard | break;
|
2440 | 313aa567 | bellard | case AUX_POLL:
|
2441 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2442 | 313aa567 | bellard | kbd_mouse_send_packet(s); |
2443 | 313aa567 | bellard | break;
|
2444 | 313aa567 | bellard | case AUX_ENABLE_DEV:
|
2445 | 313aa567 | bellard | s->mouse_status |= MOUSE_STATUS_ENABLED; |
2446 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2447 | 313aa567 | bellard | break;
|
2448 | 313aa567 | bellard | case AUX_DISABLE_DEV:
|
2449 | 313aa567 | bellard | s->mouse_status &= ~MOUSE_STATUS_ENABLED; |
2450 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2451 | 313aa567 | bellard | break;
|
2452 | 313aa567 | bellard | case AUX_SET_DEFAULT:
|
2453 | 313aa567 | bellard | s->mouse_sample_rate = 100;
|
2454 | 313aa567 | bellard | s->mouse_resolution = 2;
|
2455 | 313aa567 | bellard | s->mouse_status = 0;
|
2456 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2457 | 313aa567 | bellard | break;
|
2458 | 313aa567 | bellard | case AUX_RESET:
|
2459 | 313aa567 | bellard | s->mouse_sample_rate = 100;
|
2460 | 313aa567 | bellard | s->mouse_resolution = 2;
|
2461 | 313aa567 | bellard | s->mouse_status = 0;
|
2462 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2463 | 313aa567 | bellard | kbd_queue(s, 0xaa, 1); |
2464 | 313aa567 | bellard | kbd_queue(s, s->mouse_type, 1);
|
2465 | 313aa567 | bellard | break;
|
2466 | 313aa567 | bellard | default:
|
2467 | 313aa567 | bellard | break;
|
2468 | 313aa567 | bellard | } |
2469 | 313aa567 | bellard | break;
|
2470 | 313aa567 | bellard | case AUX_SET_SAMPLE:
|
2471 | 313aa567 | bellard | s->mouse_sample_rate = val; |
2472 | 313aa567 | bellard | #if 0
|
2473 | 313aa567 | bellard | /* detect IMPS/2 or IMEX */
|
2474 | 313aa567 | bellard | switch(s->mouse_detect_state) {
|
2475 | 313aa567 | bellard | default:
|
2476 | 313aa567 | bellard | case 0:
|
2477 | 313aa567 | bellard | if (val == 200)
|
2478 | 313aa567 | bellard | s->mouse_detect_state = 1;
|
2479 | 313aa567 | bellard | break;
|
2480 | 313aa567 | bellard | case 1:
|
2481 | 313aa567 | bellard | if (val == 100)
|
2482 | 313aa567 | bellard | s->mouse_detect_state = 2;
|
2483 | 313aa567 | bellard | else if (val == 200)
|
2484 | 313aa567 | bellard | s->mouse_detect_state = 3;
|
2485 | 313aa567 | bellard | else
|
2486 | 313aa567 | bellard | s->mouse_detect_state = 0;
|
2487 | 313aa567 | bellard | break;
|
2488 | 313aa567 | bellard | case 2:
|
2489 | 313aa567 | bellard | if (val == 80)
|
2490 | 313aa567 | bellard | s->mouse_type = 3; /* IMPS/2 */
|
2491 | 313aa567 | bellard | s->mouse_detect_state = 0;
|
2492 | 313aa567 | bellard | break;
|
2493 | 313aa567 | bellard | case 3:
|
2494 | 313aa567 | bellard | if (val == 80)
|
2495 | 313aa567 | bellard | s->mouse_type = 4; /* IMEX */
|
2496 | 313aa567 | bellard | s->mouse_detect_state = 0;
|
2497 | 313aa567 | bellard | break;
|
2498 | 313aa567 | bellard | }
|
2499 | 313aa567 | bellard | #endif
|
2500 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2501 | 313aa567 | bellard | s->mouse_write_cmd = -1;
|
2502 | 313aa567 | bellard | break;
|
2503 | 313aa567 | bellard | case AUX_SET_RES:
|
2504 | 313aa567 | bellard | s->mouse_resolution = val; |
2505 | 313aa567 | bellard | kbd_queue(s, AUX_ACK, 1);
|
2506 | 313aa567 | bellard | s->mouse_write_cmd = -1;
|
2507 | 330d0414 | bellard | break;
|
2508 | 330d0414 | bellard | } |
2509 | 330d0414 | bellard | } |
2510 | 330d0414 | bellard | |
2511 | 330d0414 | bellard | void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
|
2512 | 330d0414 | bellard | { |
2513 | 330d0414 | bellard | KBDState *s = &kbd_state; |
2514 | 330d0414 | bellard | |
2515 | 330d0414 | bellard | #ifdef DEBUG_KBD
|
2516 | 330d0414 | bellard | printf("kbd: write data=0x%02x\n", val);
|
2517 | 330d0414 | bellard | #endif
|
2518 | 330d0414 | bellard | |
2519 | 330d0414 | bellard | switch(s->write_cmd) {
|
2520 | 330d0414 | bellard | case 0: |
2521 | 330d0414 | bellard | kbd_write_keyboard(s, val); |
2522 | 330d0414 | bellard | break;
|
2523 | 330d0414 | bellard | case KBD_CCMD_WRITE_MODE:
|
2524 | 330d0414 | bellard | s->mode = val; |
2525 | 330d0414 | bellard | kbd_update_irq(s); |
2526 | 330d0414 | bellard | break;
|
2527 | 330d0414 | bellard | case KBD_CCMD_WRITE_OBUF:
|
2528 | 330d0414 | bellard | kbd_queue(s, val, 0);
|
2529 | 330d0414 | bellard | break;
|
2530 | 330d0414 | bellard | case KBD_CCMD_WRITE_AUX_OBUF:
|
2531 | 330d0414 | bellard | kbd_queue(s, val, 1);
|
2532 | 330d0414 | bellard | break;
|
2533 | 330d0414 | bellard | case KBD_CCMD_WRITE_OUTPORT:
|
2534 | 1f5476fc | bellard | cpu_x86_set_a20(env, (val >> 1) & 1); |
2535 | 330d0414 | bellard | if (!(val & 1)) { |
2536 | 330d0414 | bellard | reset_requested = 1;
|
2537 | 330d0414 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2538 | 330d0414 | bellard | } |
2539 | 330d0414 | bellard | break;
|
2540 | 313aa567 | bellard | case KBD_CCMD_WRITE_MOUSE:
|
2541 | 313aa567 | bellard | kbd_write_mouse(s, val); |
2542 | 313aa567 | bellard | break;
|
2543 | 330d0414 | bellard | default:
|
2544 | cd4c3e88 | bellard | break;
|
2545 | cd4c3e88 | bellard | } |
2546 | 330d0414 | bellard | s->write_cmd = 0;
|
2547 | 330d0414 | bellard | } |
2548 | 330d0414 | bellard | |
2549 | 330d0414 | bellard | void kbd_reset(KBDState *s)
|
2550 | 330d0414 | bellard | { |
2551 | 330d0414 | bellard | KBDQueue *q; |
2552 | 330d0414 | bellard | int i;
|
2553 | 330d0414 | bellard | |
2554 | 330d0414 | bellard | s->kbd_write_cmd = -1;
|
2555 | 313aa567 | bellard | s->mouse_write_cmd = -1;
|
2556 | 330d0414 | bellard | s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
2557 | 313aa567 | bellard | s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; |
2558 | 330d0414 | bellard | for(i = 0; i < 2; i++) { |
2559 | 330d0414 | bellard | q = &s->queues[i]; |
2560 | 330d0414 | bellard | q->rptr = 0;
|
2561 | 330d0414 | bellard | q->wptr = 0;
|
2562 | 330d0414 | bellard | q->count = 0;
|
2563 | 330d0414 | bellard | } |
2564 | cd4c3e88 | bellard | } |
2565 | cd4c3e88 | bellard | |
2566 | cd4c3e88 | bellard | void kbd_init(void) |
2567 | cd4c3e88 | bellard | { |
2568 | 330d0414 | bellard | kbd_reset(&kbd_state); |
2569 | 330d0414 | bellard | register_ioport_read(0x60, 1, kbd_read_data, 1); |
2570 | 330d0414 | bellard | register_ioport_write(0x60, 1, kbd_write_data, 1); |
2571 | cd4c3e88 | bellard | register_ioport_read(0x64, 1, kbd_read_status, 1); |
2572 | cd4c3e88 | bellard | register_ioport_write(0x64, 1, kbd_write_command, 1); |
2573 | cd4c3e88 | bellard | } |
2574 | cd4c3e88 | bellard | |
2575 | cd4c3e88 | bellard | /***********************************************************/
|
2576 | 330d0414 | bellard | /* Bochs BIOS debug ports */
|
2577 | 330d0414 | bellard | |
2578 | 330d0414 | bellard | void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2579 | 330d0414 | bellard | { |
2580 | 330d0414 | bellard | switch(addr) {
|
2581 | 330d0414 | bellard | /* Bochs BIOS messages */
|
2582 | 330d0414 | bellard | case 0x400: |
2583 | 330d0414 | bellard | case 0x401: |
2584 | 330d0414 | bellard | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
2585 | 330d0414 | bellard | exit(1);
|
2586 | 330d0414 | bellard | case 0x402: |
2587 | 330d0414 | bellard | case 0x403: |
2588 | 330d0414 | bellard | #ifdef DEBUG_BIOS
|
2589 | 330d0414 | bellard | fprintf(stderr, "%c", val);
|
2590 | 330d0414 | bellard | #endif
|
2591 | 330d0414 | bellard | break;
|
2592 | 330d0414 | bellard | |
2593 | 330d0414 | bellard | /* LGPL'ed VGA BIOS messages */
|
2594 | 330d0414 | bellard | case 0x501: |
2595 | 330d0414 | bellard | case 0x502: |
2596 | 330d0414 | bellard | fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
2597 | 330d0414 | bellard | exit(1);
|
2598 | 330d0414 | bellard | case 0x500: |
2599 | 330d0414 | bellard | case 0x503: |
2600 | 330d0414 | bellard | #ifdef DEBUG_BIOS
|
2601 | 330d0414 | bellard | fprintf(stderr, "%c", val);
|
2602 | 330d0414 | bellard | #endif
|
2603 | 330d0414 | bellard | break;
|
2604 | 330d0414 | bellard | } |
2605 | 330d0414 | bellard | } |
2606 | 330d0414 | bellard | |
2607 | 330d0414 | bellard | void bochs_bios_init(void) |
2608 | 330d0414 | bellard | { |
2609 | 330d0414 | bellard | register_ioport_write(0x400, 1, bochs_bios_write, 2); |
2610 | 330d0414 | bellard | register_ioport_write(0x401, 1, bochs_bios_write, 2); |
2611 | 330d0414 | bellard | register_ioport_write(0x402, 1, bochs_bios_write, 1); |
2612 | 330d0414 | bellard | register_ioport_write(0x403, 1, bochs_bios_write, 1); |
2613 | 330d0414 | bellard | |
2614 | 330d0414 | bellard | register_ioport_write(0x501, 1, bochs_bios_write, 2); |
2615 | 330d0414 | bellard | register_ioport_write(0x502, 1, bochs_bios_write, 2); |
2616 | 330d0414 | bellard | register_ioport_write(0x500, 1, bochs_bios_write, 1); |
2617 | 330d0414 | bellard | register_ioport_write(0x503, 1, bochs_bios_write, 1); |
2618 | 330d0414 | bellard | } |
2619 | 330d0414 | bellard | |
2620 | 330d0414 | bellard | /***********************************************************/
|
2621 | 313aa567 | bellard | /* dumb display */
|
2622 | 313aa567 | bellard | |
2623 | 313aa567 | bellard | /* init terminal so that we can grab keys */
|
2624 | 313aa567 | bellard | static struct termios oldtty; |
2625 | 313aa567 | bellard | |
2626 | 313aa567 | bellard | static void term_exit(void) |
2627 | 313aa567 | bellard | { |
2628 | 313aa567 | bellard | tcsetattr (0, TCSANOW, &oldtty);
|
2629 | 313aa567 | bellard | } |
2630 | 313aa567 | bellard | |
2631 | 313aa567 | bellard | static void term_init(void) |
2632 | 313aa567 | bellard | { |
2633 | 313aa567 | bellard | struct termios tty;
|
2634 | 313aa567 | bellard | |
2635 | 313aa567 | bellard | tcgetattr (0, &tty);
|
2636 | 313aa567 | bellard | oldtty = tty; |
2637 | 313aa567 | bellard | |
2638 | 313aa567 | bellard | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP |
2639 | 313aa567 | bellard | |INLCR|IGNCR|ICRNL|IXON); |
2640 | 313aa567 | bellard | tty.c_oflag |= OPOST; |
2641 | a20dd508 | bellard | tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN); |
2642 | a20dd508 | bellard | /* if graphical mode, we allow Ctrl-C handling */
|
2643 | a20dd508 | bellard | if (nographic)
|
2644 | a20dd508 | bellard | tty.c_lflag &= ~ISIG; |
2645 | 313aa567 | bellard | tty.c_cflag &= ~(CSIZE|PARENB); |
2646 | 313aa567 | bellard | tty.c_cflag |= CS8; |
2647 | 313aa567 | bellard | tty.c_cc[VMIN] = 1;
|
2648 | 313aa567 | bellard | tty.c_cc[VTIME] = 0;
|
2649 | 313aa567 | bellard | |
2650 | 313aa567 | bellard | tcsetattr (0, TCSANOW, &tty);
|
2651 | 313aa567 | bellard | |
2652 | 313aa567 | bellard | atexit(term_exit); |
2653 | 313aa567 | bellard | |
2654 | 313aa567 | bellard | fcntl(0, F_SETFL, O_NONBLOCK);
|
2655 | 313aa567 | bellard | } |
2656 | 313aa567 | bellard | |
2657 | 313aa567 | bellard | static void dumb_update(DisplayState *ds, int x, int y, int w, int h) |
2658 | 313aa567 | bellard | { |
2659 | 313aa567 | bellard | } |
2660 | 313aa567 | bellard | |
2661 | 313aa567 | bellard | static void dumb_resize(DisplayState *ds, int w, int h) |
2662 | 313aa567 | bellard | { |
2663 | 313aa567 | bellard | } |
2664 | 313aa567 | bellard | |
2665 | 313aa567 | bellard | static void dumb_refresh(DisplayState *ds) |
2666 | 313aa567 | bellard | { |
2667 | 313aa567 | bellard | vga_update_display(); |
2668 | 313aa567 | bellard | } |
2669 | 313aa567 | bellard | |
2670 | 313aa567 | bellard | void dumb_display_init(DisplayState *ds)
|
2671 | 313aa567 | bellard | { |
2672 | 313aa567 | bellard | ds->data = NULL;
|
2673 | 313aa567 | bellard | ds->linesize = 0;
|
2674 | 313aa567 | bellard | ds->depth = 0;
|
2675 | 313aa567 | bellard | ds->dpy_update = dumb_update; |
2676 | 313aa567 | bellard | ds->dpy_resize = dumb_resize; |
2677 | 313aa567 | bellard | ds->dpy_refresh = dumb_refresh; |
2678 | 313aa567 | bellard | } |
2679 | 313aa567 | bellard | |
2680 | 3a51dee6 | bellard | #if !defined(CONFIG_SOFTMMU)
|
2681 | 313aa567 | bellard | /***********************************************************/
|
2682 | 0824d6fc | bellard | /* cpu signal handler */
|
2683 | 0824d6fc | bellard | static void host_segv_handler(int host_signum, siginfo_t *info, |
2684 | 0824d6fc | bellard | void *puc)
|
2685 | 0824d6fc | bellard | { |
2686 | 0824d6fc | bellard | if (cpu_signal_handler(host_signum, info, puc))
|
2687 | 0824d6fc | bellard | return;
|
2688 | 0824d6fc | bellard | term_exit(); |
2689 | 0824d6fc | bellard | abort(); |
2690 | 0824d6fc | bellard | } |
2691 | 3a51dee6 | bellard | #endif
|
2692 | 0824d6fc | bellard | |
2693 | 0824d6fc | bellard | static int timer_irq_pending; |
2694 | 87858c89 | bellard | static int timer_irq_count; |
2695 | 0824d6fc | bellard | |
2696 | 313aa567 | bellard | static int timer_ms; |
2697 | 313aa567 | bellard | static int gui_refresh_pending, gui_refresh_count; |
2698 | 313aa567 | bellard | |
2699 | 0824d6fc | bellard | static void host_alarm_handler(int host_signum, siginfo_t *info, |
2700 | 0824d6fc | bellard | void *puc)
|
2701 | 0824d6fc | bellard | { |
2702 | 87858c89 | bellard | /* NOTE: since usually the OS asks a 100 Hz clock, there can be
|
2703 | 87858c89 | bellard | some drift between cpu_get_ticks() and the interrupt time. So
|
2704 | 87858c89 | bellard | we queue some interrupts to avoid missing some */
|
2705 | 87858c89 | bellard | timer_irq_count += pit_get_out_edges(&pit_channels[0]);
|
2706 | 87858c89 | bellard | if (timer_irq_count) {
|
2707 | 87858c89 | bellard | if (timer_irq_count > 2) |
2708 | 87858c89 | bellard | timer_irq_count = 2;
|
2709 | 87858c89 | bellard | timer_irq_count--; |
2710 | 313aa567 | bellard | timer_irq_pending = 1;
|
2711 | 313aa567 | bellard | } |
2712 | 313aa567 | bellard | gui_refresh_count += timer_ms; |
2713 | 313aa567 | bellard | if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
|
2714 | 313aa567 | bellard | gui_refresh_count = 0;
|
2715 | 313aa567 | bellard | gui_refresh_pending = 1;
|
2716 | 313aa567 | bellard | } |
2717 | 313aa567 | bellard | |
2718 | 27503323 | bellard | /* XXX: seems dangerous to run that here. */
|
2719 | 27503323 | bellard | DMA_run(); |
2720 | 27503323 | bellard | SB16_run(); |
2721 | 27503323 | bellard | |
2722 | 313aa567 | bellard | if (gui_refresh_pending || timer_irq_pending) {
|
2723 | 87858c89 | bellard | /* just exit from the cpu to have a chance to handle timers */
|
2724 | c9159e53 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2725 | 87858c89 | bellard | } |
2726 | 0824d6fc | bellard | } |
2727 | 0824d6fc | bellard | |
2728 | 7f7f9873 | bellard | #ifdef CONFIG_SOFTMMU
|
2729 | 7f7f9873 | bellard | void *get_mmap_addr(unsigned long size) |
2730 | 7f7f9873 | bellard | { |
2731 | 7f7f9873 | bellard | return NULL; |
2732 | 7f7f9873 | bellard | } |
2733 | 7f7f9873 | bellard | #else
|
2734 | 33e3963e | bellard | unsigned long mmap_addr = PHYS_RAM_BASE; |
2735 | 33e3963e | bellard | |
2736 | 33e3963e | bellard | void *get_mmap_addr(unsigned long size) |
2737 | 33e3963e | bellard | { |
2738 | 33e3963e | bellard | unsigned long addr; |
2739 | 33e3963e | bellard | addr = mmap_addr; |
2740 | 33e3963e | bellard | mmap_addr += ((size + 4095) & ~4095) + 4096; |
2741 | 33e3963e | bellard | return (void *)addr; |
2742 | 33e3963e | bellard | } |
2743 | 7f7f9873 | bellard | #endif
|
2744 | 33e3963e | bellard | |
2745 | b4608c04 | bellard | /* main execution loop */
|
2746 | b4608c04 | bellard | |
2747 | b4608c04 | bellard | CPUState *cpu_gdbstub_get_env(void *opaque)
|
2748 | b4608c04 | bellard | { |
2749 | b4608c04 | bellard | return global_env;
|
2750 | b4608c04 | bellard | } |
2751 | b4608c04 | bellard | |
2752 | 4c3a88a2 | bellard | int main_loop(void *opaque) |
2753 | b4608c04 | bellard | { |
2754 | 27c3f2cb | bellard | struct pollfd ufds[3], *pf, *serial_ufd, *net_ufd, *gdb_ufd; |
2755 | 27c3f2cb | bellard | int ret, n, timeout, serial_ok;
|
2756 | b4608c04 | bellard | uint8_t ch; |
2757 | b4608c04 | bellard | CPUState *env = global_env; |
2758 | b4608c04 | bellard | |
2759 | a20dd508 | bellard | if (!term_inited) {
|
2760 | 313aa567 | bellard | /* initialize terminal only there so that the user has a
|
2761 | 313aa567 | bellard | chance to stop QEMU with Ctrl-C before the gdb connection
|
2762 | 313aa567 | bellard | is launched */
|
2763 | 313aa567 | bellard | term_inited = 1;
|
2764 | 313aa567 | bellard | term_init(); |
2765 | 313aa567 | bellard | } |
2766 | 313aa567 | bellard | |
2767 | 27c3f2cb | bellard | serial_ok = 1;
|
2768 | 34865134 | bellard | cpu_enable_ticks(); |
2769 | b4608c04 | bellard | for(;;) {
|
2770 | b4608c04 | bellard | ret = cpu_x86_exec(env); |
2771 | 34865134 | bellard | if (reset_requested) {
|
2772 | 34865134 | bellard | ret = EXCP_INTERRUPT; |
2773 | cd4c3e88 | bellard | break;
|
2774 | 34865134 | bellard | } |
2775 | 34865134 | bellard | if (ret == EXCP_DEBUG) {
|
2776 | 34865134 | bellard | ret = EXCP_DEBUG; |
2777 | 34865134 | bellard | break;
|
2778 | 34865134 | bellard | } |
2779 | b4608c04 | bellard | /* if hlt instruction, we wait until the next IRQ */
|
2780 | b4608c04 | bellard | if (ret == EXCP_HLT)
|
2781 | b4608c04 | bellard | timeout = 10;
|
2782 | b4608c04 | bellard | else
|
2783 | b4608c04 | bellard | timeout = 0;
|
2784 | b4608c04 | bellard | /* poll any events */
|
2785 | b4608c04 | bellard | serial_ufd = NULL;
|
2786 | b4608c04 | bellard | pf = ufds; |
2787 | 27c3f2cb | bellard | if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) { |
2788 | b4608c04 | bellard | serial_ufd = pf; |
2789 | b4608c04 | bellard | pf->fd = 0;
|
2790 | b4608c04 | bellard | pf->events = POLLIN; |
2791 | b4608c04 | bellard | pf++; |
2792 | b4608c04 | bellard | } |
2793 | b4608c04 | bellard | net_ufd = NULL;
|
2794 | b4608c04 | bellard | if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { |
2795 | b4608c04 | bellard | net_ufd = pf; |
2796 | b4608c04 | bellard | pf->fd = net_fd; |
2797 | b4608c04 | bellard | pf->events = POLLIN; |
2798 | b4608c04 | bellard | pf++; |
2799 | b4608c04 | bellard | } |
2800 | b4608c04 | bellard | gdb_ufd = NULL;
|
2801 | b4608c04 | bellard | if (gdbstub_fd > 0) { |
2802 | b4608c04 | bellard | gdb_ufd = pf; |
2803 | b4608c04 | bellard | pf->fd = gdbstub_fd; |
2804 | b4608c04 | bellard | pf->events = POLLIN; |
2805 | b4608c04 | bellard | pf++; |
2806 | b4608c04 | bellard | } |
2807 | b4608c04 | bellard | |
2808 | b4608c04 | bellard | ret = poll(ufds, pf - ufds, timeout); |
2809 | b4608c04 | bellard | if (ret > 0) { |
2810 | b4608c04 | bellard | if (serial_ufd && (serial_ufd->revents & POLLIN)) {
|
2811 | b4608c04 | bellard | n = read(0, &ch, 1); |
2812 | b4608c04 | bellard | if (n == 1) { |
2813 | b4608c04 | bellard | serial_received_byte(&serial_ports[0], ch);
|
2814 | 27c3f2cb | bellard | } else {
|
2815 | 27c3f2cb | bellard | /* Closed, stop polling. */
|
2816 | 27c3f2cb | bellard | serial_ok = 0;
|
2817 | b4608c04 | bellard | } |
2818 | b4608c04 | bellard | } |
2819 | b4608c04 | bellard | if (net_ufd && (net_ufd->revents & POLLIN)) {
|
2820 | b4608c04 | bellard | uint8_t buf[MAX_ETH_FRAME_SIZE]; |
2821 | b4608c04 | bellard | |
2822 | b4608c04 | bellard | n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); |
2823 | b4608c04 | bellard | if (n > 0) { |
2824 | b4608c04 | bellard | if (n < 60) { |
2825 | b4608c04 | bellard | memset(buf + n, 0, 60 - n); |
2826 | b4608c04 | bellard | n = 60;
|
2827 | b4608c04 | bellard | } |
2828 | b4608c04 | bellard | ne2000_receive(&ne2000_state, buf, n); |
2829 | b4608c04 | bellard | } |
2830 | b4608c04 | bellard | } |
2831 | b4608c04 | bellard | if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
|
2832 | b4608c04 | bellard | uint8_t buf[1];
|
2833 | b4608c04 | bellard | /* stop emulation if requested by gdb */
|
2834 | b4608c04 | bellard | n = read(gdbstub_fd, buf, 1);
|
2835 | 34865134 | bellard | if (n == 1) { |
2836 | 34865134 | bellard | ret = EXCP_INTERRUPT; |
2837 | b4608c04 | bellard | break;
|
2838 | 34865134 | bellard | } |
2839 | b4608c04 | bellard | } |
2840 | b4608c04 | bellard | } |
2841 | b4608c04 | bellard | |
2842 | b4608c04 | bellard | /* timer IRQ */
|
2843 | b4608c04 | bellard | if (timer_irq_pending) {
|
2844 | b4608c04 | bellard | pic_set_irq(0, 1); |
2845 | b4608c04 | bellard | pic_set_irq(0, 0); |
2846 | b4608c04 | bellard | timer_irq_pending = 0;
|
2847 | 7dea1da4 | bellard | /* XXX: RTC test */
|
2848 | 8f2b1fb0 | bellard | if (cmos_data[RTC_REG_B] & 0x50) { |
2849 | 7dea1da4 | bellard | pic_set_irq(8, 1); |
2850 | 7dea1da4 | bellard | } |
2851 | b4608c04 | bellard | } |
2852 | 313aa567 | bellard | |
2853 | 313aa567 | bellard | /* VGA */
|
2854 | 313aa567 | bellard | if (gui_refresh_pending) {
|
2855 | 313aa567 | bellard | display_state.dpy_refresh(&display_state); |
2856 | 313aa567 | bellard | gui_refresh_pending = 0;
|
2857 | 313aa567 | bellard | } |
2858 | b4608c04 | bellard | } |
2859 | 34865134 | bellard | cpu_disable_ticks(); |
2860 | 34865134 | bellard | return ret;
|
2861 | b4608c04 | bellard | } |
2862 | b4608c04 | bellard | |
2863 | 0824d6fc | bellard | void help(void) |
2864 | 0824d6fc | bellard | { |
2865 | a20dd508 | bellard | printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
2866 | 0db63474 | bellard | "usage: %s [options] [disk_image]\n"
|
2867 | 0824d6fc | bellard | "\n"
|
2868 | a20dd508 | bellard | "'disk_image' is a raw hard image image for IDE hard disk 0\n"
|
2869 | fc01f7e7 | bellard | "\n"
|
2870 | a20dd508 | bellard | "Standard options:\n"
|
2871 | 36b486bb | bellard | "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
|
2872 | 36b486bb | bellard | "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
|
2873 | 36b486bb | bellard | "-cdrom file use 'file' as IDE cdrom 2 image\n"
|
2874 | 27503323 | bellard | "-boot [c|d] boot on hard disk (c) or CD-ROM (d)\n"
|
2875 | a20dd508 | bellard | "-snapshot write to temporary files instead of disk image files\n"
|
2876 | a20dd508 | bellard | "-m megs set virtual RAM size to megs MB\n"
|
2877 | a20dd508 | bellard | "-n script set network init script [default=%s]\n"
|
2878 | 42f1e0e4 | bellard | "-tun-fd fd this fd talks to tap/tun, use it.\n"
|
2879 | a20dd508 | bellard | "-nographic disable graphical output\n"
|
2880 | a20dd508 | bellard | "\n"
|
2881 | a20dd508 | bellard | "Linux boot specific (does not require PC BIOS):\n"
|
2882 | a20dd508 | bellard | "-kernel bzImage use 'bzImage' as kernel image\n"
|
2883 | a20dd508 | bellard | "-append cmdline use 'cmdline' as kernel command line\n"
|
2884 | a20dd508 | bellard | "-initrd file use 'file' as initial ram disk\n"
|
2885 | fc01f7e7 | bellard | "\n"
|
2886 | 330d0414 | bellard | "Debug/Expert options:\n"
|
2887 | a20dd508 | bellard | "-s wait gdb connection to port %d\n"
|
2888 | a20dd508 | bellard | "-p port change gdb connection port\n"
|
2889 | a20dd508 | bellard | "-d output log in /tmp/vl.log\n"
|
2890 | a20dd508 | bellard | "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
|
2891 | a20dd508 | bellard | "-L path set the directory for the BIOS and VGA BIOS\n"
|
2892 | 0824d6fc | bellard | "\n"
|
2893 | f1510b2c | bellard | "During emulation, use C-a h to get terminal commands:\n",
|
2894 | 0db63474 | bellard | #ifdef CONFIG_SOFTMMU
|
2895 | 0db63474 | bellard | "qemu",
|
2896 | 0db63474 | bellard | #else
|
2897 | 0db63474 | bellard | "qemu-fast",
|
2898 | 0db63474 | bellard | #endif
|
2899 | 0db63474 | bellard | DEFAULT_NETWORK_SCRIPT, |
2900 | 0db63474 | bellard | DEFAULT_GDBSTUB_PORT); |
2901 | 0824d6fc | bellard | term_print_help(); |
2902 | 0db63474 | bellard | #ifndef CONFIG_SOFTMMU
|
2903 | 0db63474 | bellard | printf("\n"
|
2904 | 0db63474 | bellard | "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
|
2905 | 0db63474 | bellard | "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
|
2906 | 0db63474 | bellard | "PC emulation.\n");
|
2907 | 0db63474 | bellard | #endif
|
2908 | 0824d6fc | bellard | exit(1);
|
2909 | 0824d6fc | bellard | } |
2910 | 0824d6fc | bellard | |
2911 | fc01f7e7 | bellard | struct option long_options[] = {
|
2912 | fc01f7e7 | bellard | { "initrd", 1, NULL, 0, }, |
2913 | fc01f7e7 | bellard | { "hda", 1, NULL, 0, }, |
2914 | fc01f7e7 | bellard | { "hdb", 1, NULL, 0, }, |
2915 | 33e3963e | bellard | { "snapshot", 0, NULL, 0, }, |
2916 | 330d0414 | bellard | { "hdachs", 1, NULL, 0, }, |
2917 | a20dd508 | bellard | { "nographic", 0, NULL, 0, }, |
2918 | a20dd508 | bellard | { "kernel", 1, NULL, 0, }, |
2919 | a20dd508 | bellard | { "append", 1, NULL, 0, }, |
2920 | 42f1e0e4 | bellard | { "tun-fd", 1, NULL, 0, }, |
2921 | 36b486bb | bellard | { "hdc", 1, NULL, 0, }, |
2922 | 36b486bb | bellard | { "hdd", 1, NULL, 0, }, |
2923 | 36b486bb | bellard | { "cdrom", 1, NULL, 0, }, |
2924 | 36b486bb | bellard | { "boot", 1, NULL, 0, }, |
2925 | fc01f7e7 | bellard | { NULL, 0, NULL, 0 }, |
2926 | fc01f7e7 | bellard | }; |
2927 | fc01f7e7 | bellard | |
2928 | a20dd508 | bellard | #ifdef CONFIG_SDL
|
2929 | a20dd508 | bellard | /* SDL use the pthreads and they modify sigaction. We don't
|
2930 | a20dd508 | bellard | want that. */
|
2931 | a20dd508 | bellard | #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3) |
2932 | a20dd508 | bellard | extern void __libc_sigaction(); |
2933 | a20dd508 | bellard | #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
|
2934 | a20dd508 | bellard | #else
|
2935 | a20dd508 | bellard | extern void __sigaction(); |
2936 | a20dd508 | bellard | #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
|
2937 | a20dd508 | bellard | #endif
|
2938 | a20dd508 | bellard | #endif /* CONFIG_SDL */ |
2939 | a20dd508 | bellard | |
2940 | 0824d6fc | bellard | int main(int argc, char **argv) |
2941 | 0824d6fc | bellard | { |
2942 | fc01f7e7 | bellard | int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
|
2943 | 313aa567 | bellard | int snapshot, linux_boot, total_ram_size;
|
2944 | 0824d6fc | bellard | struct linux_params *params;
|
2945 | 0824d6fc | bellard | struct sigaction act;
|
2946 | 0824d6fc | bellard | struct itimerval itv;
|
2947 | 0824d6fc | bellard | CPUX86State *env; |
2948 | 7f7f9873 | bellard | const char *initrd_filename; |
2949 | fc01f7e7 | bellard | const char *hd_filename[MAX_DISKS]; |
2950 | a20dd508 | bellard | const char *kernel_filename, *kernel_cmdline; |
2951 | 313aa567 | bellard | DisplayState *ds = &display_state; |
2952 | 313aa567 | bellard | |
2953 | 0824d6fc | bellard | /* we never want that malloc() uses mmap() */
|
2954 | 0824d6fc | bellard | mallopt(M_MMAP_THRESHOLD, 4096 * 1024); |
2955 | fc01f7e7 | bellard | initrd_filename = NULL;
|
2956 | fc01f7e7 | bellard | for(i = 0; i < MAX_DISKS; i++) |
2957 | fc01f7e7 | bellard | hd_filename[i] = NULL;
|
2958 | 0824d6fc | bellard | phys_ram_size = 32 * 1024 * 1024; |
2959 | 313aa567 | bellard | vga_ram_size = VGA_RAM_SIZE; |
2960 | f1510b2c | bellard | pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
|
2961 | b4608c04 | bellard | use_gdbstub = 0;
|
2962 | b4608c04 | bellard | gdbstub_port = DEFAULT_GDBSTUB_PORT; |
2963 | 33e3963e | bellard | snapshot = 0;
|
2964 | a20dd508 | bellard | nographic = 0;
|
2965 | a20dd508 | bellard | kernel_filename = NULL;
|
2966 | a20dd508 | bellard | kernel_cmdline = "";
|
2967 | 0824d6fc | bellard | for(;;) {
|
2968 | 330d0414 | bellard | c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
|
2969 | 0824d6fc | bellard | if (c == -1) |
2970 | 0824d6fc | bellard | break;
|
2971 | 0824d6fc | bellard | switch(c) {
|
2972 | fc01f7e7 | bellard | case 0: |
2973 | fc01f7e7 | bellard | switch(long_index) {
|
2974 | fc01f7e7 | bellard | case 0: |
2975 | fc01f7e7 | bellard | initrd_filename = optarg; |
2976 | fc01f7e7 | bellard | break;
|
2977 | fc01f7e7 | bellard | case 1: |
2978 | fc01f7e7 | bellard | hd_filename[0] = optarg;
|
2979 | fc01f7e7 | bellard | break;
|
2980 | fc01f7e7 | bellard | case 2: |
2981 | fc01f7e7 | bellard | hd_filename[1] = optarg;
|
2982 | fc01f7e7 | bellard | break;
|
2983 | 33e3963e | bellard | case 3: |
2984 | 33e3963e | bellard | snapshot = 1;
|
2985 | 33e3963e | bellard | break;
|
2986 | 330d0414 | bellard | case 4: |
2987 | 330d0414 | bellard | { |
2988 | 330d0414 | bellard | int cyls, heads, secs;
|
2989 | 330d0414 | bellard | const char *p; |
2990 | 330d0414 | bellard | p = optarg; |
2991 | 330d0414 | bellard | cyls = strtol(p, (char **)&p, 0); |
2992 | 330d0414 | bellard | if (*p != ',') |
2993 | 330d0414 | bellard | goto chs_fail;
|
2994 | 330d0414 | bellard | p++; |
2995 | 330d0414 | bellard | heads = strtol(p, (char **)&p, 0); |
2996 | 330d0414 | bellard | if (*p != ',') |
2997 | 330d0414 | bellard | goto chs_fail;
|
2998 | 330d0414 | bellard | p++; |
2999 | 330d0414 | bellard | secs = strtol(p, (char **)&p, 0); |
3000 | 330d0414 | bellard | if (*p != '\0') |
3001 | 330d0414 | bellard | goto chs_fail;
|
3002 | 5391d806 | bellard | ide_set_geometry(0, cyls, heads, secs);
|
3003 | 330d0414 | bellard | chs_fail: ;
|
3004 | 330d0414 | bellard | } |
3005 | 330d0414 | bellard | break;
|
3006 | 313aa567 | bellard | case 5: |
3007 | a20dd508 | bellard | nographic = 1;
|
3008 | a20dd508 | bellard | break;
|
3009 | a20dd508 | bellard | case 6: |
3010 | a20dd508 | bellard | kernel_filename = optarg; |
3011 | a20dd508 | bellard | break;
|
3012 | a20dd508 | bellard | case 7: |
3013 | a20dd508 | bellard | kernel_cmdline = optarg; |
3014 | 313aa567 | bellard | break;
|
3015 | 42f1e0e4 | bellard | case 8: |
3016 | 42f1e0e4 | bellard | net_fd = atoi(optarg); |
3017 | 42f1e0e4 | bellard | break;
|
3018 | 36b486bb | bellard | case 9: |
3019 | 36b486bb | bellard | hd_filename[2] = optarg;
|
3020 | 36b486bb | bellard | break;
|
3021 | 36b486bb | bellard | case 10: |
3022 | 36b486bb | bellard | hd_filename[3] = optarg;
|
3023 | 36b486bb | bellard | break;
|
3024 | 36b486bb | bellard | case 11: |
3025 | 36b486bb | bellard | hd_filename[2] = optarg;
|
3026 | 5391d806 | bellard | ide_set_cdrom(2, 1); |
3027 | 36b486bb | bellard | break;
|
3028 | 36b486bb | bellard | case 12: |
3029 | 36b486bb | bellard | boot_device = optarg[0];
|
3030 | 36b486bb | bellard | if (boot_device != 'c' && boot_device != 'd') { |
3031 | 36b486bb | bellard | fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
|
3032 | 36b486bb | bellard | exit(1);
|
3033 | 36b486bb | bellard | } |
3034 | 36b486bb | bellard | break;
|
3035 | fc01f7e7 | bellard | } |
3036 | fc01f7e7 | bellard | break;
|
3037 | 0824d6fc | bellard | case 'h': |
3038 | 0824d6fc | bellard | help(); |
3039 | 0824d6fc | bellard | break;
|
3040 | 0824d6fc | bellard | case 'm': |
3041 | 0824d6fc | bellard | phys_ram_size = atoi(optarg) * 1024 * 1024; |
3042 | 0824d6fc | bellard | if (phys_ram_size <= 0) |
3043 | 0824d6fc | bellard | help(); |
3044 | 7916e224 | bellard | if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
|
3045 | 36b486bb | bellard | fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
|
3046 | 7916e224 | bellard | PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
3047 | 7916e224 | bellard | exit(1);
|
3048 | 7916e224 | bellard | } |
3049 | 0824d6fc | bellard | break;
|
3050 | 0824d6fc | bellard | case 'd': |
3051 | 34865134 | bellard | cpu_set_log(CPU_LOG_ALL); |
3052 | 0824d6fc | bellard | break;
|
3053 | f1510b2c | bellard | case 'n': |
3054 | f1510b2c | bellard | pstrcpy(network_script, sizeof(network_script), optarg);
|
3055 | f1510b2c | bellard | break;
|
3056 | b4608c04 | bellard | case 's': |
3057 | b4608c04 | bellard | use_gdbstub = 1;
|
3058 | b4608c04 | bellard | break;
|
3059 | b4608c04 | bellard | case 'p': |
3060 | b4608c04 | bellard | gdbstub_port = atoi(optarg); |
3061 | b4608c04 | bellard | break;
|
3062 | 330d0414 | bellard | case 'L': |
3063 | 5a67135a | bellard | bios_dir = optarg; |
3064 | 330d0414 | bellard | break;
|
3065 | 0824d6fc | bellard | } |
3066 | 0824d6fc | bellard | } |
3067 | 330d0414 | bellard | |
3068 | a20dd508 | bellard | if (optind < argc) {
|
3069 | a20dd508 | bellard | hd_filename[0] = argv[optind++];
|
3070 | a20dd508 | bellard | } |
3071 | a20dd508 | bellard | |
3072 | a20dd508 | bellard | linux_boot = (kernel_filename != NULL);
|
3073 | 330d0414 | bellard | |
3074 | 36b486bb | bellard | if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0') |
3075 | 0824d6fc | bellard | help(); |
3076 | 8f2b1fb0 | bellard | |
3077 | 8f2b1fb0 | bellard | /* boot to cd by default if no hard disk */
|
3078 | 8f2b1fb0 | bellard | if (hd_filename[0] == '\0' && boot_device == 'c') |
3079 | 8f2b1fb0 | bellard | boot_device = 'd';
|
3080 | 0824d6fc | bellard | |
3081 | 0824d6fc | bellard | /* init debug */
|
3082 | b118d61e | bellard | setvbuf(stdout, NULL, _IOLBF, 0); |
3083 | 0824d6fc | bellard | |
3084 | f1510b2c | bellard | /* init network tun interface */
|
3085 | 42f1e0e4 | bellard | if (net_fd < 0) |
3086 | 42f1e0e4 | bellard | net_init(); |
3087 | f1510b2c | bellard | |
3088 | 0824d6fc | bellard | /* init the memory */
|
3089 | 313aa567 | bellard | total_ram_size = phys_ram_size + vga_ram_size; |
3090 | 7f7f9873 | bellard | |
3091 | 7f7f9873 | bellard | #ifdef CONFIG_SOFTMMU
|
3092 | 7f7f9873 | bellard | phys_ram_base = malloc(total_ram_size); |
3093 | 7f7f9873 | bellard | if (!phys_ram_base) {
|
3094 | 7f7f9873 | bellard | fprintf(stderr, "Could not allocate physical memory\n");
|
3095 | 0824d6fc | bellard | exit(1);
|
3096 | 0824d6fc | bellard | } |
3097 | 7f7f9873 | bellard | #else
|
3098 | 7f7f9873 | bellard | /* as we must map the same page at several addresses, we must use
|
3099 | 7f7f9873 | bellard | a fd */
|
3100 | 7f7f9873 | bellard | { |
3101 | 7f7f9873 | bellard | const char *tmpdir; |
3102 | 7f7f9873 | bellard | |
3103 | 7f7f9873 | bellard | tmpdir = getenv("QEMU_TMPDIR");
|
3104 | 7f7f9873 | bellard | if (!tmpdir)
|
3105 | 7f7f9873 | bellard | tmpdir = "/tmp";
|
3106 | 7f7f9873 | bellard | snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); |
3107 | 7f7f9873 | bellard | if (mkstemp(phys_ram_file) < 0) { |
3108 | 7f7f9873 | bellard | fprintf(stderr, "Could not create temporary memory file '%s'\n",
|
3109 | 7f7f9873 | bellard | phys_ram_file); |
3110 | 7f7f9873 | bellard | exit(1);
|
3111 | 7f7f9873 | bellard | } |
3112 | 7f7f9873 | bellard | phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
|
3113 | 7f7f9873 | bellard | if (phys_ram_fd < 0) { |
3114 | 7f7f9873 | bellard | fprintf(stderr, "Could not open temporary memory file '%s'\n",
|
3115 | 7f7f9873 | bellard | phys_ram_file); |
3116 | 7f7f9873 | bellard | exit(1);
|
3117 | 7f7f9873 | bellard | } |
3118 | 7f7f9873 | bellard | ftruncate(phys_ram_fd, total_ram_size); |
3119 | 7f7f9873 | bellard | unlink(phys_ram_file); |
3120 | 7f7f9873 | bellard | phys_ram_base = mmap(get_mmap_addr(total_ram_size), |
3121 | 7f7f9873 | bellard | total_ram_size, |
3122 | 7f7f9873 | bellard | PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, |
3123 | 7f7f9873 | bellard | phys_ram_fd, 0);
|
3124 | 7f7f9873 | bellard | if (phys_ram_base == MAP_FAILED) {
|
3125 | 7f7f9873 | bellard | fprintf(stderr, "Could not map physical memory\n");
|
3126 | 7f7f9873 | bellard | exit(1);
|
3127 | 7f7f9873 | bellard | } |
3128 | 7f7f9873 | bellard | } |
3129 | 7f7f9873 | bellard | #endif
|
3130 | 0824d6fc | bellard | |
3131 | 33e3963e | bellard | /* open the virtual block devices */
|
3132 | 33e3963e | bellard | for(i = 0; i < MAX_DISKS; i++) { |
3133 | 33e3963e | bellard | if (hd_filename[i]) {
|
3134 | 33e3963e | bellard | bs_table[i] = bdrv_open(hd_filename[i], snapshot); |
3135 | 33e3963e | bellard | if (!bs_table[i]) {
|
3136 | 36b486bb | bellard | fprintf(stderr, "qemu: could not open hard disk image '%s\n",
|
3137 | 33e3963e | bellard | hd_filename[i]); |
3138 | 33e3963e | bellard | exit(1);
|
3139 | 33e3963e | bellard | } |
3140 | 33e3963e | bellard | } |
3141 | 33e3963e | bellard | } |
3142 | 33e3963e | bellard | |
3143 | 330d0414 | bellard | /* init CPU state */
|
3144 | 330d0414 | bellard | env = cpu_init(); |
3145 | 330d0414 | bellard | global_env = env; |
3146 | 330d0414 | bellard | cpu_single_env = env; |
3147 | 330d0414 | bellard | |
3148 | 330d0414 | bellard | init_ioports(); |
3149 | 0824d6fc | bellard | |
3150 | 313aa567 | bellard | /* allocate RAM */
|
3151 | 313aa567 | bellard | cpu_register_physical_memory(0, phys_ram_size, 0); |
3152 | 313aa567 | bellard | |
3153 | 330d0414 | bellard | if (linux_boot) {
|
3154 | 330d0414 | bellard | /* now we can load the kernel */
|
3155 | a20dd508 | bellard | ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
3156 | 330d0414 | bellard | if (ret < 0) { |
3157 | 36b486bb | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
3158 | a20dd508 | bellard | kernel_filename); |
3159 | fc01f7e7 | bellard | exit(1);
|
3160 | fc01f7e7 | bellard | } |
3161 | 330d0414 | bellard | |
3162 | 330d0414 | bellard | /* load initrd */
|
3163 | 330d0414 | bellard | initrd_size = 0;
|
3164 | 330d0414 | bellard | if (initrd_filename) {
|
3165 | 330d0414 | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
3166 | 330d0414 | bellard | if (initrd_size < 0) { |
3167 | 36b486bb | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
3168 | 330d0414 | bellard | initrd_filename); |
3169 | 330d0414 | bellard | exit(1);
|
3170 | 330d0414 | bellard | } |
3171 | 330d0414 | bellard | } |
3172 | 330d0414 | bellard | |
3173 | 330d0414 | bellard | /* init kernel params */
|
3174 | 330d0414 | bellard | params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
|
3175 | 330d0414 | bellard | memset(params, 0, sizeof(struct linux_params)); |
3176 | 330d0414 | bellard | params->mount_root_rdonly = 0;
|
3177 | 7f7f9873 | bellard | stw_raw(¶ms->cl_magic, 0xA33F);
|
3178 | 7f7f9873 | bellard | stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params); |
3179 | 7f7f9873 | bellard | stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024); |
3180 | a20dd508 | bellard | pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
|
3181 | 330d0414 | bellard | params->loader_type = 0x01;
|
3182 | 330d0414 | bellard | if (initrd_size > 0) { |
3183 | 7f7f9873 | bellard | stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR); |
3184 | 7f7f9873 | bellard | stl_raw(¶ms->initrd_size, initrd_size); |
3185 | 330d0414 | bellard | } |
3186 | 330d0414 | bellard | params->orig_video_lines = 25;
|
3187 | 330d0414 | bellard | params->orig_video_cols = 80;
|
3188 | 330d0414 | bellard | |
3189 | 330d0414 | bellard | /* setup basic memory access */
|
3190 | 330d0414 | bellard | env->cr[0] = 0x00000033; |
3191 | 330d0414 | bellard | cpu_x86_init_mmu(env); |
3192 | 330d0414 | bellard | |
3193 | 330d0414 | bellard | memset(params->idt_table, 0, sizeof(params->idt_table)); |
3194 | 330d0414 | bellard | |
3195 | 7f7f9873 | bellard | stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3196 | 7f7f9873 | bellard | stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */ |
3197 | dd6ee15c | bellard | /* for newer kernels (2.6.0) CS/DS are at different addresses */
|
3198 | 7f7f9873 | bellard | stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3199 | 7f7f9873 | bellard | stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */ |
3200 | 330d0414 | bellard | |
3201 | dd6ee15c | bellard | env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
|
3202 | 330d0414 | bellard | env->idt.limit = sizeof(params->idt_table) - 1; |
3203 | dd6ee15c | bellard | env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
|
3204 | 330d0414 | bellard | env->gdt.limit = sizeof(params->gdt_table) - 1; |
3205 | 330d0414 | bellard | |
3206 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00); |
3207 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3208 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3209 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3210 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3211 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); |
3212 | 330d0414 | bellard | |
3213 | 330d0414 | bellard | env->eip = KERNEL_LOAD_ADDR; |
3214 | 330d0414 | bellard | env->regs[R_ESI] = KERNEL_PARAMS_ADDR; |
3215 | 330d0414 | bellard | env->eflags = 0x2;
|
3216 | 0824d6fc | bellard | |
3217 | 330d0414 | bellard | } else {
|
3218 | 330d0414 | bellard | char buf[1024]; |
3219 | a20dd508 | bellard | |
3220 | 330d0414 | bellard | /* RAW PC boot */
|
3221 | 330d0414 | bellard | |
3222 | 330d0414 | bellard | /* BIOS load */
|
3223 | 5a67135a | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
3224 | 330d0414 | bellard | ret = load_image(buf, phys_ram_base + 0x000f0000);
|
3225 | 330d0414 | bellard | if (ret != 0x10000) { |
3226 | 36b486bb | bellard | fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
|
3227 | 330d0414 | bellard | exit(1);
|
3228 | 330d0414 | bellard | } |
3229 | 330d0414 | bellard | |
3230 | 330d0414 | bellard | /* VGA BIOS load */
|
3231 | 5a67135a | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
3232 | 330d0414 | bellard | ret = load_image(buf, phys_ram_base + 0x000c0000);
|
3233 | 330d0414 | bellard | |
3234 | 330d0414 | bellard | /* setup basic memory access */
|
3235 | 330d0414 | bellard | env->cr[0] = 0x60000010; |
3236 | 330d0414 | bellard | cpu_x86_init_mmu(env); |
3237 | 330d0414 | bellard | |
3238 | 330d0414 | bellard | env->idt.limit = 0xffff;
|
3239 | 330d0414 | bellard | env->gdt.limit = 0xffff;
|
3240 | 330d0414 | bellard | env->ldt.limit = 0xffff;
|
3241 | 7dea1da4 | bellard | env->ldt.flags = DESC_P_MASK; |
3242 | 7dea1da4 | bellard | env->tr.limit = 0xffff;
|
3243 | 7dea1da4 | bellard | env->tr.flags = DESC_P_MASK; |
3244 | 330d0414 | bellard | |
3245 | 330d0414 | bellard | /* not correct (CS base=0xffff0000) */
|
3246 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0); |
3247 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0); |
3248 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0); |
3249 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0); |
3250 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0); |
3251 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0); |
3252 | 330d0414 | bellard | |
3253 | 330d0414 | bellard | env->eip = 0xfff0;
|
3254 | 330d0414 | bellard | env->regs[R_EDX] = 0x600; /* indicate P6 processor */ |
3255 | 330d0414 | bellard | |
3256 | 330d0414 | bellard | env->eflags = 0x2;
|
3257 | 330d0414 | bellard | |
3258 | 330d0414 | bellard | bochs_bios_init(); |
3259 | 0824d6fc | bellard | } |
3260 | 0824d6fc | bellard | |
3261 | 313aa567 | bellard | /* terminal init */
|
3262 | a20dd508 | bellard | if (nographic) {
|
3263 | 313aa567 | bellard | dumb_display_init(ds); |
3264 | 313aa567 | bellard | } else {
|
3265 | 313aa567 | bellard | #ifdef CONFIG_SDL
|
3266 | 313aa567 | bellard | sdl_display_init(ds); |
3267 | 313aa567 | bellard | #else
|
3268 | 313aa567 | bellard | dumb_display_init(ds); |
3269 | 313aa567 | bellard | #endif
|
3270 | 313aa567 | bellard | } |
3271 | 0824d6fc | bellard | /* init basic PC hardware */
|
3272 | fc01f7e7 | bellard | register_ioport_write(0x80, 1, ioport80_write, 1); |
3273 | 0824d6fc | bellard | |
3274 | 313aa567 | bellard | vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size, |
3275 | 313aa567 | bellard | vga_ram_size); |
3276 | 0824d6fc | bellard | cmos_init(); |
3277 | 0824d6fc | bellard | pic_init(); |
3278 | 0824d6fc | bellard | pit_init(); |
3279 | 0824d6fc | bellard | serial_init(); |
3280 | f1510b2c | bellard | ne2000_init(); |
3281 | fc01f7e7 | bellard | ide_init(); |
3282 | cd4c3e88 | bellard | kbd_init(); |
3283 | 27503323 | bellard | AUD_init(); |
3284 | 27503323 | bellard | DMA_init(); |
3285 | 27503323 | bellard | SB16_init(); |
3286 | 313aa567 | bellard | |
3287 | 0824d6fc | bellard | /* setup cpu signal handlers for MMU / self modifying code handling */
|
3288 | 0824d6fc | bellard | sigfillset(&act.sa_mask); |
3289 | 0824d6fc | bellard | act.sa_flags = SA_SIGINFO; |
3290 | 3a51dee6 | bellard | #if !defined(CONFIG_SOFTMMU)
|
3291 | 0824d6fc | bellard | act.sa_sigaction = host_segv_handler; |
3292 | 0824d6fc | bellard | sigaction(SIGSEGV, &act, NULL);
|
3293 | 0824d6fc | bellard | sigaction(SIGBUS, &act, NULL);
|
3294 | 3a51dee6 | bellard | #endif
|
3295 | 0824d6fc | bellard | |
3296 | 0824d6fc | bellard | act.sa_sigaction = host_alarm_handler; |
3297 | 0824d6fc | bellard | sigaction(SIGALRM, &act, NULL);
|
3298 | 0824d6fc | bellard | |
3299 | 0824d6fc | bellard | itv.it_interval.tv_sec = 0;
|
3300 | 87858c89 | bellard | itv.it_interval.tv_usec = 1000;
|
3301 | 0824d6fc | bellard | itv.it_value.tv_sec = 0;
|
3302 | 0824d6fc | bellard | itv.it_value.tv_usec = 10 * 1000; |
3303 | 0824d6fc | bellard | setitimer(ITIMER_REAL, &itv, NULL);
|
3304 | 87858c89 | bellard | /* we probe the tick duration of the kernel to inform the user if
|
3305 | 87858c89 | bellard | the emulated kernel requested a too high timer frequency */
|
3306 | 87858c89 | bellard | getitimer(ITIMER_REAL, &itv); |
3307 | 313aa567 | bellard | timer_ms = itv.it_interval.tv_usec / 1000;
|
3308 | 87858c89 | bellard | pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
3309 | 87858c89 | bellard | 1000000;
|
3310 | 7f7f9873 | bellard | |
3311 | b4608c04 | bellard | if (use_gdbstub) {
|
3312 | b4608c04 | bellard | cpu_gdbstub(NULL, main_loop, gdbstub_port);
|
3313 | b4608c04 | bellard | } else {
|
3314 | b4608c04 | bellard | main_loop(NULL);
|
3315 | 0824d6fc | bellard | } |
3316 | 0824d6fc | bellard | return 0; |
3317 | 0824d6fc | bellard | } |