Revision 08307563 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 843 | 843 |
} |
| 844 | 844 |
} |
| 845 | 845 |
|
| 846 |
/* Abstractions of "generate code to do a guest load/store for |
|
| 847 |
* AArch32", where a vaddr is always 32 bits (and is zero |
|
| 848 |
* extended if we're a 64 bit core) and data is also |
|
| 849 |
* 32 bits unless specifically doing a 64 bit access. |
|
| 850 |
* These functions work like tcg_gen_qemu_{ld,st}* except
|
|
| 851 |
* that their arguments are TCGv_i32 rather than TCGv. |
|
| 852 |
*/ |
|
| 853 |
#if TARGET_LONG_BITS == 32 |
|
| 854 |
|
|
| 855 |
#define DO_GEN_LD(OP) \ |
|
| 856 |
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ |
|
| 857 |
{ \
|
|
| 858 |
tcg_gen_qemu_##OP(val, addr, index); \ |
|
| 859 |
} |
|
| 860 |
|
|
| 861 |
#define DO_GEN_ST(OP) \ |
|
| 862 |
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ |
|
| 863 |
{ \
|
|
| 864 |
tcg_gen_qemu_##OP(val, addr, index); \ |
|
| 865 |
} |
|
| 866 |
|
|
| 867 |
static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index) |
|
| 868 |
{
|
|
| 869 |
tcg_gen_qemu_ld64(val, addr, index); |
|
| 870 |
} |
|
| 871 |
|
|
| 872 |
static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index) |
|
| 873 |
{
|
|
| 874 |
tcg_gen_qemu_st64(val, addr, index); |
|
| 875 |
} |
|
| 876 |
|
|
| 877 |
#else |
|
| 878 |
|
|
| 879 |
#define DO_GEN_LD(OP) \ |
|
| 880 |
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ |
|
| 881 |
{ \
|
|
| 882 |
TCGv addr64 = tcg_temp_new(); \ |
|
| 883 |
TCGv val64 = tcg_temp_new(); \ |
|
| 884 |
tcg_gen_extu_i32_i64(addr64, addr); \ |
|
| 885 |
tcg_gen_qemu_##OP(val64, addr64, index); \ |
|
| 886 |
tcg_temp_free(addr64); \ |
|
| 887 |
tcg_gen_trunc_i64_i32(val, val64); \ |
|
| 888 |
tcg_temp_free(val64); \ |
|
| 889 |
} |
|
| 890 |
|
|
| 891 |
#define DO_GEN_ST(OP) \ |
|
| 892 |
static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \ |
|
| 893 |
{ \
|
|
| 894 |
TCGv addr64 = tcg_temp_new(); \ |
|
| 895 |
TCGv val64 = tcg_temp_new(); \ |
|
| 896 |
tcg_gen_extu_i32_i64(addr64, addr); \ |
|
| 897 |
tcg_gen_extu_i32_i64(val64, val); \ |
|
| 898 |
tcg_gen_qemu_##OP(val64, addr64, index); \ |
|
| 899 |
tcg_temp_free(addr64); \ |
|
| 900 |
tcg_temp_free(val64); \ |
|
| 901 |
} |
|
| 902 |
|
|
| 903 |
static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index) |
|
| 904 |
{
|
|
| 905 |
TCGv addr64 = tcg_temp_new(); |
|
| 906 |
tcg_gen_extu_i32_i64(addr64, addr); |
|
| 907 |
tcg_gen_qemu_ld64(val, addr64, index); |
|
| 908 |
tcg_temp_free(addr64); |
|
| 909 |
} |
|
| 910 |
|
|
| 911 |
static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index) |
|
| 912 |
{
|
|
| 913 |
TCGv addr64 = tcg_temp_new(); |
|
| 914 |
tcg_gen_extu_i32_i64(addr64, addr); |
|
| 915 |
tcg_gen_qemu_st64(val, addr64, index); |
|
| 916 |
tcg_temp_free(addr64); |
|
| 917 |
} |
|
| 918 |
|
|
| 919 |
#endif |
|
| 920 |
|
|
| 921 |
DO_GEN_LD(ld8s) |
|
| 922 |
DO_GEN_LD(ld8u) |
|
| 923 |
DO_GEN_LD(ld16s) |
|
| 924 |
DO_GEN_LD(ld16u) |
|
| 925 |
DO_GEN_LD(ld32u) |
|
| 926 |
DO_GEN_ST(st8) |
|
| 927 |
DO_GEN_ST(st16) |
|
| 928 |
DO_GEN_ST(st32) |
|
| 929 |
|
|
| 846 | 930 |
static inline void gen_set_pc_im(uint32_t val) |
| 847 | 931 |
{
|
| 848 | 932 |
tcg_gen_movi_i32(cpu_R[15], val); |
| ... | ... | |
| 1072 | 1156 |
|
| 1073 | 1157 |
static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr) |
| 1074 | 1158 |
{
|
| 1075 |
if (dp) |
|
| 1076 |
tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s)); |
|
| 1077 |
else |
|
| 1078 |
tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s)); |
|
| 1159 |
if (dp) {
|
|
| 1160 |
gen_aa32_ld64(cpu_F0d, addr, IS_USER(s)); |
|
| 1161 |
} else {
|
|
| 1162 |
gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s)); |
|
| 1163 |
} |
|
| 1079 | 1164 |
} |
| 1080 | 1165 |
|
| 1081 | 1166 |
static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr) |
| 1082 | 1167 |
{
|
| 1083 |
if (dp) |
|
| 1084 |
tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s)); |
|
| 1085 |
else |
|
| 1086 |
tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s)); |
|
| 1168 |
if (dp) {
|
|
| 1169 |
gen_aa32_st64(cpu_F0d, addr, IS_USER(s)); |
|
| 1170 |
} else {
|
|
| 1171 |
gen_aa32_st32(cpu_F0s, addr, IS_USER(s)); |
|
| 1172 |
} |
|
| 1087 | 1173 |
} |
| 1088 | 1174 |
|
| 1089 | 1175 |
static inline long |
| ... | ... | |
| 1420 | 1506 |
if (insn & ARM_CP_RW_BIT) {
|
| 1421 | 1507 |
if ((insn >> 28) == 0xf) { /* WLDRW wCx */
|
| 1422 | 1508 |
tmp = tcg_temp_new_i32(); |
| 1423 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 1509 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 1424 | 1510 |
iwmmxt_store_creg(wrd, tmp); |
| 1425 | 1511 |
} else {
|
| 1426 | 1512 |
i = 1; |
| 1427 | 1513 |
if (insn & (1 << 8)) {
|
| 1428 | 1514 |
if (insn & (1 << 22)) { /* WLDRD */
|
| 1429 |
tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
|
|
| 1515 |
gen_aa32_ld64(cpu_M0, addr, IS_USER(s));
|
|
| 1430 | 1516 |
i = 0; |
| 1431 | 1517 |
} else { /* WLDRW wRd */
|
| 1432 | 1518 |
tmp = tcg_temp_new_i32(); |
| 1433 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 1519 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 1434 | 1520 |
} |
| 1435 | 1521 |
} else {
|
| 1436 | 1522 |
tmp = tcg_temp_new_i32(); |
| 1437 | 1523 |
if (insn & (1 << 22)) { /* WLDRH */
|
| 1438 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 1524 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 1439 | 1525 |
} else { /* WLDRB */
|
| 1440 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 1526 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 1441 | 1527 |
} |
| 1442 | 1528 |
} |
| 1443 | 1529 |
if (i) {
|
| ... | ... | |
| 1449 | 1535 |
} else {
|
| 1450 | 1536 |
if ((insn >> 28) == 0xf) { /* WSTRW wCx */
|
| 1451 | 1537 |
tmp = iwmmxt_load_creg(wrd); |
| 1452 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 1538 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 1453 | 1539 |
} else {
|
| 1454 | 1540 |
gen_op_iwmmxt_movq_M0_wRn(wrd); |
| 1455 | 1541 |
tmp = tcg_temp_new_i32(); |
| 1456 | 1542 |
if (insn & (1 << 8)) {
|
| 1457 | 1543 |
if (insn & (1 << 22)) { /* WSTRD */
|
| 1458 |
tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
|
|
| 1544 |
gen_aa32_st64(cpu_M0, addr, IS_USER(s));
|
|
| 1459 | 1545 |
} else { /* WSTRW wRd */
|
| 1460 | 1546 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1461 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 1547 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 1462 | 1548 |
} |
| 1463 | 1549 |
} else {
|
| 1464 | 1550 |
if (insn & (1 << 22)) { /* WSTRH */
|
| 1465 | 1551 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1466 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 1552 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 1467 | 1553 |
} else { /* WSTRB */
|
| 1468 | 1554 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1469 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 1555 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 1470 | 1556 |
} |
| 1471 | 1557 |
} |
| 1472 | 1558 |
} |
| ... | ... | |
| 2531 | 2617 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
| 2532 | 2618 |
switch (size) {
|
| 2533 | 2619 |
case 0: |
| 2534 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 2620 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 2535 | 2621 |
gen_neon_dup_u8(tmp, 0); |
| 2536 | 2622 |
break; |
| 2537 | 2623 |
case 1: |
| 2538 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 2624 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 2539 | 2625 |
gen_neon_dup_low16(tmp); |
| 2540 | 2626 |
break; |
| 2541 | 2627 |
case 2: |
| 2542 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 2628 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 2543 | 2629 |
break; |
| 2544 | 2630 |
default: /* Avoid compiler warnings. */ |
| 2545 | 2631 |
abort(); |
| ... | ... | |
| 3817 | 3903 |
if (size == 3) {
|
| 3818 | 3904 |
tmp64 = tcg_temp_new_i64(); |
| 3819 | 3905 |
if (load) {
|
| 3820 |
tcg_gen_qemu_ld64(tmp64, addr, IS_USER(s));
|
|
| 3906 |
gen_aa32_ld64(tmp64, addr, IS_USER(s));
|
|
| 3821 | 3907 |
neon_store_reg64(tmp64, rd); |
| 3822 | 3908 |
} else {
|
| 3823 | 3909 |
neon_load_reg64(tmp64, rd); |
| 3824 |
tcg_gen_qemu_st64(tmp64, addr, IS_USER(s));
|
|
| 3910 |
gen_aa32_st64(tmp64, addr, IS_USER(s));
|
|
| 3825 | 3911 |
} |
| 3826 | 3912 |
tcg_temp_free_i64(tmp64); |
| 3827 | 3913 |
tcg_gen_addi_i32(addr, addr, stride); |
| ... | ... | |
| 3830 | 3916 |
if (size == 2) {
|
| 3831 | 3917 |
if (load) {
|
| 3832 | 3918 |
tmp = tcg_temp_new_i32(); |
| 3833 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 3919 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 3834 | 3920 |
neon_store_reg(rd, pass, tmp); |
| 3835 | 3921 |
} else {
|
| 3836 | 3922 |
tmp = neon_load_reg(rd, pass); |
| 3837 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 3923 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 3838 | 3924 |
tcg_temp_free_i32(tmp); |
| 3839 | 3925 |
} |
| 3840 | 3926 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3841 | 3927 |
} else if (size == 1) {
|
| 3842 | 3928 |
if (load) {
|
| 3843 | 3929 |
tmp = tcg_temp_new_i32(); |
| 3844 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 3930 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 3845 | 3931 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3846 | 3932 |
tmp2 = tcg_temp_new_i32(); |
| 3847 |
tcg_gen_qemu_ld16u(tmp2, addr, IS_USER(s));
|
|
| 3933 |
gen_aa32_ld16u(tmp2, addr, IS_USER(s));
|
|
| 3848 | 3934 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3849 | 3935 |
tcg_gen_shli_i32(tmp2, tmp2, 16); |
| 3850 | 3936 |
tcg_gen_or_i32(tmp, tmp, tmp2); |
| ... | ... | |
| 3854 | 3940 |
tmp = neon_load_reg(rd, pass); |
| 3855 | 3941 |
tmp2 = tcg_temp_new_i32(); |
| 3856 | 3942 |
tcg_gen_shri_i32(tmp2, tmp, 16); |
| 3857 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 3943 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 3858 | 3944 |
tcg_temp_free_i32(tmp); |
| 3859 | 3945 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3860 |
tcg_gen_qemu_st16(tmp2, addr, IS_USER(s));
|
|
| 3946 |
gen_aa32_st16(tmp2, addr, IS_USER(s));
|
|
| 3861 | 3947 |
tcg_temp_free_i32(tmp2); |
| 3862 | 3948 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3863 | 3949 |
} |
| ... | ... | |
| 3866 | 3952 |
TCGV_UNUSED_I32(tmp2); |
| 3867 | 3953 |
for (n = 0; n < 4; n++) {
|
| 3868 | 3954 |
tmp = tcg_temp_new_i32(); |
| 3869 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 3955 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 3870 | 3956 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3871 | 3957 |
if (n == 0) {
|
| 3872 | 3958 |
tmp2 = tmp; |
| ... | ... | |
| 3886 | 3972 |
} else {
|
| 3887 | 3973 |
tcg_gen_shri_i32(tmp, tmp2, n * 8); |
| 3888 | 3974 |
} |
| 3889 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 3975 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 3890 | 3976 |
tcg_temp_free_i32(tmp); |
| 3891 | 3977 |
tcg_gen_addi_i32(addr, addr, stride); |
| 3892 | 3978 |
} |
| ... | ... | |
| 4010 | 4096 |
tmp = tcg_temp_new_i32(); |
| 4011 | 4097 |
switch (size) {
|
| 4012 | 4098 |
case 0: |
| 4013 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 4099 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 4014 | 4100 |
break; |
| 4015 | 4101 |
case 1: |
| 4016 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 4102 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 4017 | 4103 |
break; |
| 4018 | 4104 |
case 2: |
| 4019 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 4105 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 4020 | 4106 |
break; |
| 4021 | 4107 |
default: /* Avoid compiler warnings. */ |
| 4022 | 4108 |
abort(); |
| ... | ... | |
| 4034 | 4120 |
tcg_gen_shri_i32(tmp, tmp, shift); |
| 4035 | 4121 |
switch (size) {
|
| 4036 | 4122 |
case 0: |
| 4037 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 4123 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 4038 | 4124 |
break; |
| 4039 | 4125 |
case 1: |
| 4040 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 4126 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 4041 | 4127 |
break; |
| 4042 | 4128 |
case 2: |
| 4043 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 4129 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 4044 | 4130 |
break; |
| 4045 | 4131 |
} |
| 4046 | 4132 |
tcg_temp_free_i32(tmp); |
| ... | ... | |
| 6464 | 6550 |
|
| 6465 | 6551 |
switch (size) {
|
| 6466 | 6552 |
case 0: |
| 6467 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 6553 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 6468 | 6554 |
break; |
| 6469 | 6555 |
case 1: |
| 6470 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 6556 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 6471 | 6557 |
break; |
| 6472 | 6558 |
case 2: |
| 6473 | 6559 |
case 3: |
| 6474 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 6560 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 6475 | 6561 |
break; |
| 6476 | 6562 |
default: |
| 6477 | 6563 |
abort(); |
| ... | ... | |
| 6482 | 6568 |
TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 6483 | 6569 |
tcg_gen_addi_i32(tmp2, addr, 4); |
| 6484 | 6570 |
tmp = tcg_temp_new_i32(); |
| 6485 |
tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
|
|
| 6571 |
gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
|
|
| 6486 | 6572 |
tcg_temp_free_i32(tmp2); |
| 6487 | 6573 |
tcg_gen_mov_i32(cpu_exclusive_high, tmp); |
| 6488 | 6574 |
store_reg(s, rt2, tmp); |
| ... | ... | |
| 6524 | 6610 |
tmp = tcg_temp_new_i32(); |
| 6525 | 6611 |
switch (size) {
|
| 6526 | 6612 |
case 0: |
| 6527 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 6613 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 6528 | 6614 |
break; |
| 6529 | 6615 |
case 1: |
| 6530 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 6616 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 6531 | 6617 |
break; |
| 6532 | 6618 |
case 2: |
| 6533 | 6619 |
case 3: |
| 6534 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 6620 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 6535 | 6621 |
break; |
| 6536 | 6622 |
default: |
| 6537 | 6623 |
abort(); |
| ... | ... | |
| 6542 | 6628 |
TCGv_i32 tmp2 = tcg_temp_new_i32(); |
| 6543 | 6629 |
tcg_gen_addi_i32(tmp2, addr, 4); |
| 6544 | 6630 |
tmp = tcg_temp_new_i32(); |
| 6545 |
tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
|
|
| 6631 |
gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
|
|
| 6546 | 6632 |
tcg_temp_free_i32(tmp2); |
| 6547 | 6633 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); |
| 6548 | 6634 |
tcg_temp_free_i32(tmp); |
| ... | ... | |
| 6550 | 6636 |
tmp = load_reg(s, rt); |
| 6551 | 6637 |
switch (size) {
|
| 6552 | 6638 |
case 0: |
| 6553 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 6639 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 6554 | 6640 |
break; |
| 6555 | 6641 |
case 1: |
| 6556 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 6642 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 6557 | 6643 |
break; |
| 6558 | 6644 |
case 2: |
| 6559 | 6645 |
case 3: |
| 6560 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 6646 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 6561 | 6647 |
break; |
| 6562 | 6648 |
default: |
| 6563 | 6649 |
abort(); |
| ... | ... | |
| 6566 | 6652 |
if (size == 3) {
|
| 6567 | 6653 |
tcg_gen_addi_i32(addr, addr, 4); |
| 6568 | 6654 |
tmp = load_reg(s, rt2); |
| 6569 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 6655 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 6570 | 6656 |
tcg_temp_free_i32(tmp); |
| 6571 | 6657 |
} |
| 6572 | 6658 |
tcg_gen_movi_i32(cpu_R[rd], 0); |
| ... | ... | |
| 6613 | 6699 |
} |
| 6614 | 6700 |
tcg_gen_addi_i32(addr, addr, offset); |
| 6615 | 6701 |
tmp = load_reg(s, 14); |
| 6616 |
tcg_gen_qemu_st32(tmp, addr, 0);
|
|
| 6702 |
gen_aa32_st32(tmp, addr, 0);
|
|
| 6617 | 6703 |
tcg_temp_free_i32(tmp); |
| 6618 | 6704 |
tmp = load_cpu_field(spsr); |
| 6619 | 6705 |
tcg_gen_addi_i32(addr, addr, 4); |
| 6620 |
tcg_gen_qemu_st32(tmp, addr, 0);
|
|
| 6706 |
gen_aa32_st32(tmp, addr, 0);
|
|
| 6621 | 6707 |
tcg_temp_free_i32(tmp); |
| 6622 | 6708 |
if (writeback) {
|
| 6623 | 6709 |
switch (amode) {
|
| ... | ... | |
| 6763 | 6849 |
tcg_gen_addi_i32(addr, addr, offset); |
| 6764 | 6850 |
/* Load PC into tmp and CPSR into tmp2. */ |
| 6765 | 6851 |
tmp = tcg_temp_new_i32(); |
| 6766 |
tcg_gen_qemu_ld32u(tmp, addr, 0);
|
|
| 6852 |
gen_aa32_ld32u(tmp, addr, 0);
|
|
| 6767 | 6853 |
tcg_gen_addi_i32(addr, addr, 4); |
| 6768 | 6854 |
tmp2 = tcg_temp_new_i32(); |
| 6769 |
tcg_gen_qemu_ld32u(tmp2, addr, 0);
|
|
| 6855 |
gen_aa32_ld32u(tmp2, addr, 0);
|
|
| 6770 | 6856 |
if (insn & (1 << 21)) {
|
| 6771 | 6857 |
/* Base writeback. */ |
| 6772 | 6858 |
switch (i) {
|
| ... | ... | |
| 7322 | 7408 |
tmp = tcg_temp_new_i32(); |
| 7323 | 7409 |
switch (op1) {
|
| 7324 | 7410 |
case 0: /* lda */ |
| 7325 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 7411 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 7326 | 7412 |
break; |
| 7327 | 7413 |
case 2: /* ldab */ |
| 7328 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 7414 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 7329 | 7415 |
break; |
| 7330 | 7416 |
case 3: /* ldah */ |
| 7331 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 7417 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 7332 | 7418 |
break; |
| 7333 | 7419 |
default: |
| 7334 | 7420 |
abort(); |
| ... | ... | |
| 7339 | 7425 |
tmp = load_reg(s, rm); |
| 7340 | 7426 |
switch (op1) {
|
| 7341 | 7427 |
case 0: /* stl */ |
| 7342 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 7428 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 7343 | 7429 |
break; |
| 7344 | 7430 |
case 2: /* stlb */ |
| 7345 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 7431 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 7346 | 7432 |
break; |
| 7347 | 7433 |
case 3: /* stlh */ |
| 7348 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 7434 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 7349 | 7435 |
break; |
| 7350 | 7436 |
default: |
| 7351 | 7437 |
abort(); |
| ... | ... | |
| 7400 | 7486 |
tmp = load_reg(s, rm); |
| 7401 | 7487 |
tmp2 = tcg_temp_new_i32(); |
| 7402 | 7488 |
if (insn & (1 << 22)) {
|
| 7403 |
tcg_gen_qemu_ld8u(tmp2, addr, IS_USER(s));
|
|
| 7404 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 7489 |
gen_aa32_ld8u(tmp2, addr, IS_USER(s));
|
|
| 7490 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 7405 | 7491 |
} else {
|
| 7406 |
tcg_gen_qemu_ld32u(tmp2, addr, IS_USER(s));
|
|
| 7407 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 7492 |
gen_aa32_ld32u(tmp2, addr, IS_USER(s));
|
|
| 7493 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 7408 | 7494 |
} |
| 7409 | 7495 |
tcg_temp_free_i32(tmp); |
| 7410 | 7496 |
tcg_temp_free_i32(addr); |
| ... | ... | |
| 7426 | 7512 |
tmp = tcg_temp_new_i32(); |
| 7427 | 7513 |
switch(sh) {
|
| 7428 | 7514 |
case 1: |
| 7429 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 7515 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 7430 | 7516 |
break; |
| 7431 | 7517 |
case 2: |
| 7432 |
tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
|
|
| 7518 |
gen_aa32_ld8s(tmp, addr, IS_USER(s));
|
|
| 7433 | 7519 |
break; |
| 7434 | 7520 |
default: |
| 7435 | 7521 |
case 3: |
| 7436 |
tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
|
|
| 7522 |
gen_aa32_ld16s(tmp, addr, IS_USER(s));
|
|
| 7437 | 7523 |
break; |
| 7438 | 7524 |
} |
| 7439 | 7525 |
load = 1; |
| ... | ... | |
| 7443 | 7529 |
if (sh & 1) {
|
| 7444 | 7530 |
/* store */ |
| 7445 | 7531 |
tmp = load_reg(s, rd); |
| 7446 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 7532 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 7447 | 7533 |
tcg_temp_free_i32(tmp); |
| 7448 | 7534 |
tcg_gen_addi_i32(addr, addr, 4); |
| 7449 | 7535 |
tmp = load_reg(s, rd + 1); |
| 7450 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 7536 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 7451 | 7537 |
tcg_temp_free_i32(tmp); |
| 7452 | 7538 |
load = 0; |
| 7453 | 7539 |
} else {
|
| 7454 | 7540 |
/* load */ |
| 7455 | 7541 |
tmp = tcg_temp_new_i32(); |
| 7456 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 7542 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 7457 | 7543 |
store_reg(s, rd, tmp); |
| 7458 | 7544 |
tcg_gen_addi_i32(addr, addr, 4); |
| 7459 | 7545 |
tmp = tcg_temp_new_i32(); |
| 7460 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 7546 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 7461 | 7547 |
rd++; |
| 7462 | 7548 |
load = 1; |
| 7463 | 7549 |
} |
| ... | ... | |
| 7465 | 7551 |
} else {
|
| 7466 | 7552 |
/* store */ |
| 7467 | 7553 |
tmp = load_reg(s, rd); |
| 7468 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 7554 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 7469 | 7555 |
tcg_temp_free_i32(tmp); |
| 7470 | 7556 |
load = 0; |
| 7471 | 7557 |
} |
| ... | ... | |
| 7798 | 7884 |
/* load */ |
| 7799 | 7885 |
tmp = tcg_temp_new_i32(); |
| 7800 | 7886 |
if (insn & (1 << 22)) {
|
| 7801 |
tcg_gen_qemu_ld8u(tmp, tmp2, i);
|
|
| 7887 |
gen_aa32_ld8u(tmp, tmp2, i);
|
|
| 7802 | 7888 |
} else {
|
| 7803 |
tcg_gen_qemu_ld32u(tmp, tmp2, i);
|
|
| 7889 |
gen_aa32_ld32u(tmp, tmp2, i);
|
|
| 7804 | 7890 |
} |
| 7805 | 7891 |
} else {
|
| 7806 | 7892 |
/* store */ |
| 7807 | 7893 |
tmp = load_reg(s, rd); |
| 7808 | 7894 |
if (insn & (1 << 22)) {
|
| 7809 |
tcg_gen_qemu_st8(tmp, tmp2, i);
|
|
| 7895 |
gen_aa32_st8(tmp, tmp2, i);
|
|
| 7810 | 7896 |
} else {
|
| 7811 |
tcg_gen_qemu_st32(tmp, tmp2, i);
|
|
| 7897 |
gen_aa32_st32(tmp, tmp2, i);
|
|
| 7812 | 7898 |
} |
| 7813 | 7899 |
tcg_temp_free_i32(tmp); |
| 7814 | 7900 |
} |
| ... | ... | |
| 7875 | 7961 |
if (insn & (1 << 20)) {
|
| 7876 | 7962 |
/* load */ |
| 7877 | 7963 |
tmp = tcg_temp_new_i32(); |
| 7878 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 7964 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 7879 | 7965 |
if (user) {
|
| 7880 | 7966 |
tmp2 = tcg_const_i32(i); |
| 7881 | 7967 |
gen_helper_set_user_reg(cpu_env, tmp2, tmp); |
| ... | ... | |
| 7902 | 7988 |
} else {
|
| 7903 | 7989 |
tmp = load_reg(s, i); |
| 7904 | 7990 |
} |
| 7905 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 7991 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 7906 | 7992 |
tcg_temp_free_i32(tmp); |
| 7907 | 7993 |
} |
| 7908 | 7994 |
j++; |
| ... | ... | |
| 8161 | 8247 |
if (insn & (1 << 20)) {
|
| 8162 | 8248 |
/* ldrd */ |
| 8163 | 8249 |
tmp = tcg_temp_new_i32(); |
| 8164 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 8250 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 8165 | 8251 |
store_reg(s, rs, tmp); |
| 8166 | 8252 |
tcg_gen_addi_i32(addr, addr, 4); |
| 8167 | 8253 |
tmp = tcg_temp_new_i32(); |
| 8168 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 8254 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 8169 | 8255 |
store_reg(s, rd, tmp); |
| 8170 | 8256 |
} else {
|
| 8171 | 8257 |
/* strd */ |
| 8172 | 8258 |
tmp = load_reg(s, rs); |
| 8173 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 8259 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 8174 | 8260 |
tcg_temp_free_i32(tmp); |
| 8175 | 8261 |
tcg_gen_addi_i32(addr, addr, 4); |
| 8176 | 8262 |
tmp = load_reg(s, rd); |
| 8177 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 8263 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 8178 | 8264 |
tcg_temp_free_i32(tmp); |
| 8179 | 8265 |
} |
| 8180 | 8266 |
if (insn & (1 << 21)) {
|
| ... | ... | |
| 8212 | 8298 |
tcg_gen_add_i32(addr, addr, tmp); |
| 8213 | 8299 |
tcg_temp_free_i32(tmp); |
| 8214 | 8300 |
tmp = tcg_temp_new_i32(); |
| 8215 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 8301 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 8216 | 8302 |
} else { /* tbb */
|
| 8217 | 8303 |
tcg_temp_free_i32(tmp); |
| 8218 | 8304 |
tmp = tcg_temp_new_i32(); |
| 8219 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 8305 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 8220 | 8306 |
} |
| 8221 | 8307 |
tcg_temp_free_i32(addr); |
| 8222 | 8308 |
tcg_gen_shli_i32(tmp, tmp, 1); |
| ... | ... | |
| 8253 | 8339 |
tmp = tcg_temp_new_i32(); |
| 8254 | 8340 |
switch (op) {
|
| 8255 | 8341 |
case 0: /* ldab */ |
| 8256 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 8342 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 8257 | 8343 |
break; |
| 8258 | 8344 |
case 1: /* ldah */ |
| 8259 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 8345 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 8260 | 8346 |
break; |
| 8261 | 8347 |
case 2: /* lda */ |
| 8262 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 8348 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 8263 | 8349 |
break; |
| 8264 | 8350 |
default: |
| 8265 | 8351 |
abort(); |
| ... | ... | |
| 8269 | 8355 |
tmp = load_reg(s, rs); |
| 8270 | 8356 |
switch (op) {
|
| 8271 | 8357 |
case 0: /* stlb */ |
| 8272 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 8358 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 8273 | 8359 |
break; |
| 8274 | 8360 |
case 1: /* stlh */ |
| 8275 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 8361 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 8276 | 8362 |
break; |
| 8277 | 8363 |
case 2: /* stl */ |
| 8278 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 8364 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 8279 | 8365 |
break; |
| 8280 | 8366 |
default: |
| 8281 | 8367 |
abort(); |
| ... | ... | |
| 8303 | 8389 |
tcg_gen_addi_i32(addr, addr, -8); |
| 8304 | 8390 |
/* Load PC into tmp and CPSR into tmp2. */ |
| 8305 | 8391 |
tmp = tcg_temp_new_i32(); |
| 8306 |
tcg_gen_qemu_ld32u(tmp, addr, 0);
|
|
| 8392 |
gen_aa32_ld32u(tmp, addr, 0);
|
|
| 8307 | 8393 |
tcg_gen_addi_i32(addr, addr, 4); |
| 8308 | 8394 |
tmp2 = tcg_temp_new_i32(); |
| 8309 |
tcg_gen_qemu_ld32u(tmp2, addr, 0);
|
|
| 8395 |
gen_aa32_ld32u(tmp2, addr, 0);
|
|
| 8310 | 8396 |
if (insn & (1 << 21)) {
|
| 8311 | 8397 |
/* Base writeback. */ |
| 8312 | 8398 |
if (insn & (1 << 24)) {
|
| ... | ... | |
| 8345 | 8431 |
if (insn & (1 << 20)) {
|
| 8346 | 8432 |
/* Load. */ |
| 8347 | 8433 |
tmp = tcg_temp_new_i32(); |
| 8348 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 8434 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 8349 | 8435 |
if (i == 15) {
|
| 8350 | 8436 |
gen_bx(s, tmp); |
| 8351 | 8437 |
} else if (i == rn) {
|
| ... | ... | |
| 8357 | 8443 |
} else {
|
| 8358 | 8444 |
/* Store. */ |
| 8359 | 8445 |
tmp = load_reg(s, i); |
| 8360 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 8446 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 8361 | 8447 |
tcg_temp_free_i32(tmp); |
| 8362 | 8448 |
} |
| 8363 | 8449 |
tcg_gen_addi_i32(addr, addr, 4); |
| ... | ... | |
| 9135 | 9221 |
tmp = tcg_temp_new_i32(); |
| 9136 | 9222 |
switch (op) {
|
| 9137 | 9223 |
case 0: |
| 9138 |
tcg_gen_qemu_ld8u(tmp, addr, user);
|
|
| 9224 |
gen_aa32_ld8u(tmp, addr, user);
|
|
| 9139 | 9225 |
break; |
| 9140 | 9226 |
case 4: |
| 9141 |
tcg_gen_qemu_ld8s(tmp, addr, user);
|
|
| 9227 |
gen_aa32_ld8s(tmp, addr, user);
|
|
| 9142 | 9228 |
break; |
| 9143 | 9229 |
case 1: |
| 9144 |
tcg_gen_qemu_ld16u(tmp, addr, user);
|
|
| 9230 |
gen_aa32_ld16u(tmp, addr, user);
|
|
| 9145 | 9231 |
break; |
| 9146 | 9232 |
case 5: |
| 9147 |
tcg_gen_qemu_ld16s(tmp, addr, user);
|
|
| 9233 |
gen_aa32_ld16s(tmp, addr, user);
|
|
| 9148 | 9234 |
break; |
| 9149 | 9235 |
case 2: |
| 9150 |
tcg_gen_qemu_ld32u(tmp, addr, user);
|
|
| 9236 |
gen_aa32_ld32u(tmp, addr, user);
|
|
| 9151 | 9237 |
break; |
| 9152 | 9238 |
default: |
| 9153 | 9239 |
tcg_temp_free_i32(tmp); |
| ... | ... | |
| 9164 | 9250 |
tmp = load_reg(s, rs); |
| 9165 | 9251 |
switch (op) {
|
| 9166 | 9252 |
case 0: |
| 9167 |
tcg_gen_qemu_st8(tmp, addr, user);
|
|
| 9253 |
gen_aa32_st8(tmp, addr, user);
|
|
| 9168 | 9254 |
break; |
| 9169 | 9255 |
case 1: |
| 9170 |
tcg_gen_qemu_st16(tmp, addr, user);
|
|
| 9256 |
gen_aa32_st16(tmp, addr, user);
|
|
| 9171 | 9257 |
break; |
| 9172 | 9258 |
case 2: |
| 9173 |
tcg_gen_qemu_st32(tmp, addr, user);
|
|
| 9259 |
gen_aa32_st32(tmp, addr, user);
|
|
| 9174 | 9260 |
break; |
| 9175 | 9261 |
default: |
| 9176 | 9262 |
tcg_temp_free_i32(tmp); |
| ... | ... | |
| 9307 | 9393 |
addr = tcg_temp_new_i32(); |
| 9308 | 9394 |
tcg_gen_movi_i32(addr, val); |
| 9309 | 9395 |
tmp = tcg_temp_new_i32(); |
| 9310 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9396 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9311 | 9397 |
tcg_temp_free_i32(addr); |
| 9312 | 9398 |
store_reg(s, rd, tmp); |
| 9313 | 9399 |
break; |
| ... | ... | |
| 9510 | 9596 |
|
| 9511 | 9597 |
switch (op) {
|
| 9512 | 9598 |
case 0: /* str */ |
| 9513 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9599 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9514 | 9600 |
break; |
| 9515 | 9601 |
case 1: /* strh */ |
| 9516 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 9602 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 9517 | 9603 |
break; |
| 9518 | 9604 |
case 2: /* strb */ |
| 9519 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 9605 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 9520 | 9606 |
break; |
| 9521 | 9607 |
case 3: /* ldrsb */ |
| 9522 |
tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
|
|
| 9608 |
gen_aa32_ld8s(tmp, addr, IS_USER(s));
|
|
| 9523 | 9609 |
break; |
| 9524 | 9610 |
case 4: /* ldr */ |
| 9525 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9611 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9526 | 9612 |
break; |
| 9527 | 9613 |
case 5: /* ldrh */ |
| 9528 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 9614 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 9529 | 9615 |
break; |
| 9530 | 9616 |
case 6: /* ldrb */ |
| 9531 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 9617 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 9532 | 9618 |
break; |
| 9533 | 9619 |
case 7: /* ldrsh */ |
| 9534 |
tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
|
|
| 9620 |
gen_aa32_ld16s(tmp, addr, IS_USER(s));
|
|
| 9535 | 9621 |
break; |
| 9536 | 9622 |
} |
| 9537 | 9623 |
if (op >= 3) { /* load */
|
| ... | ... | |
| 9553 | 9639 |
if (insn & (1 << 11)) {
|
| 9554 | 9640 |
/* load */ |
| 9555 | 9641 |
tmp = tcg_temp_new_i32(); |
| 9556 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9642 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9557 | 9643 |
store_reg(s, rd, tmp); |
| 9558 | 9644 |
} else {
|
| 9559 | 9645 |
/* store */ |
| 9560 | 9646 |
tmp = load_reg(s, rd); |
| 9561 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9647 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9562 | 9648 |
tcg_temp_free_i32(tmp); |
| 9563 | 9649 |
} |
| 9564 | 9650 |
tcg_temp_free_i32(addr); |
| ... | ... | |
| 9575 | 9661 |
if (insn & (1 << 11)) {
|
| 9576 | 9662 |
/* load */ |
| 9577 | 9663 |
tmp = tcg_temp_new_i32(); |
| 9578 |
tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
|
|
| 9664 |
gen_aa32_ld8u(tmp, addr, IS_USER(s));
|
|
| 9579 | 9665 |
store_reg(s, rd, tmp); |
| 9580 | 9666 |
} else {
|
| 9581 | 9667 |
/* store */ |
| 9582 | 9668 |
tmp = load_reg(s, rd); |
| 9583 |
tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
|
|
| 9669 |
gen_aa32_st8(tmp, addr, IS_USER(s));
|
|
| 9584 | 9670 |
tcg_temp_free_i32(tmp); |
| 9585 | 9671 |
} |
| 9586 | 9672 |
tcg_temp_free_i32(addr); |
| ... | ... | |
| 9597 | 9683 |
if (insn & (1 << 11)) {
|
| 9598 | 9684 |
/* load */ |
| 9599 | 9685 |
tmp = tcg_temp_new_i32(); |
| 9600 |
tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
|
|
| 9686 |
gen_aa32_ld16u(tmp, addr, IS_USER(s));
|
|
| 9601 | 9687 |
store_reg(s, rd, tmp); |
| 9602 | 9688 |
} else {
|
| 9603 | 9689 |
/* store */ |
| 9604 | 9690 |
tmp = load_reg(s, rd); |
| 9605 |
tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
|
|
| 9691 |
gen_aa32_st16(tmp, addr, IS_USER(s));
|
|
| 9606 | 9692 |
tcg_temp_free_i32(tmp); |
| 9607 | 9693 |
} |
| 9608 | 9694 |
tcg_temp_free_i32(addr); |
| ... | ... | |
| 9618 | 9704 |
if (insn & (1 << 11)) {
|
| 9619 | 9705 |
/* load */ |
| 9620 | 9706 |
tmp = tcg_temp_new_i32(); |
| 9621 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9707 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9622 | 9708 |
store_reg(s, rd, tmp); |
| 9623 | 9709 |
} else {
|
| 9624 | 9710 |
/* store */ |
| 9625 | 9711 |
tmp = load_reg(s, rd); |
| 9626 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9712 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9627 | 9713 |
tcg_temp_free_i32(tmp); |
| 9628 | 9714 |
} |
| 9629 | 9715 |
tcg_temp_free_i32(addr); |
| ... | ... | |
| 9691 | 9777 |
if (insn & (1 << 11)) {
|
| 9692 | 9778 |
/* pop */ |
| 9693 | 9779 |
tmp = tcg_temp_new_i32(); |
| 9694 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9780 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9695 | 9781 |
store_reg(s, i, tmp); |
| 9696 | 9782 |
} else {
|
| 9697 | 9783 |
/* push */ |
| 9698 | 9784 |
tmp = load_reg(s, i); |
| 9699 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9785 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9700 | 9786 |
tcg_temp_free_i32(tmp); |
| 9701 | 9787 |
} |
| 9702 | 9788 |
/* advance to the next address. */ |
| ... | ... | |
| 9708 | 9794 |
if (insn & (1 << 11)) {
|
| 9709 | 9795 |
/* pop pc */ |
| 9710 | 9796 |
tmp = tcg_temp_new_i32(); |
| 9711 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9797 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9712 | 9798 |
/* don't set the pc until the rest of the instruction |
| 9713 | 9799 |
has completed */ |
| 9714 | 9800 |
} else {
|
| 9715 | 9801 |
/* push lr */ |
| 9716 | 9802 |
tmp = load_reg(s, 14); |
| 9717 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9803 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9718 | 9804 |
tcg_temp_free_i32(tmp); |
| 9719 | 9805 |
} |
| 9720 | 9806 |
tcg_gen_addi_i32(addr, addr, 4); |
| ... | ... | |
| 9840 | 9926 |
if (insn & (1 << 11)) {
|
| 9841 | 9927 |
/* load */ |
| 9842 | 9928 |
tmp = tcg_temp_new_i32(); |
| 9843 |
tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
|
|
| 9929 |
gen_aa32_ld32u(tmp, addr, IS_USER(s));
|
|
| 9844 | 9930 |
if (i == rn) {
|
| 9845 | 9931 |
loaded_var = tmp; |
| 9846 | 9932 |
} else {
|
| ... | ... | |
| 9849 | 9935 |
} else {
|
| 9850 | 9936 |
/* store */ |
| 9851 | 9937 |
tmp = load_reg(s, i); |
| 9852 |
tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
|
|
| 9938 |
gen_aa32_st32(tmp, addr, IS_USER(s));
|
|
| 9853 | 9939 |
tcg_temp_free_i32(tmp); |
| 9854 | 9940 |
} |
| 9855 | 9941 |
/* advance to the next address */ |
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