root / hw / cirrus_vga.c @ 08406b03
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/*
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* QEMU Cirrus CLGD 54xx VGA Emulator.
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*
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* Copyright (c) 2004 Fabrice Bellard
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* Copyright (c) 2004 Makoto Suzuki (suzu)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* Reference: Finn Thogersons' VGADOC4b
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* available at http://home.worldonline.dk/~finth/
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "vga-pci.h" |
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#include "console.h" |
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#include "vga_int.h" |
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#include "loader.h" |
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/*
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* TODO:
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* - destination write mask support not complete (bits 5..7)
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* - optimize linear mappings
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* - optimize bitblt functions
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*/
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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#define VGA_RAM_SIZE (8192 * 1024) |
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/***************************************
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*
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* definitions
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*
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***************************************/
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// ID
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#define CIRRUS_ID_CLGD5422 (0x23<<2) |
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#define CIRRUS_ID_CLGD5426 (0x24<<2) |
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#define CIRRUS_ID_CLGD5424 (0x25<<2) |
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#define CIRRUS_ID_CLGD5428 (0x26<<2) |
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#define CIRRUS_ID_CLGD5430 (0x28<<2) |
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#define CIRRUS_ID_CLGD5434 (0x2A<<2) |
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#define CIRRUS_ID_CLGD5436 (0x2B<<2) |
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#define CIRRUS_ID_CLGD5446 (0x2E<<2) |
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA 0x00 |
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#define CIRRUS_SR7_BPP_SVGA 0x01 |
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#define CIRRUS_SR7_BPP_MASK 0x0e |
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#define CIRRUS_SR7_BPP_8 0x00 |
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
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#define CIRRUS_SR7_BPP_24 0x04 |
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#define CIRRUS_SR7_BPP_16 0x06 |
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#define CIRRUS_SR7_BPP_32 0x08 |
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#define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k 0x08 |
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#define CIRRUS_MEMSIZE_1M 0x10 |
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#define CIRRUS_MEMSIZE_2M 0x18 |
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW 0x01 |
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#define CIRRUS_CURSOR_HIDDENPEL 0x02 |
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#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST 0x10 |
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#define CIRRUS_BUSTYPE_PCI 0x20 |
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#define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
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#define CIRRUS_BUSTYPE_ISA 0x38 |
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#define CIRRUS_MMIO_ENABLE 0x04 |
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#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
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// control 0x0b
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#define CIRRUS_BANKING_DUAL 0x01 |
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#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS 0x01 |
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#define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
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#define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
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#define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
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#define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
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#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
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#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
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#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
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#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
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// control 0x31
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#define CIRRUS_BLT_BUSY 0x01 |
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#define CIRRUS_BLT_START 0x02 |
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#define CIRRUS_BLT_RESET 0x04 |
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#define CIRRUS_BLT_FIFOUSED 0x10 |
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#define CIRRUS_BLT_AUTOSTART 0x80 |
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// control 0x32
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#define CIRRUS_ROP_0 0x00 |
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#define CIRRUS_ROP_SRC_AND_DST 0x05 |
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#define CIRRUS_ROP_NOP 0x06 |
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#define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
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#define CIRRUS_ROP_NOTDST 0x0b |
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#define CIRRUS_ROP_SRC 0x0d |
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#define CIRRUS_ROP_1 0x0e |
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#define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
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#define CIRRUS_ROP_SRC_XOR_DST 0x59 |
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#define CIRRUS_ROP_SRC_OR_DST 0x6d |
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
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#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
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#define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
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#define CIRRUS_ROP_NOTSRC 0xd0 |
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#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
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#define CIRRUS_ROP_NOP_INDEX 2 |
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#define CIRRUS_ROP_SRC_INDEX 5 |
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
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#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
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#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
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#define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
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#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
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#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
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#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
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#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
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#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
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#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
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#define CIRRUS_MMIO_BLTMODE 0x18 // byte |
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#define CIRRUS_MMIO_BLTROP 0x1a // byte |
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#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
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#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
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#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
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#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
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#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
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#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
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#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
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#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
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#define CIRRUS_PNPMMIO_SIZE 0x1000 |
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#define BLTUNSAFE(s) \
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( \ |
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( /* check dst is within bounds */ \
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(s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ |
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+ ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ |
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(s)->vga.vram_size \ |
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) || \ |
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( /* check src is within bounds */ \
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(s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ |
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+ ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ |
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(s)->vga.vram_size \ |
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) \ |
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) |
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struct CirrusVGAState;
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typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, |
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uint8_t * dst, const uint8_t * src,
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int dstpitch, int srcpitch, |
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int bltwidth, int bltheight); |
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typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
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uint8_t *dst, int dst_pitch, int width, int height); |
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typedef struct CirrusVGAState { |
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VGACommonState vga; |
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MemoryRegion cirrus_linear_io; |
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MemoryRegion cirrus_linear_bitblt_io; |
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MemoryRegion cirrus_mmio_io; |
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MemoryRegion pci_bar; |
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bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ |
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MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
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MemoryRegion low_mem; /* always mapped, overridden by: */
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MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ |
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uint32_t cirrus_addr_mask; |
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uint32_t linear_mmio_mask; |
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uint8_t cirrus_shadow_gr0; |
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uint8_t cirrus_shadow_gr1; |
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uint8_t cirrus_hidden_dac_lockindex; |
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uint8_t cirrus_hidden_dac_data; |
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uint32_t cirrus_bank_base[2];
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uint32_t cirrus_bank_limit[2];
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uint8_t cirrus_hidden_palette[48];
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uint32_t hw_cursor_x; |
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uint32_t hw_cursor_y; |
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int cirrus_blt_pixelwidth;
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int cirrus_blt_width;
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int cirrus_blt_height;
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int cirrus_blt_dstpitch;
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int cirrus_blt_srcpitch;
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uint32_t cirrus_blt_fgcol; |
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uint32_t cirrus_blt_bgcol; |
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uint32_t cirrus_blt_dstaddr; |
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uint32_t cirrus_blt_srcaddr; |
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uint8_t cirrus_blt_mode; |
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uint8_t cirrus_blt_modeext; |
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cirrus_bitblt_rop_t cirrus_rop; |
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
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uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
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uint8_t *cirrus_srcptr; |
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uint8_t *cirrus_srcptr_end; |
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uint32_t cirrus_srccounter; |
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/* hwcursor display state */
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int last_hw_cursor_size;
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int last_hw_cursor_x;
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int last_hw_cursor_y;
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int last_hw_cursor_y_start;
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int last_hw_cursor_y_end;
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int real_vram_size; /* XXX: suppress that */ |
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int device_id;
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int bustype;
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} CirrusVGAState; |
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typedef struct PCICirrusVGAState { |
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PCIDevice dev; |
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CirrusVGAState cirrus_vga; |
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} PCICirrusVGAState; |
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typedef struct ISACirrusVGAState { |
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ISADevice dev; |
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CirrusVGAState cirrus_vga; |
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} ISACirrusVGAState; |
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static uint8_t rop_to_index[256]; |
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/***************************************
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*
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* prototypes.
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*
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***************************************/
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static void cirrus_bitblt_reset(CirrusVGAState *s); |
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static void cirrus_update_memory_access(CirrusVGAState *s); |
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/***************************************
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*
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* raster operations
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*
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***************************************/
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static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
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uint8_t *dst,const uint8_t *src,
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int dstpitch,int srcpitch, |
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int bltwidth,int bltheight) |
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{
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} |
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static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
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uint8_t *dst, |
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int dstpitch, int bltwidth,int bltheight) |
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{
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} |
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#define ROP_NAME 0 |
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#define ROP_FN(d, s) 0 |
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_and_dst
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#define ROP_FN(d, s) (s) & (d)
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_and_notdst
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#define ROP_FN(d, s) (s) & (~(d))
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME notdst
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#define ROP_FN(d, s) ~(d)
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src
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#define ROP_FN(d, s) s
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME 1 |
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#define ROP_FN(d, s) ~0 |
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME notsrc_and_dst
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#define ROP_FN(d, s) (~(s)) & (d)
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_xor_dst
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#define ROP_FN(d, s) (s) ^ (d)
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_or_dst
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#define ROP_FN(d, s) (s) | (d)
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME notsrc_or_notdst
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#define ROP_FN(d, s) (~(s)) | (~(d))
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_notxor_dst
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#define ROP_FN(d, s) ~((s) ^ (d))
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#include "cirrus_vga_rop.h" |
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#define ROP_NAME src_or_notdst
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#define ROP_FN(d, s) (s) | (~(d))
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#include "cirrus_vga_rop.h" |
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|
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#define ROP_NAME notsrc
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#define ROP_FN(d, s) (~(s))
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#include "cirrus_vga_rop.h" |
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|
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#define ROP_NAME notsrc_or_dst
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#define ROP_FN(d, s) (~(s)) | (d)
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#include "cirrus_vga_rop.h" |
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|
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#define ROP_NAME notsrc_and_notdst
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#define ROP_FN(d, s) (~(s)) & (~(d))
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#include "cirrus_vga_rop.h" |
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|
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static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { |
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cirrus_bitblt_rop_fwd_0, |
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cirrus_bitblt_rop_fwd_src_and_dst, |
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cirrus_bitblt_rop_nop, |
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cirrus_bitblt_rop_fwd_src_and_notdst, |
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cirrus_bitblt_rop_fwd_notdst, |
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cirrus_bitblt_rop_fwd_src, |
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cirrus_bitblt_rop_fwd_1, |
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cirrus_bitblt_rop_fwd_notsrc_and_dst, |
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cirrus_bitblt_rop_fwd_src_xor_dst, |
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cirrus_bitblt_rop_fwd_src_or_dst, |
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cirrus_bitblt_rop_fwd_notsrc_or_notdst, |
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cirrus_bitblt_rop_fwd_src_notxor_dst, |
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cirrus_bitblt_rop_fwd_src_or_notdst, |
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cirrus_bitblt_rop_fwd_notsrc, |
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cirrus_bitblt_rop_fwd_notsrc_or_dst, |
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cirrus_bitblt_rop_fwd_notsrc_and_notdst, |
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}; |
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|
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static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { |
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cirrus_bitblt_rop_bkwd_0, |
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cirrus_bitblt_rop_bkwd_src_and_dst, |
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cirrus_bitblt_rop_nop, |
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cirrus_bitblt_rop_bkwd_src_and_notdst, |
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cirrus_bitblt_rop_bkwd_notdst, |
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cirrus_bitblt_rop_bkwd_src, |
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cirrus_bitblt_rop_bkwd_1, |
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cirrus_bitblt_rop_bkwd_notsrc_and_dst, |
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cirrus_bitblt_rop_bkwd_src_xor_dst, |
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cirrus_bitblt_rop_bkwd_src_or_dst, |
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cirrus_bitblt_rop_bkwd_notsrc_or_notdst, |
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cirrus_bitblt_rop_bkwd_src_notxor_dst, |
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cirrus_bitblt_rop_bkwd_src_or_notdst, |
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cirrus_bitblt_rop_bkwd_notsrc, |
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cirrus_bitblt_rop_bkwd_notsrc_or_dst, |
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cirrus_bitblt_rop_bkwd_notsrc_and_notdst, |
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}; |
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|
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#define TRANSP_ROP(name) {\
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name ## _8,\ |
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name ## _16,\ |
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} |
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#define TRANSP_NOP(func) {\
|
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func,\ |
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func,\ |
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} |
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|
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static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { |
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TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), |
| 400 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), |
| 401 |
TRANSP_NOP(cirrus_bitblt_rop_nop), |
| 402 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), |
| 403 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), |
| 404 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), |
| 405 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), |
| 406 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), |
| 407 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), |
| 408 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), |
| 409 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), |
| 410 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), |
| 411 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), |
| 412 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), |
| 413 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), |
| 414 |
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), |
| 415 |
}; |
| 416 |
|
| 417 |
static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { |
| 418 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), |
| 419 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), |
| 420 |
TRANSP_NOP(cirrus_bitblt_rop_nop), |
| 421 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), |
| 422 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), |
| 423 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), |
| 424 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), |
| 425 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), |
| 426 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), |
| 427 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), |
| 428 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), |
| 429 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), |
| 430 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), |
| 431 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), |
| 432 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), |
| 433 |
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), |
| 434 |
}; |
| 435 |
|
| 436 |
#define ROP2(name) {\
|
| 437 |
name ## _8,\ |
| 438 |
name ## _16,\ |
| 439 |
name ## _24,\ |
| 440 |
name ## _32,\ |
| 441 |
} |
| 442 |
|
| 443 |
#define ROP_NOP2(func) {\
|
| 444 |
func,\ |
| 445 |
func,\ |
| 446 |
func,\ |
| 447 |
func,\ |
| 448 |
} |
| 449 |
|
| 450 |
static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
| 451 |
ROP2(cirrus_patternfill_0), |
| 452 |
ROP2(cirrus_patternfill_src_and_dst), |
| 453 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
| 454 |
ROP2(cirrus_patternfill_src_and_notdst), |
| 455 |
ROP2(cirrus_patternfill_notdst), |
| 456 |
ROP2(cirrus_patternfill_src), |
| 457 |
ROP2(cirrus_patternfill_1), |
| 458 |
ROP2(cirrus_patternfill_notsrc_and_dst), |
| 459 |
ROP2(cirrus_patternfill_src_xor_dst), |
| 460 |
ROP2(cirrus_patternfill_src_or_dst), |
| 461 |
ROP2(cirrus_patternfill_notsrc_or_notdst), |
| 462 |
ROP2(cirrus_patternfill_src_notxor_dst), |
| 463 |
ROP2(cirrus_patternfill_src_or_notdst), |
| 464 |
ROP2(cirrus_patternfill_notsrc), |
| 465 |
ROP2(cirrus_patternfill_notsrc_or_dst), |
| 466 |
ROP2(cirrus_patternfill_notsrc_and_notdst), |
| 467 |
}; |
| 468 |
|
| 469 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
| 470 |
ROP2(cirrus_colorexpand_transp_0), |
| 471 |
ROP2(cirrus_colorexpand_transp_src_and_dst), |
| 472 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
| 473 |
ROP2(cirrus_colorexpand_transp_src_and_notdst), |
| 474 |
ROP2(cirrus_colorexpand_transp_notdst), |
| 475 |
ROP2(cirrus_colorexpand_transp_src), |
| 476 |
ROP2(cirrus_colorexpand_transp_1), |
| 477 |
ROP2(cirrus_colorexpand_transp_notsrc_and_dst), |
| 478 |
ROP2(cirrus_colorexpand_transp_src_xor_dst), |
| 479 |
ROP2(cirrus_colorexpand_transp_src_or_dst), |
| 480 |
ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), |
| 481 |
ROP2(cirrus_colorexpand_transp_src_notxor_dst), |
| 482 |
ROP2(cirrus_colorexpand_transp_src_or_notdst), |
| 483 |
ROP2(cirrus_colorexpand_transp_notsrc), |
| 484 |
ROP2(cirrus_colorexpand_transp_notsrc_or_dst), |
| 485 |
ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
| 486 |
}; |
| 487 |
|
| 488 |
static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
| 489 |
ROP2(cirrus_colorexpand_0), |
| 490 |
ROP2(cirrus_colorexpand_src_and_dst), |
| 491 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
| 492 |
ROP2(cirrus_colorexpand_src_and_notdst), |
| 493 |
ROP2(cirrus_colorexpand_notdst), |
| 494 |
ROP2(cirrus_colorexpand_src), |
| 495 |
ROP2(cirrus_colorexpand_1), |
| 496 |
ROP2(cirrus_colorexpand_notsrc_and_dst), |
| 497 |
ROP2(cirrus_colorexpand_src_xor_dst), |
| 498 |
ROP2(cirrus_colorexpand_src_or_dst), |
| 499 |
ROP2(cirrus_colorexpand_notsrc_or_notdst), |
| 500 |
ROP2(cirrus_colorexpand_src_notxor_dst), |
| 501 |
ROP2(cirrus_colorexpand_src_or_notdst), |
| 502 |
ROP2(cirrus_colorexpand_notsrc), |
| 503 |
ROP2(cirrus_colorexpand_notsrc_or_dst), |
| 504 |
ROP2(cirrus_colorexpand_notsrc_and_notdst), |
| 505 |
}; |
| 506 |
|
| 507 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
| 508 |
ROP2(cirrus_colorexpand_pattern_transp_0), |
| 509 |
ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
| 510 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
| 511 |
ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
| 512 |
ROP2(cirrus_colorexpand_pattern_transp_notdst), |
| 513 |
ROP2(cirrus_colorexpand_pattern_transp_src), |
| 514 |
ROP2(cirrus_colorexpand_pattern_transp_1), |
| 515 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
| 516 |
ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
| 517 |
ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
| 518 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
| 519 |
ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
| 520 |
ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
| 521 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
| 522 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
| 523 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
| 524 |
}; |
| 525 |
|
| 526 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
| 527 |
ROP2(cirrus_colorexpand_pattern_0), |
| 528 |
ROP2(cirrus_colorexpand_pattern_src_and_dst), |
| 529 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
| 530 |
ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
| 531 |
ROP2(cirrus_colorexpand_pattern_notdst), |
| 532 |
ROP2(cirrus_colorexpand_pattern_src), |
| 533 |
ROP2(cirrus_colorexpand_pattern_1), |
| 534 |
ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
| 535 |
ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
| 536 |
ROP2(cirrus_colorexpand_pattern_src_or_dst), |
| 537 |
ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
| 538 |
ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
| 539 |
ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
| 540 |
ROP2(cirrus_colorexpand_pattern_notsrc), |
| 541 |
ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
| 542 |
ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
| 543 |
}; |
| 544 |
|
| 545 |
static const cirrus_fill_t cirrus_fill[16][4] = { |
| 546 |
ROP2(cirrus_fill_0), |
| 547 |
ROP2(cirrus_fill_src_and_dst), |
| 548 |
ROP_NOP2(cirrus_bitblt_fill_nop), |
| 549 |
ROP2(cirrus_fill_src_and_notdst), |
| 550 |
ROP2(cirrus_fill_notdst), |
| 551 |
ROP2(cirrus_fill_src), |
| 552 |
ROP2(cirrus_fill_1), |
| 553 |
ROP2(cirrus_fill_notsrc_and_dst), |
| 554 |
ROP2(cirrus_fill_src_xor_dst), |
| 555 |
ROP2(cirrus_fill_src_or_dst), |
| 556 |
ROP2(cirrus_fill_notsrc_or_notdst), |
| 557 |
ROP2(cirrus_fill_src_notxor_dst), |
| 558 |
ROP2(cirrus_fill_src_or_notdst), |
| 559 |
ROP2(cirrus_fill_notsrc), |
| 560 |
ROP2(cirrus_fill_notsrc_or_dst), |
| 561 |
ROP2(cirrus_fill_notsrc_and_notdst), |
| 562 |
}; |
| 563 |
|
| 564 |
static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) |
| 565 |
{
|
| 566 |
unsigned int color; |
| 567 |
switch (s->cirrus_blt_pixelwidth) {
|
| 568 |
case 1: |
| 569 |
s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; |
| 570 |
break;
|
| 571 |
case 2: |
| 572 |
color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); |
| 573 |
s->cirrus_blt_fgcol = le16_to_cpu(color); |
| 574 |
break;
|
| 575 |
case 3: |
| 576 |
s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
| 577 |
(s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); |
| 578 |
break;
|
| 579 |
default:
|
| 580 |
case 4: |
| 581 |
color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | |
| 582 |
(s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); |
| 583 |
s->cirrus_blt_fgcol = le32_to_cpu(color); |
| 584 |
break;
|
| 585 |
} |
| 586 |
} |
| 587 |
|
| 588 |
static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
| 589 |
{
|
| 590 |
unsigned int color; |
| 591 |
switch (s->cirrus_blt_pixelwidth) {
|
| 592 |
case 1: |
| 593 |
s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
| 594 |
break;
|
| 595 |
case 2: |
| 596 |
color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); |
| 597 |
s->cirrus_blt_bgcol = le16_to_cpu(color); |
| 598 |
break;
|
| 599 |
case 3: |
| 600 |
s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
| 601 |
(s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); |
| 602 |
break;
|
| 603 |
default:
|
| 604 |
case 4: |
| 605 |
color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | |
| 606 |
(s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); |
| 607 |
s->cirrus_blt_bgcol = le32_to_cpu(color); |
| 608 |
break;
|
| 609 |
} |
| 610 |
} |
| 611 |
|
| 612 |
static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
| 613 |
int off_pitch, int bytesperline, |
| 614 |
int lines)
|
| 615 |
{
|
| 616 |
int y;
|
| 617 |
int off_cur;
|
| 618 |
int off_cur_end;
|
| 619 |
|
| 620 |
for (y = 0; y < lines; y++) { |
| 621 |
off_cur = off_begin; |
| 622 |
off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; |
| 623 |
memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); |
| 624 |
off_begin += off_pitch; |
| 625 |
} |
| 626 |
} |
| 627 |
|
| 628 |
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
| 629 |
const uint8_t * src)
|
| 630 |
{
|
| 631 |
uint8_t *dst; |
| 632 |
|
| 633 |
dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); |
| 634 |
|
| 635 |
if (BLTUNSAFE(s))
|
| 636 |
return 0; |
| 637 |
|
| 638 |
(*s->cirrus_rop) (s, dst, src, |
| 639 |
s->cirrus_blt_dstpitch, 0,
|
| 640 |
s->cirrus_blt_width, s->cirrus_blt_height); |
| 641 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
| 642 |
s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
| 643 |
s->cirrus_blt_height); |
| 644 |
return 1; |
| 645 |
} |
| 646 |
|
| 647 |
/* fill */
|
| 648 |
|
| 649 |
static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
| 650 |
{
|
| 651 |
cirrus_fill_t rop_func; |
| 652 |
|
| 653 |
if (BLTUNSAFE(s))
|
| 654 |
return 0; |
| 655 |
rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 656 |
rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
| 657 |
s->cirrus_blt_dstpitch, |
| 658 |
s->cirrus_blt_width, s->cirrus_blt_height); |
| 659 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
| 660 |
s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
| 661 |
s->cirrus_blt_height); |
| 662 |
cirrus_bitblt_reset(s); |
| 663 |
return 1; |
| 664 |
} |
| 665 |
|
| 666 |
/***************************************
|
| 667 |
*
|
| 668 |
* bitblt (video-to-video)
|
| 669 |
*
|
| 670 |
***************************************/
|
| 671 |
|
| 672 |
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
| 673 |
{
|
| 674 |
return cirrus_bitblt_common_patterncopy(s,
|
| 675 |
s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
|
| 676 |
s->cirrus_addr_mask)); |
| 677 |
} |
| 678 |
|
| 679 |
static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) |
| 680 |
{
|
| 681 |
int sx = 0, sy = 0; |
| 682 |
int dx = 0, dy = 0; |
| 683 |
int depth = 0; |
| 684 |
int notify = 0; |
| 685 |
|
| 686 |
/* make sure to only copy if it's a plain copy ROP */
|
| 687 |
if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
|
| 688 |
*s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
|
| 689 |
|
| 690 |
int width, height;
|
| 691 |
|
| 692 |
depth = s->vga.get_bpp(&s->vga) / 8;
|
| 693 |
s->vga.get_resolution(&s->vga, &width, &height); |
| 694 |
|
| 695 |
/* extra x, y */
|
| 696 |
sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; |
| 697 |
sy = (src / ABS(s->cirrus_blt_srcpitch)); |
| 698 |
dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; |
| 699 |
dy = (dst / ABS(s->cirrus_blt_dstpitch)); |
| 700 |
|
| 701 |
/* normalize width */
|
| 702 |
w /= depth; |
| 703 |
|
| 704 |
/* if we're doing a backward copy, we have to adjust
|
| 705 |
our x/y to be the upper left corner (instead of the lower
|
| 706 |
right corner) */
|
| 707 |
if (s->cirrus_blt_dstpitch < 0) { |
| 708 |
sx -= (s->cirrus_blt_width / depth) - 1;
|
| 709 |
dx -= (s->cirrus_blt_width / depth) - 1;
|
| 710 |
sy -= s->cirrus_blt_height - 1;
|
| 711 |
dy -= s->cirrus_blt_height - 1;
|
| 712 |
} |
| 713 |
|
| 714 |
/* are we in the visible portion of memory? */
|
| 715 |
if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && |
| 716 |
(sx + w) <= width && (sy + h) <= height && |
| 717 |
(dx + w) <= width && (dy + h) <= height) {
|
| 718 |
notify = 1;
|
| 719 |
} |
| 720 |
} |
| 721 |
|
| 722 |
/* we have to flush all pending changes so that the copy
|
| 723 |
is generated at the appropriate moment in time */
|
| 724 |
if (notify)
|
| 725 |
vga_hw_update(); |
| 726 |
|
| 727 |
(*s->cirrus_rop) (s, s->vga.vram_ptr + |
| 728 |
(s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
| 729 |
s->vga.vram_ptr + |
| 730 |
(s->cirrus_blt_srcaddr & s->cirrus_addr_mask), |
| 731 |
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
| 732 |
s->cirrus_blt_width, s->cirrus_blt_height); |
| 733 |
|
| 734 |
if (notify)
|
| 735 |
qemu_console_copy(s->vga.ds, |
| 736 |
sx, sy, dx, dy, |
| 737 |
s->cirrus_blt_width / depth, |
| 738 |
s->cirrus_blt_height); |
| 739 |
|
| 740 |
/* we don't have to notify the display that this portion has
|
| 741 |
changed since qemu_console_copy implies this */
|
| 742 |
|
| 743 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
| 744 |
s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
| 745 |
s->cirrus_blt_height); |
| 746 |
} |
| 747 |
|
| 748 |
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
| 749 |
{
|
| 750 |
if (BLTUNSAFE(s))
|
| 751 |
return 0; |
| 752 |
|
| 753 |
cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, |
| 754 |
s->cirrus_blt_srcaddr - s->vga.start_addr, |
| 755 |
s->cirrus_blt_width, s->cirrus_blt_height); |
| 756 |
|
| 757 |
return 1; |
| 758 |
} |
| 759 |
|
| 760 |
/***************************************
|
| 761 |
*
|
| 762 |
* bitblt (cpu-to-video)
|
| 763 |
*
|
| 764 |
***************************************/
|
| 765 |
|
| 766 |
static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
| 767 |
{
|
| 768 |
int copy_count;
|
| 769 |
uint8_t *end_ptr; |
| 770 |
|
| 771 |
if (s->cirrus_srccounter > 0) { |
| 772 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
| 773 |
cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); |
| 774 |
the_end:
|
| 775 |
s->cirrus_srccounter = 0;
|
| 776 |
cirrus_bitblt_reset(s); |
| 777 |
} else {
|
| 778 |
/* at least one scan line */
|
| 779 |
do {
|
| 780 |
(*s->cirrus_rop)(s, s->vga.vram_ptr + |
| 781 |
(s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
| 782 |
s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); |
| 783 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
| 784 |
s->cirrus_blt_width, 1);
|
| 785 |
s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; |
| 786 |
s->cirrus_srccounter -= s->cirrus_blt_srcpitch; |
| 787 |
if (s->cirrus_srccounter <= 0) |
| 788 |
goto the_end;
|
| 789 |
/* more bytes than needed can be transferred because of
|
| 790 |
word alignment, so we keep them for the next line */
|
| 791 |
/* XXX: keep alignment to speed up transfer */
|
| 792 |
end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
| 793 |
copy_count = s->cirrus_srcptr_end - end_ptr; |
| 794 |
memmove(s->cirrus_bltbuf, end_ptr, copy_count); |
| 795 |
s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; |
| 796 |
s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
| 797 |
} while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
|
| 798 |
} |
| 799 |
} |
| 800 |
} |
| 801 |
|
| 802 |
/***************************************
|
| 803 |
*
|
| 804 |
* bitblt wrapper
|
| 805 |
*
|
| 806 |
***************************************/
|
| 807 |
|
| 808 |
static void cirrus_bitblt_reset(CirrusVGAState * s) |
| 809 |
{
|
| 810 |
int need_update;
|
| 811 |
|
| 812 |
s->vga.gr[0x31] &=
|
| 813 |
~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
| 814 |
need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
|
| 815 |
|| s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
|
| 816 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
| 817 |
s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
| 818 |
s->cirrus_srccounter = 0;
|
| 819 |
if (!need_update)
|
| 820 |
return;
|
| 821 |
cirrus_update_memory_access(s); |
| 822 |
} |
| 823 |
|
| 824 |
static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
| 825 |
{
|
| 826 |
int w;
|
| 827 |
|
| 828 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
| 829 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
| 830 |
s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
| 831 |
|
| 832 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
| 833 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
| 834 |
s->cirrus_blt_srcpitch = 8;
|
| 835 |
} else {
|
| 836 |
/* XXX: check for 24 bpp */
|
| 837 |
s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
| 838 |
} |
| 839 |
s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
| 840 |
} else {
|
| 841 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
| 842 |
w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
| 843 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
|
| 844 |
s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
| 845 |
else
|
| 846 |
s->cirrus_blt_srcpitch = ((w + 7) >> 3); |
| 847 |
} else {
|
| 848 |
/* always align input size to 32 bits */
|
| 849 |
s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; |
| 850 |
} |
| 851 |
s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
| 852 |
} |
| 853 |
s->cirrus_srcptr = s->cirrus_bltbuf; |
| 854 |
s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
| 855 |
cirrus_update_memory_access(s); |
| 856 |
return 1; |
| 857 |
} |
| 858 |
|
| 859 |
static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
| 860 |
{
|
| 861 |
/* XXX */
|
| 862 |
#ifdef DEBUG_BITBLT
|
| 863 |
printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
| 864 |
#endif
|
| 865 |
return 0; |
| 866 |
} |
| 867 |
|
| 868 |
static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
| 869 |
{
|
| 870 |
int ret;
|
| 871 |
|
| 872 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
| 873 |
ret = cirrus_bitblt_videotovideo_patterncopy(s); |
| 874 |
} else {
|
| 875 |
ret = cirrus_bitblt_videotovideo_copy(s); |
| 876 |
} |
| 877 |
if (ret)
|
| 878 |
cirrus_bitblt_reset(s); |
| 879 |
return ret;
|
| 880 |
} |
| 881 |
|
| 882 |
static void cirrus_bitblt_start(CirrusVGAState * s) |
| 883 |
{
|
| 884 |
uint8_t blt_rop; |
| 885 |
|
| 886 |
s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
|
| 887 |
|
| 888 |
s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; |
| 889 |
s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; |
| 890 |
s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); |
| 891 |
s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); |
| 892 |
s->cirrus_blt_dstaddr = |
| 893 |
(s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); |
| 894 |
s->cirrus_blt_srcaddr = |
| 895 |
(s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); |
| 896 |
s->cirrus_blt_mode = s->vga.gr[0x30];
|
| 897 |
s->cirrus_blt_modeext = s->vga.gr[0x33];
|
| 898 |
blt_rop = s->vga.gr[0x32];
|
| 899 |
|
| 900 |
#ifdef DEBUG_BITBLT
|
| 901 |
printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
|
| 902 |
blt_rop, |
| 903 |
s->cirrus_blt_mode, |
| 904 |
s->cirrus_blt_modeext, |
| 905 |
s->cirrus_blt_width, |
| 906 |
s->cirrus_blt_height, |
| 907 |
s->cirrus_blt_dstpitch, |
| 908 |
s->cirrus_blt_srcpitch, |
| 909 |
s->cirrus_blt_dstaddr, |
| 910 |
s->cirrus_blt_srcaddr, |
| 911 |
s->vga.gr[0x2f]);
|
| 912 |
#endif
|
| 913 |
|
| 914 |
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
| 915 |
case CIRRUS_BLTMODE_PIXELWIDTH8:
|
| 916 |
s->cirrus_blt_pixelwidth = 1;
|
| 917 |
break;
|
| 918 |
case CIRRUS_BLTMODE_PIXELWIDTH16:
|
| 919 |
s->cirrus_blt_pixelwidth = 2;
|
| 920 |
break;
|
| 921 |
case CIRRUS_BLTMODE_PIXELWIDTH24:
|
| 922 |
s->cirrus_blt_pixelwidth = 3;
|
| 923 |
break;
|
| 924 |
case CIRRUS_BLTMODE_PIXELWIDTH32:
|
| 925 |
s->cirrus_blt_pixelwidth = 4;
|
| 926 |
break;
|
| 927 |
default:
|
| 928 |
#ifdef DEBUG_BITBLT
|
| 929 |
printf("cirrus: bitblt - pixel width is unknown\n");
|
| 930 |
#endif
|
| 931 |
goto bitblt_ignore;
|
| 932 |
} |
| 933 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
| 934 |
|
| 935 |
if ((s->
|
| 936 |
cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
| 937 |
CIRRUS_BLTMODE_MEMSYSDEST)) |
| 938 |
== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
|
| 939 |
#ifdef DEBUG_BITBLT
|
| 940 |
printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
| 941 |
#endif
|
| 942 |
goto bitblt_ignore;
|
| 943 |
} |
| 944 |
|
| 945 |
if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
|
| 946 |
(s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
| 947 |
CIRRUS_BLTMODE_TRANSPARENTCOMP | |
| 948 |
CIRRUS_BLTMODE_PATTERNCOPY | |
| 949 |
CIRRUS_BLTMODE_COLOREXPAND)) == |
| 950 |
(CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
|
| 951 |
cirrus_bitblt_fgcol(s); |
| 952 |
cirrus_bitblt_solidfill(s, blt_rop); |
| 953 |
} else {
|
| 954 |
if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
|
| 955 |
CIRRUS_BLTMODE_PATTERNCOPY)) == |
| 956 |
CIRRUS_BLTMODE_COLOREXPAND) {
|
| 957 |
|
| 958 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
| 959 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
| 960 |
cirrus_bitblt_bgcol(s); |
| 961 |
else
|
| 962 |
cirrus_bitblt_fgcol(s); |
| 963 |
s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 964 |
} else {
|
| 965 |
cirrus_bitblt_fgcol(s); |
| 966 |
cirrus_bitblt_bgcol(s); |
| 967 |
s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 968 |
} |
| 969 |
} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
| 970 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
| 971 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
| 972 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
| 973 |
cirrus_bitblt_bgcol(s); |
| 974 |
else
|
| 975 |
cirrus_bitblt_fgcol(s); |
| 976 |
s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 977 |
} else {
|
| 978 |
cirrus_bitblt_fgcol(s); |
| 979 |
cirrus_bitblt_bgcol(s); |
| 980 |
s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 981 |
} |
| 982 |
} else {
|
| 983 |
s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 984 |
} |
| 985 |
} else {
|
| 986 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
| 987 |
if (s->cirrus_blt_pixelwidth > 2) { |
| 988 |
printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
|
| 989 |
goto bitblt_ignore;
|
| 990 |
} |
| 991 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
| 992 |
s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
| 993 |
s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
| 994 |
s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 995 |
} else {
|
| 996 |
s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
| 997 |
} |
| 998 |
} else {
|
| 999 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
| 1000 |
s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
| 1001 |
s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
| 1002 |
s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; |
| 1003 |
} else {
|
| 1004 |
s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; |
| 1005 |
} |
| 1006 |
} |
| 1007 |
} |
| 1008 |
// setup bitblt engine.
|
| 1009 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
| 1010 |
if (!cirrus_bitblt_cputovideo(s))
|
| 1011 |
goto bitblt_ignore;
|
| 1012 |
} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
| 1013 |
if (!cirrus_bitblt_videotocpu(s))
|
| 1014 |
goto bitblt_ignore;
|
| 1015 |
} else {
|
| 1016 |
if (!cirrus_bitblt_videotovideo(s))
|
| 1017 |
goto bitblt_ignore;
|
| 1018 |
} |
| 1019 |
} |
| 1020 |
return;
|
| 1021 |
bitblt_ignore:;
|
| 1022 |
cirrus_bitblt_reset(s); |
| 1023 |
} |
| 1024 |
|
| 1025 |
static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
| 1026 |
{
|
| 1027 |
unsigned old_value;
|
| 1028 |
|
| 1029 |
old_value = s->vga.gr[0x31];
|
| 1030 |
s->vga.gr[0x31] = reg_value;
|
| 1031 |
|
| 1032 |
if (((old_value & CIRRUS_BLT_RESET) != 0) && |
| 1033 |
((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
| 1034 |
cirrus_bitblt_reset(s); |
| 1035 |
} else if (((old_value & CIRRUS_BLT_START) == 0) && |
| 1036 |
((reg_value & CIRRUS_BLT_START) != 0)) {
|
| 1037 |
cirrus_bitblt_start(s); |
| 1038 |
} |
| 1039 |
} |
| 1040 |
|
| 1041 |
|
| 1042 |
/***************************************
|
| 1043 |
*
|
| 1044 |
* basic parameters
|
| 1045 |
*
|
| 1046 |
***************************************/
|
| 1047 |
|
| 1048 |
static void cirrus_get_offsets(VGACommonState *s1, |
| 1049 |
uint32_t *pline_offset, |
| 1050 |
uint32_t *pstart_addr, |
| 1051 |
uint32_t *pline_compare) |
| 1052 |
{
|
| 1053 |
CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
| 1054 |
uint32_t start_addr, line_offset, line_compare; |
| 1055 |
|
| 1056 |
line_offset = s->vga.cr[0x13]
|
| 1057 |
| ((s->vga.cr[0x1b] & 0x10) << 4); |
| 1058 |
line_offset <<= 3;
|
| 1059 |
*pline_offset = line_offset; |
| 1060 |
|
| 1061 |
start_addr = (s->vga.cr[0x0c] << 8) |
| 1062 |
| s->vga.cr[0x0d]
|
| 1063 |
| ((s->vga.cr[0x1b] & 0x01) << 16) |
| 1064 |
| ((s->vga.cr[0x1b] & 0x0c) << 15) |
| 1065 |
| ((s->vga.cr[0x1d] & 0x80) << 12); |
| 1066 |
*pstart_addr = start_addr; |
| 1067 |
|
| 1068 |
line_compare = s->vga.cr[0x18] |
|
| 1069 |
((s->vga.cr[0x07] & 0x10) << 4) | |
| 1070 |
((s->vga.cr[0x09] & 0x40) << 3); |
| 1071 |
*pline_compare = line_compare; |
| 1072 |
} |
| 1073 |
|
| 1074 |
static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
| 1075 |
{
|
| 1076 |
uint32_t ret = 16;
|
| 1077 |
|
| 1078 |
switch (s->cirrus_hidden_dac_data & 0xf) { |
| 1079 |
case 0: |
| 1080 |
ret = 15;
|
| 1081 |
break; /* Sierra HiColor */ |
| 1082 |
case 1: |
| 1083 |
ret = 16;
|
| 1084 |
break; /* XGA HiColor */ |
| 1085 |
default:
|
| 1086 |
#ifdef DEBUG_CIRRUS
|
| 1087 |
printf("cirrus: invalid DAC value %x in 16bpp\n",
|
| 1088 |
(s->cirrus_hidden_dac_data & 0xf));
|
| 1089 |
#endif
|
| 1090 |
ret = 15; /* XXX */ |
| 1091 |
break;
|
| 1092 |
} |
| 1093 |
return ret;
|
| 1094 |
} |
| 1095 |
|
| 1096 |
static int cirrus_get_bpp(VGACommonState *s1) |
| 1097 |
{
|
| 1098 |
CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
| 1099 |
uint32_t ret = 8;
|
| 1100 |
|
| 1101 |
if ((s->vga.sr[0x07] & 0x01) != 0) { |
| 1102 |
/* Cirrus SVGA */
|
| 1103 |
switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
| 1104 |
case CIRRUS_SR7_BPP_8:
|
| 1105 |
ret = 8;
|
| 1106 |
break;
|
| 1107 |
case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
| 1108 |
ret = cirrus_get_bpp16_depth(s); |
| 1109 |
break;
|
| 1110 |
case CIRRUS_SR7_BPP_24:
|
| 1111 |
ret = 24;
|
| 1112 |
break;
|
| 1113 |
case CIRRUS_SR7_BPP_16:
|
| 1114 |
ret = cirrus_get_bpp16_depth(s); |
| 1115 |
break;
|
| 1116 |
case CIRRUS_SR7_BPP_32:
|
| 1117 |
ret = 32;
|
| 1118 |
break;
|
| 1119 |
default:
|
| 1120 |
#ifdef DEBUG_CIRRUS
|
| 1121 |
printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); |
| 1122 |
#endif
|
| 1123 |
ret = 8;
|
| 1124 |
break;
|
| 1125 |
} |
| 1126 |
} else {
|
| 1127 |
/* VGA */
|
| 1128 |
ret = 0;
|
| 1129 |
} |
| 1130 |
|
| 1131 |
return ret;
|
| 1132 |
} |
| 1133 |
|
| 1134 |
static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
| 1135 |
{
|
| 1136 |
int width, height;
|
| 1137 |
|
| 1138 |
width = (s->cr[0x01] + 1) * 8; |
| 1139 |
height = s->cr[0x12] |
|
| 1140 |
((s->cr[0x07] & 0x02) << 7) | |
| 1141 |
((s->cr[0x07] & 0x40) << 3); |
| 1142 |
height = (height + 1);
|
| 1143 |
/* interlace support */
|
| 1144 |
if (s->cr[0x1a] & 0x01) |
| 1145 |
height = height * 2;
|
| 1146 |
*pwidth = width; |
| 1147 |
*pheight = height; |
| 1148 |
} |
| 1149 |
|
| 1150 |
/***************************************
|
| 1151 |
*
|
| 1152 |
* bank memory
|
| 1153 |
*
|
| 1154 |
***************************************/
|
| 1155 |
|
| 1156 |
static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
| 1157 |
{
|
| 1158 |
unsigned offset;
|
| 1159 |
unsigned limit;
|
| 1160 |
|
| 1161 |
if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ |
| 1162 |
offset = s->vga.gr[0x09 + bank_index];
|
| 1163 |
else /* single bank */ |
| 1164 |
offset = s->vga.gr[0x09];
|
| 1165 |
|
| 1166 |
if ((s->vga.gr[0x0b] & 0x20) != 0) |
| 1167 |
offset <<= 14;
|
| 1168 |
else
|
| 1169 |
offset <<= 12;
|
| 1170 |
|
| 1171 |
if (s->real_vram_size <= offset)
|
| 1172 |
limit = 0;
|
| 1173 |
else
|
| 1174 |
limit = s->real_vram_size - offset; |
| 1175 |
|
| 1176 |
if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
| 1177 |
if (limit > 0x8000) { |
| 1178 |
offset += 0x8000;
|
| 1179 |
limit -= 0x8000;
|
| 1180 |
} else {
|
| 1181 |
limit = 0;
|
| 1182 |
} |
| 1183 |
} |
| 1184 |
|
| 1185 |
if (limit > 0) { |
| 1186 |
s->cirrus_bank_base[bank_index] = offset; |
| 1187 |
s->cirrus_bank_limit[bank_index] = limit; |
| 1188 |
} else {
|
| 1189 |
s->cirrus_bank_base[bank_index] = 0;
|
| 1190 |
s->cirrus_bank_limit[bank_index] = 0;
|
| 1191 |
} |
| 1192 |
} |
| 1193 |
|
| 1194 |
/***************************************
|
| 1195 |
*
|
| 1196 |
* I/O access between 0x3c4-0x3c5
|
| 1197 |
*
|
| 1198 |
***************************************/
|
| 1199 |
|
| 1200 |
static int cirrus_vga_read_sr(CirrusVGAState * s) |
| 1201 |
{
|
| 1202 |
switch (s->vga.sr_index) {
|
| 1203 |
case 0x00: // Standard VGA |
| 1204 |
case 0x01: // Standard VGA |
| 1205 |
case 0x02: // Standard VGA |
| 1206 |
case 0x03: // Standard VGA |
| 1207 |
case 0x04: // Standard VGA |
| 1208 |
return s->vga.sr[s->vga.sr_index];
|
| 1209 |
case 0x06: // Unlock Cirrus extensions |
| 1210 |
return s->vga.sr[s->vga.sr_index];
|
| 1211 |
case 0x10: |
| 1212 |
case 0x30: |
| 1213 |
case 0x50: |
| 1214 |
case 0x70: // Graphics Cursor X |
| 1215 |
case 0x90: |
| 1216 |
case 0xb0: |
| 1217 |
case 0xd0: |
| 1218 |
case 0xf0: // Graphics Cursor X |
| 1219 |
return s->vga.sr[0x10]; |
| 1220 |
case 0x11: |
| 1221 |
case 0x31: |
| 1222 |
case 0x51: |
| 1223 |
case 0x71: // Graphics Cursor Y |
| 1224 |
case 0x91: |
| 1225 |
case 0xb1: |
| 1226 |
case 0xd1: |
| 1227 |
case 0xf1: // Graphics Cursor Y |
| 1228 |
return s->vga.sr[0x11]; |
| 1229 |
case 0x05: // ??? |
| 1230 |
case 0x07: // Extended Sequencer Mode |
| 1231 |
case 0x08: // EEPROM Control |
| 1232 |
case 0x09: // Scratch Register 0 |
| 1233 |
case 0x0a: // Scratch Register 1 |
| 1234 |
case 0x0b: // VCLK 0 |
| 1235 |
case 0x0c: // VCLK 1 |
| 1236 |
case 0x0d: // VCLK 2 |
| 1237 |
case 0x0e: // VCLK 3 |
| 1238 |
case 0x0f: // DRAM Control |
| 1239 |
case 0x12: // Graphics Cursor Attribute |
| 1240 |
case 0x13: // Graphics Cursor Pattern Address |
| 1241 |
case 0x14: // Scratch Register 2 |
| 1242 |
case 0x15: // Scratch Register 3 |
| 1243 |
case 0x16: // Performance Tuning Register |
| 1244 |
case 0x17: // Configuration Readback and Extended Control |
| 1245 |
case 0x18: // Signature Generator Control |
| 1246 |
case 0x19: // Signal Generator Result |
| 1247 |
case 0x1a: // Signal Generator Result |
| 1248 |
case 0x1b: // VCLK 0 Denominator & Post |
| 1249 |
case 0x1c: // VCLK 1 Denominator & Post |
| 1250 |
case 0x1d: // VCLK 2 Denominator & Post |
| 1251 |
case 0x1e: // VCLK 3 Denominator & Post |
| 1252 |
case 0x1f: // BIOS Write Enable and MCLK select |
| 1253 |
#ifdef DEBUG_CIRRUS
|
| 1254 |
printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
|
| 1255 |
#endif
|
| 1256 |
return s->vga.sr[s->vga.sr_index];
|
| 1257 |
default:
|
| 1258 |
#ifdef DEBUG_CIRRUS
|
| 1259 |
printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
|
| 1260 |
#endif
|
| 1261 |
return 0xff; |
| 1262 |
break;
|
| 1263 |
} |
| 1264 |
} |
| 1265 |
|
| 1266 |
static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
| 1267 |
{
|
| 1268 |
switch (s->vga.sr_index) {
|
| 1269 |
case 0x00: // Standard VGA |
| 1270 |
case 0x01: // Standard VGA |
| 1271 |
case 0x02: // Standard VGA |
| 1272 |
case 0x03: // Standard VGA |
| 1273 |
case 0x04: // Standard VGA |
| 1274 |
s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
| 1275 |
if (s->vga.sr_index == 1) |
| 1276 |
s->vga.update_retrace_info(&s->vga); |
| 1277 |
break;
|
| 1278 |
case 0x06: // Unlock Cirrus extensions |
| 1279 |
val &= 0x17;
|
| 1280 |
if (val == 0x12) { |
| 1281 |
s->vga.sr[s->vga.sr_index] = 0x12;
|
| 1282 |
} else {
|
| 1283 |
s->vga.sr[s->vga.sr_index] = 0x0f;
|
| 1284 |
} |
| 1285 |
break;
|
| 1286 |
case 0x10: |
| 1287 |
case 0x30: |
| 1288 |
case 0x50: |
| 1289 |
case 0x70: // Graphics Cursor X |
| 1290 |
case 0x90: |
| 1291 |
case 0xb0: |
| 1292 |
case 0xd0: |
| 1293 |
case 0xf0: // Graphics Cursor X |
| 1294 |
s->vga.sr[0x10] = val;
|
| 1295 |
s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); |
| 1296 |
break;
|
| 1297 |
case 0x11: |
| 1298 |
case 0x31: |
| 1299 |
case 0x51: |
| 1300 |
case 0x71: // Graphics Cursor Y |
| 1301 |
case 0x91: |
| 1302 |
case 0xb1: |
| 1303 |
case 0xd1: |
| 1304 |
case 0xf1: // Graphics Cursor Y |
| 1305 |
s->vga.sr[0x11] = val;
|
| 1306 |
s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); |
| 1307 |
break;
|
| 1308 |
case 0x07: // Extended Sequencer Mode |
| 1309 |
cirrus_update_memory_access(s); |
| 1310 |
case 0x08: // EEPROM Control |
| 1311 |
case 0x09: // Scratch Register 0 |
| 1312 |
case 0x0a: // Scratch Register 1 |
| 1313 |
case 0x0b: // VCLK 0 |
| 1314 |
case 0x0c: // VCLK 1 |
| 1315 |
case 0x0d: // VCLK 2 |
| 1316 |
case 0x0e: // VCLK 3 |
| 1317 |
case 0x0f: // DRAM Control |
| 1318 |
case 0x12: // Graphics Cursor Attribute |
| 1319 |
case 0x13: // Graphics Cursor Pattern Address |
| 1320 |
case 0x14: // Scratch Register 2 |
| 1321 |
case 0x15: // Scratch Register 3 |
| 1322 |
case 0x16: // Performance Tuning Register |
| 1323 |
case 0x18: // Signature Generator Control |
| 1324 |
case 0x19: // Signature Generator Result |
| 1325 |
case 0x1a: // Signature Generator Result |
| 1326 |
case 0x1b: // VCLK 0 Denominator & Post |
| 1327 |
case 0x1c: // VCLK 1 Denominator & Post |
| 1328 |
case 0x1d: // VCLK 2 Denominator & Post |
| 1329 |
case 0x1e: // VCLK 3 Denominator & Post |
| 1330 |
case 0x1f: // BIOS Write Enable and MCLK select |
| 1331 |
s->vga.sr[s->vga.sr_index] = val; |
| 1332 |
#ifdef DEBUG_CIRRUS
|
| 1333 |
printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
| 1334 |
s->vga.sr_index, val); |
| 1335 |
#endif
|
| 1336 |
break;
|
| 1337 |
case 0x17: // Configuration Readback and Extended Control |
| 1338 |
s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
|
| 1339 |
| (val & 0xc7);
|
| 1340 |
cirrus_update_memory_access(s); |
| 1341 |
break;
|
| 1342 |
default:
|
| 1343 |
#ifdef DEBUG_CIRRUS
|
| 1344 |
printf("cirrus: outport sr_index %02x, sr_value %02x\n",
|
| 1345 |
s->vga.sr_index, val); |
| 1346 |
#endif
|
| 1347 |
break;
|
| 1348 |
} |
| 1349 |
} |
| 1350 |
|
| 1351 |
/***************************************
|
| 1352 |
*
|
| 1353 |
* I/O access at 0x3c6
|
| 1354 |
*
|
| 1355 |
***************************************/
|
| 1356 |
|
| 1357 |
static int cirrus_read_hidden_dac(CirrusVGAState * s) |
| 1358 |
{
|
| 1359 |
if (++s->cirrus_hidden_dac_lockindex == 5) { |
| 1360 |
s->cirrus_hidden_dac_lockindex = 0;
|
| 1361 |
return s->cirrus_hidden_dac_data;
|
| 1362 |
} |
| 1363 |
return 0xff; |
| 1364 |
} |
| 1365 |
|
| 1366 |
static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
| 1367 |
{
|
| 1368 |
if (s->cirrus_hidden_dac_lockindex == 4) { |
| 1369 |
s->cirrus_hidden_dac_data = reg_value; |
| 1370 |
#if defined(DEBUG_CIRRUS)
|
| 1371 |
printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
| 1372 |
#endif
|
| 1373 |
} |
| 1374 |
s->cirrus_hidden_dac_lockindex = 0;
|
| 1375 |
} |
| 1376 |
|
| 1377 |
/***************************************
|
| 1378 |
*
|
| 1379 |
* I/O access at 0x3c9
|
| 1380 |
*
|
| 1381 |
***************************************/
|
| 1382 |
|
| 1383 |
static int cirrus_vga_read_palette(CirrusVGAState * s) |
| 1384 |
{
|
| 1385 |
int val;
|
| 1386 |
|
| 1387 |
if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
| 1388 |
val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + |
| 1389 |
s->vga.dac_sub_index]; |
| 1390 |
} else {
|
| 1391 |
val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
|
| 1392 |
} |
| 1393 |
if (++s->vga.dac_sub_index == 3) { |
| 1394 |
s->vga.dac_sub_index = 0;
|
| 1395 |
s->vga.dac_read_index++; |
| 1396 |
} |
| 1397 |
return val;
|
| 1398 |
} |
| 1399 |
|
| 1400 |
static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) |
| 1401 |
{
|
| 1402 |
s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; |
| 1403 |
if (++s->vga.dac_sub_index == 3) { |
| 1404 |
if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
| 1405 |
memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], |
| 1406 |
s->vga.dac_cache, 3);
|
| 1407 |
} else {
|
| 1408 |
memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); |
| 1409 |
} |
| 1410 |
/* XXX update cursor */
|
| 1411 |
s->vga.dac_sub_index = 0;
|
| 1412 |
s->vga.dac_write_index++; |
| 1413 |
} |
| 1414 |
} |
| 1415 |
|
| 1416 |
/***************************************
|
| 1417 |
*
|
| 1418 |
* I/O access between 0x3ce-0x3cf
|
| 1419 |
*
|
| 1420 |
***************************************/
|
| 1421 |
|
| 1422 |
static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) |
| 1423 |
{
|
| 1424 |
switch (reg_index) {
|
| 1425 |
case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
| 1426 |
return s->cirrus_shadow_gr0;
|
| 1427 |
case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
| 1428 |
return s->cirrus_shadow_gr1;
|
| 1429 |
case 0x02: // Standard VGA |
| 1430 |
case 0x03: // Standard VGA |
| 1431 |
case 0x04: // Standard VGA |
| 1432 |
case 0x06: // Standard VGA |
| 1433 |
case 0x07: // Standard VGA |
| 1434 |
case 0x08: // Standard VGA |
| 1435 |
return s->vga.gr[s->vga.gr_index];
|
| 1436 |
case 0x05: // Standard VGA, Cirrus extended mode |
| 1437 |
default:
|
| 1438 |
break;
|
| 1439 |
} |
| 1440 |
|
| 1441 |
if (reg_index < 0x3a) { |
| 1442 |
return s->vga.gr[reg_index];
|
| 1443 |
} else {
|
| 1444 |
#ifdef DEBUG_CIRRUS
|
| 1445 |
printf("cirrus: inport gr_index %02x\n", reg_index);
|
| 1446 |
#endif
|
| 1447 |
return 0xff; |
| 1448 |
} |
| 1449 |
} |
| 1450 |
|
| 1451 |
static void |
| 1452 |
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
| 1453 |
{
|
| 1454 |
#if defined(DEBUG_BITBLT) && 0 |
| 1455 |
printf("gr%02x: %02x\n", reg_index, reg_value);
|
| 1456 |
#endif
|
| 1457 |
switch (reg_index) {
|
| 1458 |
case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
| 1459 |
s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
| 1460 |
s->cirrus_shadow_gr0 = reg_value; |
| 1461 |
break;
|
| 1462 |
case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
| 1463 |
s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
| 1464 |
s->cirrus_shadow_gr1 = reg_value; |
| 1465 |
break;
|
| 1466 |
case 0x02: // Standard VGA |
| 1467 |
case 0x03: // Standard VGA |
| 1468 |
case 0x04: // Standard VGA |
| 1469 |
case 0x06: // Standard VGA |
| 1470 |
case 0x07: // Standard VGA |
| 1471 |
case 0x08: // Standard VGA |
| 1472 |
s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
| 1473 |
break;
|
| 1474 |
case 0x05: // Standard VGA, Cirrus extended mode |
| 1475 |
s->vga.gr[reg_index] = reg_value & 0x7f;
|
| 1476 |
cirrus_update_memory_access(s); |
| 1477 |
break;
|
| 1478 |
case 0x09: // bank offset #0 |
| 1479 |
case 0x0A: // bank offset #1 |
| 1480 |
s->vga.gr[reg_index] = reg_value; |
| 1481 |
cirrus_update_bank_ptr(s, 0);
|
| 1482 |
cirrus_update_bank_ptr(s, 1);
|
| 1483 |
cirrus_update_memory_access(s); |
| 1484 |
break;
|
| 1485 |
case 0x0B: |
| 1486 |
s->vga.gr[reg_index] = reg_value; |
| 1487 |
cirrus_update_bank_ptr(s, 0);
|
| 1488 |
cirrus_update_bank_ptr(s, 1);
|
| 1489 |
cirrus_update_memory_access(s); |
| 1490 |
break;
|
| 1491 |
case 0x10: // BGCOLOR 0x0000ff00 |
| 1492 |
case 0x11: // FGCOLOR 0x0000ff00 |
| 1493 |
case 0x12: // BGCOLOR 0x00ff0000 |
| 1494 |
case 0x13: // FGCOLOR 0x00ff0000 |
| 1495 |
case 0x14: // BGCOLOR 0xff000000 |
| 1496 |
case 0x15: // FGCOLOR 0xff000000 |
| 1497 |
case 0x20: // BLT WIDTH 0x0000ff |
| 1498 |
case 0x22: // BLT HEIGHT 0x0000ff |
| 1499 |
case 0x24: // BLT DEST PITCH 0x0000ff |
| 1500 |
case 0x26: // BLT SRC PITCH 0x0000ff |
| 1501 |
case 0x28: // BLT DEST ADDR 0x0000ff |
| 1502 |
case 0x29: // BLT DEST ADDR 0x00ff00 |
| 1503 |
case 0x2c: // BLT SRC ADDR 0x0000ff |
| 1504 |
case 0x2d: // BLT SRC ADDR 0x00ff00 |
| 1505 |
case 0x2f: // BLT WRITEMASK |
| 1506 |
case 0x30: // BLT MODE |
| 1507 |
case 0x32: // RASTER OP |
| 1508 |
case 0x33: // BLT MODEEXT |
| 1509 |
case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
| 1510 |
case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
| 1511 |
case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
| 1512 |
case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
| 1513 |
s->vga.gr[reg_index] = reg_value; |
| 1514 |
break;
|
| 1515 |
case 0x21: // BLT WIDTH 0x001f00 |
| 1516 |
case 0x23: // BLT HEIGHT 0x001f00 |
| 1517 |
case 0x25: // BLT DEST PITCH 0x001f00 |
| 1518 |
case 0x27: // BLT SRC PITCH 0x001f00 |
| 1519 |
s->vga.gr[reg_index] = reg_value & 0x1f;
|
| 1520 |
break;
|
| 1521 |
case 0x2a: // BLT DEST ADDR 0x3f0000 |
| 1522 |
s->vga.gr[reg_index] = reg_value & 0x3f;
|
| 1523 |
/* if auto start mode, starts bit blt now */
|
| 1524 |
if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
| 1525 |
cirrus_bitblt_start(s); |
| 1526 |
} |
| 1527 |
break;
|
| 1528 |
case 0x2e: // BLT SRC ADDR 0x3f0000 |
| 1529 |
s->vga.gr[reg_index] = reg_value & 0x3f;
|
| 1530 |
break;
|
| 1531 |
case 0x31: // BLT STATUS/START |
| 1532 |
cirrus_write_bitblt(s, reg_value); |
| 1533 |
break;
|
| 1534 |
default:
|
| 1535 |
#ifdef DEBUG_CIRRUS
|
| 1536 |
printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
| 1537 |
reg_value); |
| 1538 |
#endif
|
| 1539 |
break;
|
| 1540 |
} |
| 1541 |
} |
| 1542 |
|
| 1543 |
/***************************************
|
| 1544 |
*
|
| 1545 |
* I/O access between 0x3d4-0x3d5
|
| 1546 |
*
|
| 1547 |
***************************************/
|
| 1548 |
|
| 1549 |
static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) |
| 1550 |
{
|
| 1551 |
switch (reg_index) {
|
| 1552 |
case 0x00: // Standard VGA |
| 1553 |
case 0x01: // Standard VGA |
| 1554 |
case 0x02: // Standard VGA |
| 1555 |
case 0x03: // Standard VGA |
| 1556 |
case 0x04: // Standard VGA |
| 1557 |
case 0x05: // Standard VGA |
| 1558 |
case 0x06: // Standard VGA |
| 1559 |
case 0x07: // Standard VGA |
| 1560 |
case 0x08: // Standard VGA |
| 1561 |
case 0x09: // Standard VGA |
| 1562 |
case 0x0a: // Standard VGA |
| 1563 |
case 0x0b: // Standard VGA |
| 1564 |
case 0x0c: // Standard VGA |
| 1565 |
case 0x0d: // Standard VGA |
| 1566 |
case 0x0e: // Standard VGA |
| 1567 |
case 0x0f: // Standard VGA |
| 1568 |
case 0x10: // Standard VGA |
| 1569 |
case 0x11: // Standard VGA |
| 1570 |
case 0x12: // Standard VGA |
| 1571 |
case 0x13: // Standard VGA |
| 1572 |
case 0x14: // Standard VGA |
| 1573 |
case 0x15: // Standard VGA |
| 1574 |
case 0x16: // Standard VGA |
| 1575 |
case 0x17: // Standard VGA |
| 1576 |
case 0x18: // Standard VGA |
| 1577 |
return s->vga.cr[s->vga.cr_index];
|
| 1578 |
case 0x24: // Attribute Controller Toggle Readback (R) |
| 1579 |
return (s->vga.ar_flip_flop << 7); |
| 1580 |
case 0x19: // Interlace End |
| 1581 |
case 0x1a: // Miscellaneous Control |
| 1582 |
case 0x1b: // Extended Display Control |
| 1583 |
case 0x1c: // Sync Adjust and Genlock |
| 1584 |
case 0x1d: // Overlay Extended Control |
| 1585 |
case 0x22: // Graphics Data Latches Readback (R) |
| 1586 |
case 0x25: // Part Status |
| 1587 |
case 0x27: // Part ID (R) |
| 1588 |
return s->vga.cr[s->vga.cr_index];
|
| 1589 |
case 0x26: // Attribute Controller Index Readback (R) |
| 1590 |
return s->vga.ar_index & 0x3f; |
| 1591 |
break;
|
| 1592 |
default:
|
| 1593 |
#ifdef DEBUG_CIRRUS
|
| 1594 |
printf("cirrus: inport cr_index %02x\n", reg_index);
|
| 1595 |
#endif
|
| 1596 |
return 0xff; |
| 1597 |
} |
| 1598 |
} |
| 1599 |
|
| 1600 |
static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) |
| 1601 |
{
|
| 1602 |
switch (s->vga.cr_index) {
|
| 1603 |
case 0x00: // Standard VGA |
| 1604 |
case 0x01: // Standard VGA |
| 1605 |
case 0x02: // Standard VGA |
| 1606 |
case 0x03: // Standard VGA |
| 1607 |
case 0x04: // Standard VGA |
| 1608 |
case 0x05: // Standard VGA |
| 1609 |
case 0x06: // Standard VGA |
| 1610 |
case 0x07: // Standard VGA |
| 1611 |
case 0x08: // Standard VGA |
| 1612 |
case 0x09: // Standard VGA |
| 1613 |
case 0x0a: // Standard VGA |
| 1614 |
case 0x0b: // Standard VGA |
| 1615 |
case 0x0c: // Standard VGA |
| 1616 |
case 0x0d: // Standard VGA |
| 1617 |
case 0x0e: // Standard VGA |
| 1618 |
case 0x0f: // Standard VGA |
| 1619 |
case 0x10: // Standard VGA |
| 1620 |
case 0x11: // Standard VGA |
| 1621 |
case 0x12: // Standard VGA |
| 1622 |
case 0x13: // Standard VGA |
| 1623 |
case 0x14: // Standard VGA |
| 1624 |
case 0x15: // Standard VGA |
| 1625 |
case 0x16: // Standard VGA |
| 1626 |
case 0x17: // Standard VGA |
| 1627 |
case 0x18: // Standard VGA |
| 1628 |
/* handle CR0-7 protection */
|
| 1629 |
if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { |
| 1630 |
/* can always write bit 4 of CR7 */
|
| 1631 |
if (s->vga.cr_index == 7) |
| 1632 |
s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); |
| 1633 |
return;
|
| 1634 |
} |
| 1635 |
s->vga.cr[s->vga.cr_index] = reg_value; |
| 1636 |
switch(s->vga.cr_index) {
|
| 1637 |
case 0x00: |
| 1638 |
case 0x04: |
| 1639 |
case 0x05: |
| 1640 |
case 0x06: |
| 1641 |
case 0x07: |
| 1642 |
case 0x11: |
| 1643 |
case 0x17: |
| 1644 |
s->vga.update_retrace_info(&s->vga); |
| 1645 |
break;
|
| 1646 |
} |
| 1647 |
break;
|
| 1648 |
case 0x19: // Interlace End |
| 1649 |
case 0x1a: // Miscellaneous Control |
| 1650 |
case 0x1b: // Extended Display Control |
| 1651 |
case 0x1c: // Sync Adjust and Genlock |
| 1652 |
case 0x1d: // Overlay Extended Control |
| 1653 |
s->vga.cr[s->vga.cr_index] = reg_value; |
| 1654 |
#ifdef DEBUG_CIRRUS
|
| 1655 |
printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
| 1656 |
s->vga.cr_index, reg_value); |
| 1657 |
#endif
|
| 1658 |
break;
|
| 1659 |
case 0x22: // Graphics Data Latches Readback (R) |
| 1660 |
case 0x24: // Attribute Controller Toggle Readback (R) |
| 1661 |
case 0x26: // Attribute Controller Index Readback (R) |
| 1662 |
case 0x27: // Part ID (R) |
| 1663 |
break;
|
| 1664 |
case 0x25: // Part Status |
| 1665 |
default:
|
| 1666 |
#ifdef DEBUG_CIRRUS
|
| 1667 |
printf("cirrus: outport cr_index %02x, cr_value %02x\n",
|
| 1668 |
s->vga.cr_index, reg_value); |
| 1669 |
#endif
|
| 1670 |
break;
|
| 1671 |
} |
| 1672 |
} |
| 1673 |
|
| 1674 |
/***************************************
|
| 1675 |
*
|
| 1676 |
* memory-mapped I/O (bitblt)
|
| 1677 |
*
|
| 1678 |
***************************************/
|
| 1679 |
|
| 1680 |
static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
| 1681 |
{
|
| 1682 |
int value = 0xff; |
| 1683 |
|
| 1684 |
switch (address) {
|
| 1685 |
case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
| 1686 |
value = cirrus_vga_read_gr(s, 0x00);
|
| 1687 |
break;
|
| 1688 |
case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
| 1689 |
value = cirrus_vga_read_gr(s, 0x10);
|
| 1690 |
break;
|
| 1691 |
case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
| 1692 |
value = cirrus_vga_read_gr(s, 0x12);
|
| 1693 |
break;
|
| 1694 |
case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
| 1695 |
value = cirrus_vga_read_gr(s, 0x14);
|
| 1696 |
break;
|
| 1697 |
case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
| 1698 |
value = cirrus_vga_read_gr(s, 0x01);
|
| 1699 |
break;
|
| 1700 |
case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
| 1701 |
value = cirrus_vga_read_gr(s, 0x11);
|
| 1702 |
break;
|
| 1703 |
case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
| 1704 |
value = cirrus_vga_read_gr(s, 0x13);
|
| 1705 |
break;
|
| 1706 |
case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
| 1707 |
value = cirrus_vga_read_gr(s, 0x15);
|
| 1708 |
break;
|
| 1709 |
case (CIRRUS_MMIO_BLTWIDTH + 0): |
| 1710 |
value = cirrus_vga_read_gr(s, 0x20);
|
| 1711 |
break;
|
| 1712 |
case (CIRRUS_MMIO_BLTWIDTH + 1): |
| 1713 |
value = cirrus_vga_read_gr(s, 0x21);
|
| 1714 |
break;
|
| 1715 |
case (CIRRUS_MMIO_BLTHEIGHT + 0): |
| 1716 |
value = cirrus_vga_read_gr(s, 0x22);
|
| 1717 |
break;
|
| 1718 |
case (CIRRUS_MMIO_BLTHEIGHT + 1): |
| 1719 |
value = cirrus_vga_read_gr(s, 0x23);
|
| 1720 |
break;
|
| 1721 |
case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
| 1722 |
value = cirrus_vga_read_gr(s, 0x24);
|
| 1723 |
break;
|
| 1724 |
case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
| 1725 |
value = cirrus_vga_read_gr(s, 0x25);
|
| 1726 |
break;
|
| 1727 |
case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
| 1728 |
value = cirrus_vga_read_gr(s, 0x26);
|
| 1729 |
break;
|
| 1730 |
case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
| 1731 |
value = cirrus_vga_read_gr(s, 0x27);
|
| 1732 |
break;
|
| 1733 |
case (CIRRUS_MMIO_BLTDESTADDR + 0): |
| 1734 |
value = cirrus_vga_read_gr(s, 0x28);
|
| 1735 |
break;
|
| 1736 |
case (CIRRUS_MMIO_BLTDESTADDR + 1): |
| 1737 |
value = cirrus_vga_read_gr(s, 0x29);
|
| 1738 |
break;
|
| 1739 |
case (CIRRUS_MMIO_BLTDESTADDR + 2): |
| 1740 |
value = cirrus_vga_read_gr(s, 0x2a);
|
| 1741 |
break;
|
| 1742 |
case (CIRRUS_MMIO_BLTSRCADDR + 0): |
| 1743 |
value = cirrus_vga_read_gr(s, 0x2c);
|
| 1744 |
break;
|
| 1745 |
case (CIRRUS_MMIO_BLTSRCADDR + 1): |
| 1746 |
value = cirrus_vga_read_gr(s, 0x2d);
|
| 1747 |
break;
|
| 1748 |
case (CIRRUS_MMIO_BLTSRCADDR + 2): |
| 1749 |
value = cirrus_vga_read_gr(s, 0x2e);
|
| 1750 |
break;
|
| 1751 |
case CIRRUS_MMIO_BLTWRITEMASK:
|
| 1752 |
value = cirrus_vga_read_gr(s, 0x2f);
|
| 1753 |
break;
|
| 1754 |
case CIRRUS_MMIO_BLTMODE:
|
| 1755 |
value = cirrus_vga_read_gr(s, 0x30);
|
| 1756 |
break;
|
| 1757 |
case CIRRUS_MMIO_BLTROP:
|
| 1758 |
value = cirrus_vga_read_gr(s, 0x32);
|
| 1759 |
break;
|
| 1760 |
case CIRRUS_MMIO_BLTMODEEXT:
|
| 1761 |
value = cirrus_vga_read_gr(s, 0x33);
|
| 1762 |
break;
|
| 1763 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
| 1764 |
value = cirrus_vga_read_gr(s, 0x34);
|
| 1765 |
break;
|
| 1766 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
| 1767 |
value = cirrus_vga_read_gr(s, 0x35);
|
| 1768 |
break;
|
| 1769 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
| 1770 |
value = cirrus_vga_read_gr(s, 0x38);
|
| 1771 |
break;
|
| 1772 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
| 1773 |
value = cirrus_vga_read_gr(s, 0x39);
|
| 1774 |
break;
|
| 1775 |
case CIRRUS_MMIO_BLTSTATUS:
|
| 1776 |
value = cirrus_vga_read_gr(s, 0x31);
|
| 1777 |
break;
|
| 1778 |
default:
|
| 1779 |
#ifdef DEBUG_CIRRUS
|
| 1780 |
printf("cirrus: mmio read - address 0x%04x\n", address);
|
| 1781 |
#endif
|
| 1782 |
break;
|
| 1783 |
} |
| 1784 |
|
| 1785 |
return (uint8_t) value;
|
| 1786 |
} |
| 1787 |
|
| 1788 |
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
| 1789 |
uint8_t value) |
| 1790 |
{
|
| 1791 |
switch (address) {
|
| 1792 |
case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
| 1793 |
cirrus_vga_write_gr(s, 0x00, value);
|
| 1794 |
break;
|
| 1795 |
case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
| 1796 |
cirrus_vga_write_gr(s, 0x10, value);
|
| 1797 |
break;
|
| 1798 |
case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
| 1799 |
cirrus_vga_write_gr(s, 0x12, value);
|
| 1800 |
break;
|
| 1801 |
case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
| 1802 |
cirrus_vga_write_gr(s, 0x14, value);
|
| 1803 |
break;
|
| 1804 |
case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
| 1805 |
cirrus_vga_write_gr(s, 0x01, value);
|
| 1806 |
break;
|
| 1807 |
case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
| 1808 |
cirrus_vga_write_gr(s, 0x11, value);
|
| 1809 |
break;
|
| 1810 |
case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
| 1811 |
cirrus_vga_write_gr(s, 0x13, value);
|
| 1812 |
break;
|
| 1813 |
case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
| 1814 |
cirrus_vga_write_gr(s, 0x15, value);
|
| 1815 |
break;
|
| 1816 |
case (CIRRUS_MMIO_BLTWIDTH + 0): |
| 1817 |
cirrus_vga_write_gr(s, 0x20, value);
|
| 1818 |
break;
|
| 1819 |
case (CIRRUS_MMIO_BLTWIDTH + 1): |
| 1820 |
cirrus_vga_write_gr(s, 0x21, value);
|
| 1821 |
break;
|
| 1822 |
case (CIRRUS_MMIO_BLTHEIGHT + 0): |
| 1823 |
cirrus_vga_write_gr(s, 0x22, value);
|
| 1824 |
break;
|
| 1825 |
case (CIRRUS_MMIO_BLTHEIGHT + 1): |
| 1826 |
cirrus_vga_write_gr(s, 0x23, value);
|
| 1827 |
break;
|
| 1828 |
case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
| 1829 |
cirrus_vga_write_gr(s, 0x24, value);
|
| 1830 |
break;
|
| 1831 |
case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
| 1832 |
cirrus_vga_write_gr(s, 0x25, value);
|
| 1833 |
break;
|
| 1834 |
case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
| 1835 |
cirrus_vga_write_gr(s, 0x26, value);
|
| 1836 |
break;
|
| 1837 |
case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
| 1838 |
cirrus_vga_write_gr(s, 0x27, value);
|
| 1839 |
break;
|
| 1840 |
case (CIRRUS_MMIO_BLTDESTADDR + 0): |
| 1841 |
cirrus_vga_write_gr(s, 0x28, value);
|
| 1842 |
break;
|
| 1843 |
case (CIRRUS_MMIO_BLTDESTADDR + 1): |
| 1844 |
cirrus_vga_write_gr(s, 0x29, value);
|
| 1845 |
break;
|
| 1846 |
case (CIRRUS_MMIO_BLTDESTADDR + 2): |
| 1847 |
cirrus_vga_write_gr(s, 0x2a, value);
|
| 1848 |
break;
|
| 1849 |
case (CIRRUS_MMIO_BLTDESTADDR + 3): |
| 1850 |
/* ignored */
|
| 1851 |
break;
|
| 1852 |
case (CIRRUS_MMIO_BLTSRCADDR + 0): |
| 1853 |
cirrus_vga_write_gr(s, 0x2c, value);
|
| 1854 |
break;
|
| 1855 |
case (CIRRUS_MMIO_BLTSRCADDR + 1): |
| 1856 |
cirrus_vga_write_gr(s, 0x2d, value);
|
| 1857 |
break;
|
| 1858 |
case (CIRRUS_MMIO_BLTSRCADDR + 2): |
| 1859 |
cirrus_vga_write_gr(s, 0x2e, value);
|
| 1860 |
break;
|
| 1861 |
case CIRRUS_MMIO_BLTWRITEMASK:
|
| 1862 |
cirrus_vga_write_gr(s, 0x2f, value);
|
| 1863 |
break;
|
| 1864 |
case CIRRUS_MMIO_BLTMODE:
|
| 1865 |
cirrus_vga_write_gr(s, 0x30, value);
|
| 1866 |
break;
|
| 1867 |
case CIRRUS_MMIO_BLTROP:
|
| 1868 |
cirrus_vga_write_gr(s, 0x32, value);
|
| 1869 |
break;
|
| 1870 |
case CIRRUS_MMIO_BLTMODEEXT:
|
| 1871 |
cirrus_vga_write_gr(s, 0x33, value);
|
| 1872 |
break;
|
| 1873 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
| 1874 |
cirrus_vga_write_gr(s, 0x34, value);
|
| 1875 |
break;
|
| 1876 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
| 1877 |
cirrus_vga_write_gr(s, 0x35, value);
|
| 1878 |
break;
|
| 1879 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
| 1880 |
cirrus_vga_write_gr(s, 0x38, value);
|
| 1881 |
break;
|
| 1882 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
| 1883 |
cirrus_vga_write_gr(s, 0x39, value);
|
| 1884 |
break;
|
| 1885 |
case CIRRUS_MMIO_BLTSTATUS:
|
| 1886 |
cirrus_vga_write_gr(s, 0x31, value);
|
| 1887 |
break;
|
| 1888 |
default:
|
| 1889 |
#ifdef DEBUG_CIRRUS
|
| 1890 |
printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
| 1891 |
address, value); |
| 1892 |
#endif
|
| 1893 |
break;
|
| 1894 |
} |
| 1895 |
} |
| 1896 |
|
| 1897 |
/***************************************
|
| 1898 |
*
|
| 1899 |
* write mode 4/5
|
| 1900 |
*
|
| 1901 |
***************************************/
|
| 1902 |
|
| 1903 |
static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
| 1904 |
unsigned mode,
|
| 1905 |
unsigned offset,
|
| 1906 |
uint32_t mem_value) |
| 1907 |
{
|
| 1908 |
int x;
|
| 1909 |
unsigned val = mem_value;
|
| 1910 |
uint8_t *dst; |
| 1911 |
|
| 1912 |
dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
| 1913 |
for (x = 0; x < 8; x++) { |
| 1914 |
if (val & 0x80) { |
| 1915 |
*dst = s->cirrus_shadow_gr1; |
| 1916 |
} else if (mode == 5) { |
| 1917 |
*dst = s->cirrus_shadow_gr0; |
| 1918 |
} |
| 1919 |
val <<= 1;
|
| 1920 |
dst++; |
| 1921 |
} |
| 1922 |
memory_region_set_dirty(&s->vga.vram, offset, 8);
|
| 1923 |
} |
| 1924 |
|
| 1925 |
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
| 1926 |
unsigned mode,
|
| 1927 |
unsigned offset,
|
| 1928 |
uint32_t mem_value) |
| 1929 |
{
|
| 1930 |
int x;
|
| 1931 |
unsigned val = mem_value;
|
| 1932 |
uint8_t *dst; |
| 1933 |
|
| 1934 |
dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
| 1935 |
for (x = 0; x < 8; x++) { |
| 1936 |
if (val & 0x80) { |
| 1937 |
*dst = s->cirrus_shadow_gr1; |
| 1938 |
*(dst + 1) = s->vga.gr[0x11]; |
| 1939 |
} else if (mode == 5) { |
| 1940 |
*dst = s->cirrus_shadow_gr0; |
| 1941 |
*(dst + 1) = s->vga.gr[0x10]; |
| 1942 |
} |
| 1943 |
val <<= 1;
|
| 1944 |
dst += 2;
|
| 1945 |
} |
| 1946 |
memory_region_set_dirty(&s->vga.vram, offset, 16);
|
| 1947 |
} |
| 1948 |
|
| 1949 |
/***************************************
|
| 1950 |
*
|
| 1951 |
* memory access between 0xa0000-0xbffff
|
| 1952 |
*
|
| 1953 |
***************************************/
|
| 1954 |
|
| 1955 |
static uint64_t cirrus_vga_mem_read(void *opaque, |
| 1956 |
target_phys_addr_t addr, |
| 1957 |
uint32_t size) |
| 1958 |
{
|
| 1959 |
CirrusVGAState *s = opaque; |
| 1960 |
unsigned bank_index;
|
| 1961 |
unsigned bank_offset;
|
| 1962 |
uint32_t val; |
| 1963 |
|
| 1964 |
if ((s->vga.sr[0x07] & 0x01) == 0) { |
| 1965 |
return vga_mem_readb(&s->vga, addr);
|
| 1966 |
} |
| 1967 |
|
| 1968 |
if (addr < 0x10000) { |
| 1969 |
/* XXX handle bitblt */
|
| 1970 |
/* video memory */
|
| 1971 |
bank_index = addr >> 15;
|
| 1972 |
bank_offset = addr & 0x7fff;
|
| 1973 |
if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
| 1974 |
bank_offset += s->cirrus_bank_base[bank_index]; |
| 1975 |
if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
| 1976 |
bank_offset <<= 4;
|
| 1977 |
} else if (s->vga.gr[0x0B] & 0x02) { |
| 1978 |
bank_offset <<= 3;
|
| 1979 |
} |
| 1980 |
bank_offset &= s->cirrus_addr_mask; |
| 1981 |
val = *(s->vga.vram_ptr + bank_offset); |
| 1982 |
} else
|
| 1983 |
val = 0xff;
|
| 1984 |
} else if (addr >= 0x18000 && addr < 0x18100) { |
| 1985 |
/* memory-mapped I/O */
|
| 1986 |
val = 0xff;
|
| 1987 |
if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
| 1988 |
val = cirrus_mmio_blt_read(s, addr & 0xff);
|
| 1989 |
} |
| 1990 |
} else {
|
| 1991 |
val = 0xff;
|
| 1992 |
#ifdef DEBUG_CIRRUS
|
| 1993 |
printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); |
| 1994 |
#endif
|
| 1995 |
} |
| 1996 |
return val;
|
| 1997 |
} |
| 1998 |
|
| 1999 |
static void cirrus_vga_mem_write(void *opaque, |
| 2000 |
target_phys_addr_t addr, |
| 2001 |
uint64_t mem_value, |
| 2002 |
uint32_t size) |
| 2003 |
{
|
| 2004 |
CirrusVGAState *s = opaque; |
| 2005 |
unsigned bank_index;
|
| 2006 |
unsigned bank_offset;
|
| 2007 |
unsigned mode;
|
| 2008 |
|
| 2009 |
if ((s->vga.sr[0x07] & 0x01) == 0) { |
| 2010 |
vga_mem_writeb(&s->vga, addr, mem_value); |
| 2011 |
return;
|
| 2012 |
} |
| 2013 |
|
| 2014 |
if (addr < 0x10000) { |
| 2015 |
if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
| 2016 |
/* bitblt */
|
| 2017 |
*s->cirrus_srcptr++ = (uint8_t) mem_value; |
| 2018 |
if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
| 2019 |
cirrus_bitblt_cputovideo_next(s); |
| 2020 |
} |
| 2021 |
} else {
|
| 2022 |
/* video memory */
|
| 2023 |
bank_index = addr >> 15;
|
| 2024 |
bank_offset = addr & 0x7fff;
|
| 2025 |
if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
| 2026 |
bank_offset += s->cirrus_bank_base[bank_index]; |
| 2027 |
if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
| 2028 |
bank_offset <<= 4;
|
| 2029 |
} else if (s->vga.gr[0x0B] & 0x02) { |
| 2030 |
bank_offset <<= 3;
|
| 2031 |
} |
| 2032 |
bank_offset &= s->cirrus_addr_mask; |
| 2033 |
mode = s->vga.gr[0x05] & 0x7; |
| 2034 |
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
| 2035 |
*(s->vga.vram_ptr + bank_offset) = mem_value; |
| 2036 |
memory_region_set_dirty(&s->vga.vram, bank_offset, |
| 2037 |
sizeof(mem_value));
|
| 2038 |
} else {
|
| 2039 |
if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
| 2040 |
cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
| 2041 |
bank_offset, |
| 2042 |
mem_value); |
| 2043 |
} else {
|
| 2044 |
cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
| 2045 |
bank_offset, |
| 2046 |
mem_value); |
| 2047 |
} |
| 2048 |
} |
| 2049 |
} |
| 2050 |
} |
| 2051 |
} else if (addr >= 0x18000 && addr < 0x18100) { |
| 2052 |
/* memory-mapped I/O */
|
| 2053 |
if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
| 2054 |
cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
| 2055 |
} |
| 2056 |
} else {
|
| 2057 |
#ifdef DEBUG_CIRRUS
|
| 2058 |
printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr, |
| 2059 |
mem_value); |
| 2060 |
#endif
|
| 2061 |
} |
| 2062 |
} |
| 2063 |
|
| 2064 |
static const MemoryRegionOps cirrus_vga_mem_ops = { |
| 2065 |
.read = cirrus_vga_mem_read, |
| 2066 |
.write = cirrus_vga_mem_write, |
| 2067 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2068 |
.impl = {
|
| 2069 |
.min_access_size = 1,
|
| 2070 |
.max_access_size = 1,
|
| 2071 |
}, |
| 2072 |
}; |
| 2073 |
|
| 2074 |
/***************************************
|
| 2075 |
*
|
| 2076 |
* hardware cursor
|
| 2077 |
*
|
| 2078 |
***************************************/
|
| 2079 |
|
| 2080 |
static inline void invalidate_cursor1(CirrusVGAState *s) |
| 2081 |
{
|
| 2082 |
if (s->last_hw_cursor_size) {
|
| 2083 |
vga_invalidate_scanlines(&s->vga, |
| 2084 |
s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
| 2085 |
s->last_hw_cursor_y + s->last_hw_cursor_y_end); |
| 2086 |
} |
| 2087 |
} |
| 2088 |
|
| 2089 |
static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) |
| 2090 |
{
|
| 2091 |
const uint8_t *src;
|
| 2092 |
uint32_t content; |
| 2093 |
int y, y_min, y_max;
|
| 2094 |
|
| 2095 |
src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
| 2096 |
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
| 2097 |
src += (s->vga.sr[0x13] & 0x3c) * 256; |
| 2098 |
y_min = 64;
|
| 2099 |
y_max = -1;
|
| 2100 |
for(y = 0; y < 64; y++) { |
| 2101 |
content = ((uint32_t *)src)[0] |
|
| 2102 |
((uint32_t *)src)[1] |
|
| 2103 |
((uint32_t *)src)[2] |
|
| 2104 |
((uint32_t *)src)[3];
|
| 2105 |
if (content) {
|
| 2106 |
if (y < y_min)
|
| 2107 |
y_min = y; |
| 2108 |
if (y > y_max)
|
| 2109 |
y_max = y; |
| 2110 |
} |
| 2111 |
src += 16;
|
| 2112 |
} |
| 2113 |
} else {
|
| 2114 |
src += (s->vga.sr[0x13] & 0x3f) * 256; |
| 2115 |
y_min = 32;
|
| 2116 |
y_max = -1;
|
| 2117 |
for(y = 0; y < 32; y++) { |
| 2118 |
content = ((uint32_t *)src)[0] |
|
| 2119 |
((uint32_t *)(src + 128))[0]; |
| 2120 |
if (content) {
|
| 2121 |
if (y < y_min)
|
| 2122 |
y_min = y; |
| 2123 |
if (y > y_max)
|
| 2124 |
y_max = y; |
| 2125 |
} |
| 2126 |
src += 4;
|
| 2127 |
} |
| 2128 |
} |
| 2129 |
if (y_min > y_max) {
|
| 2130 |
s->last_hw_cursor_y_start = 0;
|
| 2131 |
s->last_hw_cursor_y_end = 0;
|
| 2132 |
} else {
|
| 2133 |
s->last_hw_cursor_y_start = y_min; |
| 2134 |
s->last_hw_cursor_y_end = y_max + 1;
|
| 2135 |
} |
| 2136 |
} |
| 2137 |
|
| 2138 |
/* NOTE: we do not currently handle the cursor bitmap change, so we
|
| 2139 |
update the cursor only if it moves. */
|
| 2140 |
static void cirrus_cursor_invalidate(VGACommonState *s1) |
| 2141 |
{
|
| 2142 |
CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
| 2143 |
int size;
|
| 2144 |
|
| 2145 |
if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { |
| 2146 |
size = 0;
|
| 2147 |
} else {
|
| 2148 |
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) |
| 2149 |
size = 64;
|
| 2150 |
else
|
| 2151 |
size = 32;
|
| 2152 |
} |
| 2153 |
/* invalidate last cursor and new cursor if any change */
|
| 2154 |
if (s->last_hw_cursor_size != size ||
|
| 2155 |
s->last_hw_cursor_x != s->hw_cursor_x || |
| 2156 |
s->last_hw_cursor_y != s->hw_cursor_y) {
|
| 2157 |
|
| 2158 |
invalidate_cursor1(s); |
| 2159 |
|
| 2160 |
s->last_hw_cursor_size = size; |
| 2161 |
s->last_hw_cursor_x = s->hw_cursor_x; |
| 2162 |
s->last_hw_cursor_y = s->hw_cursor_y; |
| 2163 |
/* compute the real cursor min and max y */
|
| 2164 |
cirrus_cursor_compute_yrange(s); |
| 2165 |
invalidate_cursor1(s); |
| 2166 |
} |
| 2167 |
} |
| 2168 |
|
| 2169 |
#define DEPTH 8 |
| 2170 |
#include "cirrus_vga_template.h" |
| 2171 |
|
| 2172 |
#define DEPTH 16 |
| 2173 |
#include "cirrus_vga_template.h" |
| 2174 |
|
| 2175 |
#define DEPTH 32 |
| 2176 |
#include "cirrus_vga_template.h" |
| 2177 |
|
| 2178 |
static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) |
| 2179 |
{
|
| 2180 |
CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
| 2181 |
int w, h, bpp, x1, x2, poffset;
|
| 2182 |
unsigned int color0, color1; |
| 2183 |
const uint8_t *palette, *src;
|
| 2184 |
uint32_t content; |
| 2185 |
|
| 2186 |
if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) |
| 2187 |
return;
|
| 2188 |
/* fast test to see if the cursor intersects with the scan line */
|
| 2189 |
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
| 2190 |
h = 64;
|
| 2191 |
} else {
|
| 2192 |
h = 32;
|
| 2193 |
} |
| 2194 |
if (scr_y < s->hw_cursor_y ||
|
| 2195 |
scr_y >= (s->hw_cursor_y + h)) |
| 2196 |
return;
|
| 2197 |
|
| 2198 |
src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
| 2199 |
if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
| 2200 |
src += (s->vga.sr[0x13] & 0x3c) * 256; |
| 2201 |
src += (scr_y - s->hw_cursor_y) * 16;
|
| 2202 |
poffset = 8;
|
| 2203 |
content = ((uint32_t *)src)[0] |
|
| 2204 |
((uint32_t *)src)[1] |
|
| 2205 |
((uint32_t *)src)[2] |
|
| 2206 |
((uint32_t *)src)[3];
|
| 2207 |
} else {
|
| 2208 |
src += (s->vga.sr[0x13] & 0x3f) * 256; |
| 2209 |
src += (scr_y - s->hw_cursor_y) * 4;
|
| 2210 |
poffset = 128;
|
| 2211 |
content = ((uint32_t *)src)[0] |
|
| 2212 |
((uint32_t *)(src + 128))[0]; |
| 2213 |
} |
| 2214 |
/* if nothing to draw, no need to continue */
|
| 2215 |
if (!content)
|
| 2216 |
return;
|
| 2217 |
w = h; |
| 2218 |
|
| 2219 |
x1 = s->hw_cursor_x; |
| 2220 |
if (x1 >= s->vga.last_scr_width)
|
| 2221 |
return;
|
| 2222 |
x2 = s->hw_cursor_x + w; |
| 2223 |
if (x2 > s->vga.last_scr_width)
|
| 2224 |
x2 = s->vga.last_scr_width; |
| 2225 |
w = x2 - x1; |
| 2226 |
palette = s->cirrus_hidden_palette; |
| 2227 |
color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
| 2228 |
c6_to_8(palette[0x0 * 3 + 1]), |
| 2229 |
c6_to_8(palette[0x0 * 3 + 2])); |
| 2230 |
color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]), |
| 2231 |
c6_to_8(palette[0xf * 3 + 1]), |
| 2232 |
c6_to_8(palette[0xf * 3 + 2])); |
| 2233 |
bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3); |
| 2234 |
d1 += x1 * bpp; |
| 2235 |
switch(ds_get_bits_per_pixel(s->vga.ds)) {
|
| 2236 |
default:
|
| 2237 |
break;
|
| 2238 |
case 8: |
| 2239 |
vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
|
| 2240 |
break;
|
| 2241 |
case 15: |
| 2242 |
vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
|
| 2243 |
break;
|
| 2244 |
case 16: |
| 2245 |
vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
|
| 2246 |
break;
|
| 2247 |
case 32: |
| 2248 |
vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
|
| 2249 |
break;
|
| 2250 |
} |
| 2251 |
} |
| 2252 |
|
| 2253 |
/***************************************
|
| 2254 |
*
|
| 2255 |
* LFB memory access
|
| 2256 |
*
|
| 2257 |
***************************************/
|
| 2258 |
|
| 2259 |
static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr, |
| 2260 |
unsigned size)
|
| 2261 |
{
|
| 2262 |
CirrusVGAState *s = opaque; |
| 2263 |
uint32_t ret; |
| 2264 |
|
| 2265 |
addr &= s->cirrus_addr_mask; |
| 2266 |
|
| 2267 |
if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
| 2268 |
((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
|
| 2269 |
/* memory-mapped I/O */
|
| 2270 |
ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
| 2271 |
} else if (0) { |
| 2272 |
/* XXX handle bitblt */
|
| 2273 |
ret = 0xff;
|
| 2274 |
} else {
|
| 2275 |
/* video memory */
|
| 2276 |
if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
| 2277 |
addr <<= 4;
|
| 2278 |
} else if (s->vga.gr[0x0B] & 0x02) { |
| 2279 |
addr <<= 3;
|
| 2280 |
} |
| 2281 |
addr &= s->cirrus_addr_mask; |
| 2282 |
ret = *(s->vga.vram_ptr + addr); |
| 2283 |
} |
| 2284 |
|
| 2285 |
return ret;
|
| 2286 |
} |
| 2287 |
|
| 2288 |
static void cirrus_linear_write(void *opaque, target_phys_addr_t addr, |
| 2289 |
uint64_t val, unsigned size)
|
| 2290 |
{
|
| 2291 |
CirrusVGAState *s = opaque; |
| 2292 |
unsigned mode;
|
| 2293 |
|
| 2294 |
addr &= s->cirrus_addr_mask; |
| 2295 |
|
| 2296 |
if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
| 2297 |
((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
|
| 2298 |
/* memory-mapped I/O */
|
| 2299 |
cirrus_mmio_blt_write(s, addr & 0xff, val);
|
| 2300 |
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
| 2301 |
/* bitblt */
|
| 2302 |
*s->cirrus_srcptr++ = (uint8_t) val; |
| 2303 |
if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
| 2304 |
cirrus_bitblt_cputovideo_next(s); |
| 2305 |
} |
| 2306 |
} else {
|
| 2307 |
/* video memory */
|
| 2308 |
if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
| 2309 |
addr <<= 4;
|
| 2310 |
} else if (s->vga.gr[0x0B] & 0x02) { |
| 2311 |
addr <<= 3;
|
| 2312 |
} |
| 2313 |
addr &= s->cirrus_addr_mask; |
| 2314 |
|
| 2315 |
mode = s->vga.gr[0x05] & 0x7; |
| 2316 |
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
| 2317 |
*(s->vga.vram_ptr + addr) = (uint8_t) val; |
| 2318 |
memory_region_set_dirty(&s->vga.vram, addr, 1);
|
| 2319 |
} else {
|
| 2320 |
if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
| 2321 |
cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
| 2322 |
} else {
|
| 2323 |
cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
| 2324 |
} |
| 2325 |
} |
| 2326 |
} |
| 2327 |
} |
| 2328 |
|
| 2329 |
/***************************************
|
| 2330 |
*
|
| 2331 |
* system to screen memory access
|
| 2332 |
*
|
| 2333 |
***************************************/
|
| 2334 |
|
| 2335 |
|
| 2336 |
static uint64_t cirrus_linear_bitblt_read(void *opaque, |
| 2337 |
target_phys_addr_t addr, |
| 2338 |
unsigned size)
|
| 2339 |
{
|
| 2340 |
CirrusVGAState *s = opaque; |
| 2341 |
uint32_t ret; |
| 2342 |
|
| 2343 |
/* XXX handle bitblt */
|
| 2344 |
(void)s;
|
| 2345 |
ret = 0xff;
|
| 2346 |
return ret;
|
| 2347 |
} |
| 2348 |
|
| 2349 |
static void cirrus_linear_bitblt_write(void *opaque, |
| 2350 |
target_phys_addr_t addr, |
| 2351 |
uint64_t val, |
| 2352 |
unsigned size)
|
| 2353 |
{
|
| 2354 |
CirrusVGAState *s = opaque; |
| 2355 |
|
| 2356 |
if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
| 2357 |
/* bitblt */
|
| 2358 |
*s->cirrus_srcptr++ = (uint8_t) val; |
| 2359 |
if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
| 2360 |
cirrus_bitblt_cputovideo_next(s); |
| 2361 |
} |
| 2362 |
} |
| 2363 |
} |
| 2364 |
|
| 2365 |
static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { |
| 2366 |
.read = cirrus_linear_bitblt_read, |
| 2367 |
.write = cirrus_linear_bitblt_write, |
| 2368 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2369 |
.impl = {
|
| 2370 |
.min_access_size = 1,
|
| 2371 |
.max_access_size = 1,
|
| 2372 |
}, |
| 2373 |
}; |
| 2374 |
|
| 2375 |
static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) |
| 2376 |
{
|
| 2377 |
MemoryRegion *mr = &s->cirrus_bank[bank]; |
| 2378 |
bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
|
| 2379 |
&& !((s->vga.sr[0x07] & 0x01) == 0) |
| 2380 |
&& !((s->vga.gr[0x0B] & 0x14) == 0x14) |
| 2381 |
&& !(s->vga.gr[0x0B] & 0x02); |
| 2382 |
|
| 2383 |
memory_region_set_enabled(mr, enabled); |
| 2384 |
memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); |
| 2385 |
} |
| 2386 |
|
| 2387 |
static void map_linear_vram(CirrusVGAState *s) |
| 2388 |
{
|
| 2389 |
if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
|
| 2390 |
s->linear_vram = true;
|
| 2391 |
memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); |
| 2392 |
} |
| 2393 |
map_linear_vram_bank(s, 0);
|
| 2394 |
map_linear_vram_bank(s, 1);
|
| 2395 |
} |
| 2396 |
|
| 2397 |
static void unmap_linear_vram(CirrusVGAState *s) |
| 2398 |
{
|
| 2399 |
if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
|
| 2400 |
s->linear_vram = false;
|
| 2401 |
memory_region_del_subregion(&s->pci_bar, &s->vga.vram); |
| 2402 |
} |
| 2403 |
memory_region_set_enabled(&s->cirrus_bank[0], false); |
| 2404 |
memory_region_set_enabled(&s->cirrus_bank[1], false); |
| 2405 |
} |
| 2406 |
|
| 2407 |
/* Compute the memory access functions */
|
| 2408 |
static void cirrus_update_memory_access(CirrusVGAState *s) |
| 2409 |
{
|
| 2410 |
unsigned mode;
|
| 2411 |
|
| 2412 |
memory_region_transaction_begin(); |
| 2413 |
if ((s->vga.sr[0x17] & 0x44) == 0x44) { |
| 2414 |
goto generic_io;
|
| 2415 |
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
| 2416 |
goto generic_io;
|
| 2417 |
} else {
|
| 2418 |
if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
| 2419 |
goto generic_io;
|
| 2420 |
} else if (s->vga.gr[0x0B] & 0x02) { |
| 2421 |
goto generic_io;
|
| 2422 |
} |
| 2423 |
|
| 2424 |
mode = s->vga.gr[0x05] & 0x7; |
| 2425 |
if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
| 2426 |
map_linear_vram(s); |
| 2427 |
} else {
|
| 2428 |
generic_io:
|
| 2429 |
unmap_linear_vram(s); |
| 2430 |
} |
| 2431 |
} |
| 2432 |
memory_region_transaction_commit(); |
| 2433 |
} |
| 2434 |
|
| 2435 |
|
| 2436 |
/* I/O ports */
|
| 2437 |
|
| 2438 |
static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) |
| 2439 |
{
|
| 2440 |
CirrusVGAState *c = opaque; |
| 2441 |
VGACommonState *s = &c->vga; |
| 2442 |
int val, index;
|
| 2443 |
|
| 2444 |
if (vga_ioport_invalid(s, addr)) {
|
| 2445 |
val = 0xff;
|
| 2446 |
} else {
|
| 2447 |
switch (addr) {
|
| 2448 |
case 0x3c0: |
| 2449 |
if (s->ar_flip_flop == 0) { |
| 2450 |
val = s->ar_index; |
| 2451 |
} else {
|
| 2452 |
val = 0;
|
| 2453 |
} |
| 2454 |
break;
|
| 2455 |
case 0x3c1: |
| 2456 |
index = s->ar_index & 0x1f;
|
| 2457 |
if (index < 21) |
| 2458 |
val = s->ar[index]; |
| 2459 |
else
|
| 2460 |
val = 0;
|
| 2461 |
break;
|
| 2462 |
case 0x3c2: |
| 2463 |
val = s->st00; |
| 2464 |
break;
|
| 2465 |
case 0x3c4: |
| 2466 |
val = s->sr_index; |
| 2467 |
break;
|
| 2468 |
case 0x3c5: |
| 2469 |
val = cirrus_vga_read_sr(c); |
| 2470 |
break;
|
| 2471 |
#ifdef DEBUG_VGA_REG
|
| 2472 |
printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
| 2473 |
#endif
|
| 2474 |
break;
|
| 2475 |
case 0x3c6: |
| 2476 |
val = cirrus_read_hidden_dac(c); |
| 2477 |
break;
|
| 2478 |
case 0x3c7: |
| 2479 |
val = s->dac_state; |
| 2480 |
break;
|
| 2481 |
case 0x3c8: |
| 2482 |
val = s->dac_write_index; |
| 2483 |
c->cirrus_hidden_dac_lockindex = 0;
|
| 2484 |
break;
|
| 2485 |
case 0x3c9: |
| 2486 |
val = cirrus_vga_read_palette(c); |
| 2487 |
break;
|
| 2488 |
case 0x3ca: |
| 2489 |
val = s->fcr; |
| 2490 |
break;
|
| 2491 |
case 0x3cc: |
| 2492 |
val = s->msr; |
| 2493 |
break;
|
| 2494 |
case 0x3ce: |
| 2495 |
val = s->gr_index; |
| 2496 |
break;
|
| 2497 |
case 0x3cf: |
| 2498 |
val = cirrus_vga_read_gr(c, s->gr_index); |
| 2499 |
#ifdef DEBUG_VGA_REG
|
| 2500 |
printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
| 2501 |
#endif
|
| 2502 |
break;
|
| 2503 |
case 0x3b4: |
| 2504 |
case 0x3d4: |
| 2505 |
val = s->cr_index; |
| 2506 |
break;
|
| 2507 |
case 0x3b5: |
| 2508 |
case 0x3d5: |
| 2509 |
val = cirrus_vga_read_cr(c, s->cr_index); |
| 2510 |
#ifdef DEBUG_VGA_REG
|
| 2511 |
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
| 2512 |
#endif
|
| 2513 |
break;
|
| 2514 |
case 0x3ba: |
| 2515 |
case 0x3da: |
| 2516 |
/* just toggle to fool polling */
|
| 2517 |
val = s->st01 = s->retrace(s); |
| 2518 |
s->ar_flip_flop = 0;
|
| 2519 |
break;
|
| 2520 |
default:
|
| 2521 |
val = 0x00;
|
| 2522 |
break;
|
| 2523 |
} |
| 2524 |
} |
| 2525 |
#if defined(DEBUG_VGA)
|
| 2526 |
printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
| 2527 |
#endif
|
| 2528 |
return val;
|
| 2529 |
} |
| 2530 |
|
| 2531 |
static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 2532 |
{
|
| 2533 |
CirrusVGAState *c = opaque; |
| 2534 |
VGACommonState *s = &c->vga; |
| 2535 |
int index;
|
| 2536 |
|
| 2537 |
/* check port range access depending on color/monochrome mode */
|
| 2538 |
if (vga_ioport_invalid(s, addr)) {
|
| 2539 |
return;
|
| 2540 |
} |
| 2541 |
#ifdef DEBUG_VGA
|
| 2542 |
printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
| 2543 |
#endif
|
| 2544 |
|
| 2545 |
switch (addr) {
|
| 2546 |
case 0x3c0: |
| 2547 |
if (s->ar_flip_flop == 0) { |
| 2548 |
val &= 0x3f;
|
| 2549 |
s->ar_index = val; |
| 2550 |
} else {
|
| 2551 |
index = s->ar_index & 0x1f;
|
| 2552 |
switch (index) {
|
| 2553 |
case 0x00 ... 0x0f: |
| 2554 |
s->ar[index] = val & 0x3f;
|
| 2555 |
break;
|
| 2556 |
case 0x10: |
| 2557 |
s->ar[index] = val & ~0x10;
|
| 2558 |
break;
|
| 2559 |
case 0x11: |
| 2560 |
s->ar[index] = val; |
| 2561 |
break;
|
| 2562 |
case 0x12: |
| 2563 |
s->ar[index] = val & ~0xc0;
|
| 2564 |
break;
|
| 2565 |
case 0x13: |
| 2566 |
s->ar[index] = val & ~0xf0;
|
| 2567 |
break;
|
| 2568 |
case 0x14: |
| 2569 |
s->ar[index] = val & ~0xf0;
|
| 2570 |
break;
|
| 2571 |
default:
|
| 2572 |
break;
|
| 2573 |
} |
| 2574 |
} |
| 2575 |
s->ar_flip_flop ^= 1;
|
| 2576 |
break;
|
| 2577 |
case 0x3c2: |
| 2578 |
s->msr = val & ~0x10;
|
| 2579 |
s->update_retrace_info(s); |
| 2580 |
break;
|
| 2581 |
case 0x3c4: |
| 2582 |
s->sr_index = val; |
| 2583 |
break;
|
| 2584 |
case 0x3c5: |
| 2585 |
#ifdef DEBUG_VGA_REG
|
| 2586 |
printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
| 2587 |
#endif
|
| 2588 |
cirrus_vga_write_sr(c, val); |
| 2589 |
break;
|
| 2590 |
break;
|
| 2591 |
case 0x3c6: |
| 2592 |
cirrus_write_hidden_dac(c, val); |
| 2593 |
break;
|
| 2594 |
case 0x3c7: |
| 2595 |
s->dac_read_index = val; |
| 2596 |
s->dac_sub_index = 0;
|
| 2597 |
s->dac_state = 3;
|
| 2598 |
break;
|
| 2599 |
case 0x3c8: |
| 2600 |
s->dac_write_index = val; |
| 2601 |
s->dac_sub_index = 0;
|
| 2602 |
s->dac_state = 0;
|
| 2603 |
break;
|
| 2604 |
case 0x3c9: |
| 2605 |
cirrus_vga_write_palette(c, val); |
| 2606 |
break;
|
| 2607 |
case 0x3ce: |
| 2608 |
s->gr_index = val; |
| 2609 |
break;
|
| 2610 |
case 0x3cf: |
| 2611 |
#ifdef DEBUG_VGA_REG
|
| 2612 |
printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
| 2613 |
#endif
|
| 2614 |
cirrus_vga_write_gr(c, s->gr_index, val); |
| 2615 |
break;
|
| 2616 |
case 0x3b4: |
| 2617 |
case 0x3d4: |
| 2618 |
s->cr_index = val; |
| 2619 |
break;
|
| 2620 |
case 0x3b5: |
| 2621 |
case 0x3d5: |
| 2622 |
#ifdef DEBUG_VGA_REG
|
| 2623 |
printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
| 2624 |
#endif
|
| 2625 |
cirrus_vga_write_cr(c, val); |
| 2626 |
break;
|
| 2627 |
case 0x3ba: |
| 2628 |
case 0x3da: |
| 2629 |
s->fcr = val & 0x10;
|
| 2630 |
break;
|
| 2631 |
} |
| 2632 |
} |
| 2633 |
|
| 2634 |
/***************************************
|
| 2635 |
*
|
| 2636 |
* memory-mapped I/O access
|
| 2637 |
*
|
| 2638 |
***************************************/
|
| 2639 |
|
| 2640 |
static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr, |
| 2641 |
unsigned size)
|
| 2642 |
{
|
| 2643 |
CirrusVGAState *s = opaque; |
| 2644 |
|
| 2645 |
if (addr >= 0x100) { |
| 2646 |
return cirrus_mmio_blt_read(s, addr - 0x100); |
| 2647 |
} else {
|
| 2648 |
return cirrus_vga_ioport_read(s, addr + 0x3c0); |
| 2649 |
} |
| 2650 |
} |
| 2651 |
|
| 2652 |
static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr, |
| 2653 |
uint64_t val, unsigned size)
|
| 2654 |
{
|
| 2655 |
CirrusVGAState *s = opaque; |
| 2656 |
|
| 2657 |
if (addr >= 0x100) { |
| 2658 |
cirrus_mmio_blt_write(s, addr - 0x100, val);
|
| 2659 |
} else {
|
| 2660 |
cirrus_vga_ioport_write(s, addr + 0x3c0, val);
|
| 2661 |
} |
| 2662 |
} |
| 2663 |
|
| 2664 |
static const MemoryRegionOps cirrus_mmio_io_ops = { |
| 2665 |
.read = cirrus_mmio_read, |
| 2666 |
.write = cirrus_mmio_write, |
| 2667 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2668 |
.impl = {
|
| 2669 |
.min_access_size = 1,
|
| 2670 |
.max_access_size = 1,
|
| 2671 |
}, |
| 2672 |
}; |
| 2673 |
|
| 2674 |
/* load/save state */
|
| 2675 |
|
| 2676 |
static int cirrus_post_load(void *opaque, int version_id) |
| 2677 |
{
|
| 2678 |
CirrusVGAState *s = opaque; |
| 2679 |
|
| 2680 |
s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
| 2681 |
s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; |
| 2682 |
|
| 2683 |
cirrus_update_memory_access(s); |
| 2684 |
/* force refresh */
|
| 2685 |
s->vga.graphic_mode = -1;
|
| 2686 |
cirrus_update_bank_ptr(s, 0);
|
| 2687 |
cirrus_update_bank_ptr(s, 1);
|
| 2688 |
return 0; |
| 2689 |
} |
| 2690 |
|
| 2691 |
static const VMStateDescription vmstate_cirrus_vga = { |
| 2692 |
.name = "cirrus_vga",
|
| 2693 |
.version_id = 2,
|
| 2694 |
.minimum_version_id = 1,
|
| 2695 |
.minimum_version_id_old = 1,
|
| 2696 |
.post_load = cirrus_post_load, |
| 2697 |
.fields = (VMStateField []) {
|
| 2698 |
VMSTATE_UINT32(vga.latch, CirrusVGAState), |
| 2699 |
VMSTATE_UINT8(vga.sr_index, CirrusVGAState), |
| 2700 |
VMSTATE_BUFFER(vga.sr, CirrusVGAState), |
| 2701 |
VMSTATE_UINT8(vga.gr_index, CirrusVGAState), |
| 2702 |
VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), |
| 2703 |
VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), |
| 2704 |
VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
|
| 2705 |
VMSTATE_UINT8(vga.ar_index, CirrusVGAState), |
| 2706 |
VMSTATE_BUFFER(vga.ar, CirrusVGAState), |
| 2707 |
VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), |
| 2708 |
VMSTATE_UINT8(vga.cr_index, CirrusVGAState), |
| 2709 |
VMSTATE_BUFFER(vga.cr, CirrusVGAState), |
| 2710 |
VMSTATE_UINT8(vga.msr, CirrusVGAState), |
| 2711 |
VMSTATE_UINT8(vga.fcr, CirrusVGAState), |
| 2712 |
VMSTATE_UINT8(vga.st00, CirrusVGAState), |
| 2713 |
VMSTATE_UINT8(vga.st01, CirrusVGAState), |
| 2714 |
VMSTATE_UINT8(vga.dac_state, CirrusVGAState), |
| 2715 |
VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), |
| 2716 |
VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), |
| 2717 |
VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), |
| 2718 |
VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), |
| 2719 |
VMSTATE_BUFFER(vga.palette, CirrusVGAState), |
| 2720 |
VMSTATE_INT32(vga.bank_offset, CirrusVGAState), |
| 2721 |
VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), |
| 2722 |
VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), |
| 2723 |
VMSTATE_UINT32(hw_cursor_x, CirrusVGAState), |
| 2724 |
VMSTATE_UINT32(hw_cursor_y, CirrusVGAState), |
| 2725 |
/* XXX: we do not save the bitblt state - we assume we do not save
|
| 2726 |
the state when the blitter is active */
|
| 2727 |
VMSTATE_END_OF_LIST() |
| 2728 |
} |
| 2729 |
}; |
| 2730 |
|
| 2731 |
static const VMStateDescription vmstate_pci_cirrus_vga = { |
| 2732 |
.name = "cirrus_vga",
|
| 2733 |
.version_id = 2,
|
| 2734 |
.minimum_version_id = 2,
|
| 2735 |
.minimum_version_id_old = 2,
|
| 2736 |
.fields = (VMStateField []) {
|
| 2737 |
VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), |
| 2738 |
VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
|
| 2739 |
vmstate_cirrus_vga, CirrusVGAState), |
| 2740 |
VMSTATE_END_OF_LIST() |
| 2741 |
} |
| 2742 |
}; |
| 2743 |
|
| 2744 |
/***************************************
|
| 2745 |
*
|
| 2746 |
* initialize
|
| 2747 |
*
|
| 2748 |
***************************************/
|
| 2749 |
|
| 2750 |
static void cirrus_reset(void *opaque) |
| 2751 |
{
|
| 2752 |
CirrusVGAState *s = opaque; |
| 2753 |
|
| 2754 |
vga_common_reset(&s->vga); |
| 2755 |
unmap_linear_vram(s); |
| 2756 |
s->vga.sr[0x06] = 0x0f; |
| 2757 |
if (s->device_id == CIRRUS_ID_CLGD5446) {
|
| 2758 |
/* 4MB 64 bit memory config, always PCI */
|
| 2759 |
s->vga.sr[0x1F] = 0x2d; // MemClock |
| 2760 |
s->vga.gr[0x18] = 0x0f; // fastest memory configuration |
| 2761 |
s->vga.sr[0x0f] = 0x98; |
| 2762 |
s->vga.sr[0x17] = 0x20; |
| 2763 |
s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ |
| 2764 |
} else {
|
| 2765 |
s->vga.sr[0x1F] = 0x22; // MemClock |
| 2766 |
s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
| 2767 |
s->vga.sr[0x17] = s->bustype;
|
| 2768 |
s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
| 2769 |
} |
| 2770 |
s->vga.cr[0x27] = s->device_id;
|
| 2771 |
|
| 2772 |
s->cirrus_hidden_dac_lockindex = 5;
|
| 2773 |
s->cirrus_hidden_dac_data = 0;
|
| 2774 |
} |
| 2775 |
|
| 2776 |
static const MemoryRegionOps cirrus_linear_io_ops = { |
| 2777 |
.read = cirrus_linear_read, |
| 2778 |
.write = cirrus_linear_write, |
| 2779 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2780 |
.impl = {
|
| 2781 |
.min_access_size = 1,
|
| 2782 |
.max_access_size = 1,
|
| 2783 |
}, |
| 2784 |
}; |
| 2785 |
|
| 2786 |
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, |
| 2787 |
MemoryRegion *system_memory) |
| 2788 |
{
|
| 2789 |
int i;
|
| 2790 |
static int inited; |
| 2791 |
|
| 2792 |
if (!inited) {
|
| 2793 |
inited = 1;
|
| 2794 |
for(i = 0;i < 256; i++) |
| 2795 |
rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
|
| 2796 |
rop_to_index[CIRRUS_ROP_0] = 0;
|
| 2797 |
rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
|
| 2798 |
rop_to_index[CIRRUS_ROP_NOP] = 2;
|
| 2799 |
rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
|
| 2800 |
rop_to_index[CIRRUS_ROP_NOTDST] = 4;
|
| 2801 |
rop_to_index[CIRRUS_ROP_SRC] = 5;
|
| 2802 |
rop_to_index[CIRRUS_ROP_1] = 6;
|
| 2803 |
rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
|
| 2804 |
rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
|
| 2805 |
rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
|
| 2806 |
rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
|
| 2807 |
rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
|
| 2808 |
rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
|
| 2809 |
rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
|
| 2810 |
rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
|
| 2811 |
rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
|
| 2812 |
s->device_id = device_id; |
| 2813 |
if (is_pci)
|
| 2814 |
s->bustype = CIRRUS_BUSTYPE_PCI; |
| 2815 |
else
|
| 2816 |
s->bustype = CIRRUS_BUSTYPE_ISA; |
| 2817 |
} |
| 2818 |
|
| 2819 |
register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s); |
| 2820 |
|
| 2821 |
register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s); |
| 2822 |
register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s); |
| 2823 |
register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s); |
| 2824 |
register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s); |
| 2825 |
|
| 2826 |
register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s); |
| 2827 |
|
| 2828 |
register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s); |
| 2829 |
register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s); |
| 2830 |
register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s); |
| 2831 |
register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s); |
| 2832 |
|
| 2833 |
memory_region_init(&s->low_mem_container, |
| 2834 |
"cirrus-lowmem-container",
|
| 2835 |
0x20000);
|
| 2836 |
|
| 2837 |
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s, |
| 2838 |
"cirrus-low-memory", 0x20000); |
| 2839 |
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
|
| 2840 |
for (i = 0; i < 2; ++i) { |
| 2841 |
static const char *names[] = { "vga.bank0", "vga.bank1" }; |
| 2842 |
MemoryRegion *bank = &s->cirrus_bank[i]; |
| 2843 |
memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000); |
| 2844 |
memory_region_set_enabled(bank, false);
|
| 2845 |
memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
|
| 2846 |
bank, 1);
|
| 2847 |
} |
| 2848 |
memory_region_add_subregion_overlap(system_memory, |
| 2849 |
isa_mem_base + 0x000a0000,
|
| 2850 |
&s->low_mem_container, |
| 2851 |
1);
|
| 2852 |
memory_region_set_coalescing(&s->low_mem); |
| 2853 |
|
| 2854 |
/* I/O handler for LFB */
|
| 2855 |
memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s, |
| 2856 |
"cirrus-linear-io", VGA_RAM_SIZE);
|
| 2857 |
|
| 2858 |
/* I/O handler for LFB */
|
| 2859 |
memory_region_init_io(&s->cirrus_linear_bitblt_io, |
| 2860 |
&cirrus_linear_bitblt_io_ops, |
| 2861 |
s, |
| 2862 |
"cirrus-bitblt-mmio",
|
| 2863 |
0x400000);
|
| 2864 |
|
| 2865 |
/* I/O handler for memory-mapped I/O */
|
| 2866 |
memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s, |
| 2867 |
"cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
|
| 2868 |
|
| 2869 |
s->real_vram_size = |
| 2870 |
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; |
| 2871 |
|
| 2872 |
/* XXX: s->vga.vram_size must be a power of two */
|
| 2873 |
s->cirrus_addr_mask = s->real_vram_size - 1;
|
| 2874 |
s->linear_mmio_mask = s->real_vram_size - 256;
|
| 2875 |
|
| 2876 |
s->vga.get_bpp = cirrus_get_bpp; |
| 2877 |
s->vga.get_offsets = cirrus_get_offsets; |
| 2878 |
s->vga.get_resolution = cirrus_get_resolution; |
| 2879 |
s->vga.cursor_invalidate = cirrus_cursor_invalidate; |
| 2880 |
s->vga.cursor_draw_line = cirrus_cursor_draw_line; |
| 2881 |
|
| 2882 |
qemu_register_reset(cirrus_reset, s); |
| 2883 |
} |
| 2884 |
|
| 2885 |
/***************************************
|
| 2886 |
*
|
| 2887 |
* ISA bus support
|
| 2888 |
*
|
| 2889 |
***************************************/
|
| 2890 |
|
| 2891 |
static int vga_initfn(ISADevice *dev) |
| 2892 |
{
|
| 2893 |
ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev); |
| 2894 |
VGACommonState *s = &d->cirrus_vga.vga; |
| 2895 |
|
| 2896 |
s->vram_size_mb = VGA_RAM_SIZE >> 20;
|
| 2897 |
vga_common_init(s); |
| 2898 |
cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
|
| 2899 |
isa_address_space(dev)); |
| 2900 |
s->ds = graphic_console_init(s->update, s->invalidate, |
| 2901 |
s->screen_dump, s->text_update, |
| 2902 |
s); |
| 2903 |
rom_add_vga(VGABIOS_CIRRUS_FILENAME); |
| 2904 |
/* XXX ISA-LFB support */
|
| 2905 |
/* FIXME not qdev yet */
|
| 2906 |
return 0; |
| 2907 |
} |
| 2908 |
|
| 2909 |
static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) |
| 2910 |
{
|
| 2911 |
ISADeviceClass *k = ISA_DEVICE_CLASS(klass); |
| 2912 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 2913 |
|
| 2914 |
dc->vmsd = &vmstate_cirrus_vga; |
| 2915 |
k->init = vga_initfn; |
| 2916 |
} |
| 2917 |
|
| 2918 |
static TypeInfo isa_cirrus_vga_info = {
|
| 2919 |
.name = "isa-cirrus-vga",
|
| 2920 |
.parent = TYPE_ISA_DEVICE, |
| 2921 |
.instance_size = sizeof(ISACirrusVGAState),
|
| 2922 |
.class_init = isa_cirrus_vga_class_init, |
| 2923 |
}; |
| 2924 |
|
| 2925 |
/***************************************
|
| 2926 |
*
|
| 2927 |
* PCI bus support
|
| 2928 |
*
|
| 2929 |
***************************************/
|
| 2930 |
|
| 2931 |
static int pci_cirrus_vga_initfn(PCIDevice *dev) |
| 2932 |
{
|
| 2933 |
PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev); |
| 2934 |
CirrusVGAState *s = &d->cirrus_vga; |
| 2935 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
| 2936 |
int16_t device_id = pc->device_id; |
| 2937 |
|
| 2938 |
/* setup VGA */
|
| 2939 |
s->vga.vram_size_mb = VGA_RAM_SIZE >> 20;
|
| 2940 |
vga_common_init(&s->vga); |
| 2941 |
cirrus_init_common(s, device_id, 1, pci_address_space(dev));
|
| 2942 |
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, |
| 2943 |
s->vga.screen_dump, s->vga.text_update, |
| 2944 |
&s->vga); |
| 2945 |
|
| 2946 |
/* setup PCI */
|
| 2947 |
|
| 2948 |
memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000); |
| 2949 |
|
| 2950 |
/* XXX: add byte swapping apertures */
|
| 2951 |
memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
|
| 2952 |
memory_region_add_subregion(&s->pci_bar, 0x1000000,
|
| 2953 |
&s->cirrus_linear_bitblt_io); |
| 2954 |
|
| 2955 |
/* setup memory space */
|
| 2956 |
/* memory #0 LFB */
|
| 2957 |
/* memory #1 memory-mapped I/O */
|
| 2958 |
/* XXX: s->vga.vram_size must be a power of two */
|
| 2959 |
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
|
| 2960 |
if (device_id == CIRRUS_ID_CLGD5446) {
|
| 2961 |
pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); |
| 2962 |
} |
| 2963 |
return 0; |
| 2964 |
} |
| 2965 |
|
| 2966 |
DeviceState *pci_cirrus_vga_init(PCIBus *bus) |
| 2967 |
{
|
| 2968 |
return &pci_create_simple(bus, -1, "cirrus-vga")->qdev; |
| 2969 |
} |
| 2970 |
|
| 2971 |
static void cirrus_vga_class_init(ObjectClass *klass, void *data) |
| 2972 |
{
|
| 2973 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 2974 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 2975 |
|
| 2976 |
k->no_hotplug = 1;
|
| 2977 |
k->init = pci_cirrus_vga_initfn; |
| 2978 |
k->romfile = VGABIOS_CIRRUS_FILENAME; |
| 2979 |
k->vendor_id = PCI_VENDOR_ID_CIRRUS; |
| 2980 |
k->device_id = CIRRUS_ID_CLGD5446; |
| 2981 |
k->class_id = PCI_CLASS_DISPLAY_VGA; |
| 2982 |
dc->desc = "Cirrus CLGD 54xx VGA";
|
| 2983 |
dc->vmsd = &vmstate_pci_cirrus_vga; |
| 2984 |
} |
| 2985 |
|
| 2986 |
static TypeInfo cirrus_vga_info = {
|
| 2987 |
.name = "cirrus-vga",
|
| 2988 |
.parent = TYPE_PCI_DEVICE, |
| 2989 |
.instance_size = sizeof(PCICirrusVGAState),
|
| 2990 |
.class_init = cirrus_vga_class_init, |
| 2991 |
}; |
| 2992 |
|
| 2993 |
static void cirrus_vga_register_types(void) |
| 2994 |
{
|
| 2995 |
type_register_static(&isa_cirrus_vga_info); |
| 2996 |
type_register_static(&cirrus_vga_info); |
| 2997 |
} |
| 2998 |
|
| 2999 |
type_init(cirrus_vga_register_types) |