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/*
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* USB xHCI controller emulation
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*
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* Copyright (c) 2011 Securiforest
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* Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
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* Based on usb-ohci.c, emulates Renesas NEC USB 3.0
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h" |
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#include "qemu-timer.h" |
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#include "hw/usb.h" |
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#include "hw/pci.h" |
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#include "hw/msi.h" |
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#include "trace.h" |
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//#define DEBUG_XHCI
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//#define DEBUG_DATA
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#ifdef DEBUG_XHCI
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#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
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#else
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#define DPRINTF(...) do {} while (0) |
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#endif
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#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ |
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__func__, __LINE__); abort(); } while (0) |
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#define MAXPORTS_2 8 |
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#define MAXPORTS_3 8 |
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#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
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#define MAXSLOTS MAXPORTS
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#define MAXINTRS 1 /* MAXPORTS */ |
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#define TD_QUEUE 24 |
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/* Very pessimistic, let's hope it's enough for all cases */
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#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) |
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/* Do not deliver ER Full events. NEC's driver does some things not bound
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* to the specs when it gets them */
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#define ER_FULL_HACK
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#define LEN_CAP 0x40 |
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#define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
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#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) |
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#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
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#define OFF_OPER LEN_CAP
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#define OFF_RUNTIME 0x1000 |
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#define OFF_DOORBELL 0x2000 |
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/* must be power of 2 */
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#define LEN_REGS 0x4000 |
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#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
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#error Increase OFF_RUNTIME
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#endif
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#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
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#error Increase OFF_DOORBELL
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#endif
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#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
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# error Increase LEN_REGS
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#endif
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#if MAXINTRS > 1 |
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# error TODO: only one interrupter supported
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#endif
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/* bit definitions */
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#define USBCMD_RS (1<<0) |
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#define USBCMD_HCRST (1<<1) |
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#define USBCMD_INTE (1<<2) |
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#define USBCMD_HSEE (1<<3) |
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#define USBCMD_LHCRST (1<<7) |
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#define USBCMD_CSS (1<<8) |
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#define USBCMD_CRS (1<<9) |
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#define USBCMD_EWE (1<<10) |
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#define USBCMD_EU3S (1<<11) |
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#define USBSTS_HCH (1<<0) |
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#define USBSTS_HSE (1<<2) |
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#define USBSTS_EINT (1<<3) |
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#define USBSTS_PCD (1<<4) |
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#define USBSTS_SSS (1<<8) |
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#define USBSTS_RSS (1<<9) |
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#define USBSTS_SRE (1<<10) |
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#define USBSTS_CNR (1<<11) |
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#define USBSTS_HCE (1<<12) |
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#define PORTSC_CCS (1<<0) |
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#define PORTSC_PED (1<<1) |
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#define PORTSC_OCA (1<<3) |
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#define PORTSC_PR (1<<4) |
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#define PORTSC_PLS_SHIFT 5 |
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#define PORTSC_PLS_MASK 0xf |
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#define PORTSC_PP (1<<9) |
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#define PORTSC_SPEED_SHIFT 10 |
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#define PORTSC_SPEED_MASK 0xf |
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#define PORTSC_SPEED_FULL (1<<10) |
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#define PORTSC_SPEED_LOW (2<<10) |
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#define PORTSC_SPEED_HIGH (3<<10) |
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#define PORTSC_SPEED_SUPER (4<<10) |
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#define PORTSC_PIC_SHIFT 14 |
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#define PORTSC_PIC_MASK 0x3 |
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#define PORTSC_LWS (1<<16) |
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#define PORTSC_CSC (1<<17) |
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#define PORTSC_PEC (1<<18) |
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#define PORTSC_WRC (1<<19) |
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#define PORTSC_OCC (1<<20) |
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#define PORTSC_PRC (1<<21) |
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#define PORTSC_PLC (1<<22) |
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#define PORTSC_CEC (1<<23) |
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#define PORTSC_CAS (1<<24) |
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#define PORTSC_WCE (1<<25) |
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#define PORTSC_WDE (1<<26) |
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#define PORTSC_WOE (1<<27) |
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#define PORTSC_DR (1<<30) |
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#define PORTSC_WPR (1<<31) |
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#define CRCR_RCS (1<<0) |
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#define CRCR_CS (1<<1) |
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#define CRCR_CA (1<<2) |
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#define CRCR_CRR (1<<3) |
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#define IMAN_IP (1<<0) |
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#define IMAN_IE (1<<1) |
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#define ERDP_EHB (1<<3) |
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#define TRB_SIZE 16 |
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typedef struct XHCITRB { |
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uint64_t parameter; |
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uint32_t status; |
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uint32_t control; |
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dma_addr_t addr; |
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bool ccs;
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} XHCITRB; |
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typedef enum TRBType { |
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TRB_RESERVED = 0,
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TR_NORMAL, |
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TR_SETUP, |
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TR_DATA, |
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TR_STATUS, |
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TR_ISOCH, |
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TR_LINK, |
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TR_EVDATA, |
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TR_NOOP, |
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CR_ENABLE_SLOT, |
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CR_DISABLE_SLOT, |
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CR_ADDRESS_DEVICE, |
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CR_CONFIGURE_ENDPOINT, |
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CR_EVALUATE_CONTEXT, |
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CR_RESET_ENDPOINT, |
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CR_STOP_ENDPOINT, |
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CR_SET_TR_DEQUEUE, |
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CR_RESET_DEVICE, |
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CR_FORCE_EVENT, |
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CR_NEGOTIATE_BW, |
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CR_SET_LATENCY_TOLERANCE, |
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CR_GET_PORT_BANDWIDTH, |
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CR_FORCE_HEADER, |
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CR_NOOP, |
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ER_TRANSFER = 32,
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ER_COMMAND_COMPLETE, |
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ER_PORT_STATUS_CHANGE, |
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ER_BANDWIDTH_REQUEST, |
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ER_DOORBELL, |
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ER_HOST_CONTROLLER, |
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ER_DEVICE_NOTIFICATION, |
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ER_MFINDEX_WRAP, |
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/* vendor specific bits */
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CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
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CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
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CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
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} TRBType; |
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#define CR_LINK TR_LINK
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typedef enum TRBCCode { |
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CC_INVALID = 0,
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CC_SUCCESS, |
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CC_DATA_BUFFER_ERROR, |
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CC_BABBLE_DETECTED, |
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CC_USB_TRANSACTION_ERROR, |
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CC_TRB_ERROR, |
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CC_STALL_ERROR, |
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CC_RESOURCE_ERROR, |
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CC_BANDWIDTH_ERROR, |
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CC_NO_SLOTS_ERROR, |
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CC_INVALID_STREAM_TYPE_ERROR, |
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CC_SLOT_NOT_ENABLED_ERROR, |
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CC_EP_NOT_ENABLED_ERROR, |
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CC_SHORT_PACKET, |
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CC_RING_UNDERRUN, |
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CC_RING_OVERRUN, |
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CC_VF_ER_FULL, |
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CC_PARAMETER_ERROR, |
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CC_BANDWIDTH_OVERRUN, |
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CC_CONTEXT_STATE_ERROR, |
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CC_NO_PING_RESPONSE_ERROR, |
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CC_EVENT_RING_FULL_ERROR, |
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CC_INCOMPATIBLE_DEVICE_ERROR, |
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CC_MISSED_SERVICE_ERROR, |
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CC_COMMAND_RING_STOPPED, |
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CC_COMMAND_ABORTED, |
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CC_STOPPED, |
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CC_STOPPED_LENGTH_INVALID, |
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CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
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CC_ISOCH_BUFFER_OVERRUN = 31,
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CC_EVENT_LOST_ERROR, |
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CC_UNDEFINED_ERROR, |
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CC_INVALID_STREAM_ID_ERROR, |
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CC_SECONDARY_BANDWIDTH_ERROR, |
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CC_SPLIT_TRANSACTION_ERROR |
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} TRBCCode; |
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#define TRB_C (1<<0) |
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#define TRB_TYPE_SHIFT 10 |
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#define TRB_TYPE_MASK 0x3f |
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#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
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#define TRB_EV_ED (1<<2) |
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#define TRB_TR_ENT (1<<1) |
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#define TRB_TR_ISP (1<<2) |
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#define TRB_TR_NS (1<<3) |
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#define TRB_TR_CH (1<<4) |
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#define TRB_TR_IOC (1<<5) |
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#define TRB_TR_IDT (1<<6) |
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#define TRB_TR_TBC_SHIFT 7 |
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#define TRB_TR_TBC_MASK 0x3 |
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#define TRB_TR_BEI (1<<9) |
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#define TRB_TR_TLBPC_SHIFT 16 |
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#define TRB_TR_TLBPC_MASK 0xf |
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#define TRB_TR_FRAMEID_SHIFT 20 |
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#define TRB_TR_FRAMEID_MASK 0x7ff |
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#define TRB_TR_SIA (1<<31) |
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#define TRB_TR_DIR (1<<16) |
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#define TRB_CR_SLOTID_SHIFT 24 |
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#define TRB_CR_SLOTID_MASK 0xff |
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#define TRB_CR_EPID_SHIFT 16 |
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#define TRB_CR_EPID_MASK 0x1f |
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#define TRB_CR_BSR (1<<9) |
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#define TRB_CR_DC (1<<9) |
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#define TRB_LK_TC (1<<1) |
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#define EP_TYPE_MASK 0x7 |
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#define EP_TYPE_SHIFT 3 |
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#define EP_STATE_MASK 0x7 |
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#define EP_DISABLED (0<<0) |
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#define EP_RUNNING (1<<0) |
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#define EP_HALTED (2<<0) |
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#define EP_STOPPED (3<<0) |
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#define EP_ERROR (4<<0) |
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#define SLOT_STATE_MASK 0x1f |
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#define SLOT_STATE_SHIFT 27 |
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#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
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#define SLOT_ENABLED 0 |
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#define SLOT_DEFAULT 1 |
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#define SLOT_ADDRESSED 2 |
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#define SLOT_CONFIGURED 3 |
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#define SLOT_CONTEXT_ENTRIES_MASK 0x1f |
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#define SLOT_CONTEXT_ENTRIES_SHIFT 27 |
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typedef enum EPType { |
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ET_INVALID = 0,
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ET_ISO_OUT, |
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ET_BULK_OUT, |
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ET_INTR_OUT, |
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ET_CONTROL, |
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ET_ISO_IN, |
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ET_BULK_IN, |
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ET_INTR_IN, |
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} EPType; |
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typedef struct XHCIRing { |
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dma_addr_t base; |
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dma_addr_t dequeue; |
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bool ccs;
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} XHCIRing; |
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typedef struct XHCIPort { |
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uint32_t portsc; |
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uint32_t portnr; |
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USBPort *uport; |
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uint32_t speedmask; |
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} XHCIPort; |
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struct XHCIState;
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typedef struct XHCIState XHCIState; |
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typedef struct XHCITransfer { |
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XHCIState *xhci; |
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USBPacket packet; |
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QEMUSGList sgl; |
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bool running_async;
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bool running_retry;
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bool cancelled;
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bool complete;
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unsigned int iso_pkts; |
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unsigned int slotid; |
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unsigned int epid; |
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bool in_xfer;
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bool iso_xfer;
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unsigned int trb_count; |
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unsigned int trb_alloced; |
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XHCITRB *trbs; |
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TRBCCode status; |
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unsigned int pkts; |
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unsigned int pktsize; |
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unsigned int cur_pkt; |
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uint64_t mfindex_kick; |
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} XHCITransfer; |
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typedef struct XHCIEPContext { |
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XHCIState *xhci; |
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unsigned int slotid; |
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unsigned int epid; |
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XHCIRing ring; |
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unsigned int next_xfer; |
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unsigned int comp_xfer; |
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XHCITransfer transfers[TD_QUEUE]; |
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XHCITransfer *retry; |
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EPType type; |
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dma_addr_t pctx; |
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unsigned int max_psize; |
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uint32_t state; |
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/* iso xfer scheduling */
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unsigned int interval; |
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int64_t mfindex_last; |
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QEMUTimer *kick_timer; |
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} XHCIEPContext; |
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typedef struct XHCISlot { |
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bool enabled;
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dma_addr_t ctx; |
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unsigned int port; |
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unsigned int devaddr; |
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XHCIEPContext * eps[31];
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} XHCISlot; |
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typedef struct XHCIEvent { |
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TRBType type; |
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TRBCCode ccode; |
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uint64_t ptr; |
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uint32_t length; |
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uint32_t flags; |
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uint8_t slotid; |
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uint8_t epid; |
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} XHCIEvent; |
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struct XHCIState {
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PCIDevice pci_dev; |
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USBBus bus; |
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qemu_irq irq; |
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MemoryRegion mem; |
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const char *name; |
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unsigned int devaddr; |
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/* properties */
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uint32_t numports_2; |
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uint32_t numports_3; |
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uint32_t msi; |
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/* Operational Registers */
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uint32_t usbcmd; |
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uint32_t usbsts; |
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uint32_t dnctrl; |
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uint32_t crcr_low; |
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uint32_t crcr_high; |
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uint32_t dcbaap_low; |
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uint32_t dcbaap_high; |
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uint32_t config; |
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USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; |
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XHCIPort ports[MAXPORTS]; |
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XHCISlot slots[MAXSLOTS]; |
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uint32_t numports; |
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|
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/* Runtime Registers */
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uint32_t iman; |
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uint32_t imod; |
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uint32_t erstsz; |
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uint32_t erstba_low; |
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uint32_t erstba_high; |
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uint32_t erdp_low; |
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uint32_t erdp_high; |
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|
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int64_t mfindex_start; |
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QEMUTimer *mfwrap_timer; |
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|
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dma_addr_t er_start; |
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uint32_t er_size; |
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bool er_pcs;
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unsigned int er_ep_idx; |
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bool er_full;
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|
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XHCIEvent ev_buffer[EV_QUEUE]; |
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unsigned int ev_buffer_put; |
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unsigned int ev_buffer_get; |
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|
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XHCIRing cmd_ring; |
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}; |
430 |
|
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typedef struct XHCIEvRingSeg { |
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uint32_t addr_low; |
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uint32_t addr_high; |
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uint32_t size; |
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uint32_t rsvd; |
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} XHCIEvRingSeg; |
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|
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static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
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unsigned int epid); |
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static void xhci_event(XHCIState *xhci, XHCIEvent *event); |
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static void xhci_write_event(XHCIState *xhci, XHCIEvent *event); |
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|
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static const char *TRBType_names[] = { |
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[TRB_RESERVED] = "TRB_RESERVED",
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[TR_NORMAL] = "TR_NORMAL",
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[TR_SETUP] = "TR_SETUP",
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[TR_DATA] = "TR_DATA",
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[TR_STATUS] = "TR_STATUS",
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[TR_ISOCH] = "TR_ISOCH",
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[TR_LINK] = "TR_LINK",
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[TR_EVDATA] = "TR_EVDATA",
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[TR_NOOP] = "TR_NOOP",
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[CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
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[CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
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[CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
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[CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
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[CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
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[CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
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[CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
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[CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
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[CR_RESET_DEVICE] = "CR_RESET_DEVICE",
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[CR_FORCE_EVENT] = "CR_FORCE_EVENT",
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[CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
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[CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
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[CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
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[CR_FORCE_HEADER] = "CR_FORCE_HEADER",
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[CR_NOOP] = "CR_NOOP",
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[ER_TRANSFER] = "ER_TRANSFER",
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[ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
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[ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
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[ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
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[ER_DOORBELL] = "ER_DOORBELL",
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[ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
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[ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
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[ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
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[CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
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[CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
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[CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
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}; |
480 |
|
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static const char *TRBCCode_names[] = { |
482 |
[CC_INVALID] = "CC_INVALID",
|
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[CC_SUCCESS] = "CC_SUCCESS",
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[CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
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[CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
|
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[CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
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[CC_TRB_ERROR] = "CC_TRB_ERROR",
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[CC_STALL_ERROR] = "CC_STALL_ERROR",
|
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[CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
|
490 |
[CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
|
491 |
[CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
|
492 |
[CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
|
493 |
[CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
|
494 |
[CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
|
495 |
[CC_SHORT_PACKET] = "CC_SHORT_PACKET",
|
496 |
[CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
|
497 |
[CC_RING_OVERRUN] = "CC_RING_OVERRUN",
|
498 |
[CC_VF_ER_FULL] = "CC_VF_ER_FULL",
|
499 |
[CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
|
500 |
[CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
|
501 |
[CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
|
502 |
[CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
|
503 |
[CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
|
504 |
[CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
|
505 |
[CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
|
506 |
[CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
|
507 |
[CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
|
508 |
[CC_STOPPED] = "CC_STOPPED",
|
509 |
[CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
|
510 |
[CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] |
511 |
= "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
|
512 |
[CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
|
513 |
[CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
|
514 |
[CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
|
515 |
[CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
|
516 |
[CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
|
517 |
[CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
|
518 |
}; |
519 |
|
520 |
static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
521 |
{ |
522 |
if (index >= llen || list[index] == NULL) { |
523 |
return "???"; |
524 |
} |
525 |
return list[index];
|
526 |
} |
527 |
|
528 |
static const char *trb_name(XHCITRB *trb) |
529 |
{ |
530 |
return lookup_name(TRB_TYPE(*trb), TRBType_names,
|
531 |
ARRAY_SIZE(TRBType_names)); |
532 |
} |
533 |
|
534 |
static const char *event_name(XHCIEvent *event) |
535 |
{ |
536 |
return lookup_name(event->ccode, TRBCCode_names,
|
537 |
ARRAY_SIZE(TRBCCode_names)); |
538 |
} |
539 |
|
540 |
static uint64_t xhci_mfindex_get(XHCIState *xhci)
|
541 |
{ |
542 |
int64_t now = qemu_get_clock_ns(vm_clock); |
543 |
return (now - xhci->mfindex_start) / 125000; |
544 |
} |
545 |
|
546 |
static void xhci_mfwrap_update(XHCIState *xhci) |
547 |
{ |
548 |
const uint32_t bits = USBCMD_RS | USBCMD_EWE;
|
549 |
uint32_t mfindex, left; |
550 |
int64_t now; |
551 |
|
552 |
if ((xhci->usbcmd & bits) == bits) {
|
553 |
now = qemu_get_clock_ns(vm_clock); |
554 |
mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; |
555 |
left = 0x4000 - mfindex;
|
556 |
qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
|
557 |
} else {
|
558 |
qemu_del_timer(xhci->mfwrap_timer); |
559 |
} |
560 |
} |
561 |
|
562 |
static void xhci_mfwrap_timer(void *opaque) |
563 |
{ |
564 |
XHCIState *xhci = opaque; |
565 |
XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; |
566 |
|
567 |
xhci_event(xhci, &wrap); |
568 |
xhci_mfwrap_update(xhci); |
569 |
} |
570 |
|
571 |
static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) |
572 |
{ |
573 |
if (sizeof(dma_addr_t) == 4) { |
574 |
return low;
|
575 |
} else {
|
576 |
return low | (((dma_addr_t)high << 16) << 16); |
577 |
} |
578 |
} |
579 |
|
580 |
static inline dma_addr_t xhci_mask64(uint64_t addr) |
581 |
{ |
582 |
if (sizeof(dma_addr_t) == 4) { |
583 |
return addr & 0xffffffff; |
584 |
} else {
|
585 |
return addr;
|
586 |
} |
587 |
} |
588 |
|
589 |
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) |
590 |
{ |
591 |
int index;
|
592 |
|
593 |
if (!uport->dev) {
|
594 |
return NULL; |
595 |
} |
596 |
switch (uport->dev->speed) {
|
597 |
case USB_SPEED_LOW:
|
598 |
case USB_SPEED_FULL:
|
599 |
case USB_SPEED_HIGH:
|
600 |
index = uport->index; |
601 |
break;
|
602 |
case USB_SPEED_SUPER:
|
603 |
index = uport->index + xhci->numports_2; |
604 |
break;
|
605 |
default:
|
606 |
return NULL; |
607 |
} |
608 |
return &xhci->ports[index];
|
609 |
} |
610 |
|
611 |
static void xhci_irq_update(XHCIState *xhci) |
612 |
{ |
613 |
int level = 0; |
614 |
|
615 |
if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
|
616 |
xhci->usbcmd & USBCMD_INTE) { |
617 |
level = 1;
|
618 |
} |
619 |
|
620 |
if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
|
621 |
if (level) {
|
622 |
trace_usb_xhci_irq_msi(0);
|
623 |
msi_notify(&xhci->pci_dev, 0);
|
624 |
} |
625 |
} else {
|
626 |
trace_usb_xhci_irq_intx(level); |
627 |
qemu_set_irq(xhci->irq, level); |
628 |
} |
629 |
} |
630 |
|
631 |
static inline int xhci_running(XHCIState *xhci) |
632 |
{ |
633 |
return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
|
634 |
} |
635 |
|
636 |
static void xhci_die(XHCIState *xhci) |
637 |
{ |
638 |
xhci->usbsts |= USBSTS_HCE; |
639 |
fprintf(stderr, "xhci: asserted controller error\n");
|
640 |
} |
641 |
|
642 |
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event) |
643 |
{ |
644 |
XHCITRB ev_trb; |
645 |
dma_addr_t addr; |
646 |
|
647 |
ev_trb.parameter = cpu_to_le64(event->ptr); |
648 |
ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
|
649 |
ev_trb.control = (event->slotid << 24) | (event->epid << 16) | |
650 |
event->flags | (event->type << TRB_TYPE_SHIFT); |
651 |
if (xhci->er_pcs) {
|
652 |
ev_trb.control |= TRB_C; |
653 |
} |
654 |
ev_trb.control = cpu_to_le32(ev_trb.control); |
655 |
|
656 |
trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb), |
657 |
event_name(event), ev_trb.parameter, |
658 |
ev_trb.status, ev_trb.control); |
659 |
|
660 |
addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx; |
661 |
pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); |
662 |
|
663 |
xhci->er_ep_idx++; |
664 |
if (xhci->er_ep_idx >= xhci->er_size) {
|
665 |
xhci->er_ep_idx = 0;
|
666 |
xhci->er_pcs = !xhci->er_pcs; |
667 |
} |
668 |
} |
669 |
|
670 |
static void xhci_events_update(XHCIState *xhci) |
671 |
{ |
672 |
dma_addr_t erdp; |
673 |
unsigned int dp_idx; |
674 |
bool do_irq = 0; |
675 |
|
676 |
if (xhci->usbsts & USBSTS_HCH) {
|
677 |
return;
|
678 |
} |
679 |
|
680 |
erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); |
681 |
if (erdp < xhci->er_start ||
|
682 |
erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { |
683 |
fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
684 |
fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n", |
685 |
xhci->er_start, xhci->er_size); |
686 |
xhci_die(xhci); |
687 |
return;
|
688 |
} |
689 |
dp_idx = (erdp - xhci->er_start) / TRB_SIZE; |
690 |
assert(dp_idx < xhci->er_size); |
691 |
|
692 |
/* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
|
693 |
* deadlocks when the ER is full. Hack it by holding off events until
|
694 |
* the driver decides to free at least half of the ring */
|
695 |
if (xhci->er_full) {
|
696 |
int er_free = dp_idx - xhci->er_ep_idx;
|
697 |
if (er_free <= 0) { |
698 |
er_free += xhci->er_size; |
699 |
} |
700 |
if (er_free < (xhci->er_size/2)) { |
701 |
DPRINTF("xhci_events_update(): event ring still "
|
702 |
"more than half full (hack)\n");
|
703 |
return;
|
704 |
} |
705 |
} |
706 |
|
707 |
while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
|
708 |
assert(xhci->er_full); |
709 |
if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) { |
710 |
DPRINTF("xhci_events_update(): event ring full again\n");
|
711 |
#ifndef ER_FULL_HACK
|
712 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; |
713 |
xhci_write_event(xhci, &full); |
714 |
#endif
|
715 |
do_irq = 1;
|
716 |
break;
|
717 |
} |
718 |
XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get]; |
719 |
xhci_write_event(xhci, event); |
720 |
xhci->ev_buffer_get++; |
721 |
do_irq = 1;
|
722 |
if (xhci->ev_buffer_get == EV_QUEUE) {
|
723 |
xhci->ev_buffer_get = 0;
|
724 |
} |
725 |
} |
726 |
|
727 |
if (do_irq) {
|
728 |
xhci->erdp_low |= ERDP_EHB; |
729 |
xhci->iman |= IMAN_IP; |
730 |
xhci->usbsts |= USBSTS_EINT; |
731 |
xhci_irq_update(xhci); |
732 |
} |
733 |
|
734 |
if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
|
735 |
DPRINTF("xhci_events_update(): event ring no longer full\n");
|
736 |
xhci->er_full = 0;
|
737 |
} |
738 |
return;
|
739 |
} |
740 |
|
741 |
static void xhci_event(XHCIState *xhci, XHCIEvent *event) |
742 |
{ |
743 |
dma_addr_t erdp; |
744 |
unsigned int dp_idx; |
745 |
|
746 |
if (xhci->er_full) {
|
747 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
748 |
if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { |
749 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
750 |
return;
|
751 |
} |
752 |
xhci->ev_buffer[xhci->ev_buffer_put++] = *event; |
753 |
if (xhci->ev_buffer_put == EV_QUEUE) {
|
754 |
xhci->ev_buffer_put = 0;
|
755 |
} |
756 |
return;
|
757 |
} |
758 |
|
759 |
erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); |
760 |
if (erdp < xhci->er_start ||
|
761 |
erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { |
762 |
fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
763 |
fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n", |
764 |
xhci->er_start, xhci->er_size); |
765 |
xhci_die(xhci); |
766 |
return;
|
767 |
} |
768 |
|
769 |
dp_idx = (erdp - xhci->er_start) / TRB_SIZE; |
770 |
assert(dp_idx < xhci->er_size); |
771 |
|
772 |
if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) { |
773 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
774 |
#ifndef ER_FULL_HACK
|
775 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; |
776 |
xhci_write_event(xhci, &full); |
777 |
#endif
|
778 |
xhci->er_full = 1;
|
779 |
if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { |
780 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
781 |
return;
|
782 |
} |
783 |
xhci->ev_buffer[xhci->ev_buffer_put++] = *event; |
784 |
if (xhci->ev_buffer_put == EV_QUEUE) {
|
785 |
xhci->ev_buffer_put = 0;
|
786 |
} |
787 |
} else {
|
788 |
xhci_write_event(xhci, event); |
789 |
} |
790 |
|
791 |
xhci->erdp_low |= ERDP_EHB; |
792 |
xhci->iman |= IMAN_IP; |
793 |
xhci->usbsts |= USBSTS_EINT; |
794 |
|
795 |
xhci_irq_update(xhci); |
796 |
} |
797 |
|
798 |
static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, |
799 |
dma_addr_t base) |
800 |
{ |
801 |
ring->base = base; |
802 |
ring->dequeue = base; |
803 |
ring->ccs = 1;
|
804 |
} |
805 |
|
806 |
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
|
807 |
dma_addr_t *addr) |
808 |
{ |
809 |
while (1) { |
810 |
TRBType type; |
811 |
pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); |
812 |
trb->addr = ring->dequeue; |
813 |
trb->ccs = ring->ccs; |
814 |
le64_to_cpus(&trb->parameter); |
815 |
le32_to_cpus(&trb->status); |
816 |
le32_to_cpus(&trb->control); |
817 |
|
818 |
trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), |
819 |
trb->parameter, trb->status, trb->control); |
820 |
|
821 |
if ((trb->control & TRB_C) != ring->ccs) {
|
822 |
return 0; |
823 |
} |
824 |
|
825 |
type = TRB_TYPE(*trb); |
826 |
|
827 |
if (type != TR_LINK) {
|
828 |
if (addr) {
|
829 |
*addr = ring->dequeue; |
830 |
} |
831 |
ring->dequeue += TRB_SIZE; |
832 |
return type;
|
833 |
} else {
|
834 |
ring->dequeue = xhci_mask64(trb->parameter); |
835 |
if (trb->control & TRB_LK_TC) {
|
836 |
ring->ccs = !ring->ccs; |
837 |
} |
838 |
} |
839 |
} |
840 |
} |
841 |
|
842 |
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) |
843 |
{ |
844 |
XHCITRB trb; |
845 |
int length = 0; |
846 |
dma_addr_t dequeue = ring->dequeue; |
847 |
bool ccs = ring->ccs;
|
848 |
/* hack to bundle together the two/three TDs that make a setup transfer */
|
849 |
bool control_td_set = 0; |
850 |
|
851 |
while (1) { |
852 |
TRBType type; |
853 |
pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); |
854 |
le64_to_cpus(&trb.parameter); |
855 |
le32_to_cpus(&trb.status); |
856 |
le32_to_cpus(&trb.control); |
857 |
|
858 |
if ((trb.control & TRB_C) != ccs) {
|
859 |
return -length;
|
860 |
} |
861 |
|
862 |
type = TRB_TYPE(trb); |
863 |
|
864 |
if (type == TR_LINK) {
|
865 |
dequeue = xhci_mask64(trb.parameter); |
866 |
if (trb.control & TRB_LK_TC) {
|
867 |
ccs = !ccs; |
868 |
} |
869 |
continue;
|
870 |
} |
871 |
|
872 |
length += 1;
|
873 |
dequeue += TRB_SIZE; |
874 |
|
875 |
if (type == TR_SETUP) {
|
876 |
control_td_set = 1;
|
877 |
} else if (type == TR_STATUS) { |
878 |
control_td_set = 0;
|
879 |
} |
880 |
|
881 |
if (!control_td_set && !(trb.control & TRB_TR_CH)) {
|
882 |
return length;
|
883 |
} |
884 |
} |
885 |
} |
886 |
|
887 |
static void xhci_er_reset(XHCIState *xhci) |
888 |
{ |
889 |
XHCIEvRingSeg seg; |
890 |
|
891 |
/* cache the (sole) event ring segment location */
|
892 |
if (xhci->erstsz != 1) { |
893 |
fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
|
894 |
xhci_die(xhci); |
895 |
return;
|
896 |
} |
897 |
dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high); |
898 |
pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
|
899 |
le32_to_cpus(&seg.addr_low); |
900 |
le32_to_cpus(&seg.addr_high); |
901 |
le32_to_cpus(&seg.size); |
902 |
if (seg.size < 16 || seg.size > 4096) { |
903 |
fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
|
904 |
xhci_die(xhci); |
905 |
return;
|
906 |
} |
907 |
xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
908 |
xhci->er_size = seg.size; |
909 |
|
910 |
xhci->er_ep_idx = 0;
|
911 |
xhci->er_pcs = 1;
|
912 |
xhci->er_full = 0;
|
913 |
|
914 |
DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n", |
915 |
xhci->er_start, xhci->er_size); |
916 |
} |
917 |
|
918 |
static void xhci_run(XHCIState *xhci) |
919 |
{ |
920 |
trace_usb_xhci_run(); |
921 |
xhci->usbsts &= ~USBSTS_HCH; |
922 |
xhci->mfindex_start = qemu_get_clock_ns(vm_clock); |
923 |
} |
924 |
|
925 |
static void xhci_stop(XHCIState *xhci) |
926 |
{ |
927 |
trace_usb_xhci_stop(); |
928 |
xhci->usbsts |= USBSTS_HCH; |
929 |
xhci->crcr_low &= ~CRCR_CRR; |
930 |
} |
931 |
|
932 |
static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
933 |
uint32_t state) |
934 |
{ |
935 |
uint32_t ctx[5];
|
936 |
if (epctx->state == state) {
|
937 |
return;
|
938 |
} |
939 |
|
940 |
pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
|
941 |
ctx[0] &= ~EP_STATE_MASK;
|
942 |
ctx[0] |= state;
|
943 |
ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
|
944 |
ctx[3] = (epctx->ring.dequeue >> 16) >> 16; |
945 |
DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", |
946 |
epctx->pctx, state, ctx[3], ctx[2]); |
947 |
pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
|
948 |
epctx->state = state; |
949 |
} |
950 |
|
951 |
static void xhci_ep_kick_timer(void *opaque) |
952 |
{ |
953 |
XHCIEPContext *epctx = opaque; |
954 |
xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); |
955 |
} |
956 |
|
957 |
static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, |
958 |
unsigned int epid, dma_addr_t pctx, |
959 |
uint32_t *ctx) |
960 |
{ |
961 |
XHCISlot *slot; |
962 |
XHCIEPContext *epctx; |
963 |
dma_addr_t dequeue; |
964 |
int i;
|
965 |
|
966 |
trace_usb_xhci_ep_enable(slotid, epid); |
967 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
968 |
assert(epid >= 1 && epid <= 31); |
969 |
|
970 |
slot = &xhci->slots[slotid-1];
|
971 |
if (slot->eps[epid-1]) { |
972 |
fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
|
973 |
return CC_TRB_ERROR;
|
974 |
} |
975 |
|
976 |
epctx = g_malloc(sizeof(XHCIEPContext));
|
977 |
memset(epctx, 0, sizeof(XHCIEPContext)); |
978 |
epctx->xhci = xhci; |
979 |
epctx->slotid = slotid; |
980 |
epctx->epid = epid; |
981 |
|
982 |
slot->eps[epid-1] = epctx;
|
983 |
|
984 |
dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); |
985 |
xhci_ring_init(xhci, &epctx->ring, dequeue); |
986 |
epctx->ring.ccs = ctx[2] & 1; |
987 |
|
988 |
epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
|
989 |
DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); |
990 |
epctx->pctx = pctx; |
991 |
epctx->max_psize = ctx[1]>>16; |
992 |
epctx->max_psize *= 1+((ctx[1]>>8)&0xff); |
993 |
DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
|
994 |
epid/2, epid%2, epctx->max_psize); |
995 |
for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { |
996 |
usb_packet_init(&epctx->transfers[i].packet); |
997 |
} |
998 |
|
999 |
epctx->interval = 1 << (ctx[0] >> 16) & 0xff; |
1000 |
epctx->mfindex_last = 0;
|
1001 |
epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); |
1002 |
|
1003 |
epctx->state = EP_RUNNING; |
1004 |
ctx[0] &= ~EP_STATE_MASK;
|
1005 |
ctx[0] |= EP_RUNNING;
|
1006 |
|
1007 |
return CC_SUCCESS;
|
1008 |
} |
1009 |
|
1010 |
static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
1011 |
unsigned int epid) |
1012 |
{ |
1013 |
XHCISlot *slot; |
1014 |
XHCIEPContext *epctx; |
1015 |
int i, xferi, killed = 0; |
1016 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1017 |
assert(epid >= 1 && epid <= 31); |
1018 |
|
1019 |
DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
|
1020 |
|
1021 |
slot = &xhci->slots[slotid-1];
|
1022 |
|
1023 |
if (!slot->eps[epid-1]) { |
1024 |
return 0; |
1025 |
} |
1026 |
|
1027 |
epctx = slot->eps[epid-1];
|
1028 |
|
1029 |
xferi = epctx->next_xfer; |
1030 |
for (i = 0; i < TD_QUEUE; i++) { |
1031 |
XHCITransfer *t = &epctx->transfers[xferi]; |
1032 |
if (t->running_async) {
|
1033 |
usb_cancel_packet(&t->packet); |
1034 |
t->running_async = 0;
|
1035 |
t->cancelled = 1;
|
1036 |
DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
|
1037 |
killed++; |
1038 |
} |
1039 |
if (t->running_retry) {
|
1040 |
t->running_retry = 0;
|
1041 |
epctx->retry = NULL;
|
1042 |
qemu_del_timer(epctx->kick_timer); |
1043 |
} |
1044 |
if (t->trbs) {
|
1045 |
g_free(t->trbs); |
1046 |
} |
1047 |
|
1048 |
t->trbs = NULL;
|
1049 |
t->trb_count = t->trb_alloced = 0;
|
1050 |
xferi = (xferi + 1) % TD_QUEUE;
|
1051 |
} |
1052 |
return killed;
|
1053 |
} |
1054 |
|
1055 |
static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
1056 |
unsigned int epid) |
1057 |
{ |
1058 |
XHCISlot *slot; |
1059 |
XHCIEPContext *epctx; |
1060 |
|
1061 |
trace_usb_xhci_ep_disable(slotid, epid); |
1062 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1063 |
assert(epid >= 1 && epid <= 31); |
1064 |
|
1065 |
slot = &xhci->slots[slotid-1];
|
1066 |
|
1067 |
if (!slot->eps[epid-1]) { |
1068 |
DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
|
1069 |
return CC_SUCCESS;
|
1070 |
} |
1071 |
|
1072 |
xhci_ep_nuke_xfers(xhci, slotid, epid); |
1073 |
|
1074 |
epctx = slot->eps[epid-1];
|
1075 |
|
1076 |
xhci_set_ep_state(xhci, epctx, EP_DISABLED); |
1077 |
|
1078 |
qemu_free_timer(epctx->kick_timer); |
1079 |
g_free(epctx); |
1080 |
slot->eps[epid-1] = NULL; |
1081 |
|
1082 |
return CC_SUCCESS;
|
1083 |
} |
1084 |
|
1085 |
static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, |
1086 |
unsigned int epid) |
1087 |
{ |
1088 |
XHCISlot *slot; |
1089 |
XHCIEPContext *epctx; |
1090 |
|
1091 |
trace_usb_xhci_ep_stop(slotid, epid); |
1092 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1093 |
|
1094 |
if (epid < 1 || epid > 31) { |
1095 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1096 |
return CC_TRB_ERROR;
|
1097 |
} |
1098 |
|
1099 |
slot = &xhci->slots[slotid-1];
|
1100 |
|
1101 |
if (!slot->eps[epid-1]) { |
1102 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1103 |
return CC_EP_NOT_ENABLED_ERROR;
|
1104 |
} |
1105 |
|
1106 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
1107 |
fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
|
1108 |
"data might be lost\n");
|
1109 |
} |
1110 |
|
1111 |
epctx = slot->eps[epid-1];
|
1112 |
|
1113 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1114 |
|
1115 |
return CC_SUCCESS;
|
1116 |
} |
1117 |
|
1118 |
static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, |
1119 |
unsigned int epid) |
1120 |
{ |
1121 |
XHCISlot *slot; |
1122 |
XHCIEPContext *epctx; |
1123 |
USBDevice *dev; |
1124 |
|
1125 |
trace_usb_xhci_ep_reset(slotid, epid); |
1126 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1127 |
|
1128 |
if (epid < 1 || epid > 31) { |
1129 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1130 |
return CC_TRB_ERROR;
|
1131 |
} |
1132 |
|
1133 |
slot = &xhci->slots[slotid-1];
|
1134 |
|
1135 |
if (!slot->eps[epid-1]) { |
1136 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1137 |
return CC_EP_NOT_ENABLED_ERROR;
|
1138 |
} |
1139 |
|
1140 |
epctx = slot->eps[epid-1];
|
1141 |
|
1142 |
if (epctx->state != EP_HALTED) {
|
1143 |
fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
|
1144 |
epid, epctx->state); |
1145 |
return CC_CONTEXT_STATE_ERROR;
|
1146 |
} |
1147 |
|
1148 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
1149 |
fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
|
1150 |
"data might be lost\n");
|
1151 |
} |
1152 |
|
1153 |
uint8_t ep = epid>>1;
|
1154 |
|
1155 |
if (epid & 1) { |
1156 |
ep |= 0x80;
|
1157 |
} |
1158 |
|
1159 |
dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev; |
1160 |
if (!dev) {
|
1161 |
return CC_USB_TRANSACTION_ERROR;
|
1162 |
} |
1163 |
|
1164 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1165 |
|
1166 |
return CC_SUCCESS;
|
1167 |
} |
1168 |
|
1169 |
static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, |
1170 |
unsigned int epid, uint64_t pdequeue) |
1171 |
{ |
1172 |
XHCISlot *slot; |
1173 |
XHCIEPContext *epctx; |
1174 |
dma_addr_t dequeue; |
1175 |
|
1176 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1177 |
|
1178 |
if (epid < 1 || epid > 31) { |
1179 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1180 |
return CC_TRB_ERROR;
|
1181 |
} |
1182 |
|
1183 |
trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); |
1184 |
dequeue = xhci_mask64(pdequeue); |
1185 |
|
1186 |
slot = &xhci->slots[slotid-1];
|
1187 |
|
1188 |
if (!slot->eps[epid-1]) { |
1189 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1190 |
return CC_EP_NOT_ENABLED_ERROR;
|
1191 |
} |
1192 |
|
1193 |
epctx = slot->eps[epid-1];
|
1194 |
|
1195 |
|
1196 |
if (epctx->state != EP_STOPPED) {
|
1197 |
fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
|
1198 |
return CC_CONTEXT_STATE_ERROR;
|
1199 |
} |
1200 |
|
1201 |
xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
|
1202 |
epctx->ring.ccs = dequeue & 1;
|
1203 |
|
1204 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1205 |
|
1206 |
return CC_SUCCESS;
|
1207 |
} |
1208 |
|
1209 |
static int xhci_xfer_map(XHCITransfer *xfer) |
1210 |
{ |
1211 |
int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
|
1212 |
XHCIState *xhci = xfer->xhci; |
1213 |
int i;
|
1214 |
|
1215 |
pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); |
1216 |
for (i = 0; i < xfer->trb_count; i++) { |
1217 |
XHCITRB *trb = &xfer->trbs[i]; |
1218 |
dma_addr_t addr; |
1219 |
unsigned int chunk = 0; |
1220 |
|
1221 |
switch (TRB_TYPE(*trb)) {
|
1222 |
case TR_DATA:
|
1223 |
if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
|
1224 |
fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
|
1225 |
goto err;
|
1226 |
} |
1227 |
/* fallthrough */
|
1228 |
case TR_NORMAL:
|
1229 |
case TR_ISOCH:
|
1230 |
addr = xhci_mask64(trb->parameter); |
1231 |
chunk = trb->status & 0x1ffff;
|
1232 |
if (trb->control & TRB_TR_IDT) {
|
1233 |
if (chunk > 8 || in_xfer) { |
1234 |
fprintf(stderr, "xhci: invalid immediate data TRB\n");
|
1235 |
goto err;
|
1236 |
} |
1237 |
qemu_sglist_add(&xfer->sgl, trb->addr, chunk); |
1238 |
} else {
|
1239 |
qemu_sglist_add(&xfer->sgl, addr, chunk); |
1240 |
} |
1241 |
break;
|
1242 |
} |
1243 |
} |
1244 |
|
1245 |
usb_packet_map(&xfer->packet, &xfer->sgl); |
1246 |
return 0; |
1247 |
|
1248 |
err:
|
1249 |
qemu_sglist_destroy(&xfer->sgl); |
1250 |
xhci_die(xhci); |
1251 |
return -1; |
1252 |
} |
1253 |
|
1254 |
static void xhci_xfer_unmap(XHCITransfer *xfer) |
1255 |
{ |
1256 |
usb_packet_unmap(&xfer->packet, &xfer->sgl); |
1257 |
qemu_sglist_destroy(&xfer->sgl); |
1258 |
} |
1259 |
|
1260 |
static void xhci_xfer_report(XHCITransfer *xfer) |
1261 |
{ |
1262 |
uint32_t edtla = 0;
|
1263 |
unsigned int left; |
1264 |
bool reported = 0; |
1265 |
bool shortpkt = 0; |
1266 |
XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; |
1267 |
XHCIState *xhci = xfer->xhci; |
1268 |
int i;
|
1269 |
|
1270 |
left = xfer->packet.result < 0 ? 0 : xfer->packet.result; |
1271 |
|
1272 |
for (i = 0; i < xfer->trb_count; i++) { |
1273 |
XHCITRB *trb = &xfer->trbs[i]; |
1274 |
unsigned int chunk = 0; |
1275 |
|
1276 |
switch (TRB_TYPE(*trb)) {
|
1277 |
case TR_DATA:
|
1278 |
case TR_NORMAL:
|
1279 |
case TR_ISOCH:
|
1280 |
chunk = trb->status & 0x1ffff;
|
1281 |
if (chunk > left) {
|
1282 |
chunk = left; |
1283 |
if (xfer->status == CC_SUCCESS) {
|
1284 |
shortpkt = 1;
|
1285 |
} |
1286 |
} |
1287 |
left -= chunk; |
1288 |
edtla += chunk; |
1289 |
break;
|
1290 |
case TR_STATUS:
|
1291 |
reported = 0;
|
1292 |
shortpkt = 0;
|
1293 |
break;
|
1294 |
} |
1295 |
|
1296 |
if (!reported && ((trb->control & TRB_TR_IOC) ||
|
1297 |
(shortpkt && (trb->control & TRB_TR_ISP)) || |
1298 |
(xfer->status != CC_SUCCESS))) { |
1299 |
event.slotid = xfer->slotid; |
1300 |
event.epid = xfer->epid; |
1301 |
event.length = (trb->status & 0x1ffff) - chunk;
|
1302 |
event.flags = 0;
|
1303 |
event.ptr = trb->addr; |
1304 |
if (xfer->status == CC_SUCCESS) {
|
1305 |
event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; |
1306 |
} else {
|
1307 |
event.ccode = xfer->status; |
1308 |
} |
1309 |
if (TRB_TYPE(*trb) == TR_EVDATA) {
|
1310 |
event.ptr = trb->parameter; |
1311 |
event.flags |= TRB_EV_ED; |
1312 |
event.length = edtla & 0xffffff;
|
1313 |
DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
|
1314 |
edtla = 0;
|
1315 |
} |
1316 |
xhci_event(xhci, &event); |
1317 |
reported = 1;
|
1318 |
if (xfer->status != CC_SUCCESS) {
|
1319 |
return;
|
1320 |
} |
1321 |
} |
1322 |
} |
1323 |
} |
1324 |
|
1325 |
static void xhci_stall_ep(XHCITransfer *xfer) |
1326 |
{ |
1327 |
XHCIState *xhci = xfer->xhci; |
1328 |
XHCISlot *slot = &xhci->slots[xfer->slotid-1];
|
1329 |
XHCIEPContext *epctx = slot->eps[xfer->epid-1];
|
1330 |
|
1331 |
epctx->ring.dequeue = xfer->trbs[0].addr;
|
1332 |
epctx->ring.ccs = xfer->trbs[0].ccs;
|
1333 |
xhci_set_ep_state(xhci, epctx, EP_HALTED); |
1334 |
DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
|
1335 |
DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); |
1336 |
} |
1337 |
|
1338 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, |
1339 |
XHCIEPContext *epctx); |
1340 |
|
1341 |
static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
|
1342 |
{ |
1343 |
if (!(port->portsc & PORTSC_PED)) {
|
1344 |
return NULL; |
1345 |
} |
1346 |
return usb_find_device(port->uport, addr);
|
1347 |
} |
1348 |
|
1349 |
static int xhci_setup_packet(XHCITransfer *xfer) |
1350 |
{ |
1351 |
XHCIState *xhci = xfer->xhci; |
1352 |
XHCIPort *port; |
1353 |
USBDevice *dev; |
1354 |
USBEndpoint *ep; |
1355 |
int dir;
|
1356 |
|
1357 |
dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; |
1358 |
|
1359 |
if (xfer->packet.ep) {
|
1360 |
ep = xfer->packet.ep; |
1361 |
dev = ep->dev; |
1362 |
} else {
|
1363 |
port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1]; |
1364 |
dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
|
1365 |
if (!dev) {
|
1366 |
fprintf(stderr, "xhci: slot %d port %d has no device\n",
|
1367 |
xfer->slotid, xhci->slots[xfer->slotid-1].port);
|
1368 |
return -1; |
1369 |
} |
1370 |
ep = usb_ep_get(dev, dir, xfer->epid >> 1);
|
1371 |
} |
1372 |
|
1373 |
usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
|
1374 |
xhci_xfer_map(xfer); |
1375 |
DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
|
1376 |
xfer->packet.pid, dev->addr, ep->nr); |
1377 |
return 0; |
1378 |
} |
1379 |
|
1380 |
static int xhci_complete_packet(XHCITransfer *xfer, int ret) |
1381 |
{ |
1382 |
if (ret == USB_RET_ASYNC) {
|
1383 |
trace_usb_xhci_xfer_async(xfer); |
1384 |
xfer->running_async = 1;
|
1385 |
xfer->running_retry = 0;
|
1386 |
xfer->complete = 0;
|
1387 |
xfer->cancelled = 0;
|
1388 |
return 0; |
1389 |
} else if (ret == USB_RET_NAK) { |
1390 |
trace_usb_xhci_xfer_nak(xfer); |
1391 |
xfer->running_async = 0;
|
1392 |
xfer->running_retry = 1;
|
1393 |
xfer->complete = 0;
|
1394 |
xfer->cancelled = 0;
|
1395 |
return 0; |
1396 |
} else {
|
1397 |
xfer->running_async = 0;
|
1398 |
xfer->running_retry = 0;
|
1399 |
xfer->complete = 1;
|
1400 |
xhci_xfer_unmap(xfer); |
1401 |
} |
1402 |
|
1403 |
if (ret >= 0) { |
1404 |
trace_usb_xhci_xfer_success(xfer, ret); |
1405 |
xfer->status = CC_SUCCESS; |
1406 |
xhci_xfer_report(xfer); |
1407 |
return 0; |
1408 |
} |
1409 |
|
1410 |
/* error */
|
1411 |
trace_usb_xhci_xfer_error(xfer, ret); |
1412 |
switch (ret) {
|
1413 |
case USB_RET_NODEV:
|
1414 |
xfer->status = CC_USB_TRANSACTION_ERROR; |
1415 |
xhci_xfer_report(xfer); |
1416 |
xhci_stall_ep(xfer); |
1417 |
break;
|
1418 |
case USB_RET_STALL:
|
1419 |
xfer->status = CC_STALL_ERROR; |
1420 |
xhci_xfer_report(xfer); |
1421 |
xhci_stall_ep(xfer); |
1422 |
break;
|
1423 |
default:
|
1424 |
fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
|
1425 |
FIXME(); |
1426 |
} |
1427 |
return 0; |
1428 |
} |
1429 |
|
1430 |
static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) |
1431 |
{ |
1432 |
XHCITRB *trb_setup, *trb_status; |
1433 |
uint8_t bmRequestType; |
1434 |
int ret;
|
1435 |
|
1436 |
trb_setup = &xfer->trbs[0];
|
1437 |
trb_status = &xfer->trbs[xfer->trb_count-1];
|
1438 |
|
1439 |
trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); |
1440 |
|
1441 |
/* at most one Event Data TRB allowed after STATUS */
|
1442 |
if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { |
1443 |
trb_status--; |
1444 |
} |
1445 |
|
1446 |
/* do some sanity checks */
|
1447 |
if (TRB_TYPE(*trb_setup) != TR_SETUP) {
|
1448 |
fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
|
1449 |
TRB_TYPE(*trb_setup)); |
1450 |
return -1; |
1451 |
} |
1452 |
if (TRB_TYPE(*trb_status) != TR_STATUS) {
|
1453 |
fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
|
1454 |
TRB_TYPE(*trb_status)); |
1455 |
return -1; |
1456 |
} |
1457 |
if (!(trb_setup->control & TRB_TR_IDT)) {
|
1458 |
fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
|
1459 |
return -1; |
1460 |
} |
1461 |
if ((trb_setup->status & 0x1ffff) != 8) { |
1462 |
fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
|
1463 |
(trb_setup->status & 0x1ffff));
|
1464 |
return -1; |
1465 |
} |
1466 |
|
1467 |
bmRequestType = trb_setup->parameter; |
1468 |
|
1469 |
xfer->in_xfer = bmRequestType & USB_DIR_IN; |
1470 |
xfer->iso_xfer = false;
|
1471 |
|
1472 |
if (xhci_setup_packet(xfer) < 0) { |
1473 |
return -1; |
1474 |
} |
1475 |
xfer->packet.parameter = trb_setup->parameter; |
1476 |
|
1477 |
ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1478 |
|
1479 |
xhci_complete_packet(xfer, ret); |
1480 |
if (!xfer->running_async && !xfer->running_retry) {
|
1481 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
1482 |
} |
1483 |
return 0; |
1484 |
} |
1485 |
|
1486 |
static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1487 |
XHCIEPContext *epctx, uint64_t mfindex) |
1488 |
{ |
1489 |
if (xfer->trbs[0].control & TRB_TR_SIA) { |
1490 |
uint64_t asap = ((mfindex + epctx->interval - 1) &
|
1491 |
~(epctx->interval-1));
|
1492 |
if (asap >= epctx->mfindex_last &&
|
1493 |
asap <= epctx->mfindex_last + epctx->interval * 4) {
|
1494 |
xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; |
1495 |
} else {
|
1496 |
xfer->mfindex_kick = asap; |
1497 |
} |
1498 |
} else {
|
1499 |
xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
|
1500 |
& TRB_TR_FRAMEID_MASK; |
1501 |
xfer->mfindex_kick |= mfindex & ~0x3fff;
|
1502 |
if (xfer->mfindex_kick < mfindex) {
|
1503 |
xfer->mfindex_kick += 0x4000;
|
1504 |
} |
1505 |
} |
1506 |
} |
1507 |
|
1508 |
static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1509 |
XHCIEPContext *epctx, uint64_t mfindex) |
1510 |
{ |
1511 |
if (xfer->mfindex_kick > mfindex) {
|
1512 |
qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + |
1513 |
(xfer->mfindex_kick - mfindex) * 125000);
|
1514 |
xfer->running_retry = 1;
|
1515 |
} else {
|
1516 |
epctx->mfindex_last = xfer->mfindex_kick; |
1517 |
qemu_del_timer(epctx->kick_timer); |
1518 |
xfer->running_retry = 0;
|
1519 |
} |
1520 |
} |
1521 |
|
1522 |
|
1523 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1524 |
{ |
1525 |
uint64_t mfindex; |
1526 |
int ret;
|
1527 |
|
1528 |
DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
|
1529 |
|
1530 |
xfer->in_xfer = epctx->type>>2;
|
1531 |
|
1532 |
switch(epctx->type) {
|
1533 |
case ET_INTR_OUT:
|
1534 |
case ET_INTR_IN:
|
1535 |
case ET_BULK_OUT:
|
1536 |
case ET_BULK_IN:
|
1537 |
xfer->pkts = 0;
|
1538 |
xfer->iso_xfer = false;
|
1539 |
break;
|
1540 |
case ET_ISO_OUT:
|
1541 |
case ET_ISO_IN:
|
1542 |
xfer->pkts = 1;
|
1543 |
xfer->iso_xfer = true;
|
1544 |
mfindex = xhci_mfindex_get(xhci); |
1545 |
xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); |
1546 |
xhci_check_iso_kick(xhci, xfer, epctx, mfindex); |
1547 |
if (xfer->running_retry) {
|
1548 |
return -1; |
1549 |
} |
1550 |
break;
|
1551 |
default:
|
1552 |
fprintf(stderr, "xhci: unknown or unhandled EP "
|
1553 |
"(type %d, in %d, ep %02x)\n",
|
1554 |
epctx->type, xfer->in_xfer, xfer->epid); |
1555 |
return -1; |
1556 |
} |
1557 |
|
1558 |
if (xhci_setup_packet(xfer) < 0) { |
1559 |
return -1; |
1560 |
} |
1561 |
ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1562 |
|
1563 |
xhci_complete_packet(xfer, ret); |
1564 |
if (!xfer->running_async && !xfer->running_retry) {
|
1565 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
1566 |
} |
1567 |
return 0; |
1568 |
} |
1569 |
|
1570 |
static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1571 |
{ |
1572 |
trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); |
1573 |
return xhci_submit(xhci, xfer, epctx);
|
1574 |
} |
1575 |
|
1576 |
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) |
1577 |
{ |
1578 |
XHCIEPContext *epctx; |
1579 |
uint64_t mfindex; |
1580 |
int length;
|
1581 |
int i;
|
1582 |
|
1583 |
trace_usb_xhci_ep_kick(slotid, epid); |
1584 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1585 |
assert(epid >= 1 && epid <= 31); |
1586 |
|
1587 |
if (!xhci->slots[slotid-1].enabled) { |
1588 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
|
1589 |
return;
|
1590 |
} |
1591 |
epctx = xhci->slots[slotid-1].eps[epid-1]; |
1592 |
if (!epctx) {
|
1593 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
|
1594 |
epid, slotid); |
1595 |
return;
|
1596 |
} |
1597 |
|
1598 |
if (epctx->retry) {
|
1599 |
XHCITransfer *xfer = epctx->retry; |
1600 |
int result;
|
1601 |
|
1602 |
trace_usb_xhci_xfer_retry(xfer); |
1603 |
assert(xfer->running_retry); |
1604 |
if (xfer->iso_xfer) {
|
1605 |
/* retry delayed iso transfer */
|
1606 |
mfindex = xhci_mfindex_get(xhci); |
1607 |
xhci_check_iso_kick(xhci, xfer, epctx, mfindex); |
1608 |
if (xfer->running_retry) {
|
1609 |
return;
|
1610 |
} |
1611 |
if (xhci_setup_packet(xfer) < 0) { |
1612 |
return;
|
1613 |
} |
1614 |
result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1615 |
assert(result != USB_RET_NAK); |
1616 |
xhci_complete_packet(xfer, result); |
1617 |
} else {
|
1618 |
/* retry nak'ed transfer */
|
1619 |
if (xhci_setup_packet(xfer) < 0) { |
1620 |
return;
|
1621 |
} |
1622 |
result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1623 |
if (result == USB_RET_NAK) {
|
1624 |
return;
|
1625 |
} |
1626 |
xhci_complete_packet(xfer, result); |
1627 |
} |
1628 |
assert(!xfer->running_retry); |
1629 |
epctx->retry = NULL;
|
1630 |
} |
1631 |
|
1632 |
if (epctx->state == EP_HALTED) {
|
1633 |
DPRINTF("xhci: ep halted, not running schedule\n");
|
1634 |
return;
|
1635 |
} |
1636 |
|
1637 |
xhci_set_ep_state(xhci, epctx, EP_RUNNING); |
1638 |
|
1639 |
while (1) { |
1640 |
XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; |
1641 |
if (xfer->running_async || xfer->running_retry) {
|
1642 |
break;
|
1643 |
} |
1644 |
length = xhci_ring_chain_length(xhci, &epctx->ring); |
1645 |
if (length < 0) { |
1646 |
break;
|
1647 |
} else if (length == 0) { |
1648 |
break;
|
1649 |
} |
1650 |
if (xfer->trbs && xfer->trb_alloced < length) {
|
1651 |
xfer->trb_count = 0;
|
1652 |
xfer->trb_alloced = 0;
|
1653 |
g_free(xfer->trbs); |
1654 |
xfer->trbs = NULL;
|
1655 |
} |
1656 |
if (!xfer->trbs) {
|
1657 |
xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
|
1658 |
xfer->trb_alloced = length; |
1659 |
} |
1660 |
xfer->trb_count = length; |
1661 |
|
1662 |
for (i = 0; i < length; i++) { |
1663 |
assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
|
1664 |
} |
1665 |
xfer->xhci = xhci; |
1666 |
xfer->epid = epid; |
1667 |
xfer->slotid = slotid; |
1668 |
|
1669 |
if (epid == 1) { |
1670 |
if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { |
1671 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
1672 |
} else {
|
1673 |
fprintf(stderr, "xhci: error firing CTL transfer\n");
|
1674 |
} |
1675 |
} else {
|
1676 |
if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { |
1677 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
1678 |
} else {
|
1679 |
if (!xfer->iso_xfer) {
|
1680 |
fprintf(stderr, "xhci: error firing data transfer\n");
|
1681 |
} |
1682 |
} |
1683 |
} |
1684 |
|
1685 |
if (epctx->state == EP_HALTED) {
|
1686 |
break;
|
1687 |
} |
1688 |
if (xfer->running_retry) {
|
1689 |
DPRINTF("xhci: xfer nacked, stopping schedule\n");
|
1690 |
epctx->retry = xfer; |
1691 |
break;
|
1692 |
} |
1693 |
} |
1694 |
} |
1695 |
|
1696 |
static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) |
1697 |
{ |
1698 |
trace_usb_xhci_slot_enable(slotid); |
1699 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1700 |
xhci->slots[slotid-1].enabled = 1; |
1701 |
xhci->slots[slotid-1].port = 0; |
1702 |
memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
1703 |
|
1704 |
return CC_SUCCESS;
|
1705 |
} |
1706 |
|
1707 |
static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) |
1708 |
{ |
1709 |
int i;
|
1710 |
|
1711 |
trace_usb_xhci_slot_disable(slotid); |
1712 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1713 |
|
1714 |
for (i = 1; i <= 31; i++) { |
1715 |
if (xhci->slots[slotid-1].eps[i-1]) { |
1716 |
xhci_disable_ep(xhci, slotid, i); |
1717 |
} |
1718 |
} |
1719 |
|
1720 |
xhci->slots[slotid-1].enabled = 0; |
1721 |
return CC_SUCCESS;
|
1722 |
} |
1723 |
|
1724 |
static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
1725 |
uint64_t pictx, bool bsr)
|
1726 |
{ |
1727 |
XHCISlot *slot; |
1728 |
USBDevice *dev; |
1729 |
dma_addr_t ictx, octx, dcbaap; |
1730 |
uint64_t poctx; |
1731 |
uint32_t ictl_ctx[2];
|
1732 |
uint32_t slot_ctx[4];
|
1733 |
uint32_t ep0_ctx[5];
|
1734 |
unsigned int port; |
1735 |
int i;
|
1736 |
TRBCCode res; |
1737 |
|
1738 |
trace_usb_xhci_slot_address(slotid); |
1739 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1740 |
|
1741 |
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); |
1742 |
pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); |
1743 |
ictx = xhci_mask64(pictx); |
1744 |
octx = xhci_mask64(le64_to_cpu(poctx)); |
1745 |
|
1746 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
1747 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
1748 |
|
1749 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
1750 |
|
1751 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { |
1752 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
1753 |
ictl_ctx[0], ictl_ctx[1]); |
1754 |
return CC_TRB_ERROR;
|
1755 |
} |
1756 |
|
1757 |
pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); |
1758 |
pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); |
1759 |
|
1760 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
1761 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1762 |
|
1763 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
1764 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
1765 |
|
1766 |
port = (slot_ctx[1]>>16) & 0xFF; |
1767 |
dev = xhci->ports[port-1].uport->dev;
|
1768 |
|
1769 |
if (port < 1 || port > xhci->numports) { |
1770 |
fprintf(stderr, "xhci: bad port %d\n", port);
|
1771 |
return CC_TRB_ERROR;
|
1772 |
} else if (!dev) { |
1773 |
fprintf(stderr, "xhci: port %d not connected\n", port);
|
1774 |
return CC_USB_TRANSACTION_ERROR;
|
1775 |
} |
1776 |
|
1777 |
for (i = 0; i < MAXSLOTS; i++) { |
1778 |
if (xhci->slots[i].port == port) {
|
1779 |
fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
|
1780 |
port, i+1);
|
1781 |
return CC_TRB_ERROR;
|
1782 |
} |
1783 |
} |
1784 |
|
1785 |
slot = &xhci->slots[slotid-1];
|
1786 |
slot->port = port; |
1787 |
slot->ctx = octx; |
1788 |
|
1789 |
if (bsr) {
|
1790 |
slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
1791 |
} else {
|
1792 |
slot->devaddr = xhci->devaddr++; |
1793 |
slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
|
1794 |
DPRINTF("xhci: device address is %d\n", slot->devaddr);
|
1795 |
usb_device_handle_control(dev, NULL,
|
1796 |
DeviceOutRequest | USB_REQ_SET_ADDRESS, |
1797 |
slot->devaddr, 0, 0, NULL); |
1798 |
} |
1799 |
|
1800 |
res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); |
1801 |
|
1802 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1803 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1804 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
1805 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
1806 |
|
1807 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1808 |
pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
1809 |
|
1810 |
return res;
|
1811 |
} |
1812 |
|
1813 |
|
1814 |
static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, |
1815 |
uint64_t pictx, bool dc)
|
1816 |
{ |
1817 |
dma_addr_t ictx, octx; |
1818 |
uint32_t ictl_ctx[2];
|
1819 |
uint32_t slot_ctx[4];
|
1820 |
uint32_t islot_ctx[4];
|
1821 |
uint32_t ep_ctx[5];
|
1822 |
int i;
|
1823 |
TRBCCode res; |
1824 |
|
1825 |
trace_usb_xhci_slot_configure(slotid); |
1826 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1827 |
|
1828 |
ictx = xhci_mask64(pictx); |
1829 |
octx = xhci->slots[slotid-1].ctx;
|
1830 |
|
1831 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
1832 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
1833 |
|
1834 |
if (dc) {
|
1835 |
for (i = 2; i <= 31; i++) { |
1836 |
if (xhci->slots[slotid-1].eps[i-1]) { |
1837 |
xhci_disable_ep(xhci, slotid, i); |
1838 |
} |
1839 |
} |
1840 |
|
1841 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1842 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
1843 |
slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
|
1844 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1845 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1846 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1847 |
|
1848 |
return CC_SUCCESS;
|
1849 |
} |
1850 |
|
1851 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
1852 |
|
1853 |
if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { |
1854 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
1855 |
ictl_ctx[0], ictl_ctx[1]); |
1856 |
return CC_TRB_ERROR;
|
1857 |
} |
1858 |
|
1859 |
pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); |
1860 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1861 |
|
1862 |
if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { |
1863 |
fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); |
1864 |
return CC_CONTEXT_STATE_ERROR;
|
1865 |
} |
1866 |
|
1867 |
for (i = 2; i <= 31; i++) { |
1868 |
if (ictl_ctx[0] & (1<<i)) { |
1869 |
xhci_disable_ep(xhci, slotid, i); |
1870 |
} |
1871 |
if (ictl_ctx[1] & (1<<i)) { |
1872 |
pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, |
1873 |
sizeof(ep_ctx));
|
1874 |
DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
1875 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
1876 |
ep_ctx[3], ep_ctx[4]); |
1877 |
xhci_disable_ep(xhci, slotid, i); |
1878 |
res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
|
1879 |
if (res != CC_SUCCESS) {
|
1880 |
return res;
|
1881 |
} |
1882 |
DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
1883 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
1884 |
ep_ctx[3], ep_ctx[4]); |
1885 |
pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); |
1886 |
} |
1887 |
} |
1888 |
|
1889 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
1890 |
slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
|
1891 |
slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
|
1892 |
slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << |
1893 |
SLOT_CONTEXT_ENTRIES_SHIFT); |
1894 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1895 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1896 |
|
1897 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1898 |
|
1899 |
return CC_SUCCESS;
|
1900 |
} |
1901 |
|
1902 |
|
1903 |
static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, |
1904 |
uint64_t pictx) |
1905 |
{ |
1906 |
dma_addr_t ictx, octx; |
1907 |
uint32_t ictl_ctx[2];
|
1908 |
uint32_t iep0_ctx[5];
|
1909 |
uint32_t ep0_ctx[5];
|
1910 |
uint32_t islot_ctx[4];
|
1911 |
uint32_t slot_ctx[4];
|
1912 |
|
1913 |
trace_usb_xhci_slot_evaluate(slotid); |
1914 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1915 |
|
1916 |
ictx = xhci_mask64(pictx); |
1917 |
octx = xhci->slots[slotid-1].ctx;
|
1918 |
|
1919 |
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
1920 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
1921 |
|
1922 |
pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
|
1923 |
|
1924 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { |
1925 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
1926 |
ictl_ctx[0], ictl_ctx[1]); |
1927 |
return CC_TRB_ERROR;
|
1928 |
} |
1929 |
|
1930 |
if (ictl_ctx[1] & 0x1) { |
1931 |
pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); |
1932 |
|
1933 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
1934 |
islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); |
1935 |
|
1936 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1937 |
|
1938 |
slot_ctx[1] &= ~0xFFFF; /* max exit latency */ |
1939 |
slot_ctx[1] |= islot_ctx[1] & 0xFFFF; |
1940 |
slot_ctx[2] &= ~0xFF00000; /* interrupter target */ |
1941 |
slot_ctx[2] |= islot_ctx[2] & 0xFF000000; |
1942 |
|
1943 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1944 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1945 |
|
1946 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1947 |
} |
1948 |
|
1949 |
if (ictl_ctx[1] & 0x2) { |
1950 |
pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); |
1951 |
|
1952 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
1953 |
iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], |
1954 |
iep0_ctx[3], iep0_ctx[4]); |
1955 |
|
1956 |
pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
1957 |
|
1958 |
ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ |
1959 |
ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; |
1960 |
|
1961 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
1962 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
1963 |
|
1964 |
pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
1965 |
} |
1966 |
|
1967 |
return CC_SUCCESS;
|
1968 |
} |
1969 |
|
1970 |
static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) |
1971 |
{ |
1972 |
uint32_t slot_ctx[4];
|
1973 |
dma_addr_t octx; |
1974 |
int i;
|
1975 |
|
1976 |
trace_usb_xhci_slot_reset(slotid); |
1977 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1978 |
|
1979 |
octx = xhci->slots[slotid-1].ctx;
|
1980 |
|
1981 |
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
1982 |
|
1983 |
for (i = 2; i <= 31; i++) { |
1984 |
if (xhci->slots[slotid-1].eps[i-1]) { |
1985 |
xhci_disable_ep(xhci, slotid, i); |
1986 |
} |
1987 |
} |
1988 |
|
1989 |
pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1990 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
1991 |
slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
1992 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1993 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1994 |
pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
|
1995 |
|
1996 |
return CC_SUCCESS;
|
1997 |
} |
1998 |
|
1999 |
static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) |
2000 |
{ |
2001 |
unsigned int slotid; |
2002 |
slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; |
2003 |
if (slotid < 1 || slotid > MAXSLOTS) { |
2004 |
fprintf(stderr, "xhci: bad slot id %d\n", slotid);
|
2005 |
event->ccode = CC_TRB_ERROR; |
2006 |
return 0; |
2007 |
} else if (!xhci->slots[slotid-1].enabled) { |
2008 |
fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
|
2009 |
event->ccode = CC_SLOT_NOT_ENABLED_ERROR; |
2010 |
return 0; |
2011 |
} |
2012 |
return slotid;
|
2013 |
} |
2014 |
|
2015 |
static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
|
2016 |
{ |
2017 |
dma_addr_t ctx; |
2018 |
uint8_t bw_ctx[xhci->numports+1];
|
2019 |
|
2020 |
DPRINTF("xhci_get_port_bandwidth()\n");
|
2021 |
|
2022 |
ctx = xhci_mask64(pctx); |
2023 |
|
2024 |
DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); |
2025 |
|
2026 |
/* TODO: actually implement real values here */
|
2027 |
bw_ctx[0] = 0; |
2028 |
memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ |
2029 |
pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
|
2030 |
|
2031 |
return CC_SUCCESS;
|
2032 |
} |
2033 |
|
2034 |
static uint32_t rotl(uint32_t v, unsigned count) |
2035 |
{ |
2036 |
count &= 31;
|
2037 |
return (v << count) | (v >> (32 - count)); |
2038 |
} |
2039 |
|
2040 |
|
2041 |
static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
|
2042 |
{ |
2043 |
uint32_t val; |
2044 |
val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); |
2045 |
val += rotl(lo + 0x49434878, hi & 0x1F); |
2046 |
val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); |
2047 |
return ~val;
|
2048 |
} |
2049 |
|
2050 |
static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) |
2051 |
{ |
2052 |
uint32_t buf[8];
|
2053 |
uint32_t obuf[8];
|
2054 |
dma_addr_t paddr = xhci_mask64(addr); |
2055 |
|
2056 |
pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
|
2057 |
|
2058 |
memcpy(obuf, buf, sizeof(obuf));
|
2059 |
|
2060 |
if ((buf[0] & 0xff) == 2) { |
2061 |
obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; |
2062 |
obuf[0] |= (buf[2] * buf[3]) & 0xff; |
2063 |
obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; |
2064 |
obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; |
2065 |
obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; |
2066 |
obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; |
2067 |
obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; |
2068 |
obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; |
2069 |
obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; |
2070 |
} |
2071 |
|
2072 |
pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
|
2073 |
} |
2074 |
|
2075 |
static void xhci_process_commands(XHCIState *xhci) |
2076 |
{ |
2077 |
XHCITRB trb; |
2078 |
TRBType type; |
2079 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; |
2080 |
dma_addr_t addr; |
2081 |
unsigned int i, slotid = 0; |
2082 |
|
2083 |
DPRINTF("xhci_process_commands()\n");
|
2084 |
if (!xhci_running(xhci)) {
|
2085 |
DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
|
2086 |
return;
|
2087 |
} |
2088 |
|
2089 |
xhci->crcr_low |= CRCR_CRR; |
2090 |
|
2091 |
while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
|
2092 |
event.ptr = addr; |
2093 |
switch (type) {
|
2094 |
case CR_ENABLE_SLOT:
|
2095 |
for (i = 0; i < MAXSLOTS; i++) { |
2096 |
if (!xhci->slots[i].enabled) {
|
2097 |
break;
|
2098 |
} |
2099 |
} |
2100 |
if (i >= MAXSLOTS) {
|
2101 |
fprintf(stderr, "xhci: no device slots available\n");
|
2102 |
event.ccode = CC_NO_SLOTS_ERROR; |
2103 |
} else {
|
2104 |
slotid = i+1;
|
2105 |
event.ccode = xhci_enable_slot(xhci, slotid); |
2106 |
} |
2107 |
break;
|
2108 |
case CR_DISABLE_SLOT:
|
2109 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2110 |
if (slotid) {
|
2111 |
event.ccode = xhci_disable_slot(xhci, slotid); |
2112 |
} |
2113 |
break;
|
2114 |
case CR_ADDRESS_DEVICE:
|
2115 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2116 |
if (slotid) {
|
2117 |
event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, |
2118 |
trb.control & TRB_CR_BSR); |
2119 |
} |
2120 |
break;
|
2121 |
case CR_CONFIGURE_ENDPOINT:
|
2122 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2123 |
if (slotid) {
|
2124 |
event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, |
2125 |
trb.control & TRB_CR_DC); |
2126 |
} |
2127 |
break;
|
2128 |
case CR_EVALUATE_CONTEXT:
|
2129 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2130 |
if (slotid) {
|
2131 |
event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); |
2132 |
} |
2133 |
break;
|
2134 |
case CR_STOP_ENDPOINT:
|
2135 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2136 |
if (slotid) {
|
2137 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2138 |
& TRB_CR_EPID_MASK; |
2139 |
event.ccode = xhci_stop_ep(xhci, slotid, epid); |
2140 |
} |
2141 |
break;
|
2142 |
case CR_RESET_ENDPOINT:
|
2143 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2144 |
if (slotid) {
|
2145 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2146 |
& TRB_CR_EPID_MASK; |
2147 |
event.ccode = xhci_reset_ep(xhci, slotid, epid); |
2148 |
} |
2149 |
break;
|
2150 |
case CR_SET_TR_DEQUEUE:
|
2151 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2152 |
if (slotid) {
|
2153 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2154 |
& TRB_CR_EPID_MASK; |
2155 |
event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, |
2156 |
trb.parameter); |
2157 |
} |
2158 |
break;
|
2159 |
case CR_RESET_DEVICE:
|
2160 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2161 |
if (slotid) {
|
2162 |
event.ccode = xhci_reset_slot(xhci, slotid); |
2163 |
} |
2164 |
break;
|
2165 |
case CR_GET_PORT_BANDWIDTH:
|
2166 |
event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); |
2167 |
break;
|
2168 |
case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
|
2169 |
xhci_via_challenge(xhci, trb.parameter); |
2170 |
break;
|
2171 |
case CR_VENDOR_NEC_FIRMWARE_REVISION:
|
2172 |
event.type = 48; /* NEC reply */ |
2173 |
event.length = 0x3025;
|
2174 |
break;
|
2175 |
case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
|
2176 |
{ |
2177 |
uint32_t chi = trb.parameter >> 32;
|
2178 |
uint32_t clo = trb.parameter; |
2179 |
uint32_t val = xhci_nec_challenge(chi, clo); |
2180 |
event.length = val & 0xFFFF;
|
2181 |
event.epid = val >> 16;
|
2182 |
slotid = val >> 24;
|
2183 |
event.type = 48; /* NEC reply */ |
2184 |
} |
2185 |
break;
|
2186 |
default:
|
2187 |
fprintf(stderr, "xhci: unimplemented command %d\n", type);
|
2188 |
event.ccode = CC_TRB_ERROR; |
2189 |
break;
|
2190 |
} |
2191 |
event.slotid = slotid; |
2192 |
xhci_event(xhci, &event); |
2193 |
} |
2194 |
} |
2195 |
|
2196 |
static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) |
2197 |
{ |
2198 |
port->portsc = PORTSC_PP; |
2199 |
if (port->uport->dev && port->uport->dev->attached && !is_detach &&
|
2200 |
(1 << port->uport->dev->speed) & port->speedmask) {
|
2201 |
port->portsc |= PORTSC_CCS; |
2202 |
switch (port->uport->dev->speed) {
|
2203 |
case USB_SPEED_LOW:
|
2204 |
port->portsc |= PORTSC_SPEED_LOW; |
2205 |
break;
|
2206 |
case USB_SPEED_FULL:
|
2207 |
port->portsc |= PORTSC_SPEED_FULL; |
2208 |
break;
|
2209 |
case USB_SPEED_HIGH:
|
2210 |
port->portsc |= PORTSC_SPEED_HIGH; |
2211 |
break;
|
2212 |
case USB_SPEED_SUPER:
|
2213 |
port->portsc |= PORTSC_SPEED_SUPER; |
2214 |
break;
|
2215 |
} |
2216 |
} |
2217 |
|
2218 |
if (xhci_running(xhci)) {
|
2219 |
port->portsc |= PORTSC_CSC; |
2220 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, |
2221 |
port->portnr << 24};
|
2222 |
xhci_event(xhci, &ev); |
2223 |
DPRINTF("xhci: port change event for port %d\n", port->portnr);
|
2224 |
} |
2225 |
} |
2226 |
|
2227 |
static void xhci_reset(DeviceState *dev) |
2228 |
{ |
2229 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); |
2230 |
int i;
|
2231 |
|
2232 |
trace_usb_xhci_reset(); |
2233 |
if (!(xhci->usbsts & USBSTS_HCH)) {
|
2234 |
fprintf(stderr, "xhci: reset while running!\n");
|
2235 |
} |
2236 |
|
2237 |
xhci->usbcmd = 0;
|
2238 |
xhci->usbsts = USBSTS_HCH; |
2239 |
xhci->dnctrl = 0;
|
2240 |
xhci->crcr_low = 0;
|
2241 |
xhci->crcr_high = 0;
|
2242 |
xhci->dcbaap_low = 0;
|
2243 |
xhci->dcbaap_high = 0;
|
2244 |
xhci->config = 0;
|
2245 |
xhci->devaddr = 2;
|
2246 |
|
2247 |
for (i = 0; i < MAXSLOTS; i++) { |
2248 |
xhci_disable_slot(xhci, i+1);
|
2249 |
} |
2250 |
|
2251 |
for (i = 0; i < xhci->numports; i++) { |
2252 |
xhci_update_port(xhci, xhci->ports + i, 0);
|
2253 |
} |
2254 |
|
2255 |
xhci->iman = 0;
|
2256 |
xhci->imod = 0;
|
2257 |
xhci->erstsz = 0;
|
2258 |
xhci->erstba_low = 0;
|
2259 |
xhci->erstba_high = 0;
|
2260 |
xhci->erdp_low = 0;
|
2261 |
xhci->erdp_high = 0;
|
2262 |
|
2263 |
xhci->er_ep_idx = 0;
|
2264 |
xhci->er_pcs = 1;
|
2265 |
xhci->er_full = 0;
|
2266 |
xhci->ev_buffer_put = 0;
|
2267 |
xhci->ev_buffer_get = 0;
|
2268 |
|
2269 |
xhci->mfindex_start = qemu_get_clock_ns(vm_clock); |
2270 |
xhci_mfwrap_update(xhci); |
2271 |
} |
2272 |
|
2273 |
static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
|
2274 |
{ |
2275 |
uint32_t ret; |
2276 |
|
2277 |
switch (reg) {
|
2278 |
case 0x00: /* HCIVERSION, CAPLENGTH */ |
2279 |
ret = 0x01000000 | LEN_CAP;
|
2280 |
break;
|
2281 |
case 0x04: /* HCSPARAMS 1 */ |
2282 |
ret = ((xhci->numports_2+xhci->numports_3)<<24)
|
2283 |
| (MAXINTRS<<8) | MAXSLOTS;
|
2284 |
break;
|
2285 |
case 0x08: /* HCSPARAMS 2 */ |
2286 |
ret = 0x0000000f;
|
2287 |
break;
|
2288 |
case 0x0c: /* HCSPARAMS 3 */ |
2289 |
ret = 0x00000000;
|
2290 |
break;
|
2291 |
case 0x10: /* HCCPARAMS */ |
2292 |
if (sizeof(dma_addr_t) == 4) { |
2293 |
ret = 0x00081000;
|
2294 |
} else {
|
2295 |
ret = 0x00081001;
|
2296 |
} |
2297 |
break;
|
2298 |
case 0x14: /* DBOFF */ |
2299 |
ret = OFF_DOORBELL; |
2300 |
break;
|
2301 |
case 0x18: /* RTSOFF */ |
2302 |
ret = OFF_RUNTIME; |
2303 |
break;
|
2304 |
|
2305 |
/* extended capabilities */
|
2306 |
case 0x20: /* Supported Protocol:00 */ |
2307 |
ret = 0x02000402; /* USB 2.0 */ |
2308 |
break;
|
2309 |
case 0x24: /* Supported Protocol:04 */ |
2310 |
ret = 0x20425455; /* "USB " */ |
2311 |
break;
|
2312 |
case 0x28: /* Supported Protocol:08 */ |
2313 |
ret = 0x00000001 | (xhci->numports_2<<8); |
2314 |
break;
|
2315 |
case 0x2c: /* Supported Protocol:0c */ |
2316 |
ret = 0x00000000; /* reserved */ |
2317 |
break;
|
2318 |
case 0x30: /* Supported Protocol:00 */ |
2319 |
ret = 0x03000002; /* USB 3.0 */ |
2320 |
break;
|
2321 |
case 0x34: /* Supported Protocol:04 */ |
2322 |
ret = 0x20425455; /* "USB " */ |
2323 |
break;
|
2324 |
case 0x38: /* Supported Protocol:08 */ |
2325 |
ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); |
2326 |
break;
|
2327 |
case 0x3c: /* Supported Protocol:0c */ |
2328 |
ret = 0x00000000; /* reserved */ |
2329 |
break;
|
2330 |
default:
|
2331 |
fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
|
2332 |
ret = 0;
|
2333 |
} |
2334 |
|
2335 |
trace_usb_xhci_cap_read(reg, ret); |
2336 |
return ret;
|
2337 |
} |
2338 |
|
2339 |
static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
|
2340 |
{ |
2341 |
uint32_t port = reg >> 4;
|
2342 |
uint32_t ret; |
2343 |
|
2344 |
if (port >= xhci->numports) {
|
2345 |
fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
|
2346 |
ret = 0;
|
2347 |
goto out;
|
2348 |
} |
2349 |
|
2350 |
switch (reg & 0xf) { |
2351 |
case 0x00: /* PORTSC */ |
2352 |
ret = xhci->ports[port].portsc; |
2353 |
break;
|
2354 |
case 0x04: /* PORTPMSC */ |
2355 |
case 0x08: /* PORTLI */ |
2356 |
ret = 0;
|
2357 |
break;
|
2358 |
case 0x0c: /* reserved */ |
2359 |
default:
|
2360 |
fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
|
2361 |
port, reg); |
2362 |
ret = 0;
|
2363 |
} |
2364 |
|
2365 |
out:
|
2366 |
trace_usb_xhci_port_read(port, reg & 0x0f, ret);
|
2367 |
return ret;
|
2368 |
} |
2369 |
|
2370 |
static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2371 |
{ |
2372 |
uint32_t port = reg >> 4;
|
2373 |
uint32_t portsc; |
2374 |
|
2375 |
trace_usb_xhci_port_write(port, reg & 0x0f, val);
|
2376 |
|
2377 |
if (port >= xhci->numports) {
|
2378 |
fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
|
2379 |
return;
|
2380 |
} |
2381 |
|
2382 |
switch (reg & 0xf) { |
2383 |
case 0x00: /* PORTSC */ |
2384 |
portsc = xhci->ports[port].portsc; |
2385 |
/* write-1-to-clear bits*/
|
2386 |
portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| |
2387 |
PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); |
2388 |
if (val & PORTSC_LWS) {
|
2389 |
/* overwrite PLS only when LWS=1 */
|
2390 |
portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
2391 |
portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
2392 |
} |
2393 |
/* read/write bits */
|
2394 |
portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); |
2395 |
portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); |
2396 |
/* write-1-to-start bits */
|
2397 |
if (val & PORTSC_PR) {
|
2398 |
DPRINTF("xhci: port %d reset\n", port);
|
2399 |
usb_device_reset(xhci->ports[port].uport->dev); |
2400 |
portsc |= PORTSC_PRC | PORTSC_PED; |
2401 |
} |
2402 |
xhci->ports[port].portsc = portsc; |
2403 |
break;
|
2404 |
case 0x04: /* PORTPMSC */ |
2405 |
case 0x08: /* PORTLI */ |
2406 |
default:
|
2407 |
fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
|
2408 |
port, reg); |
2409 |
} |
2410 |
} |
2411 |
|
2412 |
static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
|
2413 |
{ |
2414 |
uint32_t ret; |
2415 |
|
2416 |
if (reg >= 0x400) { |
2417 |
return xhci_port_read(xhci, reg - 0x400); |
2418 |
} |
2419 |
|
2420 |
switch (reg) {
|
2421 |
case 0x00: /* USBCMD */ |
2422 |
ret = xhci->usbcmd; |
2423 |
break;
|
2424 |
case 0x04: /* USBSTS */ |
2425 |
ret = xhci->usbsts; |
2426 |
break;
|
2427 |
case 0x08: /* PAGESIZE */ |
2428 |
ret = 1; /* 4KiB */ |
2429 |
break;
|
2430 |
case 0x14: /* DNCTRL */ |
2431 |
ret = xhci->dnctrl; |
2432 |
break;
|
2433 |
case 0x18: /* CRCR low */ |
2434 |
ret = xhci->crcr_low & ~0xe;
|
2435 |
break;
|
2436 |
case 0x1c: /* CRCR high */ |
2437 |
ret = xhci->crcr_high; |
2438 |
break;
|
2439 |
case 0x30: /* DCBAAP low */ |
2440 |
ret = xhci->dcbaap_low; |
2441 |
break;
|
2442 |
case 0x34: /* DCBAAP high */ |
2443 |
ret = xhci->dcbaap_high; |
2444 |
break;
|
2445 |
case 0x38: /* CONFIG */ |
2446 |
ret = xhci->config; |
2447 |
break;
|
2448 |
default:
|
2449 |
fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
|
2450 |
ret = 0;
|
2451 |
} |
2452 |
|
2453 |
trace_usb_xhci_oper_read(reg, ret); |
2454 |
return ret;
|
2455 |
} |
2456 |
|
2457 |
static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2458 |
{ |
2459 |
if (reg >= 0x400) { |
2460 |
xhci_port_write(xhci, reg - 0x400, val);
|
2461 |
return;
|
2462 |
} |
2463 |
|
2464 |
trace_usb_xhci_oper_write(reg, val); |
2465 |
|
2466 |
switch (reg) {
|
2467 |
case 0x00: /* USBCMD */ |
2468 |
if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
|
2469 |
xhci_run(xhci); |
2470 |
} else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { |
2471 |
xhci_stop(xhci); |
2472 |
} |
2473 |
xhci->usbcmd = val & 0xc0f;
|
2474 |
xhci_mfwrap_update(xhci); |
2475 |
if (val & USBCMD_HCRST) {
|
2476 |
xhci_reset(&xhci->pci_dev.qdev); |
2477 |
} |
2478 |
xhci_irq_update(xhci); |
2479 |
break;
|
2480 |
|
2481 |
case 0x04: /* USBSTS */ |
2482 |
/* these bits are write-1-to-clear */
|
2483 |
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); |
2484 |
xhci_irq_update(xhci); |
2485 |
break;
|
2486 |
|
2487 |
case 0x14: /* DNCTRL */ |
2488 |
xhci->dnctrl = val & 0xffff;
|
2489 |
break;
|
2490 |
case 0x18: /* CRCR low */ |
2491 |
xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
|
2492 |
break;
|
2493 |
case 0x1c: /* CRCR high */ |
2494 |
xhci->crcr_high = val; |
2495 |
if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
|
2496 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; |
2497 |
xhci->crcr_low &= ~CRCR_CRR; |
2498 |
xhci_event(xhci, &event); |
2499 |
DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
|
2500 |
} else {
|
2501 |
dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
|
2502 |
xhci_ring_init(xhci, &xhci->cmd_ring, base); |
2503 |
} |
2504 |
xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); |
2505 |
break;
|
2506 |
case 0x30: /* DCBAAP low */ |
2507 |
xhci->dcbaap_low = val & 0xffffffc0;
|
2508 |
break;
|
2509 |
case 0x34: /* DCBAAP high */ |
2510 |
xhci->dcbaap_high = val; |
2511 |
break;
|
2512 |
case 0x38: /* CONFIG */ |
2513 |
xhci->config = val & 0xff;
|
2514 |
break;
|
2515 |
default:
|
2516 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
|
2517 |
} |
2518 |
} |
2519 |
|
2520 |
static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
|
2521 |
{ |
2522 |
uint32_t ret; |
2523 |
|
2524 |
switch (reg) {
|
2525 |
case 0x00: /* MFINDEX */ |
2526 |
ret = xhci_mfindex_get(xhci) & 0x3fff;
|
2527 |
break;
|
2528 |
case 0x20: /* IMAN */ |
2529 |
ret = xhci->iman; |
2530 |
break;
|
2531 |
case 0x24: /* IMOD */ |
2532 |
ret = xhci->imod; |
2533 |
break;
|
2534 |
case 0x28: /* ERSTSZ */ |
2535 |
ret = xhci->erstsz; |
2536 |
break;
|
2537 |
case 0x30: /* ERSTBA low */ |
2538 |
ret = xhci->erstba_low; |
2539 |
break;
|
2540 |
case 0x34: /* ERSTBA high */ |
2541 |
ret = xhci->erstba_high; |
2542 |
break;
|
2543 |
case 0x38: /* ERDP low */ |
2544 |
ret = xhci->erdp_low; |
2545 |
break;
|
2546 |
case 0x3c: /* ERDP high */ |
2547 |
ret = xhci->erdp_high; |
2548 |
break;
|
2549 |
default:
|
2550 |
fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
|
2551 |
ret = 0;
|
2552 |
} |
2553 |
|
2554 |
trace_usb_xhci_runtime_read(reg, ret); |
2555 |
return ret;
|
2556 |
} |
2557 |
|
2558 |
static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2559 |
{ |
2560 |
trace_usb_xhci_runtime_write(reg, val); |
2561 |
|
2562 |
switch (reg) {
|
2563 |
case 0x20: /* IMAN */ |
2564 |
if (val & IMAN_IP) {
|
2565 |
xhci->iman &= ~IMAN_IP; |
2566 |
} |
2567 |
xhci->iman &= ~IMAN_IE; |
2568 |
xhci->iman |= val & IMAN_IE; |
2569 |
xhci_irq_update(xhci); |
2570 |
break;
|
2571 |
case 0x24: /* IMOD */ |
2572 |
xhci->imod = val; |
2573 |
break;
|
2574 |
case 0x28: /* ERSTSZ */ |
2575 |
xhci->erstsz = val & 0xffff;
|
2576 |
break;
|
2577 |
case 0x30: /* ERSTBA low */ |
2578 |
/* XXX NEC driver bug: it doesn't align this to 64 bytes
|
2579 |
xhci->erstba_low = val & 0xffffffc0; */
|
2580 |
xhci->erstba_low = val & 0xfffffff0;
|
2581 |
break;
|
2582 |
case 0x34: /* ERSTBA high */ |
2583 |
xhci->erstba_high = val; |
2584 |
xhci_er_reset(xhci); |
2585 |
break;
|
2586 |
case 0x38: /* ERDP low */ |
2587 |
if (val & ERDP_EHB) {
|
2588 |
xhci->erdp_low &= ~ERDP_EHB; |
2589 |
} |
2590 |
xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB); |
2591 |
break;
|
2592 |
case 0x3c: /* ERDP high */ |
2593 |
xhci->erdp_high = val; |
2594 |
xhci_events_update(xhci); |
2595 |
break;
|
2596 |
default:
|
2597 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
|
2598 |
} |
2599 |
} |
2600 |
|
2601 |
static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
|
2602 |
{ |
2603 |
/* doorbells always read as 0 */
|
2604 |
trace_usb_xhci_doorbell_read(reg, 0);
|
2605 |
return 0; |
2606 |
} |
2607 |
|
2608 |
static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2609 |
{ |
2610 |
trace_usb_xhci_doorbell_write(reg, val); |
2611 |
|
2612 |
if (!xhci_running(xhci)) {
|
2613 |
fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
|
2614 |
return;
|
2615 |
} |
2616 |
|
2617 |
reg >>= 2;
|
2618 |
|
2619 |
if (reg == 0) { |
2620 |
if (val == 0) { |
2621 |
xhci_process_commands(xhci); |
2622 |
} else {
|
2623 |
fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
|
2624 |
} |
2625 |
} else {
|
2626 |
if (reg > MAXSLOTS) {
|
2627 |
fprintf(stderr, "xhci: bad doorbell %d\n", reg);
|
2628 |
} else if (val > 31) { |
2629 |
fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
|
2630 |
} else {
|
2631 |
xhci_kick_ep(xhci, reg, val); |
2632 |
} |
2633 |
} |
2634 |
} |
2635 |
|
2636 |
static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr, |
2637 |
unsigned size)
|
2638 |
{ |
2639 |
XHCIState *xhci = ptr; |
2640 |
|
2641 |
/* Only aligned reads are allowed on xHCI */
|
2642 |
if (addr & 3) { |
2643 |
fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
|
2644 |
return 0; |
2645 |
} |
2646 |
|
2647 |
if (addr < LEN_CAP) {
|
2648 |
return xhci_cap_read(xhci, addr);
|
2649 |
} else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { |
2650 |
return xhci_oper_read(xhci, addr - OFF_OPER);
|
2651 |
} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { |
2652 |
return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
|
2653 |
} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { |
2654 |
return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
|
2655 |
} else {
|
2656 |
fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr); |
2657 |
return 0; |
2658 |
} |
2659 |
} |
2660 |
|
2661 |
static void xhci_mem_write(void *ptr, target_phys_addr_t addr, |
2662 |
uint64_t val, unsigned size)
|
2663 |
{ |
2664 |
XHCIState *xhci = ptr; |
2665 |
|
2666 |
/* Only aligned writes are allowed on xHCI */
|
2667 |
if (addr & 3) { |
2668 |
fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
|
2669 |
return;
|
2670 |
} |
2671 |
|
2672 |
if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
|
2673 |
xhci_oper_write(xhci, addr - OFF_OPER, val); |
2674 |
} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { |
2675 |
xhci_runtime_write(xhci, addr - OFF_RUNTIME, val); |
2676 |
} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { |
2677 |
xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val); |
2678 |
} else {
|
2679 |
fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr); |
2680 |
} |
2681 |
} |
2682 |
|
2683 |
static const MemoryRegionOps xhci_mem_ops = { |
2684 |
.read = xhci_mem_read, |
2685 |
.write = xhci_mem_write, |
2686 |
.valid.min_access_size = 4,
|
2687 |
.valid.max_access_size = 4,
|
2688 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2689 |
}; |
2690 |
|
2691 |
static void xhci_attach(USBPort *usbport) |
2692 |
{ |
2693 |
XHCIState *xhci = usbport->opaque; |
2694 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
2695 |
|
2696 |
xhci_update_port(xhci, port, 0);
|
2697 |
} |
2698 |
|
2699 |
static void xhci_detach(USBPort *usbport) |
2700 |
{ |
2701 |
XHCIState *xhci = usbport->opaque; |
2702 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
2703 |
|
2704 |
xhci_update_port(xhci, port, 1);
|
2705 |
} |
2706 |
|
2707 |
static void xhci_wakeup(USBPort *usbport) |
2708 |
{ |
2709 |
XHCIState *xhci = usbport->opaque; |
2710 |
XHCIPort *port = xhci_lookup_port(xhci, usbport); |
2711 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, |
2712 |
port->portnr << 24};
|
2713 |
uint32_t pls; |
2714 |
|
2715 |
pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; |
2716 |
if (pls != 3) { |
2717 |
return;
|
2718 |
} |
2719 |
port->portsc |= 0xf << PORTSC_PLS_SHIFT;
|
2720 |
if (port->portsc & PORTSC_PLC) {
|
2721 |
return;
|
2722 |
} |
2723 |
port->portsc |= PORTSC_PLC; |
2724 |
xhci_event(xhci, &ev); |
2725 |
} |
2726 |
|
2727 |
static void xhci_complete(USBPort *port, USBPacket *packet) |
2728 |
{ |
2729 |
XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); |
2730 |
|
2731 |
xhci_complete_packet(xfer, packet->result); |
2732 |
xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); |
2733 |
} |
2734 |
|
2735 |
static void xhci_child_detach(USBPort *port, USBDevice *child) |
2736 |
{ |
2737 |
FIXME(); |
2738 |
} |
2739 |
|
2740 |
static USBPortOps xhci_port_ops = {
|
2741 |
.attach = xhci_attach, |
2742 |
.detach = xhci_detach, |
2743 |
.wakeup = xhci_wakeup, |
2744 |
.complete = xhci_complete, |
2745 |
.child_detach = xhci_child_detach, |
2746 |
}; |
2747 |
|
2748 |
static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) |
2749 |
{ |
2750 |
XHCISlot *slot; |
2751 |
int slotid;
|
2752 |
|
2753 |
for (slotid = 1; slotid <= MAXSLOTS; slotid++) { |
2754 |
slot = &xhci->slots[slotid-1];
|
2755 |
if (slot->devaddr == dev->addr) {
|
2756 |
return slotid;
|
2757 |
} |
2758 |
} |
2759 |
return 0; |
2760 |
} |
2761 |
|
2762 |
static int xhci_find_epid(USBEndpoint *ep) |
2763 |
{ |
2764 |
if (ep->nr == 0) { |
2765 |
return 1; |
2766 |
} |
2767 |
if (ep->pid == USB_TOKEN_IN) {
|
2768 |
return ep->nr * 2 + 1; |
2769 |
} else {
|
2770 |
return ep->nr * 2; |
2771 |
} |
2772 |
} |
2773 |
|
2774 |
static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) |
2775 |
{ |
2776 |
XHCIState *xhci = container_of(bus, XHCIState, bus); |
2777 |
int slotid;
|
2778 |
|
2779 |
DPRINTF("%s\n", __func__);
|
2780 |
slotid = xhci_find_slotid(xhci, ep->dev); |
2781 |
if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
2782 |
DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
|
2783 |
return;
|
2784 |
} |
2785 |
xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); |
2786 |
} |
2787 |
|
2788 |
static USBBusOps xhci_bus_ops = {
|
2789 |
.wakeup_endpoint = xhci_wakeup_endpoint, |
2790 |
}; |
2791 |
|
2792 |
static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) |
2793 |
{ |
2794 |
XHCIPort *port; |
2795 |
int i, usbports, speedmask;
|
2796 |
|
2797 |
xhci->usbsts = USBSTS_HCH; |
2798 |
|
2799 |
if (xhci->numports_2 > MAXPORTS_2) {
|
2800 |
xhci->numports_2 = MAXPORTS_2; |
2801 |
} |
2802 |
if (xhci->numports_3 > MAXPORTS_3) {
|
2803 |
xhci->numports_3 = MAXPORTS_3; |
2804 |
} |
2805 |
usbports = MAX(xhci->numports_2, xhci->numports_3); |
2806 |
xhci->numports = xhci->numports_2 + xhci->numports_3; |
2807 |
|
2808 |
usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); |
2809 |
|
2810 |
for (i = 0; i < usbports; i++) { |
2811 |
speedmask = 0;
|
2812 |
if (i < xhci->numports_2) {
|
2813 |
port = &xhci->ports[i]; |
2814 |
port->portnr = i + 1;
|
2815 |
port->uport = &xhci->uports[i]; |
2816 |
port->speedmask = |
2817 |
USB_SPEED_MASK_LOW | |
2818 |
USB_SPEED_MASK_FULL | |
2819 |
USB_SPEED_MASK_HIGH; |
2820 |
speedmask |= port->speedmask; |
2821 |
} |
2822 |
if (i < xhci->numports_3) {
|
2823 |
port = &xhci->ports[i + xhci->numports_2]; |
2824 |
port->portnr = i + 1 + xhci->numports_2;
|
2825 |
port->uport = &xhci->uports[i]; |
2826 |
port->speedmask = USB_SPEED_MASK_SUPER; |
2827 |
speedmask |= port->speedmask; |
2828 |
} |
2829 |
usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, |
2830 |
&xhci_port_ops, speedmask); |
2831 |
} |
2832 |
} |
2833 |
|
2834 |
static int usb_xhci_initfn(struct PCIDevice *dev) |
2835 |
{ |
2836 |
int ret;
|
2837 |
|
2838 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); |
2839 |
|
2840 |
xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ |
2841 |
xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ |
2842 |
xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
|
2843 |
xhci->pci_dev.config[0x60] = 0x30; /* release number */ |
2844 |
|
2845 |
usb_xhci_init(xhci, &dev->qdev); |
2846 |
|
2847 |
xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); |
2848 |
|
2849 |
xhci->irq = xhci->pci_dev.irq[0];
|
2850 |
|
2851 |
memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci, |
2852 |
"xhci", LEN_REGS);
|
2853 |
pci_register_bar(&xhci->pci_dev, 0,
|
2854 |
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, |
2855 |
&xhci->mem); |
2856 |
|
2857 |
ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); |
2858 |
assert(ret >= 0);
|
2859 |
|
2860 |
if (xhci->msi) {
|
2861 |
ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false); |
2862 |
assert(ret >= 0);
|
2863 |
} |
2864 |
|
2865 |
return 0; |
2866 |
} |
2867 |
|
2868 |
static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, |
2869 |
int len)
|
2870 |
{ |
2871 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); |
2872 |
|
2873 |
pci_default_write_config(dev, addr, val, len); |
2874 |
if (xhci->msi) {
|
2875 |
msi_write_config(dev, addr, val, len); |
2876 |
} |
2877 |
} |
2878 |
|
2879 |
static const VMStateDescription vmstate_xhci = { |
2880 |
.name = "xhci",
|
2881 |
.unmigratable = 1,
|
2882 |
}; |
2883 |
|
2884 |
static Property xhci_properties[] = {
|
2885 |
DEFINE_PROP_UINT32("msi", XHCIState, msi, 0), |
2886 |
DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), |
2887 |
DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), |
2888 |
DEFINE_PROP_END_OF_LIST(), |
2889 |
}; |
2890 |
|
2891 |
static void xhci_class_init(ObjectClass *klass, void *data) |
2892 |
{ |
2893 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2894 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2895 |
|
2896 |
dc->vmsd = &vmstate_xhci; |
2897 |
dc->props = xhci_properties; |
2898 |
dc->reset = xhci_reset; |
2899 |
k->init = usb_xhci_initfn; |
2900 |
k->vendor_id = PCI_VENDOR_ID_NEC; |
2901 |
k->device_id = PCI_DEVICE_ID_NEC_UPD720200; |
2902 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2903 |
k->revision = 0x03;
|
2904 |
k->is_express = 1;
|
2905 |
k->config_write = xhci_write_config; |
2906 |
} |
2907 |
|
2908 |
static TypeInfo xhci_info = {
|
2909 |
.name = "nec-usb-xhci",
|
2910 |
.parent = TYPE_PCI_DEVICE, |
2911 |
.instance_size = sizeof(XHCIState),
|
2912 |
.class_init = xhci_class_init, |
2913 |
}; |
2914 |
|
2915 |
static void xhci_register_types(void) |
2916 |
{ |
2917 |
type_register_static(&xhci_info); |
2918 |
} |
2919 |
|
2920 |
type_init(xhci_register_types) |