Archipelago » qemu

/*

 * StrongARM SA-1100/SA-1110 emulation

 *

 * Copyright (C) 2011 Dmitry Eremin-Solenikov

 *

 * Largely based on StrongARM emulation:

 * Copyright (c) 2006 Openedhand Ltd.

 * Written by Andrzej Zaborowski <balrog@zabor.org>

 *

 * UART code based on QEMU 16550A UART emulation

 * Copyright (c) 2003-2004 Fabrice Bellard

 * Copyright (c) 2008 Citrix Systems, Inc.

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  published by the Free Software Foundation.

 *

 *  This program is distributed in the hope that it will be useful,

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *  GNU General Public License for more details.

 *

 *  You should have received a copy of the GNU General Public License along

 *  with this program; if not, see <http://www.gnu.org/licenses/>.

 */

#include "sysbus.h"

#include "strongarm.h"

#include "qemu-error.h"

#include "arm-misc.h"

#include "sysemu.h"

#include "ssi.h"

//#define DEBUG

/*

 TODO

 - Implement cp15, c14 ?

 - Implement cp15, c15 !!! (idle used in L)

 - Implement idle mode handling/DIM

 - Implement sleep mode/Wake sources

 - Implement reset control

 - Implement memory control regs

 - PCMCIA handling

 - Maybe support MBGNT/MBREQ

 - DMA channels

 - GPCLK

 - IrDA

 - MCP

 - Enhance UART with modem signals

 */

#ifdef DEBUG

# define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)

#else

# define DPRINTF(format, ...) do { } while (0)

#endif

static struct {

    target_phys_addr_t io_base;

    int irq;

} sa_serial[] = {

    { 0x80010000, SA_PIC_UART1 },

    { 0x80030000, SA_PIC_UART2 },

    { 0x80050000, SA_PIC_UART3 },

    { 0, 0 }

};

/* Interrupt Controller */

typedef struct {

    SysBusDevice busdev;

    qemu_irq    irq;

    qemu_irq    fiq;

    uint32_t pending;

    uint32_t enabled;

    uint32_t is_fiq;

    uint32_t int_idle;

} StrongARMPICState;

#define ICIP    0x00

#define ICMR    0x04

#define ICLR    0x08

#define ICFP    0x10

#define ICPR    0x20

#define ICCR    0x0c

#define SA_PIC_SRCS     32

static void strongarm_pic_update(void *opaque)

{

    StrongARMPICState *s = opaque;

    /* FIXME: reflect DIM */

    qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);

    qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);

}

static void strongarm_pic_set_irq(void *opaque, int irq, int level)

{

    StrongARMPICState *s = opaque;

    if (level) {

        s->pending |= 1 << irq;

    } else {

        s->pending &= ~(1 << irq);

    }

    strongarm_pic_update(s);

}

static uint32_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset)

{

    StrongARMPICState *s = opaque;

    switch (offset) {

    case ICIP:

        return s->pending & ~s->is_fiq & s->enabled;

    case ICMR:

        return s->enabled;

    case ICLR:

        return s->is_fiq;

    case ICCR:

        return s->int_idle == 0;

    case ICFP:

        return s->pending & s->is_fiq & s->enabled;

    case ICPR:

        return s->pending;

    default:

        printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",

                        __func__, offset);

        return 0;

    }

}

static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,

                uint32_t value)

{

    StrongARMPICState *s = opaque;

    switch (offset) {

    case ICMR:

        s->enabled = value;

        break;

    case ICLR:

        s->is_fiq = value;

        break;

    case ICCR:

        s->int_idle = (value & 1) ? 0 : ~0;

        break;

    default:

        printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",

                        __func__, offset);

        break;

    }

    strongarm_pic_update(s);

}

static CPUReadMemoryFunc * const strongarm_pic_readfn[] = {

    strongarm_pic_mem_read,

    strongarm_pic_mem_read,

    strongarm_pic_mem_read,

};

static CPUWriteMemoryFunc * const strongarm_pic_writefn[] = {

    strongarm_pic_mem_write,

    strongarm_pic_mem_write,

    strongarm_pic_mem_write,

};

static int strongarm_pic_initfn(SysBusDevice *dev)

{

    StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);

    int iomemtype;

    qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);

    iomemtype = cpu_register_io_memory(strongarm_pic_readfn,

                    strongarm_pic_writefn, s, DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    sysbus_init_irq(dev, &s->irq);

    sysbus_init_irq(dev, &s->fiq);

    return 0;

}

static int strongarm_pic_post_load(void *opaque, int version_id)

{

    strongarm_pic_update(opaque);

    return 0;

}

static VMStateDescription vmstate_strongarm_pic_regs = {

    .name = "strongarm_pic",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .post_load = strongarm_pic_post_load,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(pending, StrongARMPICState),

        VMSTATE_UINT32(enabled, StrongARMPICState),

        VMSTATE_UINT32(is_fiq, StrongARMPICState),

        VMSTATE_UINT32(int_idle, StrongARMPICState),

        VMSTATE_END_OF_LIST(),

    },

};

static SysBusDeviceInfo strongarm_pic_info = {

    .init       = strongarm_pic_initfn,

    .qdev.name  = "strongarm_pic",

    .qdev.desc  = "StrongARM PIC",

    .qdev.size  = sizeof(StrongARMPICState),

    .qdev.vmsd  = &vmstate_strongarm_pic_regs,

};

/* Real-Time Clock */

#define RTAR 0x00 /* RTC Alarm register */

#define RCNR 0x04 /* RTC Counter register */

#define RTTR 0x08 /* RTC Timer Trim register */

#define RTSR 0x10 /* RTC Status register */

#define RTSR_AL (1 << 0) /* RTC Alarm detected */

#define RTSR_HZ (1 << 1) /* RTC 1Hz detected */

#define RTSR_ALE (1 << 2) /* RTC Alarm enable */

#define RTSR_HZE (1 << 3) /* RTC 1Hz enable */

/* 16 LSB of RTTR are clockdiv for internal trim logic,

 * trim delete isn't emulated, so

 * f = 32 768 / (RTTR_trim + 1) */

typedef struct {

    SysBusDevice busdev;

    uint32_t rttr;

    uint32_t rtsr;

    uint32_t rtar;

    uint32_t last_rcnr;

    int64_t last_hz;

    QEMUTimer *rtc_alarm;

    QEMUTimer *rtc_hz;

    qemu_irq rtc_irq;

    qemu_irq rtc_hz_irq;

} StrongARMRTCState;

static inline void strongarm_rtc_int_update(StrongARMRTCState *s)

{

    qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);

    qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);

}

static void strongarm_rtc_hzupdate(StrongARMRTCState *s)

{

    int64_t rt = qemu_get_clock_ms(rt_clock);

    s->last_rcnr += ((rt - s->last_hz) << 15) /

            (1000 * ((s->rttr & 0xffff) + 1));

    s->last_hz = rt;

}

static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)

{

    if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {

        qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);

    } else {

        qemu_del_timer(s->rtc_hz);

    }

    if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {

        qemu_mod_timer(s->rtc_alarm, s->last_hz +

                (((s->rtar - s->last_rcnr) * 1000 *

                  ((s->rttr & 0xffff) + 1)) >> 15));

    } else {

        qemu_del_timer(s->rtc_alarm);

    }

}

static inline void strongarm_rtc_alarm_tick(void *opaque)

{

    StrongARMRTCState *s = opaque;

    s->rtsr |= RTSR_AL;

    strongarm_rtc_timer_update(s);

    strongarm_rtc_int_update(s);

}

static inline void strongarm_rtc_hz_tick(void *opaque)

{

    StrongARMRTCState *s = opaque;

    s->rtsr |= RTSR_HZ;

    strongarm_rtc_timer_update(s);

    strongarm_rtc_int_update(s);

}

static uint32_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr)

{

    StrongARMRTCState *s = opaque;

    switch (addr) {

    case RTTR:

        return s->rttr;

    case RTSR:

        return s->rtsr;

    case RTAR:

        return s->rtar;

    case RCNR:

        return s->last_rcnr +

                ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /

                (1000 * ((s->rttr & 0xffff) + 1));

    default:

        printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);

        return 0;

    }

}

static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    StrongARMRTCState *s = opaque;

    uint32_t old_rtsr;

    switch (addr) {

    case RTTR:

        strongarm_rtc_hzupdate(s);

        s->rttr = value;

        strongarm_rtc_timer_update(s);

        break;

    case RTSR:

        old_rtsr = s->rtsr;

        s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |

                  (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));

        if (s->rtsr != old_rtsr) {

            strongarm_rtc_timer_update(s);

        }

        strongarm_rtc_int_update(s);

        break;

    case RTAR:

        s->rtar = value;

        strongarm_rtc_timer_update(s);

        break;

    case RCNR:

        strongarm_rtc_hzupdate(s);

        s->last_rcnr = value;

        strongarm_rtc_timer_update(s);

        break;

    default:

        printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);

    }

}

static CPUReadMemoryFunc * const strongarm_rtc_readfn[] = {

    strongarm_rtc_read,

    strongarm_rtc_read,

    strongarm_rtc_read,

};

static CPUWriteMemoryFunc * const strongarm_rtc_writefn[] = {

    strongarm_rtc_write,

    strongarm_rtc_write,

    strongarm_rtc_write,

};

static int strongarm_rtc_init(SysBusDevice *dev)

{

    StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);

    struct tm tm;

    int iomemtype;

    s->rttr = 0x0;

    s->rtsr = 0;

    qemu_get_timedate(&tm, 0);

    s->last_rcnr = (uint32_t) mktimegm(&tm);

    s->last_hz = qemu_get_clock_ms(rt_clock);

    s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);

    s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);

    sysbus_init_irq(dev, &s->rtc_irq);

    sysbus_init_irq(dev, &s->rtc_hz_irq);

    iomemtype = cpu_register_io_memory(strongarm_rtc_readfn,

                    strongarm_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x10000, iomemtype);

    return 0;

}

static void strongarm_rtc_pre_save(void *opaque)

{

    StrongARMRTCState *s = opaque;

    strongarm_rtc_hzupdate(s);

}

static int strongarm_rtc_post_load(void *opaque, int version_id)

{

    StrongARMRTCState *s = opaque;

    strongarm_rtc_timer_update(s);

    strongarm_rtc_int_update(s);

    return 0;

}

static const VMStateDescription vmstate_strongarm_rtc_regs = {

    .name = "strongarm-rtc",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .pre_save = strongarm_rtc_pre_save,

    .post_load = strongarm_rtc_post_load,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(rttr, StrongARMRTCState),

        VMSTATE_UINT32(rtsr, StrongARMRTCState),

        VMSTATE_UINT32(rtar, StrongARMRTCState),

        VMSTATE_UINT32(last_rcnr, StrongARMRTCState),

        VMSTATE_INT64(last_hz, StrongARMRTCState),

        VMSTATE_END_OF_LIST(),

    },

};

static SysBusDeviceInfo strongarm_rtc_sysbus_info = {

    .init       = strongarm_rtc_init,

    .qdev.name  = "strongarm-rtc",

    .qdev.desc  = "StrongARM RTC Controller",

    .qdev.size  = sizeof(StrongARMRTCState),

    .qdev.vmsd  = &vmstate_strongarm_rtc_regs,

};

/* GPIO */

#define GPLR 0x00

#define GPDR 0x04

#define GPSR 0x08

#define GPCR 0x0c

#define GRER 0x10

#define GFER 0x14

#define GEDR 0x18

#define GAFR 0x1c

typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;

struct StrongARMGPIOInfo {

    SysBusDevice busdev;

    qemu_irq handler[28];

    qemu_irq irqs[11];

    qemu_irq irqX;

    uint32_t ilevel;

    uint32_t olevel;

    uint32_t dir;

    uint32_t rising;

    uint32_t falling;

    uint32_t status;

    uint32_t gpsr;

    uint32_t gafr;

    uint32_t prev_level;

};

static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)

{

    int i;

    for (i = 0; i < 11; i++) {

        qemu_set_irq(s->irqs[i], s->status & (1 << i));

    }

    qemu_set_irq(s->irqX, (s->status & ~0x7ff));

}

static void strongarm_gpio_set(void *opaque, int line, int level)

{

    StrongARMGPIOInfo *s = opaque;

    uint32_t mask;

    mask = 1 << line;

    if (level) {

        s->status |= s->rising & mask &

                ~s->ilevel & ~s->dir;

        s->ilevel |= mask;

    } else {

        s->status |= s->falling & mask &

                s->ilevel & ~s->dir;

        s->ilevel &= ~mask;

    }

    if (s->status & mask) {

        strongarm_gpio_irq_update(s);

    }

}

static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)

{

    uint32_t level, diff;

    int bit;

    level = s->olevel & s->dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {

        bit = ffs(diff) - 1;

        qemu_set_irq(s->handler[bit], (level >> bit) & 1);

    }

    s->prev_level = level;

}

static uint32_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset)

{

    StrongARMGPIOInfo *s = opaque;

    switch (offset) {

    case GPDR:        /* GPIO Pin-Direction registers */

        return s->dir;

    case GPSR:        /* GPIO Pin-Output Set registers */

        DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",

                        __func__, offset);

        return s->gpsr;    /* Return last written value.  */

    case GPCR:        /* GPIO Pin-Output Clear registers */

        DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",

                        __func__, offset);

        return 31337;        /* Specified as unpredictable in the docs.  */

    case GRER:        /* GPIO Rising-Edge Detect Enable registers */

        return s->rising;

    case GFER:        /* GPIO Falling-Edge Detect Enable registers */

        return s->falling;

    case GAFR:        /* GPIO Alternate Function registers */

        return s->gafr;

    case GPLR:        /* GPIO Pin-Level registers */

        return (s->olevel & s->dir) |

               (s->ilevel & ~s->dir);

    case GEDR:        /* GPIO Edge Detect Status registers */

        return s->status;

    default:

        printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);

    }

    return 0;

}

static void strongarm_gpio_write(void *opaque,

                target_phys_addr_t offset, uint32_t value)

{

    StrongARMGPIOInfo *s = opaque;

    switch (offset) {

    case GPDR:        /* GPIO Pin-Direction registers */

        s->dir = value;

        strongarm_gpio_handler_update(s);

        break;

    case GPSR:        /* GPIO Pin-Output Set registers */

        s->olevel |= value;

        strongarm_gpio_handler_update(s);

        s->gpsr = value;

        break;

    case GPCR:        /* GPIO Pin-Output Clear registers */

        s->olevel &= ~value;

        strongarm_gpio_handler_update(s);

        break;

    case GRER:        /* GPIO Rising-Edge Detect Enable registers */

        s->rising = value;

        break;

    case GFER:        /* GPIO Falling-Edge Detect Enable registers */

        s->falling = value;

        break;

    case GAFR:        /* GPIO Alternate Function registers */

        s->gafr = value;

        break;

    case GEDR:        /* GPIO Edge Detect Status registers */

        s->status &= ~value;

        strongarm_gpio_irq_update(s);

        break;

    default:

        printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);

    }

}

static CPUReadMemoryFunc * const strongarm_gpio_readfn[] = {

    strongarm_gpio_read,

    strongarm_gpio_read,

    strongarm_gpio_read

};

static CPUWriteMemoryFunc * const strongarm_gpio_writefn[] = {

    strongarm_gpio_write,

    strongarm_gpio_write,

    strongarm_gpio_write

};

static DeviceState *strongarm_gpio_init(target_phys_addr_t base,

                DeviceState *pic)

{

    DeviceState *dev;

    int i;

    dev = qdev_create(NULL, "strongarm-gpio");

    qdev_init_nofail(dev);

    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);

    for (i = 0; i < 12; i++)

        sysbus_connect_irq(sysbus_from_qdev(dev), i,

                    qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));

    return dev;

}

static int strongarm_gpio_initfn(SysBusDevice *dev)

{

    int iomemtype;

    StrongARMGPIOInfo *s;

    int i;

    s = FROM_SYSBUS(StrongARMGPIOInfo, dev);

    qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);

    qdev_init_gpio_out(&dev->qdev, s->handler, 28);

    iomemtype = cpu_register_io_memory(strongarm_gpio_readfn,

                    strongarm_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    for (i = 0; i < 11; i++) {

        sysbus_init_irq(dev, &s->irqs[i]);

    }

    sysbus_init_irq(dev, &s->irqX);

    return 0;

}

static const VMStateDescription vmstate_strongarm_gpio_regs = {

    .name = "strongarm-gpio",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),

        VMSTATE_UINT32(olevel, StrongARMGPIOInfo),

        VMSTATE_UINT32(dir, StrongARMGPIOInfo),

        VMSTATE_UINT32(rising, StrongARMGPIOInfo),

        VMSTATE_UINT32(falling, StrongARMGPIOInfo),

        VMSTATE_UINT32(status, StrongARMGPIOInfo),

        VMSTATE_UINT32(gafr, StrongARMGPIOInfo),

        VMSTATE_END_OF_LIST(),

    },

};

static SysBusDeviceInfo strongarm_gpio_info = {

    .init       = strongarm_gpio_initfn,

    .qdev.name  = "strongarm-gpio",

    .qdev.desc  = "StrongARM GPIO controller",

    .qdev.size  = sizeof(StrongARMGPIOInfo),

};

/* Peripheral Pin Controller */

#define PPDR 0x00

#define PPSR 0x04

#define PPAR 0x08

#define PSDR 0x0c

#define PPFR 0x10

typedef struct StrongARMPPCInfo StrongARMPPCInfo;

struct StrongARMPPCInfo {

    SysBusDevice busdev;

    qemu_irq handler[28];

    uint32_t ilevel;

    uint32_t olevel;

    uint32_t dir;

    uint32_t ppar;

    uint32_t psdr;

    uint32_t ppfr;

    uint32_t prev_level;

};

static void strongarm_ppc_set(void *opaque, int line, int level)

{

    StrongARMPPCInfo *s = opaque;

    if (level) {

        s->ilevel |= 1 << line;

    } else {

        s->ilevel &= ~(1 << line);

    }

}

static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)

{

    uint32_t level, diff;

    int bit;

    level = s->olevel & s->dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {

        bit = ffs(diff) - 1;

        qemu_set_irq(s->handler[bit], (level >> bit) & 1);

    }

    s->prev_level = level;

}

static uint32_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset)

{

    StrongARMPPCInfo *s = opaque;

    switch (offset) {

    case PPDR:        /* PPC Pin Direction registers */

        return s->dir | ~0x3fffff;

    case PPSR:        /* PPC Pin State registers */

        return (s->olevel & s->dir) |

               (s->ilevel & ~s->dir) |

               ~0x3fffff;

    case PPAR:

        return s->ppar | ~0x41000;

    case PSDR:

        return s->psdr;

    case PPFR:

        return s->ppfr | ~0x7f001;

    default:

        printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);

    }

    return 0;

}

static void strongarm_ppc_write(void *opaque,

                target_phys_addr_t offset, uint32_t value)

{

    StrongARMPPCInfo *s = opaque;

    switch (offset) {

    case PPDR:        /* PPC Pin Direction registers */

        s->dir = value & 0x3fffff;

        strongarm_ppc_handler_update(s);

        break;

    case PPSR:        /* PPC Pin State registers */

        s->olevel = value & s->dir & 0x3fffff;

        strongarm_ppc_handler_update(s);

        break;

    case PPAR:

        s->ppar = value & 0x41000;

        break;

    case PSDR:

        s->psdr = value & 0x3fffff;

        break;

    case PPFR:

        s->ppfr = value & 0x7f001;

        break;

    default:

        printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);

    }

}

static CPUReadMemoryFunc * const strongarm_ppc_readfn[] = {

    strongarm_ppc_read,

    strongarm_ppc_read,

    strongarm_ppc_read

};

static CPUWriteMemoryFunc * const strongarm_ppc_writefn[] = {

    strongarm_ppc_write,

    strongarm_ppc_write,

    strongarm_ppc_write

};

static int strongarm_ppc_init(SysBusDevice *dev)

{

    int iomemtype;

    StrongARMPPCInfo *s;

    s = FROM_SYSBUS(StrongARMPPCInfo, dev);

    qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);

    qdev_init_gpio_out(&dev->qdev, s->handler, 22);

    iomemtype = cpu_register_io_memory(strongarm_ppc_readfn,

                    strongarm_ppc_writefn, s, DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    return 0;

}

static const VMStateDescription vmstate_strongarm_ppc_regs = {

    .name = "strongarm-ppc",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(ilevel, StrongARMPPCInfo),

        VMSTATE_UINT32(olevel, StrongARMPPCInfo),

        VMSTATE_UINT32(dir, StrongARMPPCInfo),

        VMSTATE_UINT32(ppar, StrongARMPPCInfo),

        VMSTATE_UINT32(psdr, StrongARMPPCInfo),

        VMSTATE_UINT32(ppfr, StrongARMPPCInfo),

        VMSTATE_END_OF_LIST(),

    },

};

static SysBusDeviceInfo strongarm_ppc_info = {

    .init       = strongarm_ppc_init,

    .qdev.name  = "strongarm-ppc",

    .qdev.desc  = "StrongARM PPC controller",

    .qdev.size  = sizeof(StrongARMPPCInfo),

};

/* UART Ports */

#define UTCR0 0x00

#define UTCR1 0x04

#define UTCR2 0x08

#define UTCR3 0x0c

#define UTDR  0x14

#define UTSR0 0x1c

#define UTSR1 0x20

#define UTCR0_PE  (1 << 0) /* Parity enable */

#define UTCR0_OES (1 << 1) /* Even parity */

#define UTCR0_SBS (1 << 2) /* 2 stop bits */

#define UTCR0_DSS (1 << 3) /* 8-bit data */

#define UTCR3_RXE (1 << 0) /* Rx enable */

#define UTCR3_TXE (1 << 1) /* Tx enable */

#define UTCR3_BRK (1 << 2) /* Force Break */

#define UTCR3_RIE (1 << 3) /* Rx int enable */

#define UTCR3_TIE (1 << 4) /* Tx int enable */

#define UTCR3_LBM (1 << 5) /* Loopback */

#define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */

#define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */

#define UTSR0_RID (1 << 2) /* Receiver Idle */

#define UTSR0_RBB (1 << 3) /* Receiver begin break */

#define UTSR0_REB (1 << 4) /* Receiver end break */

#define UTSR0_EIF (1 << 5) /* Error in FIFO */

#define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */

#define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */

#define UTSR1_PRE (1 << 3) /* Parity error */

#define UTSR1_FRE (1 << 4) /* Frame error */

#define UTSR1_ROR (1 << 5) /* Receive Over Run */

#define RX_FIFO_PRE (1 << 8)

#define RX_FIFO_FRE (1 << 9)

#define RX_FIFO_ROR (1 << 10)

typedef struct {

    SysBusDevice busdev;

    CharDriverState *chr;

    qemu_irq irq;

    uint8_t utcr0;

    uint16_t brd;

    uint8_t utcr3;

    uint8_t utsr0;

    uint8_t utsr1;

    uint8_t tx_fifo[8];

    uint8_t tx_start;

    uint8_t tx_len;

    uint16_t rx_fifo[12]; /* value + error flags in high bits */

    uint8_t rx_start;

    uint8_t rx_len;

    uint64_t char_transmit_time; /* time to transmit a char in ticks*/

    bool wait_break_end;

    QEMUTimer *rx_timeout_timer;

    QEMUTimer *tx_timer;

} StrongARMUARTState;

static void strongarm_uart_update_status(StrongARMUARTState *s)