Archipelago » qemu

        ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;

}

#undef ESI

#define ESI (env->regs[R_ESI])

#undef EDI

        cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);

        cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);

        cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);

        cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);

        cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);

        cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);

        cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);

    env->regs[R_ECX] = new_regs[1];

    env->regs[R_EDX] = new_regs[2];

    env->regs[R_EBX] = new_regs[3];

    env->regs[R_EBP] = new_regs[5];

    ESI = new_regs[6];

    EDI = new_regs[7];

}

#ifdef TARGET_X86_64

    } while (0)

#else

    } while (0)

#endif

            } else {

                mask = 0xffff;

            }

            ssp = env->segs[R_SS].base + esp;

            if (shift) {

                cpu_stl_kernel(env, ssp, error_code);

        new_stack = 0;

        sp_mask = get_sp_mask(env->segs[R_SS].flags);

        ssp = env->segs[R_SS].base;

        dpl = cpl;

    } else {

        raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);

                PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);

            }

            PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);

        }

        PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));

        PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);

                PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);

            }

            PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);

        }

        PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));

        PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);

        if (ist != 0) {

            esp = get_rsp_from_tss(env, ist + 3);

        } else {

        }

        esp &= ~0xfLL; /* align stack */

        dpl = cpl;

    }

    PUSHQ(esp, env->segs[R_SS].selector);

    PUSHQ(esp, cpu_compute_eflags(env));

    PUSHQ(esp, env->segs[R_CS].selector);

    PUSHQ(esp, old_eip);

        ss = 0 | dpl;

        cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);

    }

    selector = (selector & ~3) | dpl;

    cpu_x86_load_seg_cache(env, R_CS, selector,

    ptr = dt->base + intno * 4;

    offset = cpu_lduw_kernel(env, ptr);

    selector = cpu_lduw_kernel(env, ptr + 2);

    ssp = env->segs[R_SS].base;

    if (is_int) {

        old_eip = next_eip;

    PUSHW(ssp, esp, 0xffff, old_eip);

    /* update processor state */

    env->eip = offset;

    env->segs[R_CS].selector = selector;

    env->segs[R_CS].base = (selector << 4);

                     env->hflags & HF_CPL_MASK,

                     env->segs[R_CS].selector, EIP,

                     (int)env->segs[R_CS].base + EIP,

            if (intno == 0x0e) {

                qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);

            } else {

    esp_mask = get_sp_mask(env->segs[R_SS].flags);

    ssp = env->segs[R_SS].base;

    ebp = env->regs[R_EBP];

    if (data32) {

        /* 32 bit */

        esp -= 4;

    target_ulong esp, ebp;

    ebp = env->regs[R_EBP];

    if (data64) {

        /* 64 bit */

    target_ulong ssp;

    new_eip = new_eip1;

    esp_mask = get_sp_mask(env->segs[R_SS].flags);

    ssp = env->segs[R_SS].base;

    if (shift) {

            target_ulong rsp;

            /* 64 bit case */

            PUSHQ(rsp, env->segs[R_CS].selector);

            PUSHQ(rsp, next_eip);

            /* from this point, not restartable */

            cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,

                                   get_seg_base(e1, e2),

                                   get_seg_limit(e1, e2), e2);

        } else

#endif

        {

            sp_mask = get_sp_mask(env->segs[R_SS].flags);

            ssp = env->segs[R_SS].base;

            if (shift) {

        if (!(e2 & DESC_C_MASK) && dpl < cpl) {

            /* to inner privilege */

            get_ss_esp_from_tss(env, &ss, &sp, dpl);

                      "\n",

            if ((ss & 0xfffc) == 0) {

                raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);

            }

            ssp = get_seg_base(ss_e1, ss_e2);

            if (shift) {

                PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);

                for (i = param_count - 1; i >= 0; i--) {

                                                         old_sp_mask));

                    PUSHL(ssp, sp, sp_mask, val);

                }

            } else {

                PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);

                for (i = param_count - 1; i >= 0; i--) {

                                                          old_sp_mask));

                    PUSHW(ssp, sp, sp_mask, val);

                }

            new_stack = 1;

        } else {

            /* to same privilege */

            sp_mask = get_sp_mask(env->segs[R_SS].flags);

            ssp = env->segs[R_SS].base;

            /* push_size = (4 << shift); */

    int eflags_mask;

    sp_mask = 0xffff; /* XXXX: use SS segment size? */

    ssp = env->segs[R_SS].base;

    if (shift == 1) {

        /* 32 bits */

        POPW(ssp, sp, sp_mask, new_cs);

        POPW(ssp, sp, sp_mask, new_eflags);

    }

    env->segs[R_CS].selector = new_cs;

    env->segs[R_CS].base = (new_cs << 4);

    env->eip = new_eip;

    {

        sp_mask = get_sp_mask(env->segs[R_SS].flags);

    }

    ssp = env->segs[R_SS].base;

    new_eflags = 0; /* avoid warning */

#ifdef TARGET_X86_64

    load_seg_vm(env, R_GS, new_gs & 0xffff);

    env->eip = new_eip & 0xffff;

}

void helper_iret_protected(CPUX86State *env, int shift, int next_eip)

                           DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |

                           DESC_S_MASK |

                           DESC_W_MASK | DESC_A_MASK);

    EIP = env->sysenter_eip;

}

                               DESC_S_MASK | (3 << DESC_DPL_SHIFT) |

                               DESC_W_MASK | DESC_A_MASK);

    }

    EIP = env->regs[R_EDX];

}

    stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);

    stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);

    stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);

    stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);

    stq_phys(sm_state + 0x7fc8, ESI);

    stq_phys(sm_state + 0x7fc0, EDI);

    stl_phys(sm_state + 0x7fec, EDI);

    stl_phys(sm_state + 0x7fe8, ESI);

    stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);

    stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);

    stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);

    stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);

    env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);

    env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);

    env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);

    env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);

    ESI = ldq_phys(sm_state + 0x7fc8);

    EDI = ldq_phys(sm_state + 0x7fc0);

    EDI = ldl_phys(sm_state + 0x7fec);

    ESI = ldl_phys(sm_state + 0x7fe8);

    env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);

    env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);

    env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);

    env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);

    stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),

             EIP + next_eip_addend);

    stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);

    /* load the interception bitmaps so we do not need to access the

    EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));

    env->eip = EIP;

    env->regs[R_EAX] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));

    env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));

    env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));

             cpu_compute_eflags(env));

    stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),

             env->eip);

    stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]);

    stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);

    stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);

                       R_DS);

    EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));

    env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));

    env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));