root / hw / serial.c @ 08cea4ee
History | View | Annotate | Download (8 kB)
1 | 80cabfad | bellard | /*
|
---|---|---|---|
2 | 80cabfad | bellard | * QEMU 16450 UART emulation
|
3 | 80cabfad | bellard | *
|
4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
|
5 | 80cabfad | bellard | *
|
6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
|
12 | 80cabfad | bellard | *
|
13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
|
15 | 80cabfad | bellard | *
|
16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 80cabfad | bellard | * THE SOFTWARE.
|
23 | 80cabfad | bellard | */
|
24 | 80cabfad | bellard | #include <stdlib.h> |
25 | 80cabfad | bellard | #include <stdio.h> |
26 | 80cabfad | bellard | #include <stdarg.h> |
27 | 80cabfad | bellard | #include <string.h> |
28 | 80cabfad | bellard | #include <getopt.h> |
29 | 80cabfad | bellard | #include <inttypes.h> |
30 | 80cabfad | bellard | #include <unistd.h> |
31 | 80cabfad | bellard | #include <sys/mman.h> |
32 | 80cabfad | bellard | #include <fcntl.h> |
33 | 80cabfad | bellard | #include <signal.h> |
34 | 80cabfad | bellard | #include <time.h> |
35 | 80cabfad | bellard | #include <sys/time.h> |
36 | 80cabfad | bellard | #include <malloc.h> |
37 | 80cabfad | bellard | #include <termios.h> |
38 | 80cabfad | bellard | #include <sys/poll.h> |
39 | 80cabfad | bellard | #include <errno.h> |
40 | 80cabfad | bellard | #include <sys/wait.h> |
41 | 80cabfad | bellard | #include <netinet/in.h> |
42 | 80cabfad | bellard | |
43 | 80cabfad | bellard | #include "cpu.h" |
44 | 80cabfad | bellard | #include "vl.h" |
45 | 80cabfad | bellard | |
46 | 80cabfad | bellard | //#define DEBUG_SERIAL
|
47 | 80cabfad | bellard | |
48 | 80cabfad | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
49 | 80cabfad | bellard | |
50 | 80cabfad | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
51 | 80cabfad | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
52 | 80cabfad | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
53 | 80cabfad | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
54 | 80cabfad | bellard | |
55 | 80cabfad | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
56 | 80cabfad | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
57 | 80cabfad | bellard | |
58 | 80cabfad | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
59 | 80cabfad | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
60 | 80cabfad | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
61 | 80cabfad | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
62 | 80cabfad | bellard | |
63 | 80cabfad | bellard | /*
|
64 | 80cabfad | bellard | * These are the definitions for the Modem Control Register
|
65 | 80cabfad | bellard | */
|
66 | 80cabfad | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
67 | 80cabfad | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
68 | 80cabfad | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
69 | 80cabfad | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
70 | 80cabfad | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
71 | 80cabfad | bellard | |
72 | 80cabfad | bellard | /*
|
73 | 80cabfad | bellard | * These are the definitions for the Modem Status Register
|
74 | 80cabfad | bellard | */
|
75 | 80cabfad | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
76 | 80cabfad | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
77 | 80cabfad | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
78 | 80cabfad | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
79 | 80cabfad | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
80 | 80cabfad | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
81 | 80cabfad | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
82 | 80cabfad | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
83 | 80cabfad | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
84 | 80cabfad | bellard | |
85 | 80cabfad | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
86 | 80cabfad | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
87 | 80cabfad | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
88 | 80cabfad | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
89 | 80cabfad | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
90 | 80cabfad | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
91 | 80cabfad | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
92 | 80cabfad | bellard | |
93 | b41a2cd1 | bellard | struct SerialState {
|
94 | 80cabfad | bellard | uint8_t divider; |
95 | 80cabfad | bellard | uint8_t rbr; /* receive register */
|
96 | 80cabfad | bellard | uint8_t ier; |
97 | 80cabfad | bellard | uint8_t iir; /* read only */
|
98 | 80cabfad | bellard | uint8_t lcr; |
99 | 80cabfad | bellard | uint8_t mcr; |
100 | 80cabfad | bellard | uint8_t lsr; /* read only */
|
101 | 80cabfad | bellard | uint8_t msr; |
102 | 80cabfad | bellard | uint8_t scr; |
103 | 80cabfad | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
|
104 | 80cabfad | bellard | it can be reset while reading iir */
|
105 | 80cabfad | bellard | int thr_ipending;
|
106 | 80cabfad | bellard | int irq;
|
107 | b41a2cd1 | bellard | int out_fd;
|
108 | b41a2cd1 | bellard | }; |
109 | 80cabfad | bellard | |
110 | b41a2cd1 | bellard | static void serial_update_irq(SerialState *s) |
111 | 80cabfad | bellard | { |
112 | 80cabfad | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
113 | 80cabfad | bellard | s->iir = UART_IIR_RDI; |
114 | 80cabfad | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
115 | 80cabfad | bellard | s->iir = UART_IIR_THRI; |
116 | 80cabfad | bellard | } else {
|
117 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
118 | 80cabfad | bellard | } |
119 | 80cabfad | bellard | if (s->iir != UART_IIR_NO_INT) {
|
120 | 80cabfad | bellard | pic_set_irq(s->irq, 1);
|
121 | 80cabfad | bellard | } else {
|
122 | 80cabfad | bellard | pic_set_irq(s->irq, 0);
|
123 | 80cabfad | bellard | } |
124 | 80cabfad | bellard | } |
125 | 80cabfad | bellard | |
126 | b41a2cd1 | bellard | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
127 | 80cabfad | bellard | { |
128 | b41a2cd1 | bellard | SerialState *s = opaque; |
129 | 80cabfad | bellard | unsigned char ch; |
130 | 80cabfad | bellard | int ret;
|
131 | 80cabfad | bellard | |
132 | 80cabfad | bellard | addr &= 7;
|
133 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
|
134 | 80cabfad | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
|
135 | 80cabfad | bellard | #endif
|
136 | 80cabfad | bellard | switch(addr) {
|
137 | 80cabfad | bellard | default:
|
138 | 80cabfad | bellard | case 0: |
139 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
|
140 | 80cabfad | bellard | s->divider = (s->divider & 0xff00) | val;
|
141 | 80cabfad | bellard | } else {
|
142 | 80cabfad | bellard | s->thr_ipending = 0;
|
143 | 80cabfad | bellard | s->lsr &= ~UART_LSR_THRE; |
144 | b41a2cd1 | bellard | serial_update_irq(s); |
145 | 80cabfad | bellard | |
146 | 80cabfad | bellard | ch = val; |
147 | 80cabfad | bellard | do {
|
148 | b41a2cd1 | bellard | ret = write(s->out_fd, &ch, 1);
|
149 | 80cabfad | bellard | } while (ret != 1); |
150 | 80cabfad | bellard | s->thr_ipending = 1;
|
151 | 80cabfad | bellard | s->lsr |= UART_LSR_THRE; |
152 | 80cabfad | bellard | s->lsr |= UART_LSR_TEMT; |
153 | b41a2cd1 | bellard | serial_update_irq(s); |
154 | 80cabfad | bellard | } |
155 | 80cabfad | bellard | break;
|
156 | 80cabfad | bellard | case 1: |
157 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
|
158 | 80cabfad | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
159 | 80cabfad | bellard | } else {
|
160 | 80cabfad | bellard | s->ier = val; |
161 | b41a2cd1 | bellard | serial_update_irq(s); |
162 | 80cabfad | bellard | } |
163 | 80cabfad | bellard | break;
|
164 | 80cabfad | bellard | case 2: |
165 | 80cabfad | bellard | break;
|
166 | 80cabfad | bellard | case 3: |
167 | 80cabfad | bellard | s->lcr = val; |
168 | 80cabfad | bellard | break;
|
169 | 80cabfad | bellard | case 4: |
170 | 80cabfad | bellard | s->mcr = val; |
171 | 80cabfad | bellard | break;
|
172 | 80cabfad | bellard | case 5: |
173 | 80cabfad | bellard | break;
|
174 | 80cabfad | bellard | case 6: |
175 | 80cabfad | bellard | s->msr = val; |
176 | 80cabfad | bellard | break;
|
177 | 80cabfad | bellard | case 7: |
178 | 80cabfad | bellard | s->scr = val; |
179 | 80cabfad | bellard | break;
|
180 | 80cabfad | bellard | } |
181 | 80cabfad | bellard | } |
182 | 80cabfad | bellard | |
183 | b41a2cd1 | bellard | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
184 | 80cabfad | bellard | { |
185 | b41a2cd1 | bellard | SerialState *s = opaque; |
186 | 80cabfad | bellard | uint32_t ret; |
187 | 80cabfad | bellard | |
188 | 80cabfad | bellard | addr &= 7;
|
189 | 80cabfad | bellard | switch(addr) {
|
190 | 80cabfad | bellard | default:
|
191 | 80cabfad | bellard | case 0: |
192 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
|
193 | 80cabfad | bellard | ret = s->divider & 0xff;
|
194 | 80cabfad | bellard | } else {
|
195 | 80cabfad | bellard | ret = s->rbr; |
196 | 80cabfad | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
197 | b41a2cd1 | bellard | serial_update_irq(s); |
198 | 80cabfad | bellard | } |
199 | 80cabfad | bellard | break;
|
200 | 80cabfad | bellard | case 1: |
201 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
|
202 | 80cabfad | bellard | ret = (s->divider >> 8) & 0xff; |
203 | 80cabfad | bellard | } else {
|
204 | 80cabfad | bellard | ret = s->ier; |
205 | 80cabfad | bellard | } |
206 | 80cabfad | bellard | break;
|
207 | 80cabfad | bellard | case 2: |
208 | 80cabfad | bellard | ret = s->iir; |
209 | 80cabfad | bellard | /* reset THR pending bit */
|
210 | 80cabfad | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
211 | 80cabfad | bellard | s->thr_ipending = 0;
|
212 | b41a2cd1 | bellard | serial_update_irq(s); |
213 | 80cabfad | bellard | break;
|
214 | 80cabfad | bellard | case 3: |
215 | 80cabfad | bellard | ret = s->lcr; |
216 | 80cabfad | bellard | break;
|
217 | 80cabfad | bellard | case 4: |
218 | 80cabfad | bellard | ret = s->mcr; |
219 | 80cabfad | bellard | break;
|
220 | 80cabfad | bellard | case 5: |
221 | 80cabfad | bellard | ret = s->lsr; |
222 | 80cabfad | bellard | break;
|
223 | 80cabfad | bellard | case 6: |
224 | 80cabfad | bellard | if (s->mcr & UART_MCR_LOOP) {
|
225 | 80cabfad | bellard | /* in loopback, the modem output pins are connected to the
|
226 | 80cabfad | bellard | inputs */
|
227 | 80cabfad | bellard | ret = (s->mcr & 0x0c) << 4; |
228 | 80cabfad | bellard | ret |= (s->mcr & 0x02) << 3; |
229 | 80cabfad | bellard | ret |= (s->mcr & 0x01) << 5; |
230 | 80cabfad | bellard | } else {
|
231 | 80cabfad | bellard | ret = s->msr; |
232 | 80cabfad | bellard | } |
233 | 80cabfad | bellard | break;
|
234 | 80cabfad | bellard | case 7: |
235 | 80cabfad | bellard | ret = s->scr; |
236 | 80cabfad | bellard | break;
|
237 | 80cabfad | bellard | } |
238 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
|
239 | 80cabfad | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
240 | 80cabfad | bellard | #endif
|
241 | 80cabfad | bellard | return ret;
|
242 | 80cabfad | bellard | } |
243 | 80cabfad | bellard | |
244 | b41a2cd1 | bellard | int serial_can_receive(SerialState *s)
|
245 | 80cabfad | bellard | { |
246 | 80cabfad | bellard | return !(s->lsr & UART_LSR_DR);
|
247 | 80cabfad | bellard | } |
248 | 80cabfad | bellard | |
249 | b41a2cd1 | bellard | void serial_receive_byte(SerialState *s, int ch) |
250 | 80cabfad | bellard | { |
251 | 80cabfad | bellard | s->rbr = ch; |
252 | 80cabfad | bellard | s->lsr |= UART_LSR_DR; |
253 | b41a2cd1 | bellard | serial_update_irq(s); |
254 | 80cabfad | bellard | } |
255 | 80cabfad | bellard | |
256 | b41a2cd1 | bellard | void serial_receive_break(SerialState *s)
|
257 | 80cabfad | bellard | { |
258 | 80cabfad | bellard | s->rbr = 0;
|
259 | 80cabfad | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
260 | b41a2cd1 | bellard | serial_update_irq(s); |
261 | 80cabfad | bellard | } |
262 | 80cabfad | bellard | |
263 | b41a2cd1 | bellard | static int serial_can_receive1(void *opaque) |
264 | 80cabfad | bellard | { |
265 | b41a2cd1 | bellard | SerialState *s = opaque; |
266 | b41a2cd1 | bellard | return serial_can_receive(s);
|
267 | b41a2cd1 | bellard | } |
268 | b41a2cd1 | bellard | |
269 | b41a2cd1 | bellard | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
270 | b41a2cd1 | bellard | { |
271 | b41a2cd1 | bellard | SerialState *s = opaque; |
272 | b41a2cd1 | bellard | serial_receive_byte(s, buf[0]);
|
273 | b41a2cd1 | bellard | } |
274 | 80cabfad | bellard | |
275 | b41a2cd1 | bellard | /* If fd is zero, it means that the serial device uses the console */
|
276 | b41a2cd1 | bellard | SerialState *serial_init(int base, int irq, int fd) |
277 | b41a2cd1 | bellard | { |
278 | b41a2cd1 | bellard | SerialState *s; |
279 | b41a2cd1 | bellard | |
280 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(SerialState));
|
281 | b41a2cd1 | bellard | if (!s)
|
282 | b41a2cd1 | bellard | return NULL; |
283 | 80cabfad | bellard | s->irq = irq; |
284 | 80cabfad | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
285 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
286 | b41a2cd1 | bellard | |
287 | b41a2cd1 | bellard | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
288 | b41a2cd1 | bellard | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
289 | b41a2cd1 | bellard | |
290 | b41a2cd1 | bellard | if (fd != 0) { |
291 | b41a2cd1 | bellard | add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); |
292 | b41a2cd1 | bellard | s->out_fd = fd; |
293 | b41a2cd1 | bellard | } else {
|
294 | b41a2cd1 | bellard | serial_console = s; |
295 | b41a2cd1 | bellard | s->out_fd = 1;
|
296 | b41a2cd1 | bellard | } |
297 | b41a2cd1 | bellard | return s;
|
298 | 80cabfad | bellard | } |