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/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h" |
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#include "qemu-timer.h" |
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#include "sun4m.h" |
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#include "nvram.h" |
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#include "sparc32_dma.h" |
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#include "fdc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "esp.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "fw_cfg.h" |
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#include "escc.h" |
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#include "empty_slot.h" |
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#include "qdev-addr.h" |
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#include "loader.h" |
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#include "elf.h" |
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//#define DEBUG_IRQ
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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* SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define CMDLINE_ADDR 0x007ff000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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#define PROM_SIZE_MAX (1024 * 1024) |
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#define PROM_VADDR 0xffd00000 |
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#define PROM_FILENAME "openbios-sparc32" |
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#define CFG_ADDR 0xd00000510ULL |
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#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
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#define MAX_CPUS 16 |
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#define MAX_PILS 16 |
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#define ESCC_CLOCK 4915200 |
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struct sun4m_hwdef {
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target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
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target_phys_addr_t ecc_base; |
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uint32_t ecc_version; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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#define MAX_IOUNITS 5 |
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
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target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base; |
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target_phys_addr_t espdma_base, esp_base; |
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target_phys_addr_t ledma_base, le_base; |
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target_phys_addr_t tcx_base; |
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target_phys_addr_t sbi_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iounit_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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struct sun4c_hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, aux1_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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|
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
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{ |
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} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
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{ |
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0; |
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} |
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static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
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const char *cmdline, const char *boot_devices, |
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ram_addr_t RAM_size, uint32_t kernel_size, |
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int width, int height, int depth, |
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int nvram_machine_id, const char *arch) |
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
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nvram_machine_id); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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} |
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static DeviceState *slavio_intctl;
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void pic_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_pic_info(mon, slavio_intctl); |
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} |
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void irq_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_irq_info(mon, slavio_intctl); |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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if (env->pil_in && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (env->pil_in & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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} |
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static void main_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 0;
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} |
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static void secondary_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 1;
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} |
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static void cpu_halt_signal(void *opaque, int irq, int level) |
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{ |
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if (level && cpu_single_env)
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
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} |
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
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{ |
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return addr - 0xf0000000ULL; |
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} |
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static unsigned long sun4m_load_kernel(const char *kernel_filename, |
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const char *initrd_filename, |
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ram_addr_t RAM_size) |
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{ |
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int linux_boot;
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unsigned int i; |
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long initrd_size, kernel_size;
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uint8_t *ptr; |
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
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TARGET_PAGE_SIZE); |
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if (kernel_size < 0) |
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kernel_size = load_image_targphys(kernel_filename, |
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KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
335 |
if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
338 |
exit(1);
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} |
340 |
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, |
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INITRD_LOAD_ADDR, |
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RAM_size - INITRD_LOAD_ADDR); |
347 |
if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
350 |
exit(1);
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} |
352 |
} |
353 |
if (initrd_size > 0) { |
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
356 |
if (ldl_p(ptr) == 0x48647253) { // HdrS |
357 |
stl_p(ptr + 16, INITRD_LOAD_ADDR);
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stl_p(ptr + 20, initrd_size);
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break;
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360 |
} |
361 |
} |
362 |
} |
363 |
} |
364 |
return kernel_size;
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} |
366 |
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367 |
static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
368 |
{ |
369 |
DeviceState *dev; |
370 |
SysBusDevice *s; |
371 |
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dev = qdev_create(NULL, "iommu"); |
373 |
qdev_prop_set_uint32(dev, "version", version);
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374 |
qdev_init_nofail(dev); |
375 |
s = sysbus_from_qdev(dev); |
376 |
sysbus_connect_irq(s, 0, irq);
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377 |
sysbus_mmio_map(s, 0, addr);
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378 |
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return s;
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} |
381 |
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static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
383 |
void *iommu, qemu_irq *dev_irq)
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{ |
385 |
DeviceState *dev; |
386 |
SysBusDevice *s; |
387 |
|
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dev = qdev_create(NULL, "sparc32_dma"); |
389 |
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
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390 |
qdev_init_nofail(dev); |
391 |
s = sysbus_from_qdev(dev); |
392 |
sysbus_connect_irq(s, 0, parent_irq);
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393 |
*dev_irq = qdev_get_gpio_in(dev, 0);
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394 |
sysbus_mmio_map(s, 0, daddr);
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395 |
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396 |
return s;
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} |
398 |
|
399 |
static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
400 |
void *dma_opaque, qemu_irq irq)
|
401 |
{ |
402 |
DeviceState *dev; |
403 |
SysBusDevice *s; |
404 |
qemu_irq reset; |
405 |
|
406 |
qemu_check_nic_model(&nd_table[0], "lance"); |
407 |
|
408 |
dev = qdev_create(NULL, "lance"); |
409 |
qdev_set_nic_properties(dev, nd); |
410 |
qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
411 |
qdev_init_nofail(dev); |
412 |
s = sysbus_from_qdev(dev); |
413 |
sysbus_mmio_map(s, 0, leaddr);
|
414 |
sysbus_connect_irq(s, 0, irq);
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415 |
reset = qdev_get_gpio_in(dev, 0);
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416 |
qdev_connect_gpio_out(dma_opaque, 0, reset);
|
417 |
} |
418 |
|
419 |
static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
|
420 |
target_phys_addr_t addrg, |
421 |
qemu_irq **parent_irq) |
422 |
{ |
423 |
DeviceState *dev; |
424 |
SysBusDevice *s; |
425 |
unsigned int i, j; |
426 |
|
427 |
dev = qdev_create(NULL, "slavio_intctl"); |
428 |
qdev_init_nofail(dev); |
429 |
|
430 |
s = sysbus_from_qdev(dev); |
431 |
|
432 |
for (i = 0; i < MAX_CPUS; i++) { |
433 |
for (j = 0; j < MAX_PILS; j++) { |
434 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
435 |
} |
436 |
} |
437 |
sysbus_mmio_map(s, 0, addrg);
|
438 |
for (i = 0; i < MAX_CPUS; i++) { |
439 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
440 |
} |
441 |
|
442 |
return dev;
|
443 |
} |
444 |
|
445 |
#define SYS_TIMER_OFFSET 0x10000ULL |
446 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
447 |
|
448 |
static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
449 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
450 |
{ |
451 |
DeviceState *dev; |
452 |
SysBusDevice *s; |
453 |
unsigned int i; |
454 |
|
455 |
dev = qdev_create(NULL, "slavio_timer"); |
456 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
457 |
qdev_init_nofail(dev); |
458 |
s = sysbus_from_qdev(dev); |
459 |
sysbus_connect_irq(s, 0, master_irq);
|
460 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
461 |
|
462 |
for (i = 0; i < MAX_CPUS; i++) { |
463 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
|
464 |
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
465 |
} |
466 |
} |
467 |
|
468 |
#define MISC_LEDS 0x01600000 |
469 |
#define MISC_CFG 0x01800000 |
470 |
#define MISC_DIAG 0x01a00000 |
471 |
#define MISC_MDM 0x01b00000 |
472 |
#define MISC_SYS 0x01f00000 |
473 |
|
474 |
static void slavio_misc_init(target_phys_addr_t base, |
475 |
target_phys_addr_t aux1_base, |
476 |
target_phys_addr_t aux2_base, qemu_irq irq, |
477 |
qemu_irq fdc_tc) |
478 |
{ |
479 |
DeviceState *dev; |
480 |
SysBusDevice *s; |
481 |
|
482 |
dev = qdev_create(NULL, "slavio_misc"); |
483 |
qdev_init_nofail(dev); |
484 |
s = sysbus_from_qdev(dev); |
485 |
if (base) {
|
486 |
/* 8 bit registers */
|
487 |
/* Slavio control */
|
488 |
sysbus_mmio_map(s, 0, base + MISC_CFG);
|
489 |
/* Diagnostics */
|
490 |
sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
491 |
/* Modem control */
|
492 |
sysbus_mmio_map(s, 2, base + MISC_MDM);
|
493 |
/* 16 bit registers */
|
494 |
/* ss600mp diag LEDs */
|
495 |
sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
496 |
/* 32 bit registers */
|
497 |
/* System control */
|
498 |
sysbus_mmio_map(s, 4, base + MISC_SYS);
|
499 |
} |
500 |
if (aux1_base) {
|
501 |
/* AUX 1 (Misc System Functions) */
|
502 |
sysbus_mmio_map(s, 5, aux1_base);
|
503 |
} |
504 |
if (aux2_base) {
|
505 |
/* AUX 2 (Software Powerdown Control) */
|
506 |
sysbus_mmio_map(s, 6, aux2_base);
|
507 |
} |
508 |
sysbus_connect_irq(s, 0, irq);
|
509 |
sysbus_connect_irq(s, 1, fdc_tc);
|
510 |
qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
511 |
} |
512 |
|
513 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
514 |
{ |
515 |
DeviceState *dev; |
516 |
SysBusDevice *s; |
517 |
|
518 |
dev = qdev_create(NULL, "eccmemctl"); |
519 |
qdev_prop_set_uint32(dev, "version", version);
|
520 |
qdev_init_nofail(dev); |
521 |
s = sysbus_from_qdev(dev); |
522 |
sysbus_connect_irq(s, 0, irq);
|
523 |
sysbus_mmio_map(s, 0, base);
|
524 |
if (version == 0) { // SS-600MP only |
525 |
sysbus_mmio_map(s, 1, base + 0x1000); |
526 |
} |
527 |
} |
528 |
|
529 |
static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
530 |
{ |
531 |
DeviceState *dev; |
532 |
SysBusDevice *s; |
533 |
|
534 |
dev = qdev_create(NULL, "apc"); |
535 |
qdev_init_nofail(dev); |
536 |
s = sysbus_from_qdev(dev); |
537 |
/* Power management (APC) XXX: not a Slavio device */
|
538 |
sysbus_mmio_map(s, 0, power_base);
|
539 |
sysbus_connect_irq(s, 0, cpu_halt);
|
540 |
} |
541 |
|
542 |
static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
543 |
int height, int depth) |
544 |
{ |
545 |
DeviceState *dev; |
546 |
SysBusDevice *s; |
547 |
|
548 |
dev = qdev_create(NULL, "SUNW,tcx"); |
549 |
qdev_prop_set_taddr(dev, "addr", addr);
|
550 |
qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
551 |
qdev_prop_set_uint16(dev, "width", width);
|
552 |
qdev_prop_set_uint16(dev, "height", height);
|
553 |
qdev_prop_set_uint16(dev, "depth", depth);
|
554 |
qdev_init_nofail(dev); |
555 |
s = sysbus_from_qdev(dev); |
556 |
/* 8-bit plane */
|
557 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
558 |
/* DAC */
|
559 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
560 |
/* TEC (dummy) */
|
561 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
562 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
563 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
564 |
if (depth == 24) { |
565 |
/* 24-bit plane */
|
566 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
567 |
/* Control plane */
|
568 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
569 |
} else {
|
570 |
/* THC 8 bit (dummy) */
|
571 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
572 |
} |
573 |
} |
574 |
|
575 |
/* NCR89C100/MACIO Internal ID register */
|
576 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
577 |
|
578 |
static void idreg_init(target_phys_addr_t addr) |
579 |
{ |
580 |
DeviceState *dev; |
581 |
SysBusDevice *s; |
582 |
|
583 |
dev = qdev_create(NULL, "macio_idreg"); |
584 |
qdev_init_nofail(dev); |
585 |
s = sysbus_from_qdev(dev); |
586 |
|
587 |
sysbus_mmio_map(s, 0, addr);
|
588 |
cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
589 |
} |
590 |
|
591 |
static int idreg_init1(SysBusDevice *dev) |
592 |
{ |
593 |
ram_addr_t idreg_offset; |
594 |
|
595 |
idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data)); |
596 |
sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
597 |
return 0; |
598 |
} |
599 |
|
600 |
static SysBusDeviceInfo idreg_info = {
|
601 |
.init = idreg_init1, |
602 |
.qdev.name = "macio_idreg",
|
603 |
.qdev.size = sizeof(SysBusDevice),
|
604 |
}; |
605 |
|
606 |
static void idreg_register_devices(void) |
607 |
{ |
608 |
sysbus_register_withprop(&idreg_info); |
609 |
} |
610 |
|
611 |
device_init(idreg_register_devices); |
612 |
|
613 |
/* SS-5 TCX AFX register */
|
614 |
static void afx_init(target_phys_addr_t addr) |
615 |
{ |
616 |
DeviceState *dev; |
617 |
SysBusDevice *s; |
618 |
|
619 |
dev = qdev_create(NULL, "tcx_afx"); |
620 |
qdev_init_nofail(dev); |
621 |
s = sysbus_from_qdev(dev); |
622 |
|
623 |
sysbus_mmio_map(s, 0, addr);
|
624 |
} |
625 |
|
626 |
static int afx_init1(SysBusDevice *dev) |
627 |
{ |
628 |
ram_addr_t afx_offset; |
629 |
|
630 |
afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4); |
631 |
sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
|
632 |
return 0; |
633 |
} |
634 |
|
635 |
static SysBusDeviceInfo afx_info = {
|
636 |
.init = afx_init1, |
637 |
.qdev.name = "tcx_afx",
|
638 |
.qdev.size = sizeof(SysBusDevice),
|
639 |
}; |
640 |
|
641 |
static void afx_register_devices(void) |
642 |
{ |
643 |
sysbus_register_withprop(&afx_info); |
644 |
} |
645 |
|
646 |
device_init(afx_register_devices); |
647 |
|
648 |
/* Boot PROM (OpenBIOS) */
|
649 |
static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
650 |
{ |
651 |
target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
652 |
return addr + *base_addr - PROM_VADDR;
|
653 |
} |
654 |
|
655 |
static void prom_init(target_phys_addr_t addr, const char *bios_name) |
656 |
{ |
657 |
DeviceState *dev; |
658 |
SysBusDevice *s; |
659 |
char *filename;
|
660 |
int ret;
|
661 |
|
662 |
dev = qdev_create(NULL, "openprom"); |
663 |
qdev_init_nofail(dev); |
664 |
s = sysbus_from_qdev(dev); |
665 |
|
666 |
sysbus_mmio_map(s, 0, addr);
|
667 |
|
668 |
/* load boot prom */
|
669 |
if (bios_name == NULL) { |
670 |
bios_name = PROM_FILENAME; |
671 |
} |
672 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
673 |
if (filename) {
|
674 |
ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
675 |
NULL, NULL, 1, ELF_MACHINE, 0); |
676 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
677 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
678 |
} |
679 |
qemu_free(filename); |
680 |
} else {
|
681 |
ret = -1;
|
682 |
} |
683 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
684 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
685 |
exit(1);
|
686 |
} |
687 |
} |
688 |
|
689 |
static int prom_init1(SysBusDevice *dev) |
690 |
{ |
691 |
ram_addr_t prom_offset; |
692 |
|
693 |
prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX); |
694 |
sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
695 |
return 0; |
696 |
} |
697 |
|
698 |
static SysBusDeviceInfo prom_info = {
|
699 |
.init = prom_init1, |
700 |
.qdev.name = "openprom",
|
701 |
.qdev.size = sizeof(SysBusDevice),
|
702 |
.qdev.props = (Property[]) { |
703 |
{/* end of property list */}
|
704 |
} |
705 |
}; |
706 |
|
707 |
static void prom_register_devices(void) |
708 |
{ |
709 |
sysbus_register_withprop(&prom_info); |
710 |
} |
711 |
|
712 |
device_init(prom_register_devices); |
713 |
|
714 |
typedef struct RamDevice |
715 |
{ |
716 |
SysBusDevice busdev; |
717 |
uint64_t size; |
718 |
} RamDevice; |
719 |
|
720 |
/* System RAM */
|
721 |
static int ram_init1(SysBusDevice *dev) |
722 |
{ |
723 |
ram_addr_t RAM_size, ram_offset; |
724 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
725 |
|
726 |
RAM_size = d->size; |
727 |
|
728 |
ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size); |
729 |
sysbus_init_mmio(dev, RAM_size, ram_offset); |
730 |
return 0; |
731 |
} |
732 |
|
733 |
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
734 |
uint64_t max_mem) |
735 |
{ |
736 |
DeviceState *dev; |
737 |
SysBusDevice *s; |
738 |
RamDevice *d; |
739 |
|
740 |
/* allocate RAM */
|
741 |
if ((uint64_t)RAM_size > max_mem) {
|
742 |
fprintf(stderr, |
743 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
744 |
(unsigned int)(RAM_size / (1024 * 1024)), |
745 |
(unsigned int)(max_mem / (1024 * 1024))); |
746 |
exit(1);
|
747 |
} |
748 |
dev = qdev_create(NULL, "memory"); |
749 |
s = sysbus_from_qdev(dev); |
750 |
|
751 |
d = FROM_SYSBUS(RamDevice, s); |
752 |
d->size = RAM_size; |
753 |
qdev_init_nofail(dev); |
754 |
|
755 |
sysbus_mmio_map(s, 0, addr);
|
756 |
} |
757 |
|
758 |
static SysBusDeviceInfo ram_info = {
|
759 |
.init = ram_init1, |
760 |
.qdev.name = "memory",
|
761 |
.qdev.size = sizeof(RamDevice),
|
762 |
.qdev.props = (Property[]) { |
763 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
764 |
DEFINE_PROP_END_OF_LIST(), |
765 |
} |
766 |
}; |
767 |
|
768 |
static void ram_register_devices(void) |
769 |
{ |
770 |
sysbus_register_withprop(&ram_info); |
771 |
} |
772 |
|
773 |
device_init(ram_register_devices); |
774 |
|
775 |
static void cpu_devinit(const char *cpu_model, unsigned int id, |
776 |
uint64_t prom_addr, qemu_irq **cpu_irqs) |
777 |
{ |
778 |
CPUState *env; |
779 |
|
780 |
env = cpu_init(cpu_model); |
781 |
if (!env) {
|
782 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
783 |
exit(1);
|
784 |
} |
785 |
|
786 |
cpu_sparc_set_id(env, id); |
787 |
if (id == 0) { |
788 |
qemu_register_reset(main_cpu_reset, env); |
789 |
} else {
|
790 |
qemu_register_reset(secondary_cpu_reset, env); |
791 |
env->halted = 1;
|
792 |
} |
793 |
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
794 |
env->prom_addr = prom_addr; |
795 |
} |
796 |
|
797 |
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
798 |
const char *boot_device, |
799 |
const char *kernel_filename, |
800 |
const char *kernel_cmdline, |
801 |
const char *initrd_filename, const char *cpu_model) |
802 |
{ |
803 |
unsigned int i; |
804 |
void *iommu, *espdma, *ledma, *nvram;
|
805 |
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
806 |
espdma_irq, ledma_irq; |
807 |
qemu_irq esp_reset; |
808 |
qemu_irq fdc_tc; |
809 |
qemu_irq *cpu_halt; |
810 |
unsigned long kernel_size; |
811 |
DriveInfo *fd[MAX_FD]; |
812 |
void *fw_cfg;
|
813 |
|
814 |
/* init CPUs */
|
815 |
if (!cpu_model)
|
816 |
cpu_model = hwdef->default_cpu_model; |
817 |
|
818 |
for(i = 0; i < smp_cpus; i++) { |
819 |
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
820 |
} |
821 |
|
822 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
823 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
824 |
|
825 |
|
826 |
/* set up devices */
|
827 |
ram_init(0, RAM_size, hwdef->max_mem);
|
828 |
/* models without ECC don't trap when missing ram is accessed */
|
829 |
if (!hwdef->ecc_base) {
|
830 |
empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); |
831 |
} |
832 |
|
833 |
prom_init(hwdef->slavio_base, bios_name); |
834 |
|
835 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
836 |
hwdef->intctl_base + 0x10000ULL,
|
837 |
cpu_irqs); |
838 |
|
839 |
for (i = 0; i < 32; i++) { |
840 |
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
841 |
} |
842 |
for (i = 0; i < MAX_CPUS; i++) { |
843 |
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
844 |
} |
845 |
|
846 |
if (hwdef->idreg_base) {
|
847 |
idreg_init(hwdef->idreg_base); |
848 |
} |
849 |
|
850 |
if (hwdef->afx_base) {
|
851 |
afx_init(hwdef->afx_base); |
852 |
} |
853 |
|
854 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
855 |
slavio_irq[30]);
|
856 |
|
857 |
if (hwdef->iommu_pad_base) {
|
858 |
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
859 |
Software shouldn't use aliased addresses, neither should it crash
|
860 |
when does. Using empty_slot instead of aliasing can help with
|
861 |
debugging such accesses */
|
862 |
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); |
863 |
} |
864 |
|
865 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
866 |
iommu, &espdma_irq); |
867 |
|
868 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
869 |
slavio_irq[16], iommu, &ledma_irq);
|
870 |
|
871 |
if (graphic_depth != 8 && graphic_depth != 24) { |
872 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
873 |
exit (1);
|
874 |
} |
875 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
876 |
graphic_depth); |
877 |
|
878 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
879 |
|
880 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
881 |
|
882 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
883 |
|
884 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
885 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
886 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
887 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
888 |
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
889 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
890 |
|
891 |
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
892 |
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
893 |
slavio_irq[30], fdc_tc);
|
894 |
|
895 |
if (hwdef->apc_base) {
|
896 |
apc_init(hwdef->apc_base, cpu_halt[0]);
|
897 |
} |
898 |
|
899 |
if (hwdef->fd_base) {
|
900 |
/* there is zero or one floppy drive */
|
901 |
memset(fd, 0, sizeof(fd)); |
902 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
903 |
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
904 |
&fdc_tc); |
905 |
} |
906 |
|
907 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
908 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
909 |
exit(1);
|
910 |
} |
911 |
|
912 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
913 |
esp_init(hwdef->esp_base, 2,
|
914 |
espdma_memory_read, espdma_memory_write, |
915 |
espdma, espdma_irq, &esp_reset); |
916 |
|
917 |
|
918 |
if (hwdef->cs_base) {
|
919 |
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
920 |
slavio_irq[5]);
|
921 |
} |
922 |
|
923 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
924 |
RAM_size); |
925 |
|
926 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
927 |
boot_device, RAM_size, kernel_size, graphic_width, |
928 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
929 |
"Sun4m");
|
930 |
|
931 |
if (hwdef->ecc_base)
|
932 |
ecc_init(hwdef->ecc_base, slavio_irq[28],
|
933 |
hwdef->ecc_version); |
934 |
|
935 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
936 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
937 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
938 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
939 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
940 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
941 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
942 |
if (kernel_cmdline) {
|
943 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
944 |
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
945 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
946 |
(uint8_t*)strdup(kernel_cmdline), |
947 |
strlen(kernel_cmdline) + 1);
|
948 |
} else {
|
949 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
950 |
} |
951 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
952 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
953 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
954 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
955 |
} |
956 |
|
957 |
enum {
|
958 |
ss2_id = 0,
|
959 |
ss5_id = 32,
|
960 |
vger_id, |
961 |
lx_id, |
962 |
ss4_id, |
963 |
scls_id, |
964 |
sbook_id, |
965 |
ss10_id = 64,
|
966 |
ss20_id, |
967 |
ss600mp_id, |
968 |
ss1000_id = 96,
|
969 |
ss2000_id, |
970 |
}; |
971 |
|
972 |
static const struct sun4m_hwdef sun4m_hwdefs[] = { |
973 |
/* SS-5 */
|
974 |
{ |
975 |
.iommu_base = 0x10000000,
|
976 |
.iommu_pad_base = 0x10004000,
|
977 |
.iommu_pad_len = 0x0fffb000,
|
978 |
.tcx_base = 0x50000000,
|
979 |
.cs_base = 0x6c000000,
|
980 |
.slavio_base = 0x70000000,
|
981 |
.ms_kb_base = 0x71000000,
|
982 |
.serial_base = 0x71100000,
|
983 |
.nvram_base = 0x71200000,
|
984 |
.fd_base = 0x71400000,
|
985 |
.counter_base = 0x71d00000,
|
986 |
.intctl_base = 0x71e00000,
|
987 |
.idreg_base = 0x78000000,
|
988 |
.dma_base = 0x78400000,
|
989 |
.esp_base = 0x78800000,
|
990 |
.le_base = 0x78c00000,
|
991 |
.apc_base = 0x6a000000,
|
992 |
.afx_base = 0x6e000000,
|
993 |
.aux1_base = 0x71900000,
|
994 |
.aux2_base = 0x71910000,
|
995 |
.nvram_machine_id = 0x80,
|
996 |
.machine_id = ss5_id, |
997 |
.iommu_version = 0x05000000,
|
998 |
.max_mem = 0x10000000,
|
999 |
.default_cpu_model = "Fujitsu MB86904",
|
1000 |
}, |
1001 |
/* SS-10 */
|
1002 |
{ |
1003 |
.iommu_base = 0xfe0000000ULL,
|
1004 |
.tcx_base = 0xe20000000ULL,
|
1005 |
.slavio_base = 0xff0000000ULL,
|
1006 |
.ms_kb_base = 0xff1000000ULL,
|
1007 |
.serial_base = 0xff1100000ULL,
|
1008 |
.nvram_base = 0xff1200000ULL,
|
1009 |
.fd_base = 0xff1700000ULL,
|
1010 |
.counter_base = 0xff1300000ULL,
|
1011 |
.intctl_base = 0xff1400000ULL,
|
1012 |
.idreg_base = 0xef0000000ULL,
|
1013 |
.dma_base = 0xef0400000ULL,
|
1014 |
.esp_base = 0xef0800000ULL,
|
1015 |
.le_base = 0xef0c00000ULL,
|
1016 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1017 |
.aux1_base = 0xff1800000ULL,
|
1018 |
.aux2_base = 0xff1a01000ULL,
|
1019 |
.ecc_base = 0xf00000000ULL,
|
1020 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
1021 |
.nvram_machine_id = 0x72,
|
1022 |
.machine_id = ss10_id, |
1023 |
.iommu_version = 0x03000000,
|
1024 |
.max_mem = 0xf00000000ULL,
|
1025 |
.default_cpu_model = "TI SuperSparc II",
|
1026 |
}, |
1027 |
/* SS-600MP */
|
1028 |
{ |
1029 |
.iommu_base = 0xfe0000000ULL,
|
1030 |
.tcx_base = 0xe20000000ULL,
|
1031 |
.slavio_base = 0xff0000000ULL,
|
1032 |
.ms_kb_base = 0xff1000000ULL,
|
1033 |
.serial_base = 0xff1100000ULL,
|
1034 |
.nvram_base = 0xff1200000ULL,
|
1035 |
.counter_base = 0xff1300000ULL,
|
1036 |
.intctl_base = 0xff1400000ULL,
|
1037 |
.dma_base = 0xef0081000ULL,
|
1038 |
.esp_base = 0xef0080000ULL,
|
1039 |
.le_base = 0xef0060000ULL,
|
1040 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1041 |
.aux1_base = 0xff1800000ULL,
|
1042 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
1043 |
.ecc_base = 0xf00000000ULL,
|
1044 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
1045 |
.nvram_machine_id = 0x71,
|
1046 |
.machine_id = ss600mp_id, |
1047 |
.iommu_version = 0x01000000,
|
1048 |
.max_mem = 0xf00000000ULL,
|
1049 |
.default_cpu_model = "TI SuperSparc II",
|
1050 |
}, |
1051 |
/* SS-20 */
|
1052 |
{ |
1053 |
.iommu_base = 0xfe0000000ULL,
|
1054 |
.tcx_base = 0xe20000000ULL,
|
1055 |
.slavio_base = 0xff0000000ULL,
|
1056 |
.ms_kb_base = 0xff1000000ULL,
|
1057 |
.serial_base = 0xff1100000ULL,
|
1058 |
.nvram_base = 0xff1200000ULL,
|
1059 |
.fd_base = 0xff1700000ULL,
|
1060 |
.counter_base = 0xff1300000ULL,
|
1061 |
.intctl_base = 0xff1400000ULL,
|
1062 |
.idreg_base = 0xef0000000ULL,
|
1063 |
.dma_base = 0xef0400000ULL,
|
1064 |
.esp_base = 0xef0800000ULL,
|
1065 |
.le_base = 0xef0c00000ULL,
|
1066 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
1067 |
.aux1_base = 0xff1800000ULL,
|
1068 |
.aux2_base = 0xff1a01000ULL,
|
1069 |
.ecc_base = 0xf00000000ULL,
|
1070 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
1071 |
.nvram_machine_id = 0x72,
|
1072 |
.machine_id = ss20_id, |
1073 |
.iommu_version = 0x13000000,
|
1074 |
.max_mem = 0xf00000000ULL,
|
1075 |
.default_cpu_model = "TI SuperSparc II",
|
1076 |
}, |
1077 |
/* Voyager */
|
1078 |
{ |
1079 |
.iommu_base = 0x10000000,
|
1080 |
.tcx_base = 0x50000000,
|
1081 |
.slavio_base = 0x70000000,
|
1082 |
.ms_kb_base = 0x71000000,
|
1083 |
.serial_base = 0x71100000,
|
1084 |
.nvram_base = 0x71200000,
|
1085 |
.fd_base = 0x71400000,
|
1086 |
.counter_base = 0x71d00000,
|
1087 |
.intctl_base = 0x71e00000,
|
1088 |
.idreg_base = 0x78000000,
|
1089 |
.dma_base = 0x78400000,
|
1090 |
.esp_base = 0x78800000,
|
1091 |
.le_base = 0x78c00000,
|
1092 |
.apc_base = 0x71300000, // pmc |
1093 |
.aux1_base = 0x71900000,
|
1094 |
.aux2_base = 0x71910000,
|
1095 |
.nvram_machine_id = 0x80,
|
1096 |
.machine_id = vger_id, |
1097 |
.iommu_version = 0x05000000,
|
1098 |
.max_mem = 0x10000000,
|
1099 |
.default_cpu_model = "Fujitsu MB86904",
|
1100 |
}, |
1101 |
/* LX */
|
1102 |
{ |
1103 |
.iommu_base = 0x10000000,
|
1104 |
.iommu_pad_base = 0x10004000,
|
1105 |
.iommu_pad_len = 0x0fffb000,
|
1106 |
.tcx_base = 0x50000000,
|
1107 |
.slavio_base = 0x70000000,
|
1108 |
.ms_kb_base = 0x71000000,
|
1109 |
.serial_base = 0x71100000,
|
1110 |
.nvram_base = 0x71200000,
|
1111 |
.fd_base = 0x71400000,
|
1112 |
.counter_base = 0x71d00000,
|
1113 |
.intctl_base = 0x71e00000,
|
1114 |
.idreg_base = 0x78000000,
|
1115 |
.dma_base = 0x78400000,
|
1116 |
.esp_base = 0x78800000,
|
1117 |
.le_base = 0x78c00000,
|
1118 |
.aux1_base = 0x71900000,
|
1119 |
.aux2_base = 0x71910000,
|
1120 |
.nvram_machine_id = 0x80,
|
1121 |
.machine_id = lx_id, |
1122 |
.iommu_version = 0x04000000,
|
1123 |
.max_mem = 0x10000000,
|
1124 |
.default_cpu_model = "TI MicroSparc I",
|
1125 |
}, |
1126 |
/* SS-4 */
|
1127 |
{ |
1128 |
.iommu_base = 0x10000000,
|
1129 |
.tcx_base = 0x50000000,
|
1130 |
.cs_base = 0x6c000000,
|
1131 |
.slavio_base = 0x70000000,
|
1132 |
.ms_kb_base = 0x71000000,
|
1133 |
.serial_base = 0x71100000,
|
1134 |
.nvram_base = 0x71200000,
|
1135 |
.fd_base = 0x71400000,
|
1136 |
.counter_base = 0x71d00000,
|
1137 |
.intctl_base = 0x71e00000,
|
1138 |
.idreg_base = 0x78000000,
|
1139 |
.dma_base = 0x78400000,
|
1140 |
.esp_base = 0x78800000,
|
1141 |
.le_base = 0x78c00000,
|
1142 |
.apc_base = 0x6a000000,
|
1143 |
.aux1_base = 0x71900000,
|
1144 |
.aux2_base = 0x71910000,
|
1145 |
.nvram_machine_id = 0x80,
|
1146 |
.machine_id = ss4_id, |
1147 |
.iommu_version = 0x05000000,
|
1148 |
.max_mem = 0x10000000,
|
1149 |
.default_cpu_model = "Fujitsu MB86904",
|
1150 |
}, |
1151 |
/* SPARCClassic */
|
1152 |
{ |
1153 |
.iommu_base = 0x10000000,
|
1154 |
.tcx_base = 0x50000000,
|
1155 |
.slavio_base = 0x70000000,
|
1156 |
.ms_kb_base = 0x71000000,
|
1157 |
.serial_base = 0x71100000,
|
1158 |
.nvram_base = 0x71200000,
|
1159 |
.fd_base = 0x71400000,
|
1160 |
.counter_base = 0x71d00000,
|
1161 |
.intctl_base = 0x71e00000,
|
1162 |
.idreg_base = 0x78000000,
|
1163 |
.dma_base = 0x78400000,
|
1164 |
.esp_base = 0x78800000,
|
1165 |
.le_base = 0x78c00000,
|
1166 |
.apc_base = 0x6a000000,
|
1167 |
.aux1_base = 0x71900000,
|
1168 |
.aux2_base = 0x71910000,
|
1169 |
.nvram_machine_id = 0x80,
|
1170 |
.machine_id = scls_id, |
1171 |
.iommu_version = 0x05000000,
|
1172 |
.max_mem = 0x10000000,
|
1173 |
.default_cpu_model = "TI MicroSparc I",
|
1174 |
}, |
1175 |
/* SPARCbook */
|
1176 |
{ |
1177 |
.iommu_base = 0x10000000,
|
1178 |
.tcx_base = 0x50000000, // XXX |
1179 |
.slavio_base = 0x70000000,
|
1180 |
.ms_kb_base = 0x71000000,
|
1181 |
.serial_base = 0x71100000,
|
1182 |
.nvram_base = 0x71200000,
|
1183 |
.fd_base = 0x71400000,
|
1184 |
.counter_base = 0x71d00000,
|
1185 |
.intctl_base = 0x71e00000,
|
1186 |
.idreg_base = 0x78000000,
|
1187 |
.dma_base = 0x78400000,
|
1188 |
.esp_base = 0x78800000,
|
1189 |
.le_base = 0x78c00000,
|
1190 |
.apc_base = 0x6a000000,
|
1191 |
.aux1_base = 0x71900000,
|
1192 |
.aux2_base = 0x71910000,
|
1193 |
.nvram_machine_id = 0x80,
|
1194 |
.machine_id = sbook_id, |
1195 |
.iommu_version = 0x05000000,
|
1196 |
.max_mem = 0x10000000,
|
1197 |
.default_cpu_model = "TI MicroSparc I",
|
1198 |
}, |
1199 |
}; |
1200 |
|
1201 |
/* SPARCstation 5 hardware initialisation */
|
1202 |
static void ss5_init(ram_addr_t RAM_size, |
1203 |
const char *boot_device, |
1204 |
const char *kernel_filename, const char *kernel_cmdline, |
1205 |
const char *initrd_filename, const char *cpu_model) |
1206 |
{ |
1207 |
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1208 |
kernel_cmdline, initrd_filename, cpu_model); |
1209 |
} |
1210 |
|
1211 |
/* SPARCstation 10 hardware initialisation */
|
1212 |
static void ss10_init(ram_addr_t RAM_size, |
1213 |
const char *boot_device, |
1214 |
const char *kernel_filename, const char *kernel_cmdline, |
1215 |
const char *initrd_filename, const char *cpu_model) |
1216 |
{ |
1217 |
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1218 |
kernel_cmdline, initrd_filename, cpu_model); |
1219 |
} |
1220 |
|
1221 |
/* SPARCserver 600MP hardware initialisation */
|
1222 |
static void ss600mp_init(ram_addr_t RAM_size, |
1223 |
const char *boot_device, |
1224 |
const char *kernel_filename, |
1225 |
const char *kernel_cmdline, |
1226 |
const char *initrd_filename, const char *cpu_model) |
1227 |
{ |
1228 |
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1229 |
kernel_cmdline, initrd_filename, cpu_model); |
1230 |
} |
1231 |
|
1232 |
/* SPARCstation 20 hardware initialisation */
|
1233 |
static void ss20_init(ram_addr_t RAM_size, |
1234 |
const char *boot_device, |
1235 |
const char *kernel_filename, const char *kernel_cmdline, |
1236 |
const char *initrd_filename, const char *cpu_model) |
1237 |
{ |
1238 |
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1239 |
kernel_cmdline, initrd_filename, cpu_model); |
1240 |
} |
1241 |
|
1242 |
/* SPARCstation Voyager hardware initialisation */
|
1243 |
static void vger_init(ram_addr_t RAM_size, |
1244 |
const char *boot_device, |
1245 |
const char *kernel_filename, const char *kernel_cmdline, |
1246 |
const char *initrd_filename, const char *cpu_model) |
1247 |
{ |
1248 |
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1249 |
kernel_cmdline, initrd_filename, cpu_model); |
1250 |
} |
1251 |
|
1252 |
/* SPARCstation LX hardware initialisation */
|
1253 |
static void ss_lx_init(ram_addr_t RAM_size, |
1254 |
const char *boot_device, |
1255 |
const char *kernel_filename, const char *kernel_cmdline, |
1256 |
const char *initrd_filename, const char *cpu_model) |
1257 |
{ |
1258 |
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1259 |
kernel_cmdline, initrd_filename, cpu_model); |
1260 |
} |
1261 |
|
1262 |
/* SPARCstation 4 hardware initialisation */
|
1263 |
static void ss4_init(ram_addr_t RAM_size, |
1264 |
const char *boot_device, |
1265 |
const char *kernel_filename, const char *kernel_cmdline, |
1266 |
const char *initrd_filename, const char *cpu_model) |
1267 |
{ |
1268 |
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1269 |
kernel_cmdline, initrd_filename, cpu_model); |
1270 |
} |
1271 |
|
1272 |
/* SPARCClassic hardware initialisation */
|
1273 |
static void scls_init(ram_addr_t RAM_size, |
1274 |
const char *boot_device, |
1275 |
const char *kernel_filename, const char *kernel_cmdline, |
1276 |
const char *initrd_filename, const char *cpu_model) |
1277 |
{ |
1278 |
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1279 |
kernel_cmdline, initrd_filename, cpu_model); |
1280 |
} |
1281 |
|
1282 |
/* SPARCbook hardware initialisation */
|
1283 |
static void sbook_init(ram_addr_t RAM_size, |
1284 |
const char *boot_device, |
1285 |
const char *kernel_filename, const char *kernel_cmdline, |
1286 |
const char *initrd_filename, const char *cpu_model) |
1287 |
{ |
1288 |
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1289 |
kernel_cmdline, initrd_filename, cpu_model); |
1290 |
} |
1291 |
|
1292 |
static QEMUMachine ss5_machine = {
|
1293 |
.name = "SS-5",
|
1294 |
.desc = "Sun4m platform, SPARCstation 5",
|
1295 |
.init = ss5_init, |
1296 |
.use_scsi = 1,
|
1297 |
.is_default = 1,
|
1298 |
}; |
1299 |
|
1300 |
static QEMUMachine ss10_machine = {
|
1301 |
.name = "SS-10",
|
1302 |
.desc = "Sun4m platform, SPARCstation 10",
|
1303 |
.init = ss10_init, |
1304 |
.use_scsi = 1,
|
1305 |
.max_cpus = 4,
|
1306 |
}; |
1307 |
|
1308 |
static QEMUMachine ss600mp_machine = {
|
1309 |
.name = "SS-600MP",
|
1310 |
.desc = "Sun4m platform, SPARCserver 600MP",
|
1311 |
.init = ss600mp_init, |
1312 |
.use_scsi = 1,
|
1313 |
.max_cpus = 4,
|
1314 |
}; |
1315 |
|
1316 |
static QEMUMachine ss20_machine = {
|
1317 |
.name = "SS-20",
|
1318 |
.desc = "Sun4m platform, SPARCstation 20",
|
1319 |
.init = ss20_init, |
1320 |
.use_scsi = 1,
|
1321 |
.max_cpus = 4,
|
1322 |
}; |
1323 |
|
1324 |
static QEMUMachine voyager_machine = {
|
1325 |
.name = "Voyager",
|
1326 |
.desc = "Sun4m platform, SPARCstation Voyager",
|
1327 |
.init = vger_init, |
1328 |
.use_scsi = 1,
|
1329 |
}; |
1330 |
|
1331 |
static QEMUMachine ss_lx_machine = {
|
1332 |
.name = "LX",
|
1333 |
.desc = "Sun4m platform, SPARCstation LX",
|
1334 |
.init = ss_lx_init, |
1335 |
.use_scsi = 1,
|
1336 |
}; |
1337 |
|
1338 |
static QEMUMachine ss4_machine = {
|
1339 |
.name = "SS-4",
|
1340 |
.desc = "Sun4m platform, SPARCstation 4",
|
1341 |
.init = ss4_init, |
1342 |
.use_scsi = 1,
|
1343 |
}; |
1344 |
|
1345 |
static QEMUMachine scls_machine = {
|
1346 |
.name = "SPARCClassic",
|
1347 |
.desc = "Sun4m platform, SPARCClassic",
|
1348 |
.init = scls_init, |
1349 |
.use_scsi = 1,
|
1350 |
}; |
1351 |
|
1352 |
static QEMUMachine sbook_machine = {
|
1353 |
.name = "SPARCbook",
|
1354 |
.desc = "Sun4m platform, SPARCbook",
|
1355 |
.init = sbook_init, |
1356 |
.use_scsi = 1,
|
1357 |
}; |
1358 |
|
1359 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1360 |
/* SS-1000 */
|
1361 |
{ |
1362 |
.iounit_bases = { |
1363 |
0xfe0200000ULL,
|
1364 |
0xfe1200000ULL,
|
1365 |
0xfe2200000ULL,
|
1366 |
0xfe3200000ULL,
|
1367 |
-1,
|
1368 |
}, |
1369 |
.tcx_base = 0x820000000ULL,
|
1370 |
.slavio_base = 0xf00000000ULL,
|
1371 |
.ms_kb_base = 0xf00240000ULL,
|
1372 |
.serial_base = 0xf00200000ULL,
|
1373 |
.nvram_base = 0xf00280000ULL,
|
1374 |
.counter_base = 0xf00300000ULL,
|
1375 |
.espdma_base = 0x800081000ULL,
|
1376 |
.esp_base = 0x800080000ULL,
|
1377 |
.ledma_base = 0x800040000ULL,
|
1378 |
.le_base = 0x800060000ULL,
|
1379 |
.sbi_base = 0xf02800000ULL,
|
1380 |
.nvram_machine_id = 0x80,
|
1381 |
.machine_id = ss1000_id, |
1382 |
.iounit_version = 0x03000000,
|
1383 |
.max_mem = 0xf00000000ULL,
|
1384 |
.default_cpu_model = "TI SuperSparc II",
|
1385 |
}, |
1386 |
/* SS-2000 */
|
1387 |
{ |
1388 |
.iounit_bases = { |
1389 |
0xfe0200000ULL,
|
1390 |
0xfe1200000ULL,
|
1391 |
0xfe2200000ULL,
|
1392 |
0xfe3200000ULL,
|
1393 |
0xfe4200000ULL,
|
1394 |
}, |
1395 |
.tcx_base = 0x820000000ULL,
|
1396 |
.slavio_base = 0xf00000000ULL,
|
1397 |
.ms_kb_base = 0xf00240000ULL,
|
1398 |
.serial_base = 0xf00200000ULL,
|
1399 |
.nvram_base = 0xf00280000ULL,
|
1400 |
.counter_base = 0xf00300000ULL,
|
1401 |
.espdma_base = 0x800081000ULL,
|
1402 |
.esp_base = 0x800080000ULL,
|
1403 |
.ledma_base = 0x800040000ULL,
|
1404 |
.le_base = 0x800060000ULL,
|
1405 |
.sbi_base = 0xf02800000ULL,
|
1406 |
.nvram_machine_id = 0x80,
|
1407 |
.machine_id = ss2000_id, |
1408 |
.iounit_version = 0x03000000,
|
1409 |
.max_mem = 0xf00000000ULL,
|
1410 |
.default_cpu_model = "TI SuperSparc II",
|
1411 |
}, |
1412 |
}; |
1413 |
|
1414 |
static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1415 |
{ |
1416 |
DeviceState *dev; |
1417 |
SysBusDevice *s; |
1418 |
unsigned int i; |
1419 |
|
1420 |
dev = qdev_create(NULL, "sbi"); |
1421 |
qdev_init_nofail(dev); |
1422 |
|
1423 |
s = sysbus_from_qdev(dev); |
1424 |
|
1425 |
for (i = 0; i < MAX_CPUS; i++) { |
1426 |
sysbus_connect_irq(s, i, *parent_irq[i]); |
1427 |
} |
1428 |
|
1429 |
sysbus_mmio_map(s, 0, addr);
|
1430 |
|
1431 |
return dev;
|
1432 |
} |
1433 |
|
1434 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1435 |
const char *boot_device, |
1436 |
const char *kernel_filename, |
1437 |
const char *kernel_cmdline, |
1438 |
const char *initrd_filename, const char *cpu_model) |
1439 |
{ |
1440 |
unsigned int i; |
1441 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1442 |
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1443 |
espdma_irq, ledma_irq; |
1444 |
qemu_irq esp_reset; |
1445 |
unsigned long kernel_size; |
1446 |
void *fw_cfg;
|
1447 |
DeviceState *dev; |
1448 |
|
1449 |
/* init CPUs */
|
1450 |
if (!cpu_model)
|
1451 |
cpu_model = hwdef->default_cpu_model; |
1452 |
|
1453 |
for(i = 0; i < smp_cpus; i++) { |
1454 |
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1455 |
} |
1456 |
|
1457 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
1458 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1459 |
|
1460 |
/* set up devices */
|
1461 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1462 |
|
1463 |
prom_init(hwdef->slavio_base, bios_name); |
1464 |
|
1465 |
dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1466 |
|
1467 |
for (i = 0; i < 32; i++) { |
1468 |
sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1469 |
} |
1470 |
for (i = 0; i < MAX_CPUS; i++) { |
1471 |
sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1472 |
} |
1473 |
|
1474 |
for (i = 0; i < MAX_IOUNITS; i++) |
1475 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1476 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1477 |
hwdef->iounit_version, |
1478 |
sbi_irq[0]);
|
1479 |
|
1480 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1481 |
iounits[0], &espdma_irq);
|
1482 |
|
1483 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1484 |
iounits[0], &ledma_irq);
|
1485 |
|
1486 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1487 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1488 |
exit (1);
|
1489 |
} |
1490 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1491 |
graphic_depth); |
1492 |
|
1493 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1494 |
|
1495 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1496 |
|
1497 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1498 |
|
1499 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1500 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1501 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1502 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1503 |
escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1504 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1505 |
|
1506 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1507 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1508 |
exit(1);
|
1509 |
} |
1510 |
|
1511 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1512 |
esp_init(hwdef->esp_base, 2,
|
1513 |
espdma_memory_read, espdma_memory_write, |
1514 |
espdma, espdma_irq, &esp_reset); |
1515 |
|
1516 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1517 |
RAM_size); |
1518 |
|
1519 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1520 |
boot_device, RAM_size, kernel_size, graphic_width, |
1521 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1522 |
"Sun4d");
|
1523 |
|
1524 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1525 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1526 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1527 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1528 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1529 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1530 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1531 |
if (kernel_cmdline) {
|
1532 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1533 |
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1534 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1535 |
(uint8_t*)strdup(kernel_cmdline), |
1536 |
strlen(kernel_cmdline) + 1);
|
1537 |
} else {
|
1538 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1539 |
} |
1540 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1541 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1542 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1543 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1544 |
} |
1545 |
|
1546 |
/* SPARCserver 1000 hardware initialisation */
|
1547 |
static void ss1000_init(ram_addr_t RAM_size, |
1548 |
const char *boot_device, |
1549 |
const char *kernel_filename, const char *kernel_cmdline, |
1550 |
const char *initrd_filename, const char *cpu_model) |
1551 |
{ |
1552 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1553 |
kernel_cmdline, initrd_filename, cpu_model); |
1554 |
} |
1555 |
|
1556 |
/* SPARCcenter 2000 hardware initialisation */
|
1557 |
static void ss2000_init(ram_addr_t RAM_size, |
1558 |
const char *boot_device, |
1559 |
const char *kernel_filename, const char *kernel_cmdline, |
1560 |
const char *initrd_filename, const char *cpu_model) |
1561 |
{ |
1562 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1563 |
kernel_cmdline, initrd_filename, cpu_model); |
1564 |
} |
1565 |
|
1566 |
static QEMUMachine ss1000_machine = {
|
1567 |
.name = "SS-1000",
|
1568 |
.desc = "Sun4d platform, SPARCserver 1000",
|
1569 |
.init = ss1000_init, |
1570 |
.use_scsi = 1,
|
1571 |
.max_cpus = 8,
|
1572 |
}; |
1573 |
|
1574 |
static QEMUMachine ss2000_machine = {
|
1575 |
.name = "SS-2000",
|
1576 |
.desc = "Sun4d platform, SPARCcenter 2000",
|
1577 |
.init = ss2000_init, |
1578 |
.use_scsi = 1,
|
1579 |
.max_cpus = 20,
|
1580 |
}; |
1581 |
|
1582 |
static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1583 |
/* SS-2 */
|
1584 |
{ |
1585 |
.iommu_base = 0xf8000000,
|
1586 |
.tcx_base = 0xfe000000,
|
1587 |
.slavio_base = 0xf6000000,
|
1588 |
.intctl_base = 0xf5000000,
|
1589 |
.counter_base = 0xf3000000,
|
1590 |
.ms_kb_base = 0xf0000000,
|
1591 |
.serial_base = 0xf1000000,
|
1592 |
.nvram_base = 0xf2000000,
|
1593 |
.fd_base = 0xf7200000,
|
1594 |
.dma_base = 0xf8400000,
|
1595 |
.esp_base = 0xf8800000,
|
1596 |
.le_base = 0xf8c00000,
|
1597 |
.aux1_base = 0xf7400003,
|
1598 |
.nvram_machine_id = 0x55,
|
1599 |
.machine_id = ss2_id, |
1600 |
.max_mem = 0x10000000,
|
1601 |
.default_cpu_model = "Cypress CY7C601",
|
1602 |
}, |
1603 |
}; |
1604 |
|
1605 |
static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1606 |
qemu_irq *parent_irq) |
1607 |
{ |
1608 |
DeviceState *dev; |
1609 |
SysBusDevice *s; |
1610 |
unsigned int i; |
1611 |
|
1612 |
dev = qdev_create(NULL, "sun4c_intctl"); |
1613 |
qdev_init_nofail(dev); |
1614 |
|
1615 |
s = sysbus_from_qdev(dev); |
1616 |
|
1617 |
for (i = 0; i < MAX_PILS; i++) { |
1618 |
sysbus_connect_irq(s, i, parent_irq[i]); |
1619 |
} |
1620 |
sysbus_mmio_map(s, 0, addr);
|
1621 |
|
1622 |
return dev;
|
1623 |
} |
1624 |
|
1625 |
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1626 |
const char *boot_device, |
1627 |
const char *kernel_filename, |
1628 |
const char *kernel_cmdline, |
1629 |
const char *initrd_filename, const char *cpu_model) |
1630 |
{ |
1631 |
void *iommu, *espdma, *ledma, *nvram;
|
1632 |
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1633 |
qemu_irq esp_reset; |
1634 |
qemu_irq fdc_tc; |
1635 |
unsigned long kernel_size; |
1636 |
DriveInfo *fd[MAX_FD]; |
1637 |
void *fw_cfg;
|
1638 |
DeviceState *dev; |
1639 |
unsigned int i; |
1640 |
|
1641 |
/* init CPU */
|
1642 |
if (!cpu_model)
|
1643 |
cpu_model = hwdef->default_cpu_model; |
1644 |
|
1645 |
cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1646 |
|
1647 |
/* set up devices */
|
1648 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1649 |
|
1650 |
prom_init(hwdef->slavio_base, bios_name); |
1651 |
|
1652 |
dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1653 |
|
1654 |
for (i = 0; i < 8; i++) { |
1655 |
slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1656 |
} |
1657 |
|
1658 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1659 |
slavio_irq[1]);
|
1660 |
|
1661 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1662 |
iommu, &espdma_irq); |
1663 |
|
1664 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1665 |
slavio_irq[3], iommu, &ledma_irq);
|
1666 |
|
1667 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1668 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1669 |
exit (1);
|
1670 |
} |
1671 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1672 |
graphic_depth); |
1673 |
|
1674 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1675 |
|
1676 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1677 |
|
1678 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1679 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1680 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1681 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1682 |
escc_init(hwdef->serial_base, slavio_irq[1],
|
1683 |
slavio_irq[1], serial_hds[0], serial_hds[1], |
1684 |
ESCC_CLOCK, 1);
|
1685 |
|
1686 |
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1687 |
|
1688 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1689 |
/* there is zero or one floppy drive */
|
1690 |
memset(fd, 0, sizeof(fd)); |
1691 |
fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1692 |
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1693 |
&fdc_tc); |
1694 |
} |
1695 |
|
1696 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1697 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1698 |
exit(1);
|
1699 |
} |
1700 |
|
1701 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1702 |
esp_init(hwdef->esp_base, 2,
|
1703 |
espdma_memory_read, espdma_memory_write, |
1704 |
espdma, espdma_irq, &esp_reset); |
1705 |
|
1706 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1707 |
RAM_size); |
1708 |
|
1709 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1710 |
boot_device, RAM_size, kernel_size, graphic_width, |
1711 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1712 |
"Sun4c");
|
1713 |
|
1714 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1715 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1716 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1717 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1718 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1719 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1720 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1721 |
if (kernel_cmdline) {
|
1722 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1723 |
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1724 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1725 |
(uint8_t*)strdup(kernel_cmdline), |
1726 |
strlen(kernel_cmdline) + 1);
|
1727 |
} else {
|
1728 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1729 |
} |
1730 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1731 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1732 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1733 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1734 |
} |
1735 |
|
1736 |
/* SPARCstation 2 hardware initialisation */
|
1737 |
static void ss2_init(ram_addr_t RAM_size, |
1738 |
const char *boot_device, |
1739 |
const char *kernel_filename, const char *kernel_cmdline, |
1740 |
const char *initrd_filename, const char *cpu_model) |
1741 |
{ |
1742 |
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1743 |
kernel_cmdline, initrd_filename, cpu_model); |
1744 |
} |
1745 |
|
1746 |
static QEMUMachine ss2_machine = {
|
1747 |
.name = "SS-2",
|
1748 |
.desc = "Sun4c platform, SPARCstation 2",
|
1749 |
.init = ss2_init, |
1750 |
.use_scsi = 1,
|
1751 |
}; |
1752 |
|
1753 |
static void ss2_machine_init(void) |
1754 |
{ |
1755 |
qemu_register_machine(&ss5_machine); |
1756 |
qemu_register_machine(&ss10_machine); |
1757 |
qemu_register_machine(&ss600mp_machine); |
1758 |
qemu_register_machine(&ss20_machine); |
1759 |
qemu_register_machine(&voyager_machine); |
1760 |
qemu_register_machine(&ss_lx_machine); |
1761 |
qemu_register_machine(&ss4_machine); |
1762 |
qemu_register_machine(&scls_machine); |
1763 |
qemu_register_machine(&sbook_machine); |
1764 |
qemu_register_machine(&ss1000_machine); |
1765 |
qemu_register_machine(&ss2000_machine); |
1766 |
qemu_register_machine(&ss2_machine); |
1767 |
} |
1768 |
|
1769 |
machine_init(ss2_machine_init); |