Revision 08fa4bab target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 1841 | 1841 |
|
| 1842 | 1842 |
val = T0 & mask; |
| 1843 | 1843 |
old = env->CP0_Status; |
| 1844 |
if (!(val & (1 << CP0St_EXL)) && |
|
| 1845 |
!(val & (1 << CP0St_ERL)) && |
|
| 1846 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 1847 |
(val & (1 << CP0St_UM))) |
|
| 1848 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 1849 |
#ifdef TARGET_MIPS64 |
|
| 1850 |
if ((env->hflags & MIPS_HFLAG_UM) && |
|
| 1851 |
!(val & (1 << CP0St_PX)) && |
|
| 1852 |
!(val & (1 << CP0St_UX))) |
|
| 1853 |
env->hflags &= ~MIPS_HFLAG_64; |
|
| 1854 |
#endif |
|
| 1855 |
if ((val & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM)) |
|
| 1856 |
env->hflags |= MIPS_HFLAG_CP0; |
|
| 1857 |
else |
|
| 1858 |
env->hflags &= ~MIPS_HFLAG_CP0; |
|
| 1859 |
if (val & (1 << CP0St_CU1)) |
|
| 1860 |
env->hflags |= MIPS_HFLAG_FPU; |
|
| 1861 |
else |
|
| 1862 |
env->hflags &= ~MIPS_HFLAG_FPU; |
|
| 1863 |
if (val & (1 << CP0St_FR)) |
|
| 1864 |
env->hflags |= MIPS_HFLAG_F64; |
|
| 1865 |
else |
|
| 1866 |
env->hflags &= ~MIPS_HFLAG_F64; |
|
| 1867 | 1844 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
| 1845 |
CALL_FROM_TB1(compute_hflags, env); |
|
| 1868 | 1846 |
if (loglevel & CPU_LOG_EXEC) |
| 1869 | 1847 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
| 1870 | 1848 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
| ... | ... | |
| 3009 | 2987 |
env->PC[env->current_tc] = env->CP0_EPC; |
| 3010 | 2988 |
env->CP0_Status &= ~(1 << CP0St_EXL); |
| 3011 | 2989 |
} |
| 3012 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
|
| 3013 |
!(env->CP0_Status & (1 << CP0St_ERL)) && |
|
| 3014 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 3015 |
(env->CP0_Status & (1 << CP0St_UM))) |
|
| 3016 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 3017 |
#ifdef TARGET_MIPS64 |
|
| 3018 |
if ((env->hflags & MIPS_HFLAG_UM) && |
|
| 3019 |
!(env->CP0_Status & (1 << CP0St_PX)) && |
|
| 3020 |
!(env->CP0_Status & (1 << CP0St_UX))) |
|
| 3021 |
env->hflags &= ~MIPS_HFLAG_64; |
|
| 3022 |
#endif |
|
| 3023 |
if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM)) |
|
| 3024 |
env->hflags |= MIPS_HFLAG_CP0; |
|
| 3025 |
else |
|
| 3026 |
env->hflags &= ~MIPS_HFLAG_CP0; |
|
| 2990 |
CALL_FROM_TB1(compute_hflags, env); |
|
| 3027 | 2991 |
if (loglevel & CPU_LOG_EXEC) |
| 3028 | 2992 |
CALL_FROM_TB0(debug_post_eret); |
| 3029 | 2993 |
env->CP0_LLAddr = 1; |
| ... | ... | |
| 3035 | 2999 |
if (loglevel & CPU_LOG_EXEC) |
| 3036 | 3000 |
CALL_FROM_TB0(debug_pre_eret); |
| 3037 | 3001 |
env->PC[env->current_tc] = env->CP0_DEPC; |
| 3038 |
env->hflags |= MIPS_HFLAG_DM; |
|
| 3039 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
|
| 3040 |
!(env->CP0_Status & (1 << CP0St_ERL)) && |
|
| 3041 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 3042 |
(env->CP0_Status & (1 << CP0St_UM))) |
|
| 3043 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 3044 |
#ifdef TARGET_MIPS64 |
|
| 3045 |
if ((env->hflags & MIPS_HFLAG_UM) && |
|
| 3046 |
!(env->CP0_Status & (1 << CP0St_PX)) && |
|
| 3047 |
!(env->CP0_Status & (1 << CP0St_UX))) |
|
| 3048 |
env->hflags &= ~MIPS_HFLAG_64; |
|
| 3049 |
#endif |
|
| 3050 |
if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM)) |
|
| 3051 |
env->hflags |= MIPS_HFLAG_CP0; |
|
| 3052 |
else |
|
| 3053 |
env->hflags &= ~MIPS_HFLAG_CP0; |
|
| 3002 |
env->hflags &= MIPS_HFLAG_DM; |
|
| 3003 |
CALL_FROM_TB1(compute_hflags, env); |
|
| 3054 | 3004 |
if (loglevel & CPU_LOG_EXEC) |
| 3055 | 3005 |
CALL_FROM_TB0(debug_post_eret); |
| 3056 | 3006 |
env->CP0_LLAddr = 1; |
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