root / hw / rtl8139.c @ 0986ac3b
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1 | a41b2ff2 | pbrook | /**
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2 | a41b2ff2 | pbrook | * QEMU RTL8139 emulation
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3 | a41b2ff2 | pbrook | *
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4 | a41b2ff2 | pbrook | * Copyright (c) 2006 Igor Kovalenko
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5 | a41b2ff2 | pbrook | *
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6 | a41b2ff2 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a41b2ff2 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | a41b2ff2 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | a41b2ff2 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a41b2ff2 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | a41b2ff2 | pbrook | * furnished to do so, subject to the following conditions:
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12 | a41b2ff2 | pbrook | *
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13 | a41b2ff2 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | a41b2ff2 | pbrook | * all copies or substantial portions of the Software.
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15 | a41b2ff2 | pbrook | *
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16 | a41b2ff2 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a41b2ff2 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a41b2ff2 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a41b2ff2 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a41b2ff2 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a41b2ff2 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a41b2ff2 | pbrook | * THE SOFTWARE.
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23 | a41b2ff2 | pbrook |
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24 | a41b2ff2 | pbrook | * Modifications:
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25 | a41b2ff2 | pbrook | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
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26 | a41b2ff2 | pbrook | *
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27 | a41b2ff2 | pbrook | */
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28 | a41b2ff2 | pbrook | |
29 | a41b2ff2 | pbrook | #include "vl.h" |
30 | a41b2ff2 | pbrook | |
31 | a41b2ff2 | pbrook | |
32 | a41b2ff2 | pbrook | /* debug RTL8139 card */
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33 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139 1
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34 | a41b2ff2 | pbrook | |
35 | a41b2ff2 | pbrook | /* debug RTL8139 card C+ mode only */
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36 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139CP 1
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37 | a41b2ff2 | pbrook | |
38 | a41b2ff2 | pbrook | /* RTL8139 provides frame CRC with received packet, this feature seems to be
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39 | a41b2ff2 | pbrook | ignored by most drivers, disabled by default */
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40 | a41b2ff2 | pbrook | //#define RTL8139_CALCULATE_RXCRC 1
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41 | a41b2ff2 | pbrook | |
42 | a41b2ff2 | pbrook | |
43 | a41b2ff2 | pbrook | #if defined(RTL8139_CALCULATE_RXCRC)
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44 | a41b2ff2 | pbrook | /* For crc32 */
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45 | a41b2ff2 | pbrook | #include <zlib.h> |
46 | a41b2ff2 | pbrook | #endif
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47 | a41b2ff2 | pbrook | |
48 | a41b2ff2 | pbrook | #define SET_MASKED(input, mask, curr) \
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49 | a41b2ff2 | pbrook | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
50 | a41b2ff2 | pbrook | |
51 | a41b2ff2 | pbrook | /* arg % size for size which is a power of 2 */
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52 | a41b2ff2 | pbrook | #define MOD2(input, size) \
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53 | a41b2ff2 | pbrook | ( ( input ) & ( size - 1 ) )
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54 | a41b2ff2 | pbrook | |
55 | a41b2ff2 | pbrook | /* Symbolic offsets to registers. */
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56 | a41b2ff2 | pbrook | enum RTL8139_registers {
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57 | a41b2ff2 | pbrook | MAC0 = 0, /* Ethernet hardware address. */ |
58 | a41b2ff2 | pbrook | MAR0 = 8, /* Multicast filter. */ |
59 | a41b2ff2 | pbrook | TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ |
60 | a41b2ff2 | pbrook | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
61 | a41b2ff2 | pbrook | RxBuf = 0x30,
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62 | a41b2ff2 | pbrook | ChipCmd = 0x37,
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63 | a41b2ff2 | pbrook | RxBufPtr = 0x38,
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64 | a41b2ff2 | pbrook | RxBufAddr = 0x3A,
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65 | a41b2ff2 | pbrook | IntrMask = 0x3C,
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66 | a41b2ff2 | pbrook | IntrStatus = 0x3E,
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67 | a41b2ff2 | pbrook | TxConfig = 0x40,
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68 | a41b2ff2 | pbrook | RxConfig = 0x44,
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69 | a41b2ff2 | pbrook | Timer = 0x48, /* A general-purpose counter. */ |
70 | a41b2ff2 | pbrook | RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
71 | a41b2ff2 | pbrook | Cfg9346 = 0x50,
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72 | a41b2ff2 | pbrook | Config0 = 0x51,
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73 | a41b2ff2 | pbrook | Config1 = 0x52,
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74 | a41b2ff2 | pbrook | FlashReg = 0x54,
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75 | a41b2ff2 | pbrook | MediaStatus = 0x58,
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76 | a41b2ff2 | pbrook | Config3 = 0x59,
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77 | a41b2ff2 | pbrook | Config4 = 0x5A, /* absent on RTL-8139A */ |
78 | a41b2ff2 | pbrook | HltClk = 0x5B,
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79 | a41b2ff2 | pbrook | MultiIntr = 0x5C,
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80 | a41b2ff2 | pbrook | PCIRevisionID = 0x5E,
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81 | a41b2ff2 | pbrook | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
82 | a41b2ff2 | pbrook | BasicModeCtrl = 0x62,
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83 | a41b2ff2 | pbrook | BasicModeStatus = 0x64,
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84 | a41b2ff2 | pbrook | NWayAdvert = 0x66,
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85 | a41b2ff2 | pbrook | NWayLPAR = 0x68,
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86 | a41b2ff2 | pbrook | NWayExpansion = 0x6A,
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87 | a41b2ff2 | pbrook | /* Undocumented registers, but required for proper operation. */
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88 | a41b2ff2 | pbrook | FIFOTMS = 0x70, /* FIFO Control and test. */ |
89 | a41b2ff2 | pbrook | CSCR = 0x74, /* Chip Status and Configuration Register. */ |
90 | a41b2ff2 | pbrook | PARA78 = 0x78,
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91 | a41b2ff2 | pbrook | PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
92 | a41b2ff2 | pbrook | Config5 = 0xD8, /* absent on RTL-8139A */ |
93 | a41b2ff2 | pbrook | /* C+ mode */
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94 | a41b2ff2 | pbrook | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
95 | a41b2ff2 | pbrook | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
96 | a41b2ff2 | pbrook | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
97 | a41b2ff2 | pbrook | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
98 | a41b2ff2 | pbrook | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
99 | a41b2ff2 | pbrook | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
100 | a41b2ff2 | pbrook | TxThresh = 0xEC, /* Early Tx threshold */ |
101 | a41b2ff2 | pbrook | }; |
102 | a41b2ff2 | pbrook | |
103 | a41b2ff2 | pbrook | enum ClearBitMasks {
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104 | a41b2ff2 | pbrook | MultiIntrClear = 0xF000,
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105 | a41b2ff2 | pbrook | ChipCmdClear = 0xE2,
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106 | a41b2ff2 | pbrook | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
107 | a41b2ff2 | pbrook | }; |
108 | a41b2ff2 | pbrook | |
109 | a41b2ff2 | pbrook | enum ChipCmdBits {
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110 | a41b2ff2 | pbrook | CmdReset = 0x10,
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111 | a41b2ff2 | pbrook | CmdRxEnb = 0x08,
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112 | a41b2ff2 | pbrook | CmdTxEnb = 0x04,
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113 | a41b2ff2 | pbrook | RxBufEmpty = 0x01,
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114 | a41b2ff2 | pbrook | }; |
115 | a41b2ff2 | pbrook | |
116 | a41b2ff2 | pbrook | /* C+ mode */
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117 | a41b2ff2 | pbrook | enum CplusCmdBits {
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118 | a41b2ff2 | pbrook | CPlusRxEnb = 0x0002,
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119 | a41b2ff2 | pbrook | CPlusTxEnb = 0x0001,
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120 | a41b2ff2 | pbrook | }; |
121 | a41b2ff2 | pbrook | |
122 | a41b2ff2 | pbrook | /* Interrupt register bits, using my own meaningful names. */
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123 | a41b2ff2 | pbrook | enum IntrStatusBits {
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124 | a41b2ff2 | pbrook | PCIErr = 0x8000,
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125 | a41b2ff2 | pbrook | PCSTimeout = 0x4000,
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126 | a41b2ff2 | pbrook | RxFIFOOver = 0x40,
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127 | a41b2ff2 | pbrook | RxUnderrun = 0x20,
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128 | a41b2ff2 | pbrook | RxOverflow = 0x10,
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129 | a41b2ff2 | pbrook | TxErr = 0x08,
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130 | a41b2ff2 | pbrook | TxOK = 0x04,
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131 | a41b2ff2 | pbrook | RxErr = 0x02,
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132 | a41b2ff2 | pbrook | RxOK = 0x01,
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133 | a41b2ff2 | pbrook | |
134 | a41b2ff2 | pbrook | RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
135 | a41b2ff2 | pbrook | }; |
136 | a41b2ff2 | pbrook | |
137 | a41b2ff2 | pbrook | enum TxStatusBits {
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138 | a41b2ff2 | pbrook | TxHostOwns = 0x2000,
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139 | a41b2ff2 | pbrook | TxUnderrun = 0x4000,
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140 | a41b2ff2 | pbrook | TxStatOK = 0x8000,
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141 | a41b2ff2 | pbrook | TxOutOfWindow = 0x20000000,
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142 | a41b2ff2 | pbrook | TxAborted = 0x40000000,
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143 | a41b2ff2 | pbrook | TxCarrierLost = 0x80000000,
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144 | a41b2ff2 | pbrook | }; |
145 | a41b2ff2 | pbrook | enum RxStatusBits {
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146 | a41b2ff2 | pbrook | RxMulticast = 0x8000,
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147 | a41b2ff2 | pbrook | RxPhysical = 0x4000,
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148 | a41b2ff2 | pbrook | RxBroadcast = 0x2000,
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149 | a41b2ff2 | pbrook | RxBadSymbol = 0x0020,
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150 | a41b2ff2 | pbrook | RxRunt = 0x0010,
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151 | a41b2ff2 | pbrook | RxTooLong = 0x0008,
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152 | a41b2ff2 | pbrook | RxCRCErr = 0x0004,
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153 | a41b2ff2 | pbrook | RxBadAlign = 0x0002,
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154 | a41b2ff2 | pbrook | RxStatusOK = 0x0001,
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155 | a41b2ff2 | pbrook | }; |
156 | a41b2ff2 | pbrook | |
157 | a41b2ff2 | pbrook | /* Bits in RxConfig. */
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158 | a41b2ff2 | pbrook | enum rx_mode_bits {
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159 | a41b2ff2 | pbrook | AcceptErr = 0x20,
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160 | a41b2ff2 | pbrook | AcceptRunt = 0x10,
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161 | a41b2ff2 | pbrook | AcceptBroadcast = 0x08,
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162 | a41b2ff2 | pbrook | AcceptMulticast = 0x04,
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163 | a41b2ff2 | pbrook | AcceptMyPhys = 0x02,
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164 | a41b2ff2 | pbrook | AcceptAllPhys = 0x01,
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165 | a41b2ff2 | pbrook | }; |
166 | a41b2ff2 | pbrook | |
167 | a41b2ff2 | pbrook | /* Bits in TxConfig. */
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168 | a41b2ff2 | pbrook | enum tx_config_bits {
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169 | a41b2ff2 | pbrook | |
170 | a41b2ff2 | pbrook | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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171 | a41b2ff2 | pbrook | TxIFGShift = 24,
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172 | a41b2ff2 | pbrook | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
173 | a41b2ff2 | pbrook | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
174 | a41b2ff2 | pbrook | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
175 | a41b2ff2 | pbrook | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
176 | a41b2ff2 | pbrook | |
177 | a41b2ff2 | pbrook | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
178 | a41b2ff2 | pbrook | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
179 | a41b2ff2 | pbrook | TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
180 | a41b2ff2 | pbrook | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
181 | a41b2ff2 | pbrook | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
182 | a41b2ff2 | pbrook | |
183 | a41b2ff2 | pbrook | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
184 | a41b2ff2 | pbrook | }; |
185 | a41b2ff2 | pbrook | |
186 | a41b2ff2 | pbrook | |
187 | a41b2ff2 | pbrook | /* Transmit Status of All Descriptors (TSAD) Register */
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188 | a41b2ff2 | pbrook | enum TSAD_bits {
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189 | a41b2ff2 | pbrook | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
190 | a41b2ff2 | pbrook | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
191 | a41b2ff2 | pbrook | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
192 | a41b2ff2 | pbrook | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
193 | a41b2ff2 | pbrook | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
194 | a41b2ff2 | pbrook | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
195 | a41b2ff2 | pbrook | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
196 | a41b2ff2 | pbrook | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
197 | a41b2ff2 | pbrook | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
198 | a41b2ff2 | pbrook | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
199 | a41b2ff2 | pbrook | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
200 | a41b2ff2 | pbrook | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
201 | a41b2ff2 | pbrook | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
202 | a41b2ff2 | pbrook | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
203 | a41b2ff2 | pbrook | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
204 | a41b2ff2 | pbrook | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
205 | a41b2ff2 | pbrook | }; |
206 | a41b2ff2 | pbrook | |
207 | a41b2ff2 | pbrook | |
208 | a41b2ff2 | pbrook | /* Bits in Config1 */
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209 | a41b2ff2 | pbrook | enum Config1Bits {
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210 | a41b2ff2 | pbrook | Cfg1_PM_Enable = 0x01,
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211 | a41b2ff2 | pbrook | Cfg1_VPD_Enable = 0x02,
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212 | a41b2ff2 | pbrook | Cfg1_PIO = 0x04,
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213 | a41b2ff2 | pbrook | Cfg1_MMIO = 0x08,
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214 | a41b2ff2 | pbrook | LWAKE = 0x10, /* not on 8139, 8139A */ |
215 | a41b2ff2 | pbrook | Cfg1_Driver_Load = 0x20,
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216 | a41b2ff2 | pbrook | Cfg1_LED0 = 0x40,
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217 | a41b2ff2 | pbrook | Cfg1_LED1 = 0x80,
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218 | a41b2ff2 | pbrook | SLEEP = (1 << 1), /* only on 8139, 8139A */ |
219 | a41b2ff2 | pbrook | PWRDN = (1 << 0), /* only on 8139, 8139A */ |
220 | a41b2ff2 | pbrook | }; |
221 | a41b2ff2 | pbrook | |
222 | a41b2ff2 | pbrook | /* Bits in Config3 */
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223 | a41b2ff2 | pbrook | enum Config3Bits {
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224 | a41b2ff2 | pbrook | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
225 | a41b2ff2 | pbrook | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
226 | a41b2ff2 | pbrook | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
227 | a41b2ff2 | pbrook | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
228 | a41b2ff2 | pbrook | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
229 | a41b2ff2 | pbrook | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
230 | a41b2ff2 | pbrook | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
231 | a41b2ff2 | pbrook | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
232 | a41b2ff2 | pbrook | }; |
233 | a41b2ff2 | pbrook | |
234 | a41b2ff2 | pbrook | /* Bits in Config4 */
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235 | a41b2ff2 | pbrook | enum Config4Bits {
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236 | a41b2ff2 | pbrook | LWPTN = (1 << 2), /* not on 8139, 8139A */ |
237 | a41b2ff2 | pbrook | }; |
238 | a41b2ff2 | pbrook | |
239 | a41b2ff2 | pbrook | /* Bits in Config5 */
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240 | a41b2ff2 | pbrook | enum Config5Bits {
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241 | a41b2ff2 | pbrook | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
242 | a41b2ff2 | pbrook | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
243 | a41b2ff2 | pbrook | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
244 | a41b2ff2 | pbrook | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
245 | a41b2ff2 | pbrook | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
246 | a41b2ff2 | pbrook | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
247 | a41b2ff2 | pbrook | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
248 | a41b2ff2 | pbrook | }; |
249 | a41b2ff2 | pbrook | |
250 | a41b2ff2 | pbrook | enum RxConfigBits {
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251 | a41b2ff2 | pbrook | /* rx fifo threshold */
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252 | a41b2ff2 | pbrook | RxCfgFIFOShift = 13,
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253 | a41b2ff2 | pbrook | RxCfgFIFONone = (7 << RxCfgFIFOShift),
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254 | a41b2ff2 | pbrook | |
255 | a41b2ff2 | pbrook | /* Max DMA burst */
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256 | a41b2ff2 | pbrook | RxCfgDMAShift = 8,
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257 | a41b2ff2 | pbrook | RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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258 | a41b2ff2 | pbrook | |
259 | a41b2ff2 | pbrook | /* rx ring buffer length */
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260 | a41b2ff2 | pbrook | RxCfgRcv8K = 0,
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261 | a41b2ff2 | pbrook | RxCfgRcv16K = (1 << 11), |
262 | a41b2ff2 | pbrook | RxCfgRcv32K = (1 << 12), |
263 | a41b2ff2 | pbrook | RxCfgRcv64K = (1 << 11) | (1 << 12), |
264 | a41b2ff2 | pbrook | |
265 | a41b2ff2 | pbrook | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
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266 | a41b2ff2 | pbrook | RxNoWrap = (1 << 7), |
267 | a41b2ff2 | pbrook | }; |
268 | a41b2ff2 | pbrook | |
269 | a41b2ff2 | pbrook | /* Twister tuning parameters from RealTek.
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270 | a41b2ff2 | pbrook | Completely undocumented, but required to tune bad links on some boards. */
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271 | a41b2ff2 | pbrook | /*
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272 | a41b2ff2 | pbrook | enum CSCRBits {
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273 | a41b2ff2 | pbrook | CSCR_LinkOKBit = 0x0400,
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274 | a41b2ff2 | pbrook | CSCR_LinkChangeBit = 0x0800,
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275 | a41b2ff2 | pbrook | CSCR_LinkStatusBits = 0x0f000,
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276 | a41b2ff2 | pbrook | CSCR_LinkDownOffCmd = 0x003c0,
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277 | a41b2ff2 | pbrook | CSCR_LinkDownCmd = 0x0f3c0,
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278 | a41b2ff2 | pbrook | */
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279 | a41b2ff2 | pbrook | enum CSCRBits {
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280 | a41b2ff2 | pbrook | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
281 | a41b2ff2 | pbrook | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
282 | a41b2ff2 | pbrook | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
283 | a41b2ff2 | pbrook | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
284 | a41b2ff2 | pbrook | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
285 | a41b2ff2 | pbrook | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
286 | a41b2ff2 | pbrook | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
287 | a41b2ff2 | pbrook | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
288 | a41b2ff2 | pbrook | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
289 | a41b2ff2 | pbrook | }; |
290 | a41b2ff2 | pbrook | |
291 | a41b2ff2 | pbrook | enum Cfg9346Bits {
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292 | a41b2ff2 | pbrook | Cfg9346_Lock = 0x00,
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293 | a41b2ff2 | pbrook | Cfg9346_Unlock = 0xC0,
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294 | a41b2ff2 | pbrook | }; |
295 | a41b2ff2 | pbrook | |
296 | a41b2ff2 | pbrook | typedef enum { |
297 | a41b2ff2 | pbrook | CH_8139 = 0,
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298 | a41b2ff2 | pbrook | CH_8139_K, |
299 | a41b2ff2 | pbrook | CH_8139A, |
300 | a41b2ff2 | pbrook | CH_8139A_G, |
301 | a41b2ff2 | pbrook | CH_8139B, |
302 | a41b2ff2 | pbrook | CH_8130, |
303 | a41b2ff2 | pbrook | CH_8139C, |
304 | a41b2ff2 | pbrook | CH_8100, |
305 | a41b2ff2 | pbrook | CH_8100B_8139D, |
306 | a41b2ff2 | pbrook | CH_8101, |
307 | a41b2ff2 | pbrook | } chip_t; |
308 | a41b2ff2 | pbrook | |
309 | a41b2ff2 | pbrook | enum chip_flags {
|
310 | a41b2ff2 | pbrook | HasHltClk = (1 << 0), |
311 | a41b2ff2 | pbrook | HasLWake = (1 << 1), |
312 | a41b2ff2 | pbrook | }; |
313 | a41b2ff2 | pbrook | |
314 | a41b2ff2 | pbrook | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
|
315 | a41b2ff2 | pbrook | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
316 | a41b2ff2 | pbrook | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
317 | a41b2ff2 | pbrook | |
318 | a41b2ff2 | pbrook | /* Size is 64 * 16bit words */
|
319 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_BITS 6 |
320 | a41b2ff2 | pbrook | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
321 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
322 | a41b2ff2 | pbrook | |
323 | a41b2ff2 | pbrook | enum Chip9346Operation
|
324 | a41b2ff2 | pbrook | { |
325 | a41b2ff2 | pbrook | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
326 | a41b2ff2 | pbrook | Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
327 | a41b2ff2 | pbrook | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
328 | a41b2ff2 | pbrook | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
329 | a41b2ff2 | pbrook | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
330 | a41b2ff2 | pbrook | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
331 | a41b2ff2 | pbrook | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
332 | a41b2ff2 | pbrook | }; |
333 | a41b2ff2 | pbrook | |
334 | a41b2ff2 | pbrook | enum Chip9346Mode
|
335 | a41b2ff2 | pbrook | { |
336 | a41b2ff2 | pbrook | Chip9346_none = 0,
|
337 | a41b2ff2 | pbrook | Chip9346_enter_command_mode, |
338 | a41b2ff2 | pbrook | Chip9346_read_command, |
339 | a41b2ff2 | pbrook | Chip9346_data_read, /* from output register */
|
340 | a41b2ff2 | pbrook | Chip9346_data_write, /* to input register, then to contents at specified address */
|
341 | a41b2ff2 | pbrook | Chip9346_data_write_all, /* to input register, then filling contents */
|
342 | a41b2ff2 | pbrook | }; |
343 | a41b2ff2 | pbrook | |
344 | a41b2ff2 | pbrook | typedef struct EEprom9346 |
345 | a41b2ff2 | pbrook | { |
346 | a41b2ff2 | pbrook | uint16_t contents[EEPROM_9346_SIZE]; |
347 | a41b2ff2 | pbrook | int mode;
|
348 | a41b2ff2 | pbrook | uint32_t tick; |
349 | a41b2ff2 | pbrook | uint8_t address; |
350 | a41b2ff2 | pbrook | uint16_t input; |
351 | a41b2ff2 | pbrook | uint16_t output; |
352 | a41b2ff2 | pbrook | |
353 | a41b2ff2 | pbrook | uint8_t eecs; |
354 | a41b2ff2 | pbrook | uint8_t eesk; |
355 | a41b2ff2 | pbrook | uint8_t eedi; |
356 | a41b2ff2 | pbrook | uint8_t eedo; |
357 | a41b2ff2 | pbrook | } EEprom9346; |
358 | a41b2ff2 | pbrook | |
359 | a41b2ff2 | pbrook | typedef struct RTL8139State { |
360 | a41b2ff2 | pbrook | uint8_t phys[8]; /* mac address */ |
361 | a41b2ff2 | pbrook | uint8_t mult[8]; /* multicast mask array */ |
362 | a41b2ff2 | pbrook | |
363 | a41b2ff2 | pbrook | uint32_t TxStatus[4]; /* TxStatus0 */ |
364 | a41b2ff2 | pbrook | uint32_t TxAddr[4]; /* TxAddr0 */ |
365 | a41b2ff2 | pbrook | uint32_t RxBuf; /* Receive buffer */
|
366 | a41b2ff2 | pbrook | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
|
367 | a41b2ff2 | pbrook | uint32_t RxBufPtr; |
368 | a41b2ff2 | pbrook | uint32_t RxBufAddr; |
369 | a41b2ff2 | pbrook | |
370 | a41b2ff2 | pbrook | uint16_t IntrStatus; |
371 | a41b2ff2 | pbrook | uint16_t IntrMask; |
372 | a41b2ff2 | pbrook | |
373 | a41b2ff2 | pbrook | uint32_t TxConfig; |
374 | a41b2ff2 | pbrook | uint32_t RxConfig; |
375 | a41b2ff2 | pbrook | uint32_t RxMissed; |
376 | a41b2ff2 | pbrook | |
377 | a41b2ff2 | pbrook | uint16_t CSCR; |
378 | a41b2ff2 | pbrook | |
379 | a41b2ff2 | pbrook | uint8_t Cfg9346; |
380 | a41b2ff2 | pbrook | uint8_t Config0; |
381 | a41b2ff2 | pbrook | uint8_t Config1; |
382 | a41b2ff2 | pbrook | uint8_t Config3; |
383 | a41b2ff2 | pbrook | uint8_t Config4; |
384 | a41b2ff2 | pbrook | uint8_t Config5; |
385 | a41b2ff2 | pbrook | |
386 | a41b2ff2 | pbrook | uint8_t clock_enabled; |
387 | a41b2ff2 | pbrook | uint8_t bChipCmdState; |
388 | a41b2ff2 | pbrook | |
389 | a41b2ff2 | pbrook | uint16_t MultiIntr; |
390 | a41b2ff2 | pbrook | |
391 | a41b2ff2 | pbrook | uint16_t BasicModeCtrl; |
392 | a41b2ff2 | pbrook | uint16_t BasicModeStatus; |
393 | a41b2ff2 | pbrook | uint16_t NWayAdvert; |
394 | a41b2ff2 | pbrook | uint16_t NWayLPAR; |
395 | a41b2ff2 | pbrook | uint16_t NWayExpansion; |
396 | a41b2ff2 | pbrook | |
397 | a41b2ff2 | pbrook | uint16_t CpCmd; |
398 | a41b2ff2 | pbrook | uint8_t TxThresh; |
399 | a41b2ff2 | pbrook | |
400 | a41b2ff2 | pbrook | int irq;
|
401 | a41b2ff2 | pbrook | PCIDevice *pci_dev; |
402 | a41b2ff2 | pbrook | VLANClientState *vc; |
403 | a41b2ff2 | pbrook | uint8_t macaddr[6];
|
404 | a41b2ff2 | pbrook | int rtl8139_mmio_io_addr;
|
405 | a41b2ff2 | pbrook | |
406 | a41b2ff2 | pbrook | /* C ring mode */
|
407 | a41b2ff2 | pbrook | uint32_t currTxDesc; |
408 | a41b2ff2 | pbrook | |
409 | a41b2ff2 | pbrook | /* C+ mode */
|
410 | a41b2ff2 | pbrook | uint32_t currCPlusRxDesc; |
411 | a41b2ff2 | pbrook | uint32_t currCPlusTxDesc; |
412 | a41b2ff2 | pbrook | |
413 | a41b2ff2 | pbrook | uint32_t RxRingAddrLO; |
414 | a41b2ff2 | pbrook | uint32_t RxRingAddrHI; |
415 | a41b2ff2 | pbrook | |
416 | a41b2ff2 | pbrook | EEprom9346 eeprom; |
417 | a41b2ff2 | pbrook | |
418 | a41b2ff2 | pbrook | } RTL8139State; |
419 | a41b2ff2 | pbrook | |
420 | a41b2ff2 | pbrook | void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
|
421 | a41b2ff2 | pbrook | { |
422 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
423 | a41b2ff2 | pbrook | printf("RTL8139: eeprom command 0x%02x\n", command);
|
424 | a41b2ff2 | pbrook | #endif
|
425 | a41b2ff2 | pbrook | |
426 | a41b2ff2 | pbrook | switch (command & Chip9346_op_mask)
|
427 | a41b2ff2 | pbrook | { |
428 | a41b2ff2 | pbrook | case Chip9346_op_read:
|
429 | a41b2ff2 | pbrook | { |
430 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
431 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
432 | a41b2ff2 | pbrook | eeprom->eedo = 0;
|
433 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
434 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_data_read; |
435 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
436 | a41b2ff2 | pbrook | printf("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
|
437 | a41b2ff2 | pbrook | eeprom->address, eeprom->output); |
438 | a41b2ff2 | pbrook | #endif
|
439 | a41b2ff2 | pbrook | } |
440 | a41b2ff2 | pbrook | break;
|
441 | a41b2ff2 | pbrook | |
442 | a41b2ff2 | pbrook | case Chip9346_op_write:
|
443 | a41b2ff2 | pbrook | { |
444 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
445 | a41b2ff2 | pbrook | eeprom->input = 0;
|
446 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
447 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
448 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
449 | a41b2ff2 | pbrook | printf("RTL8139: eeprom begin write to address 0x%02x\n",
|
450 | a41b2ff2 | pbrook | eeprom->address); |
451 | a41b2ff2 | pbrook | #endif
|
452 | a41b2ff2 | pbrook | } |
453 | a41b2ff2 | pbrook | break;
|
454 | a41b2ff2 | pbrook | default:
|
455 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; |
456 | a41b2ff2 | pbrook | switch (command & Chip9346_op_ext_mask)
|
457 | a41b2ff2 | pbrook | { |
458 | a41b2ff2 | pbrook | case Chip9346_op_write_enable:
|
459 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
460 | a41b2ff2 | pbrook | printf("RTL8139: eeprom write enabled\n");
|
461 | a41b2ff2 | pbrook | #endif
|
462 | a41b2ff2 | pbrook | break;
|
463 | a41b2ff2 | pbrook | case Chip9346_op_write_all:
|
464 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
465 | a41b2ff2 | pbrook | printf("RTL8139: eeprom begin write all\n");
|
466 | a41b2ff2 | pbrook | #endif
|
467 | a41b2ff2 | pbrook | break;
|
468 | a41b2ff2 | pbrook | case Chip9346_op_write_disable:
|
469 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
470 | a41b2ff2 | pbrook | printf("RTL8139: eeprom write disabled\n");
|
471 | a41b2ff2 | pbrook | #endif
|
472 | a41b2ff2 | pbrook | break;
|
473 | a41b2ff2 | pbrook | } |
474 | a41b2ff2 | pbrook | break;
|
475 | a41b2ff2 | pbrook | } |
476 | a41b2ff2 | pbrook | } |
477 | a41b2ff2 | pbrook | |
478 | a41b2ff2 | pbrook | void prom9346_shift_clock(EEprom9346 *eeprom)
|
479 | a41b2ff2 | pbrook | { |
480 | a41b2ff2 | pbrook | int bit = eeprom->eedi?1:0; |
481 | a41b2ff2 | pbrook | |
482 | a41b2ff2 | pbrook | ++ eeprom->tick; |
483 | a41b2ff2 | pbrook | |
484 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
485 | a41b2ff2 | pbrook | printf("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo);
|
486 | a41b2ff2 | pbrook | #endif
|
487 | a41b2ff2 | pbrook | |
488 | a41b2ff2 | pbrook | switch (eeprom->mode)
|
489 | a41b2ff2 | pbrook | { |
490 | a41b2ff2 | pbrook | case Chip9346_enter_command_mode:
|
491 | a41b2ff2 | pbrook | if (bit)
|
492 | a41b2ff2 | pbrook | { |
493 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_read_command; |
494 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
495 | a41b2ff2 | pbrook | eeprom->input = 0;
|
496 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
497 | a41b2ff2 | pbrook | printf("eeprom: +++ synchronized, begin command read\n");
|
498 | a41b2ff2 | pbrook | #endif
|
499 | a41b2ff2 | pbrook | } |
500 | a41b2ff2 | pbrook | break;
|
501 | a41b2ff2 | pbrook | |
502 | a41b2ff2 | pbrook | case Chip9346_read_command:
|
503 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
504 | a41b2ff2 | pbrook | if (eeprom->tick == 8) |
505 | a41b2ff2 | pbrook | { |
506 | a41b2ff2 | pbrook | prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
507 | a41b2ff2 | pbrook | } |
508 | a41b2ff2 | pbrook | break;
|
509 | a41b2ff2 | pbrook | |
510 | a41b2ff2 | pbrook | case Chip9346_data_read:
|
511 | a41b2ff2 | pbrook | eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
512 | a41b2ff2 | pbrook | eeprom->output <<= 1;
|
513 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
514 | a41b2ff2 | pbrook | { |
515 | a41b2ff2 | pbrook | ++eeprom->address; |
516 | a41b2ff2 | pbrook | eeprom->address &= EEPROM_9346_ADDR_MASK; |
517 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
518 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
519 | a41b2ff2 | pbrook | |
520 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
521 | a41b2ff2 | pbrook | printf("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
522 | a41b2ff2 | pbrook | eeprom->address, eeprom->output); |
523 | a41b2ff2 | pbrook | #endif
|
524 | a41b2ff2 | pbrook | } |
525 | a41b2ff2 | pbrook | break;
|
526 | a41b2ff2 | pbrook | |
527 | a41b2ff2 | pbrook | case Chip9346_data_write:
|
528 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
529 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
530 | a41b2ff2 | pbrook | { |
531 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
532 | a41b2ff2 | pbrook | printf("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
|
533 | a41b2ff2 | pbrook | eeprom->address, eeprom->input); |
534 | a41b2ff2 | pbrook | #endif
|
535 | a41b2ff2 | pbrook | eeprom->contents[eeprom->address] = eeprom->input; |
536 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
537 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
538 | a41b2ff2 | pbrook | eeprom->input = 0;
|
539 | a41b2ff2 | pbrook | } |
540 | a41b2ff2 | pbrook | break;
|
541 | a41b2ff2 | pbrook | |
542 | a41b2ff2 | pbrook | case Chip9346_data_write_all:
|
543 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
544 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
545 | a41b2ff2 | pbrook | { |
546 | a41b2ff2 | pbrook | int i;
|
547 | a41b2ff2 | pbrook | for (i = 0; i < EEPROM_9346_SIZE; i++) |
548 | a41b2ff2 | pbrook | { |
549 | a41b2ff2 | pbrook | eeprom->contents[i] = eeprom->input; |
550 | a41b2ff2 | pbrook | } |
551 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
552 | a41b2ff2 | pbrook | printf("RTL8139: eeprom filled with data=0x%04x\n",
|
553 | a41b2ff2 | pbrook | eeprom->input); |
554 | a41b2ff2 | pbrook | #endif
|
555 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
556 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
557 | a41b2ff2 | pbrook | eeprom->input = 0;
|
558 | a41b2ff2 | pbrook | } |
559 | a41b2ff2 | pbrook | break;
|
560 | a41b2ff2 | pbrook | |
561 | a41b2ff2 | pbrook | default:
|
562 | a41b2ff2 | pbrook | break;
|
563 | a41b2ff2 | pbrook | } |
564 | a41b2ff2 | pbrook | } |
565 | a41b2ff2 | pbrook | |
566 | a41b2ff2 | pbrook | int prom9346_get_wire(RTL8139State *s)
|
567 | a41b2ff2 | pbrook | { |
568 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
569 | a41b2ff2 | pbrook | if (!eeprom->eecs)
|
570 | a41b2ff2 | pbrook | return 0; |
571 | a41b2ff2 | pbrook | |
572 | a41b2ff2 | pbrook | return eeprom->eedo;
|
573 | a41b2ff2 | pbrook | } |
574 | a41b2ff2 | pbrook | |
575 | a41b2ff2 | pbrook | void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
576 | a41b2ff2 | pbrook | { |
577 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
578 | a41b2ff2 | pbrook | uint8_t old_eecs = eeprom->eecs; |
579 | a41b2ff2 | pbrook | uint8_t old_eesk = eeprom->eesk; |
580 | a41b2ff2 | pbrook | |
581 | a41b2ff2 | pbrook | eeprom->eecs = eecs; |
582 | a41b2ff2 | pbrook | eeprom->eesk = eesk; |
583 | a41b2ff2 | pbrook | eeprom->eedi = eedi; |
584 | a41b2ff2 | pbrook | |
585 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
586 | a41b2ff2 | pbrook | printf("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo);
|
587 | a41b2ff2 | pbrook | #endif
|
588 | a41b2ff2 | pbrook | |
589 | a41b2ff2 | pbrook | if (!old_eecs && eecs)
|
590 | a41b2ff2 | pbrook | { |
591 | a41b2ff2 | pbrook | /* Synchronize start */
|
592 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
593 | a41b2ff2 | pbrook | eeprom->input = 0;
|
594 | a41b2ff2 | pbrook | eeprom->output = 0;
|
595 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
596 | a41b2ff2 | pbrook | |
597 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
598 | a41b2ff2 | pbrook | printf("=== eeprom: begin access, enter command mode\n");
|
599 | a41b2ff2 | pbrook | #endif
|
600 | a41b2ff2 | pbrook | |
601 | a41b2ff2 | pbrook | } |
602 | a41b2ff2 | pbrook | |
603 | a41b2ff2 | pbrook | if (!eecs)
|
604 | a41b2ff2 | pbrook | { |
605 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
606 | a41b2ff2 | pbrook | printf("=== eeprom: end access\n");
|
607 | a41b2ff2 | pbrook | #endif
|
608 | a41b2ff2 | pbrook | return;
|
609 | a41b2ff2 | pbrook | } |
610 | a41b2ff2 | pbrook | |
611 | a41b2ff2 | pbrook | if (!old_eesk && eesk)
|
612 | a41b2ff2 | pbrook | { |
613 | a41b2ff2 | pbrook | /* SK front rules */
|
614 | a41b2ff2 | pbrook | prom9346_shift_clock(eeprom); |
615 | a41b2ff2 | pbrook | } |
616 | a41b2ff2 | pbrook | } |
617 | a41b2ff2 | pbrook | |
618 | a41b2ff2 | pbrook | static void rtl8139_update_irq(RTL8139State *s) |
619 | a41b2ff2 | pbrook | { |
620 | a41b2ff2 | pbrook | int isr;
|
621 | a41b2ff2 | pbrook | isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
622 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
623 | a41b2ff2 | pbrook | printf("RTL8139: Set IRQ line %d to %d (%04x %04x)\n",
|
624 | a41b2ff2 | pbrook | s->irq, isr ? 1 : 0, s->IntrStatus, s->IntrMask); |
625 | a41b2ff2 | pbrook | #endif
|
626 | a41b2ff2 | pbrook | if (s->irq == 16) { |
627 | a41b2ff2 | pbrook | /* PCI irq */
|
628 | a41b2ff2 | pbrook | pci_set_irq(s->pci_dev, 0, (isr != 0)); |
629 | a41b2ff2 | pbrook | } else {
|
630 | a41b2ff2 | pbrook | /* ISA irq */
|
631 | a41b2ff2 | pbrook | pic_set_irq(s->irq, (isr != 0));
|
632 | a41b2ff2 | pbrook | } |
633 | a41b2ff2 | pbrook | } |
634 | a41b2ff2 | pbrook | |
635 | a41b2ff2 | pbrook | #define POLYNOMIAL 0x04c11db6 |
636 | a41b2ff2 | pbrook | |
637 | a41b2ff2 | pbrook | /* From FreeBSD */
|
638 | a41b2ff2 | pbrook | /* XXX: optimize */
|
639 | a41b2ff2 | pbrook | static int compute_mcast_idx(const uint8_t *ep) |
640 | a41b2ff2 | pbrook | { |
641 | a41b2ff2 | pbrook | uint32_t crc; |
642 | a41b2ff2 | pbrook | int carry, i, j;
|
643 | a41b2ff2 | pbrook | uint8_t b; |
644 | a41b2ff2 | pbrook | |
645 | a41b2ff2 | pbrook | crc = 0xffffffff;
|
646 | a41b2ff2 | pbrook | for (i = 0; i < 6; i++) { |
647 | a41b2ff2 | pbrook | b = *ep++; |
648 | a41b2ff2 | pbrook | for (j = 0; j < 8; j++) { |
649 | a41b2ff2 | pbrook | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
650 | a41b2ff2 | pbrook | crc <<= 1;
|
651 | a41b2ff2 | pbrook | b >>= 1;
|
652 | a41b2ff2 | pbrook | if (carry)
|
653 | a41b2ff2 | pbrook | crc = ((crc ^ POLYNOMIAL) | carry); |
654 | a41b2ff2 | pbrook | } |
655 | a41b2ff2 | pbrook | } |
656 | a41b2ff2 | pbrook | return (crc >> 26); |
657 | a41b2ff2 | pbrook | } |
658 | a41b2ff2 | pbrook | |
659 | a41b2ff2 | pbrook | static int rtl8139_RxWrap(RTL8139State *s) |
660 | a41b2ff2 | pbrook | { |
661 | a41b2ff2 | pbrook | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
662 | a41b2ff2 | pbrook | return (s->RxConfig & (1 << 7)); |
663 | a41b2ff2 | pbrook | } |
664 | a41b2ff2 | pbrook | |
665 | a41b2ff2 | pbrook | static int rtl8139_receiver_enabled(RTL8139State *s) |
666 | a41b2ff2 | pbrook | { |
667 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdRxEnb;
|
668 | a41b2ff2 | pbrook | } |
669 | a41b2ff2 | pbrook | |
670 | a41b2ff2 | pbrook | static int rtl8139_transmitter_enabled(RTL8139State *s) |
671 | a41b2ff2 | pbrook | { |
672 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdTxEnb;
|
673 | a41b2ff2 | pbrook | } |
674 | a41b2ff2 | pbrook | |
675 | a41b2ff2 | pbrook | static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
676 | a41b2ff2 | pbrook | { |
677 | a41b2ff2 | pbrook | return s->CpCmd & CPlusRxEnb;
|
678 | a41b2ff2 | pbrook | } |
679 | a41b2ff2 | pbrook | |
680 | a41b2ff2 | pbrook | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
681 | a41b2ff2 | pbrook | { |
682 | a41b2ff2 | pbrook | return s->CpCmd & CPlusTxEnb;
|
683 | a41b2ff2 | pbrook | } |
684 | a41b2ff2 | pbrook | |
685 | a41b2ff2 | pbrook | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
686 | a41b2ff2 | pbrook | { |
687 | a41b2ff2 | pbrook | if (s->RxBufAddr + size > s->RxBufferSize)
|
688 | a41b2ff2 | pbrook | { |
689 | a41b2ff2 | pbrook | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
690 | a41b2ff2 | pbrook | |
691 | a41b2ff2 | pbrook | /* write packet data */
|
692 | a41b2ff2 | pbrook | if (wrapped && s->RxBufferSize < 65536 && !rtl8139_RxWrap(s)) |
693 | a41b2ff2 | pbrook | { |
694 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
695 | a41b2ff2 | pbrook | printf(">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped);
|
696 | a41b2ff2 | pbrook | #endif
|
697 | a41b2ff2 | pbrook | |
698 | a41b2ff2 | pbrook | if (size > wrapped)
|
699 | a41b2ff2 | pbrook | { |
700 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
701 | a41b2ff2 | pbrook | buf, size-wrapped ); |
702 | a41b2ff2 | pbrook | } |
703 | a41b2ff2 | pbrook | |
704 | a41b2ff2 | pbrook | /* reset buffer pointer */
|
705 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
706 | a41b2ff2 | pbrook | |
707 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
708 | a41b2ff2 | pbrook | buf + (size-wrapped), wrapped ); |
709 | a41b2ff2 | pbrook | |
710 | a41b2ff2 | pbrook | s->RxBufAddr = wrapped; |
711 | a41b2ff2 | pbrook | |
712 | a41b2ff2 | pbrook | return;
|
713 | a41b2ff2 | pbrook | } |
714 | a41b2ff2 | pbrook | } |
715 | a41b2ff2 | pbrook | |
716 | a41b2ff2 | pbrook | /* non-wrapping path or overwrapping enabled */
|
717 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); |
718 | a41b2ff2 | pbrook | |
719 | a41b2ff2 | pbrook | s->RxBufAddr += size; |
720 | a41b2ff2 | pbrook | } |
721 | a41b2ff2 | pbrook | |
722 | a41b2ff2 | pbrook | #define MIN_BUF_SIZE 60 |
723 | a41b2ff2 | pbrook | static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
724 | a41b2ff2 | pbrook | { |
725 | a41b2ff2 | pbrook | #if TARGET_PHYS_ADDR_BITS > 32 |
726 | a41b2ff2 | pbrook | return low | ((target_phys_addr_t)high << 32); |
727 | a41b2ff2 | pbrook | #else
|
728 | a41b2ff2 | pbrook | return low;
|
729 | a41b2ff2 | pbrook | #endif
|
730 | a41b2ff2 | pbrook | } |
731 | a41b2ff2 | pbrook | |
732 | a41b2ff2 | pbrook | static int rtl8139_can_receive(void *opaque) |
733 | a41b2ff2 | pbrook | { |
734 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
735 | a41b2ff2 | pbrook | int avail;
|
736 | a41b2ff2 | pbrook | |
737 | a41b2ff2 | pbrook | /* Recieve (drop) packets if card is disabled. */
|
738 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
739 | a41b2ff2 | pbrook | return 1; |
740 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
741 | a41b2ff2 | pbrook | return 1; |
742 | a41b2ff2 | pbrook | |
743 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s)) {
|
744 | a41b2ff2 | pbrook | /* ??? Flow control not implemented in c+ mode.
|
745 | a41b2ff2 | pbrook | This is a hack to work around slirp deficiencies anyway. */
|
746 | a41b2ff2 | pbrook | return 1; |
747 | a41b2ff2 | pbrook | } else {
|
748 | a41b2ff2 | pbrook | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
749 | a41b2ff2 | pbrook | s->RxBufferSize); |
750 | a41b2ff2 | pbrook | return (avail == 0 || avail >= 1514); |
751 | a41b2ff2 | pbrook | } |
752 | a41b2ff2 | pbrook | } |
753 | a41b2ff2 | pbrook | |
754 | a41b2ff2 | pbrook | static void rtl8139_receive(void *opaque, const uint8_t *buf, int size) |
755 | a41b2ff2 | pbrook | { |
756 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
757 | a41b2ff2 | pbrook | |
758 | a41b2ff2 | pbrook | uint32_t packet_header = 0;
|
759 | a41b2ff2 | pbrook | |
760 | a41b2ff2 | pbrook | uint8_t buf1[60];
|
761 | a41b2ff2 | pbrook | static const uint8_t broadcast_macaddr[6] = |
762 | a41b2ff2 | pbrook | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
763 | a41b2ff2 | pbrook | |
764 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
765 | a41b2ff2 | pbrook | printf(">>> RTL8139: received len=%d\n", size);
|
766 | a41b2ff2 | pbrook | #endif
|
767 | a41b2ff2 | pbrook | |
768 | a41b2ff2 | pbrook | /* test if board clock is stopped */
|
769 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
770 | a41b2ff2 | pbrook | { |
771 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
772 | a41b2ff2 | pbrook | printf("RTL8139: stopped ==========================\n");
|
773 | a41b2ff2 | pbrook | #endif
|
774 | a41b2ff2 | pbrook | return;
|
775 | a41b2ff2 | pbrook | } |
776 | a41b2ff2 | pbrook | |
777 | a41b2ff2 | pbrook | /* first check if receiver is enabled */
|
778 | a41b2ff2 | pbrook | |
779 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
780 | a41b2ff2 | pbrook | { |
781 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
782 | a41b2ff2 | pbrook | printf("RTL8139: receiver disabled ================\n");
|
783 | a41b2ff2 | pbrook | #endif
|
784 | a41b2ff2 | pbrook | return;
|
785 | a41b2ff2 | pbrook | } |
786 | a41b2ff2 | pbrook | |
787 | a41b2ff2 | pbrook | /* XXX: check this */
|
788 | a41b2ff2 | pbrook | if (s->RxConfig & AcceptAllPhys) {
|
789 | a41b2ff2 | pbrook | /* promiscuous: receive all */
|
790 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
791 | a41b2ff2 | pbrook | printf(">>> RTL8139: packet received in promiscuous mode\n");
|
792 | a41b2ff2 | pbrook | #endif
|
793 | a41b2ff2 | pbrook | |
794 | a41b2ff2 | pbrook | } else {
|
795 | a41b2ff2 | pbrook | if (!memcmp(buf, broadcast_macaddr, 6)) { |
796 | a41b2ff2 | pbrook | /* broadcast address */
|
797 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptBroadcast))
|
798 | a41b2ff2 | pbrook | { |
799 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
800 | a41b2ff2 | pbrook | printf(">>> RTL8139: broadcast packet rejected\n");
|
801 | a41b2ff2 | pbrook | #endif
|
802 | a41b2ff2 | pbrook | return;
|
803 | a41b2ff2 | pbrook | } |
804 | a41b2ff2 | pbrook | |
805 | a41b2ff2 | pbrook | packet_header |= RxBroadcast; |
806 | a41b2ff2 | pbrook | |
807 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
808 | a41b2ff2 | pbrook | printf(">>> RTL8139: broadcast packet received\n");
|
809 | a41b2ff2 | pbrook | #endif
|
810 | a41b2ff2 | pbrook | } else if (buf[0] & 0x01) { |
811 | a41b2ff2 | pbrook | /* multicast */
|
812 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMulticast))
|
813 | a41b2ff2 | pbrook | { |
814 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
815 | a41b2ff2 | pbrook | printf(">>> RTL8139: multicast packet rejected\n");
|
816 | a41b2ff2 | pbrook | #endif
|
817 | a41b2ff2 | pbrook | return;
|
818 | a41b2ff2 | pbrook | } |
819 | a41b2ff2 | pbrook | |
820 | a41b2ff2 | pbrook | int mcast_idx = compute_mcast_idx(buf);
|
821 | a41b2ff2 | pbrook | |
822 | a41b2ff2 | pbrook | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
823 | a41b2ff2 | pbrook | { |
824 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
825 | a41b2ff2 | pbrook | printf(">>> RTL8139: multicast address mismatch\n");
|
826 | a41b2ff2 | pbrook | #endif
|
827 | a41b2ff2 | pbrook | return;
|
828 | a41b2ff2 | pbrook | } |
829 | a41b2ff2 | pbrook | |
830 | a41b2ff2 | pbrook | packet_header |= RxMulticast; |
831 | a41b2ff2 | pbrook | |
832 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
833 | a41b2ff2 | pbrook | printf(">>> RTL8139: multicast packet received\n");
|
834 | a41b2ff2 | pbrook | #endif
|
835 | a41b2ff2 | pbrook | } else if (s->phys[0] == buf[0] && |
836 | a41b2ff2 | pbrook | s->phys[1] == buf[1] && |
837 | a41b2ff2 | pbrook | s->phys[2] == buf[2] && |
838 | a41b2ff2 | pbrook | s->phys[3] == buf[3] && |
839 | a41b2ff2 | pbrook | s->phys[4] == buf[4] && |
840 | a41b2ff2 | pbrook | s->phys[5] == buf[5]) { |
841 | a41b2ff2 | pbrook | /* match */
|
842 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMyPhys))
|
843 | a41b2ff2 | pbrook | { |
844 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
845 | a41b2ff2 | pbrook | printf(">>> RTL8139: rejecting physical address matching packet\n");
|
846 | a41b2ff2 | pbrook | #endif
|
847 | a41b2ff2 | pbrook | return;
|
848 | a41b2ff2 | pbrook | } |
849 | a41b2ff2 | pbrook | |
850 | a41b2ff2 | pbrook | packet_header |= RxPhysical; |
851 | a41b2ff2 | pbrook | |
852 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
853 | a41b2ff2 | pbrook | printf(">>> RTL8139: physical address matching packet received\n");
|
854 | a41b2ff2 | pbrook | #endif
|
855 | a41b2ff2 | pbrook | |
856 | a41b2ff2 | pbrook | } else {
|
857 | a41b2ff2 | pbrook | |
858 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
859 | a41b2ff2 | pbrook | printf(">>> RTL8139: unknown packet\n");
|
860 | a41b2ff2 | pbrook | #endif
|
861 | a41b2ff2 | pbrook | return;
|
862 | a41b2ff2 | pbrook | } |
863 | a41b2ff2 | pbrook | } |
864 | a41b2ff2 | pbrook | |
865 | a41b2ff2 | pbrook | /* if too small buffer, then expand it */
|
866 | a41b2ff2 | pbrook | if (size < MIN_BUF_SIZE) {
|
867 | a41b2ff2 | pbrook | memcpy(buf1, buf, size); |
868 | a41b2ff2 | pbrook | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
|
869 | a41b2ff2 | pbrook | buf = buf1; |
870 | a41b2ff2 | pbrook | size = MIN_BUF_SIZE; |
871 | a41b2ff2 | pbrook | } |
872 | a41b2ff2 | pbrook | |
873 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s))
|
874 | a41b2ff2 | pbrook | { |
875 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
876 | a41b2ff2 | pbrook | printf("RTL8139: in C+ Rx mode ================\n");
|
877 | a41b2ff2 | pbrook | #endif
|
878 | a41b2ff2 | pbrook | |
879 | a41b2ff2 | pbrook | /* begin C+ receiver mode */
|
880 | a41b2ff2 | pbrook | |
881 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
882 | a41b2ff2 | pbrook | #define CP_RX_OWN (1<<31) |
883 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
884 | a41b2ff2 | pbrook | #define CP_RX_EOR (1<<30) |
885 | a41b2ff2 | pbrook | /* w0 bits 0...12 : buffer size */
|
886 | a41b2ff2 | pbrook | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
887 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
888 | a41b2ff2 | pbrook | #define CP_RX_TAVA (1<<16) |
889 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
890 | a41b2ff2 | pbrook | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
891 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
892 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
893 | a41b2ff2 | pbrook | |
894 | a41b2ff2 | pbrook | int descriptor = s->currCPlusRxDesc;
|
895 | a41b2ff2 | pbrook | target_phys_addr_t cplus_rx_ring_desc; |
896 | a41b2ff2 | pbrook | |
897 | a41b2ff2 | pbrook | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
898 | a41b2ff2 | pbrook | cplus_rx_ring_desc += 16 * descriptor;
|
899 | a41b2ff2 | pbrook | |
900 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
901 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = 0x%8lx\n",
|
902 | a41b2ff2 | pbrook | descriptor, s->RxRingAddrHI, s->RxRingAddrLO, cplus_rx_ring_desc); |
903 | a41b2ff2 | pbrook | #endif
|
904 | a41b2ff2 | pbrook | |
905 | a41b2ff2 | pbrook | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
906 | a41b2ff2 | pbrook | |
907 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
908 | a41b2ff2 | pbrook | rxdw0 = le32_to_cpu(val); |
909 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
910 | a41b2ff2 | pbrook | rxdw1 = le32_to_cpu(val); |
911 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); |
912 | a41b2ff2 | pbrook | rxbufLO = le32_to_cpu(val); |
913 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); |
914 | a41b2ff2 | pbrook | rxbufHI = le32_to_cpu(val); |
915 | a41b2ff2 | pbrook | |
916 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
917 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
918 | a41b2ff2 | pbrook | descriptor, |
919 | a41b2ff2 | pbrook | rxdw0, rxdw1, rxbufLO, rxbufHI); |
920 | a41b2ff2 | pbrook | #endif
|
921 | a41b2ff2 | pbrook | |
922 | a41b2ff2 | pbrook | if (!(rxdw0 & CP_RX_OWN))
|
923 | a41b2ff2 | pbrook | { |
924 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
925 | a41b2ff2 | pbrook | printf("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor);
|
926 | a41b2ff2 | pbrook | #endif
|
927 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
928 | a41b2ff2 | pbrook | ++s->RxMissed; |
929 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
930 | a41b2ff2 | pbrook | return;
|
931 | a41b2ff2 | pbrook | } |
932 | a41b2ff2 | pbrook | |
933 | a41b2ff2 | pbrook | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
934 | a41b2ff2 | pbrook | |
935 | a41b2ff2 | pbrook | if (size+4 > rx_space) |
936 | a41b2ff2 | pbrook | { |
937 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
938 | a41b2ff2 | pbrook | printf("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
939 | a41b2ff2 | pbrook | descriptor, rx_space, size); |
940 | a41b2ff2 | pbrook | #endif
|
941 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
942 | a41b2ff2 | pbrook | ++s->RxMissed; |
943 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
944 | a41b2ff2 | pbrook | return;
|
945 | a41b2ff2 | pbrook | } |
946 | a41b2ff2 | pbrook | |
947 | a41b2ff2 | pbrook | target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
948 | a41b2ff2 | pbrook | |
949 | a41b2ff2 | pbrook | /* receive/copy to target memory */
|
950 | a41b2ff2 | pbrook | cpu_physical_memory_write( rx_addr, buf, size ); |
951 | a41b2ff2 | pbrook | |
952 | a41b2ff2 | pbrook | /* write checksum */
|
953 | a41b2ff2 | pbrook | #if defined (RTL8139_CALCULATE_RXCRC)
|
954 | a41b2ff2 | pbrook | val = cpu_to_le32(crc32(~0, buf, size));
|
955 | a41b2ff2 | pbrook | #else
|
956 | a41b2ff2 | pbrook | val = 0;
|
957 | a41b2ff2 | pbrook | #endif
|
958 | a41b2ff2 | pbrook | cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
|
959 | a41b2ff2 | pbrook | |
960 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
961 | a41b2ff2 | pbrook | #define CP_RX_STATUS_FS (1<<29) |
962 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
963 | a41b2ff2 | pbrook | #define CP_RX_STATUS_LS (1<<28) |
964 | a41b2ff2 | pbrook | /* multicast packet flag */
|
965 | a41b2ff2 | pbrook | #define CP_RX_STATUS_MAR (1<<26) |
966 | a41b2ff2 | pbrook | /* physical-matching packet flag */
|
967 | a41b2ff2 | pbrook | #define CP_RX_STATUS_PAM (1<<25) |
968 | a41b2ff2 | pbrook | /* broadcast packet flag */
|
969 | a41b2ff2 | pbrook | #define CP_RX_STATUS_BAR (1<<24) |
970 | a41b2ff2 | pbrook | /* runt packet flag */
|
971 | a41b2ff2 | pbrook | #define CP_RX_STATUS_RUNT (1<<19) |
972 | a41b2ff2 | pbrook | /* crc error flag */
|
973 | a41b2ff2 | pbrook | #define CP_RX_STATUS_CRC (1<<18) |
974 | a41b2ff2 | pbrook | /* IP checksum error flag */
|
975 | a41b2ff2 | pbrook | #define CP_RX_STATUS_IPF (1<<15) |
976 | a41b2ff2 | pbrook | /* UDP checksum error flag */
|
977 | a41b2ff2 | pbrook | #define CP_RX_STATUS_UDPF (1<<14) |
978 | a41b2ff2 | pbrook | /* TCP checksum error flag */
|
979 | a41b2ff2 | pbrook | #define CP_RX_STATUS_TCPF (1<<13) |
980 | a41b2ff2 | pbrook | |
981 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
982 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_OWN; |
983 | a41b2ff2 | pbrook | |
984 | a41b2ff2 | pbrook | /* set first segment bit */
|
985 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_FS; |
986 | a41b2ff2 | pbrook | |
987 | a41b2ff2 | pbrook | /* set last segment bit */
|
988 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_LS; |
989 | a41b2ff2 | pbrook | |
990 | a41b2ff2 | pbrook | /* set received packet type flags */
|
991 | a41b2ff2 | pbrook | if (packet_header & RxBroadcast)
|
992 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_BAR; |
993 | a41b2ff2 | pbrook | if (packet_header & RxMulticast)
|
994 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_MAR; |
995 | a41b2ff2 | pbrook | if (packet_header & RxPhysical)
|
996 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_PAM; |
997 | a41b2ff2 | pbrook | |
998 | a41b2ff2 | pbrook | /* set received size */
|
999 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
1000 | a41b2ff2 | pbrook | rxdw0 |= (size+4);
|
1001 | a41b2ff2 | pbrook | |
1002 | a41b2ff2 | pbrook | /* reset VLAN tag flag */
|
1003 | a41b2ff2 | pbrook | rxdw1 &= ~CP_RX_TAVA; |
1004 | a41b2ff2 | pbrook | |
1005 | a41b2ff2 | pbrook | /* update ring data */
|
1006 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw0); |
1007 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
1008 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw1); |
1009 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
1010 | a41b2ff2 | pbrook | |
1011 | a41b2ff2 | pbrook | /* seek to next Rx descriptor */
|
1012 | a41b2ff2 | pbrook | if (rxdw0 & CP_RX_EOR)
|
1013 | a41b2ff2 | pbrook | { |
1014 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1015 | a41b2ff2 | pbrook | } |
1016 | a41b2ff2 | pbrook | else
|
1017 | a41b2ff2 | pbrook | { |
1018 | a41b2ff2 | pbrook | ++s->currCPlusRxDesc; |
1019 | a41b2ff2 | pbrook | } |
1020 | a41b2ff2 | pbrook | |
1021 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1022 | a41b2ff2 | pbrook | printf("RTL8139: done C+ Rx mode ----------------\n");
|
1023 | a41b2ff2 | pbrook | #endif
|
1024 | a41b2ff2 | pbrook | |
1025 | a41b2ff2 | pbrook | } |
1026 | a41b2ff2 | pbrook | else
|
1027 | a41b2ff2 | pbrook | { |
1028 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1029 | a41b2ff2 | pbrook | printf("RTL8139: in ring Rx mode ================\n");
|
1030 | a41b2ff2 | pbrook | #endif
|
1031 | a41b2ff2 | pbrook | /* begin ring receiver mode */
|
1032 | a41b2ff2 | pbrook | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
1033 | a41b2ff2 | pbrook | |
1034 | a41b2ff2 | pbrook | /* if receiver buffer is empty then avail == 0 */
|
1035 | a41b2ff2 | pbrook | |
1036 | a41b2ff2 | pbrook | if (avail != 0 && size + 8 >= avail) |
1037 | a41b2ff2 | pbrook | { |
1038 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1039 | a41b2ff2 | pbrook | printf("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
|
1040 | a41b2ff2 | pbrook | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
|
1041 | a41b2ff2 | pbrook | #endif
|
1042 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1043 | a41b2ff2 | pbrook | ++s->RxMissed; |
1044 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1045 | a41b2ff2 | pbrook | return;
|
1046 | a41b2ff2 | pbrook | } |
1047 | a41b2ff2 | pbrook | |
1048 | a41b2ff2 | pbrook | packet_header |= RxStatusOK; |
1049 | a41b2ff2 | pbrook | |
1050 | a41b2ff2 | pbrook | packet_header |= (((size+4) << 16) & 0xffff0000); |
1051 | a41b2ff2 | pbrook | |
1052 | a41b2ff2 | pbrook | /* write header */
|
1053 | a41b2ff2 | pbrook | uint32_t val = cpu_to_le32(packet_header); |
1054 | a41b2ff2 | pbrook | |
1055 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1056 | a41b2ff2 | pbrook | |
1057 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, buf, size); |
1058 | a41b2ff2 | pbrook | |
1059 | a41b2ff2 | pbrook | /* write checksum */
|
1060 | a41b2ff2 | pbrook | #if defined (RTL8139_CALCULATE_RXCRC)
|
1061 | a41b2ff2 | pbrook | val = cpu_to_le32(crc32(~0, buf, size));
|
1062 | a41b2ff2 | pbrook | #else
|
1063 | a41b2ff2 | pbrook | val = 0;
|
1064 | a41b2ff2 | pbrook | #endif
|
1065 | a41b2ff2 | pbrook | |
1066 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1067 | a41b2ff2 | pbrook | |
1068 | a41b2ff2 | pbrook | /* correct buffer write pointer */
|
1069 | a41b2ff2 | pbrook | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
1070 | a41b2ff2 | pbrook | |
1071 | a41b2ff2 | pbrook | /* now we can signal we have received something */
|
1072 | a41b2ff2 | pbrook | |
1073 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1074 | a41b2ff2 | pbrook | printf(" received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
1075 | a41b2ff2 | pbrook | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
1076 | a41b2ff2 | pbrook | #endif
|
1077 | a41b2ff2 | pbrook | |
1078 | a41b2ff2 | pbrook | } |
1079 | a41b2ff2 | pbrook | |
1080 | a41b2ff2 | pbrook | s->IntrStatus |= RxOK; |
1081 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1082 | a41b2ff2 | pbrook | } |
1083 | a41b2ff2 | pbrook | |
1084 | a41b2ff2 | pbrook | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
1085 | a41b2ff2 | pbrook | { |
1086 | a41b2ff2 | pbrook | s->RxBufferSize = bufferSize; |
1087 | a41b2ff2 | pbrook | s->RxBufPtr = 0;
|
1088 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
1089 | a41b2ff2 | pbrook | } |
1090 | a41b2ff2 | pbrook | |
1091 | a41b2ff2 | pbrook | static void rtl8139_reset(RTL8139State *s) |
1092 | a41b2ff2 | pbrook | { |
1093 | a41b2ff2 | pbrook | int i;
|
1094 | a41b2ff2 | pbrook | |
1095 | a41b2ff2 | pbrook | /* restore MAC address */
|
1096 | a41b2ff2 | pbrook | memcpy(s->phys, s->macaddr, 6);
|
1097 | a41b2ff2 | pbrook | |
1098 | a41b2ff2 | pbrook | /* reset interrupt mask */
|
1099 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
1100 | a41b2ff2 | pbrook | s->IntrMask = 0;
|
1101 | a41b2ff2 | pbrook | |
1102 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1103 | a41b2ff2 | pbrook | |
1104 | a41b2ff2 | pbrook | /* prepare eeprom */
|
1105 | a41b2ff2 | pbrook | s->eeprom.contents[0] = 0x8129; |
1106 | a41b2ff2 | pbrook | memcpy(&s->eeprom.contents[7], s->macaddr, 6); |
1107 | a41b2ff2 | pbrook | |
1108 | a41b2ff2 | pbrook | /* mark all status registers as owned by host */
|
1109 | a41b2ff2 | pbrook | for (i = 0; i < 4; ++i) |
1110 | a41b2ff2 | pbrook | { |
1111 | a41b2ff2 | pbrook | s->TxStatus[i] = TxHostOwns; |
1112 | a41b2ff2 | pbrook | } |
1113 | a41b2ff2 | pbrook | |
1114 | a41b2ff2 | pbrook | s->currTxDesc = 0;
|
1115 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1116 | a41b2ff2 | pbrook | s->currCPlusTxDesc = 0;
|
1117 | a41b2ff2 | pbrook | |
1118 | a41b2ff2 | pbrook | s->RxRingAddrLO = 0;
|
1119 | a41b2ff2 | pbrook | s->RxRingAddrHI = 0;
|
1120 | a41b2ff2 | pbrook | |
1121 | a41b2ff2 | pbrook | s->RxBuf = 0;
|
1122 | a41b2ff2 | pbrook | |
1123 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192);
|
1124 | a41b2ff2 | pbrook | |
1125 | a41b2ff2 | pbrook | /* ACK the reset */
|
1126 | a41b2ff2 | pbrook | s->TxConfig = 0;
|
1127 | a41b2ff2 | pbrook | |
1128 | a41b2ff2 | pbrook | #if 0
|
1129 | a41b2ff2 | pbrook | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
1130 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
1131 | a41b2ff2 | pbrook | #else
|
1132 | a41b2ff2 | pbrook | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 0, 0); // RTL-8139C HasLWake |
1133 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
1134 | a41b2ff2 | pbrook | #endif
|
1135 | a41b2ff2 | pbrook | |
1136 | a41b2ff2 | pbrook | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
1137 | a41b2ff2 | pbrook | |
1138 | a41b2ff2 | pbrook | /* set initial state data */
|
1139 | a41b2ff2 | pbrook | s->Config0 = 0x0; /* No boot ROM */ |
1140 | a41b2ff2 | pbrook | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
1141 | a41b2ff2 | pbrook | s->Config3 = 0x1; /* fast back-to-back compatible */ |
1142 | a41b2ff2 | pbrook | s->Config5 = 0x0;
|
1143 | a41b2ff2 | pbrook | |
1144 | a41b2ff2 | pbrook | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
1145 | a41b2ff2 | pbrook | |
1146 | a41b2ff2 | pbrook | s->CpCmd = 0x0; /* reset C+ mode */ |
1147 | a41b2ff2 | pbrook | |
1148 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
1149 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
1150 | a41b2ff2 | pbrook | s->BasicModeCtrl = 0x1000; // autonegotiation |
1151 | a41b2ff2 | pbrook | |
1152 | a41b2ff2 | pbrook | s->BasicModeStatus = 0x7809;
|
1153 | a41b2ff2 | pbrook | //s->BasicModeStatus |= 0x0040; /* UTP medium */
|
1154 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
1155 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0004; /* link is up */ |
1156 | a41b2ff2 | pbrook | |
1157 | a41b2ff2 | pbrook | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
1158 | a41b2ff2 | pbrook | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
1159 | a41b2ff2 | pbrook | s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
1160 | a41b2ff2 | pbrook | } |
1161 | a41b2ff2 | pbrook | |
1162 | a41b2ff2 | pbrook | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
1163 | a41b2ff2 | pbrook | { |
1164 | a41b2ff2 | pbrook | val &= 0xff;
|
1165 | a41b2ff2 | pbrook | |
1166 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1167 | a41b2ff2 | pbrook | printf("RTL8139: ChipCmd write val=0x%08x\n", val);
|
1168 | a41b2ff2 | pbrook | #endif
|
1169 | a41b2ff2 | pbrook | |
1170 | a41b2ff2 | pbrook | if (val & CmdReset)
|
1171 | a41b2ff2 | pbrook | { |
1172 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1173 | a41b2ff2 | pbrook | printf("RTL8139: ChipCmd reset\n");
|
1174 | a41b2ff2 | pbrook | #endif
|
1175 | a41b2ff2 | pbrook | rtl8139_reset(s); |
1176 | a41b2ff2 | pbrook | } |
1177 | a41b2ff2 | pbrook | if (val & CmdRxEnb)
|
1178 | a41b2ff2 | pbrook | { |
1179 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1180 | a41b2ff2 | pbrook | printf("RTL8139: ChipCmd enable receiver\n");
|
1181 | a41b2ff2 | pbrook | #endif
|
1182 | a41b2ff2 | pbrook | } |
1183 | a41b2ff2 | pbrook | if (val & CmdTxEnb)
|
1184 | a41b2ff2 | pbrook | { |
1185 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1186 | a41b2ff2 | pbrook | printf("RTL8139: ChipCmd enable transmitter\n");
|
1187 | a41b2ff2 | pbrook | #endif
|
1188 | a41b2ff2 | pbrook | } |
1189 | a41b2ff2 | pbrook | |
1190 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1191 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
1192 | a41b2ff2 | pbrook | |
1193 | a41b2ff2 | pbrook | /* Deassert reset pin before next read */
|
1194 | a41b2ff2 | pbrook | val &= ~CmdReset; |
1195 | a41b2ff2 | pbrook | |
1196 | a41b2ff2 | pbrook | s->bChipCmdState = val; |
1197 | a41b2ff2 | pbrook | } |
1198 | a41b2ff2 | pbrook | |
1199 | a41b2ff2 | pbrook | static int rtl8139_RxBufferEmpty(RTL8139State *s) |
1200 | a41b2ff2 | pbrook | { |
1201 | a41b2ff2 | pbrook | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
1202 | a41b2ff2 | pbrook | |
1203 | a41b2ff2 | pbrook | if (unread != 0) |
1204 | a41b2ff2 | pbrook | { |
1205 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1206 | a41b2ff2 | pbrook | printf("RTL8139: receiver buffer data available 0x%04x\n", unread);
|
1207 | a41b2ff2 | pbrook | #endif
|
1208 | a41b2ff2 | pbrook | return 0; |
1209 | a41b2ff2 | pbrook | } |
1210 | a41b2ff2 | pbrook | |
1211 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1212 | a41b2ff2 | pbrook | printf("RTL8139: receiver buffer is empty\n");
|
1213 | a41b2ff2 | pbrook | #endif
|
1214 | a41b2ff2 | pbrook | |
1215 | a41b2ff2 | pbrook | return 1; |
1216 | a41b2ff2 | pbrook | } |
1217 | a41b2ff2 | pbrook | |
1218 | a41b2ff2 | pbrook | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
1219 | a41b2ff2 | pbrook | { |
1220 | a41b2ff2 | pbrook | uint32_t ret = s->bChipCmdState; |
1221 | a41b2ff2 | pbrook | |
1222 | a41b2ff2 | pbrook | if (rtl8139_RxBufferEmpty(s))
|
1223 | a41b2ff2 | pbrook | ret |= RxBufEmpty; |
1224 | a41b2ff2 | pbrook | |
1225 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1226 | a41b2ff2 | pbrook | printf("RTL8139: ChipCmd read val=0x%04x\n", ret);
|
1227 | a41b2ff2 | pbrook | #endif
|
1228 | a41b2ff2 | pbrook | |
1229 | a41b2ff2 | pbrook | return ret;
|
1230 | a41b2ff2 | pbrook | } |
1231 | a41b2ff2 | pbrook | |
1232 | a41b2ff2 | pbrook | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
1233 | a41b2ff2 | pbrook | { |
1234 | a41b2ff2 | pbrook | val &= 0xffff;
|
1235 | a41b2ff2 | pbrook | |
1236 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1237 | a41b2ff2 | pbrook | printf("RTL8139C+ command register write(w) val=0x%04x\n", val);
|
1238 | a41b2ff2 | pbrook | #endif
|
1239 | a41b2ff2 | pbrook | |
1240 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1241 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff84, s->CpCmd);
|
1242 | a41b2ff2 | pbrook | |
1243 | a41b2ff2 | pbrook | s->CpCmd = val; |
1244 | a41b2ff2 | pbrook | } |
1245 | a41b2ff2 | pbrook | |
1246 | a41b2ff2 | pbrook | static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
1247 | a41b2ff2 | pbrook | { |
1248 | a41b2ff2 | pbrook | uint32_t ret = s->CpCmd; |
1249 | a41b2ff2 | pbrook | |
1250 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1251 | a41b2ff2 | pbrook | printf("RTL8139C+ command register read(w) val=0x%04x\n", ret);
|
1252 | a41b2ff2 | pbrook | #endif
|
1253 | a41b2ff2 | pbrook | |
1254 | a41b2ff2 | pbrook | return ret;
|
1255 | a41b2ff2 | pbrook | } |
1256 | a41b2ff2 | pbrook | |
1257 | a41b2ff2 | pbrook | int rtl8139_config_writeable(RTL8139State *s)
|
1258 | a41b2ff2 | pbrook | { |
1259 | a41b2ff2 | pbrook | if (s->Cfg9346 & Cfg9346_Unlock)
|
1260 | a41b2ff2 | pbrook | { |
1261 | a41b2ff2 | pbrook | return 1; |
1262 | a41b2ff2 | pbrook | } |
1263 | a41b2ff2 | pbrook | |
1264 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1265 | a41b2ff2 | pbrook | printf("RTL8139: Configuration registers are write-protected\n");
|
1266 | a41b2ff2 | pbrook | #endif
|
1267 | a41b2ff2 | pbrook | |
1268 | a41b2ff2 | pbrook | return 0; |
1269 | a41b2ff2 | pbrook | } |
1270 | a41b2ff2 | pbrook | |
1271 | a41b2ff2 | pbrook | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
1272 | a41b2ff2 | pbrook | { |
1273 | a41b2ff2 | pbrook | val &= 0xffff;
|
1274 | a41b2ff2 | pbrook | |
1275 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1276 | a41b2ff2 | pbrook | printf("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val);
|
1277 | a41b2ff2 | pbrook | #endif
|
1278 | a41b2ff2 | pbrook | |
1279 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1280 | a41b2ff2 | pbrook | uint32 mask = 0x4cff;
|
1281 | a41b2ff2 | pbrook | |
1282 | a41b2ff2 | pbrook | if (1 || !rtl8139_config_writeable(s)) |
1283 | a41b2ff2 | pbrook | { |
1284 | a41b2ff2 | pbrook | /* Speed setting and autonegotiation enable bits are read-only */
|
1285 | a41b2ff2 | pbrook | mask |= 0x3000;
|
1286 | a41b2ff2 | pbrook | /* Duplex mode setting is read-only */
|
1287 | a41b2ff2 | pbrook | mask |= 0x0100;
|
1288 | a41b2ff2 | pbrook | } |
1289 | a41b2ff2 | pbrook | |
1290 | a41b2ff2 | pbrook | val = SET_MASKED(val, mask, s->BasicModeCtrl); |
1291 | a41b2ff2 | pbrook | |
1292 | a41b2ff2 | pbrook | s->BasicModeCtrl = val; |
1293 | a41b2ff2 | pbrook | } |
1294 | a41b2ff2 | pbrook | |
1295 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
1296 | a41b2ff2 | pbrook | { |
1297 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeCtrl; |
1298 | a41b2ff2 | pbrook | |
1299 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1300 | a41b2ff2 | pbrook | printf("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret);
|
1301 | a41b2ff2 | pbrook | #endif
|
1302 | a41b2ff2 | pbrook | |
1303 | a41b2ff2 | pbrook | return ret;
|
1304 | a41b2ff2 | pbrook | } |
1305 | a41b2ff2 | pbrook | |
1306 | a41b2ff2 | pbrook | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
1307 | a41b2ff2 | pbrook | { |
1308 | a41b2ff2 | pbrook | val &= 0xffff;
|
1309 | a41b2ff2 | pbrook | |
1310 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1311 | a41b2ff2 | pbrook | printf("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val);
|
1312 | a41b2ff2 | pbrook | #endif
|
1313 | a41b2ff2 | pbrook | |
1314 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1315 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
1316 | a41b2ff2 | pbrook | |
1317 | a41b2ff2 | pbrook | s->BasicModeStatus = val; |
1318 | a41b2ff2 | pbrook | } |
1319 | a41b2ff2 | pbrook | |
1320 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
1321 | a41b2ff2 | pbrook | { |
1322 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeStatus; |
1323 | a41b2ff2 | pbrook | |
1324 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1325 | a41b2ff2 | pbrook | printf("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret);
|
1326 | a41b2ff2 | pbrook | #endif
|
1327 | a41b2ff2 | pbrook | |
1328 | a41b2ff2 | pbrook | return ret;
|
1329 | a41b2ff2 | pbrook | } |
1330 | a41b2ff2 | pbrook | |
1331 | a41b2ff2 | pbrook | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
1332 | a41b2ff2 | pbrook | { |
1333 | a41b2ff2 | pbrook | val &= 0xff;
|
1334 | a41b2ff2 | pbrook | |
1335 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1336 | a41b2ff2 | pbrook | printf("RTL8139: Cfg9346 write val=0x%02x\n", val);
|
1337 | a41b2ff2 | pbrook | #endif
|
1338 | a41b2ff2 | pbrook | |
1339 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1340 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x31, s->Cfg9346);
|
1341 | a41b2ff2 | pbrook | |
1342 | a41b2ff2 | pbrook | uint32_t opmode = val & 0xc0;
|
1343 | a41b2ff2 | pbrook | uint32_t eeprom_val = val & 0xf;
|
1344 | a41b2ff2 | pbrook | |
1345 | a41b2ff2 | pbrook | if (opmode == 0x80) { |
1346 | a41b2ff2 | pbrook | /* eeprom access */
|
1347 | a41b2ff2 | pbrook | int eecs = (eeprom_val & 0x08)?1:0; |
1348 | a41b2ff2 | pbrook | int eesk = (eeprom_val & 0x04)?1:0; |
1349 | a41b2ff2 | pbrook | int eedi = (eeprom_val & 0x02)?1:0; |
1350 | a41b2ff2 | pbrook | prom9346_set_wire(s, eecs, eesk, eedi); |
1351 | a41b2ff2 | pbrook | } else if (opmode == 0x40) { |
1352 | a41b2ff2 | pbrook | /* Reset. */
|
1353 | a41b2ff2 | pbrook | val = 0;
|
1354 | a41b2ff2 | pbrook | rtl8139_reset(s); |
1355 | a41b2ff2 | pbrook | } |
1356 | a41b2ff2 | pbrook | |
1357 | a41b2ff2 | pbrook | s->Cfg9346 = val; |
1358 | a41b2ff2 | pbrook | } |
1359 | a41b2ff2 | pbrook | |
1360 | a41b2ff2 | pbrook | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
1361 | a41b2ff2 | pbrook | { |
1362 | a41b2ff2 | pbrook | uint32_t ret = s->Cfg9346; |
1363 | a41b2ff2 | pbrook | |
1364 | a41b2ff2 | pbrook | uint32_t opmode = ret & 0xc0;
|
1365 | a41b2ff2 | pbrook | |
1366 | a41b2ff2 | pbrook | if (opmode == 0x80) |
1367 | a41b2ff2 | pbrook | { |
1368 | a41b2ff2 | pbrook | /* eeprom access */
|
1369 | a41b2ff2 | pbrook | int eedo = prom9346_get_wire(s);
|
1370 | a41b2ff2 | pbrook | if (eedo)
|
1371 | a41b2ff2 | pbrook | { |
1372 | a41b2ff2 | pbrook | ret |= 0x01;
|
1373 | a41b2ff2 | pbrook | } |
1374 | a41b2ff2 | pbrook | else
|
1375 | a41b2ff2 | pbrook | { |
1376 | a41b2ff2 | pbrook | ret &= ~0x01;
|
1377 | a41b2ff2 | pbrook | } |
1378 | a41b2ff2 | pbrook | } |
1379 | a41b2ff2 | pbrook | |
1380 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1381 | a41b2ff2 | pbrook | printf("RTL8139: Cfg9346 read val=0x%02x\n", ret);
|
1382 | a41b2ff2 | pbrook | #endif
|
1383 | a41b2ff2 | pbrook | |
1384 | a41b2ff2 | pbrook | return ret;
|
1385 | a41b2ff2 | pbrook | } |
1386 | a41b2ff2 | pbrook | |
1387 | a41b2ff2 | pbrook | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
1388 | a41b2ff2 | pbrook | { |
1389 | a41b2ff2 | pbrook | val &= 0xff;
|
1390 | a41b2ff2 | pbrook | |
1391 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1392 | a41b2ff2 | pbrook | printf("RTL8139: Config0 write val=0x%02x\n", val);
|
1393 | a41b2ff2 | pbrook | #endif
|
1394 | a41b2ff2 | pbrook | |
1395 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1396 | a41b2ff2 | pbrook | return;
|
1397 | a41b2ff2 | pbrook | |
1398 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1399 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf8, s->Config0);
|
1400 | a41b2ff2 | pbrook | |
1401 | a41b2ff2 | pbrook | s->Config0 = val; |
1402 | a41b2ff2 | pbrook | } |
1403 | a41b2ff2 | pbrook | |
1404 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
1405 | a41b2ff2 | pbrook | { |
1406 | a41b2ff2 | pbrook | uint32_t ret = s->Config0; |
1407 | a41b2ff2 | pbrook | |
1408 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1409 | a41b2ff2 | pbrook | printf("RTL8139: Config0 read val=0x%02x\n", ret);
|
1410 | a41b2ff2 | pbrook | #endif
|
1411 | a41b2ff2 | pbrook | |
1412 | a41b2ff2 | pbrook | return ret;
|
1413 | a41b2ff2 | pbrook | } |
1414 | a41b2ff2 | pbrook | |
1415 | a41b2ff2 | pbrook | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
1416 | a41b2ff2 | pbrook | { |
1417 | a41b2ff2 | pbrook | val &= 0xff;
|
1418 | a41b2ff2 | pbrook | |
1419 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1420 | a41b2ff2 | pbrook | printf("RTL8139: Config1 write val=0x%02x\n", val);
|
1421 | a41b2ff2 | pbrook | #endif
|
1422 | a41b2ff2 | pbrook | |
1423 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1424 | a41b2ff2 | pbrook | return;
|
1425 | a41b2ff2 | pbrook | |
1426 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1427 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xC, s->Config1);
|
1428 | a41b2ff2 | pbrook | |
1429 | a41b2ff2 | pbrook | s->Config1 = val; |
1430 | a41b2ff2 | pbrook | } |
1431 | a41b2ff2 | pbrook | |
1432 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
1433 | a41b2ff2 | pbrook | { |
1434 | a41b2ff2 | pbrook | uint32_t ret = s->Config1; |
1435 | a41b2ff2 | pbrook | |
1436 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1437 | a41b2ff2 | pbrook | printf("RTL8139: Config1 read val=0x%02x\n", ret);
|
1438 | a41b2ff2 | pbrook | #endif
|
1439 | a41b2ff2 | pbrook | |
1440 | a41b2ff2 | pbrook | return ret;
|
1441 | a41b2ff2 | pbrook | } |
1442 | a41b2ff2 | pbrook | |
1443 | a41b2ff2 | pbrook | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
1444 | a41b2ff2 | pbrook | { |
1445 | a41b2ff2 | pbrook | val &= 0xff;
|
1446 | a41b2ff2 | pbrook | |
1447 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1448 | a41b2ff2 | pbrook | printf("RTL8139: Config3 write val=0x%02x\n", val);
|
1449 | a41b2ff2 | pbrook | #endif
|
1450 | a41b2ff2 | pbrook | |
1451 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1452 | a41b2ff2 | pbrook | return;
|
1453 | a41b2ff2 | pbrook | |
1454 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1455 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x8F, s->Config3);
|
1456 | a41b2ff2 | pbrook | |
1457 | a41b2ff2 | pbrook | s->Config3 = val; |
1458 | a41b2ff2 | pbrook | } |
1459 | a41b2ff2 | pbrook | |
1460 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
1461 | a41b2ff2 | pbrook | { |
1462 | a41b2ff2 | pbrook | uint32_t ret = s->Config3; |
1463 | a41b2ff2 | pbrook | |
1464 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1465 | a41b2ff2 | pbrook | printf("RTL8139: Config3 read val=0x%02x\n", ret);
|
1466 | a41b2ff2 | pbrook | #endif
|
1467 | a41b2ff2 | pbrook | |
1468 | a41b2ff2 | pbrook | return ret;
|
1469 | a41b2ff2 | pbrook | } |
1470 | a41b2ff2 | pbrook | |
1471 | a41b2ff2 | pbrook | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
1472 | a41b2ff2 | pbrook | { |
1473 | a41b2ff2 | pbrook | val &= 0xff;
|
1474 | a41b2ff2 | pbrook | |
1475 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1476 | a41b2ff2 | pbrook | printf("RTL8139: Config4 write val=0x%02x\n", val);
|
1477 | a41b2ff2 | pbrook | #endif
|
1478 | a41b2ff2 | pbrook | |
1479 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1480 | a41b2ff2 | pbrook | return;
|
1481 | a41b2ff2 | pbrook | |
1482 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1483 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x0a, s->Config4);
|
1484 | a41b2ff2 | pbrook | |
1485 | a41b2ff2 | pbrook | s->Config4 = val; |
1486 | a41b2ff2 | pbrook | } |
1487 | a41b2ff2 | pbrook | |
1488 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
1489 | a41b2ff2 | pbrook | { |
1490 | a41b2ff2 | pbrook | uint32_t ret = s->Config4; |
1491 | a41b2ff2 | pbrook | |
1492 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1493 | a41b2ff2 | pbrook | printf("RTL8139: Config4 read val=0x%02x\n", ret);
|
1494 | a41b2ff2 | pbrook | #endif
|
1495 | a41b2ff2 | pbrook | |
1496 | a41b2ff2 | pbrook | return ret;
|
1497 | a41b2ff2 | pbrook | } |
1498 | a41b2ff2 | pbrook | |
1499 | a41b2ff2 | pbrook | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
1500 | a41b2ff2 | pbrook | { |
1501 | a41b2ff2 | pbrook | val &= 0xff;
|
1502 | a41b2ff2 | pbrook | |
1503 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1504 | a41b2ff2 | pbrook | printf("RTL8139: Config5 write val=0x%02x\n", val);
|
1505 | a41b2ff2 | pbrook | #endif
|
1506 | a41b2ff2 | pbrook | |
1507 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1508 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x80, s->Config5);
|
1509 | a41b2ff2 | pbrook | |
1510 | a41b2ff2 | pbrook | s->Config5 = val; |
1511 | a41b2ff2 | pbrook | } |
1512 | a41b2ff2 | pbrook | |
1513 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
1514 | a41b2ff2 | pbrook | { |
1515 | a41b2ff2 | pbrook | uint32_t ret = s->Config5; |
1516 | a41b2ff2 | pbrook | |
1517 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1518 | a41b2ff2 | pbrook | printf("RTL8139: Config5 read val=0x%02x\n", ret);
|
1519 | a41b2ff2 | pbrook | #endif
|
1520 | a41b2ff2 | pbrook | |
1521 | a41b2ff2 | pbrook | return ret;
|
1522 | a41b2ff2 | pbrook | } |
1523 | a41b2ff2 | pbrook | |
1524 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
1525 | a41b2ff2 | pbrook | { |
1526 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1527 | a41b2ff2 | pbrook | { |
1528 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1529 | a41b2ff2 | pbrook | printf("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val);
|
1530 | a41b2ff2 | pbrook | #endif
|
1531 | a41b2ff2 | pbrook | return;
|
1532 | a41b2ff2 | pbrook | } |
1533 | a41b2ff2 | pbrook | |
1534 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1535 | a41b2ff2 | pbrook | printf("RTL8139: TxConfig write val=0x%08x\n", val);
|
1536 | a41b2ff2 | pbrook | #endif
|
1537 | a41b2ff2 | pbrook | |
1538 | a41b2ff2 | pbrook | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
1539 | a41b2ff2 | pbrook | |
1540 | a41b2ff2 | pbrook | s->TxConfig = val; |
1541 | a41b2ff2 | pbrook | } |
1542 | a41b2ff2 | pbrook | |
1543 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
1544 | a41b2ff2 | pbrook | { |
1545 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1546 | a41b2ff2 | pbrook | printf("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
|
1547 | a41b2ff2 | pbrook | #endif
|
1548 | a41b2ff2 | pbrook | uint32_t tc = s->TxConfig; |
1549 | a41b2ff2 | pbrook | tc &= 0xFFFFFF00;
|
1550 | a41b2ff2 | pbrook | tc |= (val & 0x000000FF);
|
1551 | a41b2ff2 | pbrook | rtl8139_TxConfig_write(s, tc); |
1552 | a41b2ff2 | pbrook | } |
1553 | a41b2ff2 | pbrook | |
1554 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
1555 | a41b2ff2 | pbrook | { |
1556 | a41b2ff2 | pbrook | uint32_t ret = s->TxConfig; |
1557 | a41b2ff2 | pbrook | |
1558 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1559 | a41b2ff2 | pbrook | printf("RTL8139: TxConfig read val=0x%04x\n", ret);
|
1560 | a41b2ff2 | pbrook | #endif
|
1561 | a41b2ff2 | pbrook | |
1562 | a41b2ff2 | pbrook | return ret;
|
1563 | a41b2ff2 | pbrook | } |
1564 | a41b2ff2 | pbrook | |
1565 | a41b2ff2 | pbrook | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
1566 | a41b2ff2 | pbrook | { |
1567 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1568 | a41b2ff2 | pbrook | printf("RTL8139: RxConfig write val=0x%08x\n", val);
|
1569 | a41b2ff2 | pbrook | #endif
|
1570 | a41b2ff2 | pbrook | |
1571 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1572 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
1573 | a41b2ff2 | pbrook | |
1574 | a41b2ff2 | pbrook | s->RxConfig = val; |
1575 | a41b2ff2 | pbrook | |
1576 | a41b2ff2 | pbrook | /* reset buffer size and read/write pointers */
|
1577 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
1578 | a41b2ff2 | pbrook | |
1579 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1580 | a41b2ff2 | pbrook | printf("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize);
|
1581 | a41b2ff2 | pbrook | #endif
|
1582 | a41b2ff2 | pbrook | } |
1583 | a41b2ff2 | pbrook | |
1584 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
1585 | a41b2ff2 | pbrook | { |
1586 | a41b2ff2 | pbrook | uint32_t ret = s->RxConfig; |
1587 | a41b2ff2 | pbrook | |
1588 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1589 | a41b2ff2 | pbrook | printf("RTL8139: RxConfig read val=0x%08x\n", ret);
|
1590 | a41b2ff2 | pbrook | #endif
|
1591 | a41b2ff2 | pbrook | |
1592 | a41b2ff2 | pbrook | return ret;
|
1593 | a41b2ff2 | pbrook | } |
1594 | a41b2ff2 | pbrook | |
1595 | a41b2ff2 | pbrook | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
1596 | a41b2ff2 | pbrook | { |
1597 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1598 | a41b2ff2 | pbrook | { |
1599 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1600 | a41b2ff2 | pbrook | printf("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n", descriptor);
|
1601 | a41b2ff2 | pbrook | #endif
|
1602 | a41b2ff2 | pbrook | return 0; |
1603 | a41b2ff2 | pbrook | } |
1604 | a41b2ff2 | pbrook | |
1605 | a41b2ff2 | pbrook | if (s->TxStatus[descriptor] & TxHostOwns)
|
1606 | a41b2ff2 | pbrook | { |
1607 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1608 | a41b2ff2 | pbrook | printf("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n", descriptor, s->TxStatus[descriptor]);
|
1609 | a41b2ff2 | pbrook | #endif
|
1610 | a41b2ff2 | pbrook | return 0; |
1611 | a41b2ff2 | pbrook | } |
1612 | a41b2ff2 | pbrook | |
1613 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1614 | a41b2ff2 | pbrook | printf("RTL8139: +++ transmitting from descriptor %d\n", descriptor);
|
1615 | a41b2ff2 | pbrook | #endif
|
1616 | a41b2ff2 | pbrook | |
1617 | a41b2ff2 | pbrook | int txsize = s->TxStatus[descriptor] & 0x1fff; |
1618 | a41b2ff2 | pbrook | uint8_t txbuffer[0x2000];
|
1619 | a41b2ff2 | pbrook | |
1620 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1621 | a41b2ff2 | pbrook | printf("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n", txsize, s->TxAddr[descriptor]);
|
1622 | a41b2ff2 | pbrook | #endif
|
1623 | a41b2ff2 | pbrook | cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); |
1624 | a41b2ff2 | pbrook | |
1625 | a41b2ff2 | pbrook | qemu_send_packet(s->vc, txbuffer, txsize); |
1626 | a41b2ff2 | pbrook | |
1627 | a41b2ff2 | pbrook | /* Mark descriptor as transferred */
|
1628 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxHostOwns; |
1629 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxStatOK; |
1630 | a41b2ff2 | pbrook | |
1631 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1632 | a41b2ff2 | pbrook | printf("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor);
|
1633 | a41b2ff2 | pbrook | #endif
|
1634 | a41b2ff2 | pbrook | |
1635 | a41b2ff2 | pbrook | /* update interrupt */
|
1636 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
1637 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1638 | a41b2ff2 | pbrook | |
1639 | a41b2ff2 | pbrook | return 1; |
1640 | a41b2ff2 | pbrook | } |
1641 | a41b2ff2 | pbrook | |
1642 | a41b2ff2 | pbrook | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
1643 | a41b2ff2 | pbrook | { |
1644 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1645 | a41b2ff2 | pbrook | { |
1646 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1647 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode: transmitter disabled\n");
|
1648 | a41b2ff2 | pbrook | #endif
|
1649 | a41b2ff2 | pbrook | return 0; |
1650 | a41b2ff2 | pbrook | } |
1651 | a41b2ff2 | pbrook | |
1652 | a41b2ff2 | pbrook | if (!rtl8139_cp_transmitter_enabled(s))
|
1653 | a41b2ff2 | pbrook | { |
1654 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1655 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode: C+ transmitter disabled\n");
|
1656 | a41b2ff2 | pbrook | #endif
|
1657 | a41b2ff2 | pbrook | return 0 ; |
1658 | a41b2ff2 | pbrook | } |
1659 | a41b2ff2 | pbrook | |
1660 | a41b2ff2 | pbrook | int descriptor = s->currCPlusTxDesc;
|
1661 | a41b2ff2 | pbrook | |
1662 | a41b2ff2 | pbrook | target_phys_addr_t cplus_tx_ring_desc = |
1663 | a41b2ff2 | pbrook | rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
1664 | a41b2ff2 | pbrook | |
1665 | a41b2ff2 | pbrook | /* Normal priority ring */
|
1666 | a41b2ff2 | pbrook | cplus_tx_ring_desc += 16 * descriptor;
|
1667 | a41b2ff2 | pbrook | |
1668 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1669 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
|
1670 | a41b2ff2 | pbrook | descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc); |
1671 | a41b2ff2 | pbrook | #endif
|
1672 | a41b2ff2 | pbrook | |
1673 | a41b2ff2 | pbrook | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
1674 | a41b2ff2 | pbrook | |
1675 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
1676 | a41b2ff2 | pbrook | txdw0 = le32_to_cpu(val); |
1677 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
1678 | a41b2ff2 | pbrook | txdw1 = le32_to_cpu(val); |
1679 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
1680 | a41b2ff2 | pbrook | txbufLO = le32_to_cpu(val); |
1681 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
1682 | a41b2ff2 | pbrook | txbufHI = le32_to_cpu(val); |
1683 | a41b2ff2 | pbrook | |
1684 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1685 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
|
1686 | a41b2ff2 | pbrook | descriptor, |
1687 | a41b2ff2 | pbrook | txdw0, txdw1, txbufLO, txbufHI); |
1688 | a41b2ff2 | pbrook | #endif
|
1689 | a41b2ff2 | pbrook | |
1690 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
1691 | a41b2ff2 | pbrook | #define CP_TX_OWN (1<<31) |
1692 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
1693 | a41b2ff2 | pbrook | #define CP_TX_EOR (1<<30) |
1694 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1695 | a41b2ff2 | pbrook | #define CP_TX_FS (1<<29) |
1696 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1697 | a41b2ff2 | pbrook | #define CP_TX_LS (1<<28) |
1698 | a41b2ff2 | pbrook | /* large send packet flag */
|
1699 | a41b2ff2 | pbrook | #define CP_TX_LGSEN (1<<27) |
1700 | a41b2ff2 | pbrook | /* IP checksum offload flag */
|
1701 | a41b2ff2 | pbrook | #define CP_TX_IPCS (1<<18) |
1702 | a41b2ff2 | pbrook | /* UDP checksum offload flag */
|
1703 | a41b2ff2 | pbrook | #define CP_TX_UDPCS (1<<17) |
1704 | a41b2ff2 | pbrook | /* TCP checksum offload flag */
|
1705 | a41b2ff2 | pbrook | #define CP_TX_TCPCS (1<<16) |
1706 | a41b2ff2 | pbrook | |
1707 | a41b2ff2 | pbrook | /* w0 bits 0...15 : buffer size */
|
1708 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE (1<<16) |
1709 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
1710 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
1711 | a41b2ff2 | pbrook | #define CP_RX_TAGC (1<<17) |
1712 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
1713 | a41b2ff2 | pbrook | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
1714 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
1715 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
1716 | a41b2ff2 | pbrook | |
1717 | a41b2ff2 | pbrook | /* set after transmission */
|
1718 | a41b2ff2 | pbrook | /* FIFO underrun flag */
|
1719 | a41b2ff2 | pbrook | #define CP_TX_STATUS_UNF (1<<25) |
1720 | a41b2ff2 | pbrook | /* transmit error summary flag, valid if set any of three below */
|
1721 | a41b2ff2 | pbrook | #define CP_TX_STATUS_TES (1<<23) |
1722 | a41b2ff2 | pbrook | /* out-of-window collision flag */
|
1723 | a41b2ff2 | pbrook | #define CP_TX_STATUS_OWC (1<<22) |
1724 | a41b2ff2 | pbrook | /* link failure flag */
|
1725 | a41b2ff2 | pbrook | #define CP_TX_STATUS_LNKF (1<<21) |
1726 | a41b2ff2 | pbrook | /* excessive collisions flag */
|
1727 | a41b2ff2 | pbrook | #define CP_TX_STATUS_EXC (1<<20) |
1728 | a41b2ff2 | pbrook | |
1729 | a41b2ff2 | pbrook | if (!(txdw0 & CP_TX_OWN))
|
1730 | a41b2ff2 | pbrook | { |
1731 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1732 | a41b2ff2 | pbrook | printf("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor);
|
1733 | a41b2ff2 | pbrook | #endif
|
1734 | a41b2ff2 | pbrook | return 0 ; |
1735 | a41b2ff2 | pbrook | } |
1736 | a41b2ff2 | pbrook | |
1737 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1738 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
|
1739 | a41b2ff2 | pbrook | #endif
|
1740 | a41b2ff2 | pbrook | |
1741 | a41b2ff2 | pbrook | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
1742 | a41b2ff2 | pbrook | target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
1743 | a41b2ff2 | pbrook | |
1744 | a41b2ff2 | pbrook | uint8_t txbuffer[CP_TX_BUFFER_SIZE]; |
1745 | a41b2ff2 | pbrook | |
1746 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1747 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at 0x%08x\n", txsize, tx_addr);
|
1748 | a41b2ff2 | pbrook | #endif
|
1749 | a41b2ff2 | pbrook | cpu_physical_memory_read(tx_addr, txbuffer, txsize); |
1750 | a41b2ff2 | pbrook | |
1751 | a41b2ff2 | pbrook | /* transmit the packet */
|
1752 | a41b2ff2 | pbrook | qemu_send_packet(s->vc, txbuffer, txsize); |
1753 | a41b2ff2 | pbrook | |
1754 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
1755 | a41b2ff2 | pbrook | txdw0 &= ~CP_RX_OWN; |
1756 | a41b2ff2 | pbrook | |
1757 | a41b2ff2 | pbrook | /* reset error indicator bits */
|
1758 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_UNF; |
1759 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_TES; |
1760 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_OWC; |
1761 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_LNKF; |
1762 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_EXC; |
1763 | a41b2ff2 | pbrook | |
1764 | a41b2ff2 | pbrook | /* update ring data */
|
1765 | a41b2ff2 | pbrook | val = cpu_to_le32(txdw0); |
1766 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
1767 | a41b2ff2 | pbrook | // val = cpu_to_le32(txdw1);
|
1768 | a41b2ff2 | pbrook | // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
|
1769 | a41b2ff2 | pbrook | |
1770 | a41b2ff2 | pbrook | /* seek to next Rx descriptor */
|
1771 | a41b2ff2 | pbrook | if (txdw0 & CP_TX_EOR)
|
1772 | a41b2ff2 | pbrook | { |
1773 | a41b2ff2 | pbrook | s->currCPlusTxDesc = 0;
|
1774 | a41b2ff2 | pbrook | } |
1775 | a41b2ff2 | pbrook | else
|
1776 | a41b2ff2 | pbrook | { |
1777 | a41b2ff2 | pbrook | ++s->currCPlusTxDesc; |
1778 | a41b2ff2 | pbrook | } |
1779 | a41b2ff2 | pbrook | |
1780 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1781 | a41b2ff2 | pbrook | printf("RTL8139: +++ C+ mode transmitted %d bytes from descriptor %d\n", txsize, descriptor);
|
1782 | a41b2ff2 | pbrook | #endif
|
1783 | a41b2ff2 | pbrook | return 1; |
1784 | a41b2ff2 | pbrook | } |
1785 | a41b2ff2 | pbrook | |
1786 | a41b2ff2 | pbrook | static void rtl8139_cplus_transmit(RTL8139State *s) |
1787 | a41b2ff2 | pbrook | { |
1788 | a41b2ff2 | pbrook | int txcount = 0; |
1789 | a41b2ff2 | pbrook | |
1790 | a41b2ff2 | pbrook | while (rtl8139_cplus_transmit_one(s))
|
1791 | a41b2ff2 | pbrook | { |
1792 | a41b2ff2 | pbrook | ++txcount; |
1793 | a41b2ff2 | pbrook | } |
1794 | a41b2ff2 | pbrook | |
1795 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
1796 | a41b2ff2 | pbrook | if (!txcount)
|
1797 | a41b2ff2 | pbrook | { |
1798 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1799 | a41b2ff2 | pbrook | printf("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n", s->currCPlusTxDesc);
|
1800 | a41b2ff2 | pbrook | #endif
|
1801 | a41b2ff2 | pbrook | } |
1802 | a41b2ff2 | pbrook | else
|
1803 | a41b2ff2 | pbrook | { |
1804 | a41b2ff2 | pbrook | /* update interrupt status */
|
1805 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
1806 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1807 | a41b2ff2 | pbrook | } |
1808 | a41b2ff2 | pbrook | } |
1809 | a41b2ff2 | pbrook | |
1810 | a41b2ff2 | pbrook | static void rtl8139_transmit(RTL8139State *s) |
1811 | a41b2ff2 | pbrook | { |
1812 | a41b2ff2 | pbrook | int descriptor = s->currTxDesc, txcount = 0; |
1813 | a41b2ff2 | pbrook | |
1814 | a41b2ff2 | pbrook | /*while*/
|
1815 | a41b2ff2 | pbrook | if (rtl8139_transmit_one(s, descriptor))
|
1816 | a41b2ff2 | pbrook | { |
1817 | a41b2ff2 | pbrook | ++s->currTxDesc; |
1818 | a41b2ff2 | pbrook | s->currTxDesc %= 4;
|
1819 | a41b2ff2 | pbrook | ++txcount; |
1820 | a41b2ff2 | pbrook | } |
1821 | a41b2ff2 | pbrook | |
1822 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
1823 | a41b2ff2 | pbrook | if (!txcount)
|
1824 | a41b2ff2 | pbrook | { |
1825 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1826 | a41b2ff2 | pbrook | printf("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc);
|
1827 | a41b2ff2 | pbrook | #endif
|
1828 | a41b2ff2 | pbrook | } |
1829 | a41b2ff2 | pbrook | } |
1830 | a41b2ff2 | pbrook | |
1831 | a41b2ff2 | pbrook | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
1832 | a41b2ff2 | pbrook | { |
1833 | a41b2ff2 | pbrook | |
1834 | a41b2ff2 | pbrook | int descriptor = txRegOffset/4; |
1835 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1836 | a41b2ff2 | pbrook | printf("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor);
|
1837 | a41b2ff2 | pbrook | #endif
|
1838 | a41b2ff2 | pbrook | |
1839 | a41b2ff2 | pbrook | /* mask only reserved bits */
|
1840 | a41b2ff2 | pbrook | val &= ~0xff00c000; /* these bits are reset on write */ |
1841 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
1842 | a41b2ff2 | pbrook | |
1843 | a41b2ff2 | pbrook | s->TxStatus[descriptor] = val; |
1844 | a41b2ff2 | pbrook | |
1845 | a41b2ff2 | pbrook | /* attempt to start transmission */
|
1846 | a41b2ff2 | pbrook | rtl8139_transmit(s); |
1847 | a41b2ff2 | pbrook | } |
1848 | a41b2ff2 | pbrook | |
1849 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
1850 | a41b2ff2 | pbrook | { |
1851 | a41b2ff2 | pbrook | uint32_t ret = s->TxStatus[txRegOffset/4];
|
1852 | a41b2ff2 | pbrook | |
1853 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1854 | a41b2ff2 | pbrook | printf("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
|
1855 | a41b2ff2 | pbrook | #endif
|
1856 | a41b2ff2 | pbrook | |
1857 | a41b2ff2 | pbrook | return ret;
|
1858 | a41b2ff2 | pbrook | } |
1859 | a41b2ff2 | pbrook | |
1860 | a41b2ff2 | pbrook | static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
1861 | a41b2ff2 | pbrook | { |
1862 | a41b2ff2 | pbrook | uint16_t ret = 0;
|
1863 | a41b2ff2 | pbrook | |
1864 | a41b2ff2 | pbrook | /* Simulate TSAD, it is read only anyway */
|
1865 | a41b2ff2 | pbrook | |
1866 | a41b2ff2 | pbrook | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
1867 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
1868 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
1869 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
1870 | a41b2ff2 | pbrook | |
1871 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
1872 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
1873 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
1874 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
1875 | a41b2ff2 | pbrook | |
1876 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
1877 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
1878 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
1879 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
1880 | a41b2ff2 | pbrook | |
1881 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
1882 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
1883 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
1884 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
1885 | a41b2ff2 | pbrook | |
1886 | a41b2ff2 | pbrook | |
1887 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1888 | a41b2ff2 | pbrook | printf("RTL8139: TSAD read val=0x%04x\n", ret);
|
1889 | a41b2ff2 | pbrook | #endif
|
1890 | a41b2ff2 | pbrook | |
1891 | a41b2ff2 | pbrook | return ret;
|
1892 | a41b2ff2 | pbrook | } |
1893 | a41b2ff2 | pbrook | |
1894 | a41b2ff2 | pbrook | static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
1895 | a41b2ff2 | pbrook | { |
1896 | a41b2ff2 | pbrook | uint16_t ret = s->CSCR; |
1897 | a41b2ff2 | pbrook | |
1898 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1899 | a41b2ff2 | pbrook | printf("RTL8139: CSCR read val=0x%04x\n", ret);
|
1900 | a41b2ff2 | pbrook | #endif
|
1901 | a41b2ff2 | pbrook | |
1902 | a41b2ff2 | pbrook | return ret;
|
1903 | a41b2ff2 | pbrook | } |
1904 | a41b2ff2 | pbrook | |
1905 | a41b2ff2 | pbrook | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
1906 | a41b2ff2 | pbrook | { |
1907 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1908 | a41b2ff2 | pbrook | printf("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
|
1909 | a41b2ff2 | pbrook | #endif
|
1910 | a41b2ff2 | pbrook | |
1911 | a41b2ff2 | pbrook | s->TxAddr[txAddrOffset/4] = le32_to_cpu(val);
|
1912 | a41b2ff2 | pbrook | } |
1913 | a41b2ff2 | pbrook | |
1914 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
1915 | a41b2ff2 | pbrook | { |
1916 | a41b2ff2 | pbrook | uint32_t ret = cpu_to_le32(s->TxAddr[txAddrOffset/4]);
|
1917 | a41b2ff2 | pbrook | |
1918 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1919 | a41b2ff2 | pbrook | printf("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
|
1920 | a41b2ff2 | pbrook | #endif
|
1921 | a41b2ff2 | pbrook | |
1922 | a41b2ff2 | pbrook | return ret;
|
1923 | a41b2ff2 | pbrook | } |
1924 | a41b2ff2 | pbrook | |
1925 | a41b2ff2 | pbrook | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
1926 | a41b2ff2 | pbrook | { |
1927 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1928 | a41b2ff2 | pbrook | printf("RTL8139: RxBufPtr write val=0x%04x\n", val);
|
1929 | a41b2ff2 | pbrook | #endif
|
1930 | a41b2ff2 | pbrook | |
1931 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
1932 | a41b2ff2 | pbrook | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
1933 | a41b2ff2 | pbrook | |
1934 | a41b2ff2 | pbrook | #if defined(DEBUG_RTL8139)
|
1935 | a41b2ff2 | pbrook | printf(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
1936 | a41b2ff2 | pbrook | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
1937 | a41b2ff2 | pbrook | #endif
|
1938 | a41b2ff2 | pbrook | } |
1939 | a41b2ff2 | pbrook | |
1940 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
1941 | a41b2ff2 | pbrook | { |
1942 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
1943 | a41b2ff2 | pbrook | uint32_t ret = s->RxBufPtr - 0x10;
|
1944 | a41b2ff2 | pbrook | |
1945 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1946 | a41b2ff2 | pbrook | printf("RTL8139: RxBufPtr read val=0x%04x\n", ret);
|
1947 | a41b2ff2 | pbrook | #endif
|
1948 | a41b2ff2 | pbrook | |
1949 | a41b2ff2 | pbrook | return ret;
|
1950 | a41b2ff2 | pbrook | } |
1951 | a41b2ff2 | pbrook | |
1952 | a41b2ff2 | pbrook | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
1953 | a41b2ff2 | pbrook | { |
1954 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1955 | a41b2ff2 | pbrook | printf("RTL8139: RxBuf write val=0x%08x\n", val);
|
1956 | a41b2ff2 | pbrook | #endif
|
1957 | a41b2ff2 | pbrook | |
1958 | a41b2ff2 | pbrook | s->RxBuf = val; |
1959 | a41b2ff2 | pbrook | |
1960 | a41b2ff2 | pbrook | /* may need to reset rxring here */
|
1961 | a41b2ff2 | pbrook | } |
1962 | a41b2ff2 | pbrook | |
1963 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
1964 | a41b2ff2 | pbrook | { |
1965 | a41b2ff2 | pbrook | uint32_t ret = s->RxBuf; |
1966 | a41b2ff2 | pbrook | |
1967 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1968 | a41b2ff2 | pbrook | printf("RTL8139: RxBuf read val=0x%08x\n", ret);
|
1969 | a41b2ff2 | pbrook | #endif
|
1970 | a41b2ff2 | pbrook | |
1971 | a41b2ff2 | pbrook | return ret;
|
1972 | a41b2ff2 | pbrook | } |
1973 | a41b2ff2 | pbrook | |
1974 | a41b2ff2 | pbrook | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
1975 | a41b2ff2 | pbrook | { |
1976 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1977 | a41b2ff2 | pbrook | printf("RTL8139: IntrMask write(w) val=0x%04x\n", val);
|
1978 | a41b2ff2 | pbrook | #endif
|
1979 | a41b2ff2 | pbrook | |
1980 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1981 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
1982 | a41b2ff2 | pbrook | |
1983 | a41b2ff2 | pbrook | s->IntrMask = val; |
1984 | a41b2ff2 | pbrook | |
1985 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1986 | a41b2ff2 | pbrook | } |
1987 | a41b2ff2 | pbrook | |
1988 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
1989 | a41b2ff2 | pbrook | { |
1990 | a41b2ff2 | pbrook | uint32_t ret = s->IntrMask; |
1991 | a41b2ff2 | pbrook | |
1992 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
1993 | a41b2ff2 | pbrook | printf("RTL8139: IntrMask read(w) val=0x%04x\n", ret);
|
1994 | a41b2ff2 | pbrook | #endif
|
1995 | a41b2ff2 | pbrook | |
1996 | a41b2ff2 | pbrook | return ret;
|
1997 | a41b2ff2 | pbrook | } |
1998 | a41b2ff2 | pbrook | |
1999 | a41b2ff2 | pbrook | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
2000 | a41b2ff2 | pbrook | { |
2001 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2002 | a41b2ff2 | pbrook | printf("RTL8139: IntrStatus write(w) val=0x%04x\n", val);
|
2003 | a41b2ff2 | pbrook | #endif
|
2004 | a41b2ff2 | pbrook | |
2005 | a41b2ff2 | pbrook | #if 0
|
2006 | a41b2ff2 | pbrook | |
2007 | a41b2ff2 | pbrook | /* writing to ISR has no effect */
|
2008 | a41b2ff2 | pbrook | |
2009 | a41b2ff2 | pbrook | return;
|
2010 | a41b2ff2 | pbrook | |
2011 | a41b2ff2 | pbrook | #else
|
2012 | a41b2ff2 | pbrook | uint16_t newStatus = s->IntrStatus & ~val; |
2013 | a41b2ff2 | pbrook | |
2014 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2015 | a41b2ff2 | pbrook | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
2016 | a41b2ff2 | pbrook | |
2017 | a41b2ff2 | pbrook | /* writing 1 to interrupt status register bit clears it */
|
2018 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2019 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2020 | a41b2ff2 | pbrook | |
2021 | a41b2ff2 | pbrook | s->IntrStatus = newStatus; |
2022 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2023 | a41b2ff2 | pbrook | #endif
|
2024 | a41b2ff2 | pbrook | } |
2025 | a41b2ff2 | pbrook | |
2026 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
2027 | a41b2ff2 | pbrook | { |
2028 | a41b2ff2 | pbrook | uint32_t ret = s->IntrStatus; |
2029 | a41b2ff2 | pbrook | |
2030 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2031 | a41b2ff2 | pbrook | printf("RTL8139: IntrStatus read(w) val=0x%04x\n", ret);
|
2032 | a41b2ff2 | pbrook | #endif
|
2033 | a41b2ff2 | pbrook | |
2034 | a41b2ff2 | pbrook | #if 0
|
2035 | a41b2ff2 | pbrook | |
2036 | a41b2ff2 | pbrook | /* reading ISR clears all interrupts */
|
2037 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2038 | a41b2ff2 | pbrook | |
2039 | a41b2ff2 | pbrook | rtl8139_update_irq(s);
|
2040 | a41b2ff2 | pbrook | |
2041 | a41b2ff2 | pbrook | #endif
|
2042 | a41b2ff2 | pbrook | |
2043 | a41b2ff2 | pbrook | return ret;
|
2044 | a41b2ff2 | pbrook | } |
2045 | a41b2ff2 | pbrook | |
2046 | a41b2ff2 | pbrook | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
2047 | a41b2ff2 | pbrook | { |
2048 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2049 | a41b2ff2 | pbrook | printf("RTL8139: MultiIntr write(w) val=0x%04x\n", val);
|
2050 | a41b2ff2 | pbrook | #endif
|
2051 | a41b2ff2 | pbrook | |
2052 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2053 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
2054 | a41b2ff2 | pbrook | |
2055 | a41b2ff2 | pbrook | s->MultiIntr = val; |
2056 | a41b2ff2 | pbrook | } |
2057 | a41b2ff2 | pbrook | |
2058 | a41b2ff2 | pbrook | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
2059 | a41b2ff2 | pbrook | { |
2060 | a41b2ff2 | pbrook | uint32_t ret = s->MultiIntr; |
2061 | a41b2ff2 | pbrook | |
2062 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2063 | a41b2ff2 | pbrook | printf("RTL8139: MultiIntr read(w) val=0x%04x\n", ret);
|
2064 | a41b2ff2 | pbrook | #endif
|
2065 | a41b2ff2 | pbrook | |
2066 | a41b2ff2 | pbrook | return ret;
|
2067 | a41b2ff2 | pbrook | } |
2068 | a41b2ff2 | pbrook | |
2069 | a41b2ff2 | pbrook | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
2070 | a41b2ff2 | pbrook | { |
2071 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2072 | a41b2ff2 | pbrook | |
2073 | a41b2ff2 | pbrook | addr &= 0xff;
|
2074 | a41b2ff2 | pbrook | |
2075 | a41b2ff2 | pbrook | switch (addr)
|
2076 | a41b2ff2 | pbrook | { |
2077 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2078 | a41b2ff2 | pbrook | s->phys[addr - MAC0] = val; |
2079 | a41b2ff2 | pbrook | break;
|
2080 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2081 | a41b2ff2 | pbrook | /* reserved */
|
2082 | a41b2ff2 | pbrook | break;
|
2083 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2084 | a41b2ff2 | pbrook | s->mult[addr - MAR0] = val; |
2085 | a41b2ff2 | pbrook | break;
|
2086 | a41b2ff2 | pbrook | case ChipCmd:
|
2087 | a41b2ff2 | pbrook | rtl8139_ChipCmd_write(s, val); |
2088 | a41b2ff2 | pbrook | break;
|
2089 | a41b2ff2 | pbrook | case Cfg9346:
|
2090 | a41b2ff2 | pbrook | rtl8139_Cfg9346_write(s, val); |
2091 | a41b2ff2 | pbrook | break;
|
2092 | a41b2ff2 | pbrook | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
2093 | a41b2ff2 | pbrook | rtl8139_TxConfig_writeb(s, val); |
2094 | a41b2ff2 | pbrook | break;
|
2095 | a41b2ff2 | pbrook | case Config0:
|
2096 | a41b2ff2 | pbrook | rtl8139_Config0_write(s, val); |
2097 | a41b2ff2 | pbrook | break;
|
2098 | a41b2ff2 | pbrook | case Config1:
|
2099 | a41b2ff2 | pbrook | rtl8139_Config1_write(s, val); |
2100 | a41b2ff2 | pbrook | break;
|
2101 | a41b2ff2 | pbrook | case Config3:
|
2102 | a41b2ff2 | pbrook | rtl8139_Config3_write(s, val); |
2103 | a41b2ff2 | pbrook | break;
|
2104 | a41b2ff2 | pbrook | case Config4:
|
2105 | a41b2ff2 | pbrook | rtl8139_Config4_write(s, val); |
2106 | a41b2ff2 | pbrook | break;
|
2107 | a41b2ff2 | pbrook | case Config5:
|
2108 | a41b2ff2 | pbrook | rtl8139_Config5_write(s, val); |
2109 | a41b2ff2 | pbrook | break;
|
2110 | a41b2ff2 | pbrook | case MediaStatus:
|
2111 | a41b2ff2 | pbrook | /* ignore */
|
2112 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2113 | a41b2ff2 | pbrook | printf("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val);
|
2114 | a41b2ff2 | pbrook | #endif
|
2115 | a41b2ff2 | pbrook | break;
|
2116 | a41b2ff2 | pbrook | |
2117 | a41b2ff2 | pbrook | case HltClk:
|
2118 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2119 | a41b2ff2 | pbrook | printf("RTL8139: HltClk write val=0x%08x\n", val);
|
2120 | a41b2ff2 | pbrook | #endif
|
2121 | a41b2ff2 | pbrook | if (val == 'R') |
2122 | a41b2ff2 | pbrook | { |
2123 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
2124 | a41b2ff2 | pbrook | } |
2125 | a41b2ff2 | pbrook | else if (val == 'H') |
2126 | a41b2ff2 | pbrook | { |
2127 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
2128 | a41b2ff2 | pbrook | } |
2129 | a41b2ff2 | pbrook | break;
|
2130 | a41b2ff2 | pbrook | |
2131 | a41b2ff2 | pbrook | case TxThresh:
|
2132 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2133 | a41b2ff2 | pbrook | printf("RTL8139C+ TxThresh write(b) val=0x%02x\n", val);
|
2134 | a41b2ff2 | pbrook | #endif
|
2135 | a41b2ff2 | pbrook | s->TxThresh = val; |
2136 | a41b2ff2 | pbrook | break;
|
2137 | a41b2ff2 | pbrook | |
2138 | a41b2ff2 | pbrook | case TxPoll:
|
2139 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2140 | a41b2ff2 | pbrook | printf("RTL8139C+ TxPoll write(b) val=0x%02x\n", val);
|
2141 | a41b2ff2 | pbrook | #endif
|
2142 | a41b2ff2 | pbrook | if (val & (1 << 7)) |
2143 | a41b2ff2 | pbrook | { |
2144 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2145 | a41b2ff2 | pbrook | printf("RTL8139C+ TxPoll high priority transmission (not implemented)\n");
|
2146 | a41b2ff2 | pbrook | #endif
|
2147 | a41b2ff2 | pbrook | //rtl8139_cplus_transmit(s);
|
2148 | a41b2ff2 | pbrook | } |
2149 | a41b2ff2 | pbrook | if (val & (1 << 6)) |
2150 | a41b2ff2 | pbrook | { |
2151 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2152 | a41b2ff2 | pbrook | printf("RTL8139C+ TxPoll normal priority transmission\n");
|
2153 | a41b2ff2 | pbrook | #endif
|
2154 | a41b2ff2 | pbrook | rtl8139_cplus_transmit(s); |
2155 | a41b2ff2 | pbrook | } |
2156 | a41b2ff2 | pbrook | |
2157 | a41b2ff2 | pbrook | break;
|
2158 | a41b2ff2 | pbrook | |
2159 | a41b2ff2 | pbrook | default:
|
2160 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2161 | a41b2ff2 | pbrook | printf("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val);
|
2162 | a41b2ff2 | pbrook | #endif
|
2163 | a41b2ff2 | pbrook | break;
|
2164 | a41b2ff2 | pbrook | } |
2165 | a41b2ff2 | pbrook | } |
2166 | a41b2ff2 | pbrook | |
2167 | a41b2ff2 | pbrook | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
2168 | a41b2ff2 | pbrook | { |
2169 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2170 | a41b2ff2 | pbrook | |
2171 | a41b2ff2 | pbrook | addr &= 0xfe;
|
2172 | a41b2ff2 | pbrook | |
2173 | a41b2ff2 | pbrook | switch (addr)
|
2174 | a41b2ff2 | pbrook | { |
2175 | a41b2ff2 | pbrook | case IntrMask:
|
2176 | a41b2ff2 | pbrook | rtl8139_IntrMask_write(s, val); |
2177 | a41b2ff2 | pbrook | break;
|
2178 | a41b2ff2 | pbrook | |
2179 | a41b2ff2 | pbrook | case IntrStatus:
|
2180 | a41b2ff2 | pbrook | rtl8139_IntrStatus_write(s, val); |
2181 | a41b2ff2 | pbrook | break;
|
2182 | a41b2ff2 | pbrook | |
2183 | a41b2ff2 | pbrook | case MultiIntr:
|
2184 | a41b2ff2 | pbrook | rtl8139_MultiIntr_write(s, val); |
2185 | a41b2ff2 | pbrook | break;
|
2186 | a41b2ff2 | pbrook | |
2187 | a41b2ff2 | pbrook | case RxBufPtr:
|
2188 | a41b2ff2 | pbrook | rtl8139_RxBufPtr_write(s, val); |
2189 | a41b2ff2 | pbrook | break;
|
2190 | a41b2ff2 | pbrook | |
2191 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2192 | a41b2ff2 | pbrook | rtl8139_BasicModeCtrl_write(s, val); |
2193 | a41b2ff2 | pbrook | break;
|
2194 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2195 | a41b2ff2 | pbrook | rtl8139_BasicModeStatus_write(s, val); |
2196 | a41b2ff2 | pbrook | break;
|
2197 | a41b2ff2 | pbrook | case NWayAdvert:
|
2198 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2199 | a41b2ff2 | pbrook | printf("RTL8139: NWayAdvert write(w) val=0x%04x\n", val);
|
2200 | a41b2ff2 | pbrook | #endif
|
2201 | a41b2ff2 | pbrook | s->NWayAdvert = val; |
2202 | a41b2ff2 | pbrook | break;
|
2203 | a41b2ff2 | pbrook | case NWayLPAR:
|
2204 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2205 | a41b2ff2 | pbrook | printf("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val);
|
2206 | a41b2ff2 | pbrook | #endif
|
2207 | a41b2ff2 | pbrook | break;
|
2208 | a41b2ff2 | pbrook | case NWayExpansion:
|
2209 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2210 | a41b2ff2 | pbrook | printf("RTL8139: NWayExpansion write(w) val=0x%04x\n", val);
|
2211 | a41b2ff2 | pbrook | #endif
|
2212 | a41b2ff2 | pbrook | s->NWayExpansion = val; |
2213 | a41b2ff2 | pbrook | break;
|
2214 | a41b2ff2 | pbrook | |
2215 | a41b2ff2 | pbrook | case CpCmd:
|
2216 | a41b2ff2 | pbrook | rtl8139_CpCmd_write(s, val); |
2217 | a41b2ff2 | pbrook | break;
|
2218 | a41b2ff2 | pbrook | |
2219 | a41b2ff2 | pbrook | default:
|
2220 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2221 | a41b2ff2 | pbrook | printf("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val);
|
2222 | a41b2ff2 | pbrook | #endif
|
2223 | a41b2ff2 | pbrook | |
2224 | a41b2ff2 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
2225 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff); |
2226 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, val & 0xff); |
2227 | a41b2ff2 | pbrook | #else
|
2228 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2229 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2230 | a41b2ff2 | pbrook | #endif
|
2231 | a41b2ff2 | pbrook | break;
|
2232 | a41b2ff2 | pbrook | } |
2233 | a41b2ff2 | pbrook | } |
2234 | a41b2ff2 | pbrook | |
2235 | a41b2ff2 | pbrook | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
2236 | a41b2ff2 | pbrook | { |
2237 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2238 | a41b2ff2 | pbrook | |
2239 | a41b2ff2 | pbrook | addr &= 0xfc;
|
2240 | a41b2ff2 | pbrook | |
2241 | a41b2ff2 | pbrook | switch (addr)
|
2242 | a41b2ff2 | pbrook | { |
2243 | a41b2ff2 | pbrook | case RxMissed:
|
2244 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2245 | a41b2ff2 | pbrook | printf("RTL8139: RxMissed clearing on write\n");
|
2246 | a41b2ff2 | pbrook | #endif
|
2247 | a41b2ff2 | pbrook | s->RxMissed = 0;
|
2248 | a41b2ff2 | pbrook | break;
|
2249 | a41b2ff2 | pbrook | |
2250 | a41b2ff2 | pbrook | case TxConfig:
|
2251 | a41b2ff2 | pbrook | rtl8139_TxConfig_write(s, val); |
2252 | a41b2ff2 | pbrook | break;
|
2253 | a41b2ff2 | pbrook | |
2254 | a41b2ff2 | pbrook | case RxConfig:
|
2255 | a41b2ff2 | pbrook | rtl8139_RxConfig_write(s, val); |
2256 | a41b2ff2 | pbrook | break;
|
2257 | a41b2ff2 | pbrook | |
2258 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
2259 | a41b2ff2 | pbrook | rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
2260 | a41b2ff2 | pbrook | break;
|
2261 | a41b2ff2 | pbrook | |
2262 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
2263 | a41b2ff2 | pbrook | rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
2264 | a41b2ff2 | pbrook | break;
|
2265 | a41b2ff2 | pbrook | |
2266 | a41b2ff2 | pbrook | case RxBuf:
|
2267 | a41b2ff2 | pbrook | rtl8139_RxBuf_write(s, val); |
2268 | a41b2ff2 | pbrook | break;
|
2269 | a41b2ff2 | pbrook | |
2270 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
2271 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2272 | a41b2ff2 | pbrook | printf("RTL8139: C+ RxRing low bits write val=0x%08x\n", val);
|
2273 | a41b2ff2 | pbrook | #endif
|
2274 | a41b2ff2 | pbrook | s->RxRingAddrLO = val; |
2275 | a41b2ff2 | pbrook | break;
|
2276 | a41b2ff2 | pbrook | |
2277 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
2278 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2279 | a41b2ff2 | pbrook | printf("RTL8139: C+ RxRing high bits write val=0x%08x\n", val);
|
2280 | a41b2ff2 | pbrook | #endif
|
2281 | a41b2ff2 | pbrook | s->RxRingAddrHI = val; |
2282 | a41b2ff2 | pbrook | break;
|
2283 | a41b2ff2 | pbrook | |
2284 | a41b2ff2 | pbrook | default:
|
2285 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2286 | a41b2ff2 | pbrook | printf("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val);
|
2287 | a41b2ff2 | pbrook | #endif
|
2288 | a41b2ff2 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
2289 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff); |
2290 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2291 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2292 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 3, val & 0xff); |
2293 | a41b2ff2 | pbrook | #else
|
2294 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2295 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2296 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2297 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2298 | a41b2ff2 | pbrook | #endif
|
2299 | a41b2ff2 | pbrook | break;
|
2300 | a41b2ff2 | pbrook | } |
2301 | a41b2ff2 | pbrook | } |
2302 | a41b2ff2 | pbrook | |
2303 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
2304 | a41b2ff2 | pbrook | { |
2305 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2306 | a41b2ff2 | pbrook | int ret;
|
2307 | a41b2ff2 | pbrook | |
2308 | a41b2ff2 | pbrook | addr &= 0xff;
|
2309 | a41b2ff2 | pbrook | |
2310 | a41b2ff2 | pbrook | switch (addr)
|
2311 | a41b2ff2 | pbrook | { |
2312 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2313 | a41b2ff2 | pbrook | ret = s->phys[addr - MAC0]; |
2314 | a41b2ff2 | pbrook | break;
|
2315 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2316 | a41b2ff2 | pbrook | ret = 0;
|
2317 | a41b2ff2 | pbrook | break;
|
2318 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2319 | a41b2ff2 | pbrook | ret = s->mult[addr - MAR0]; |
2320 | a41b2ff2 | pbrook | break;
|
2321 | a41b2ff2 | pbrook | case ChipCmd:
|
2322 | a41b2ff2 | pbrook | ret = rtl8139_ChipCmd_read(s); |
2323 | a41b2ff2 | pbrook | break;
|
2324 | a41b2ff2 | pbrook | case Cfg9346:
|
2325 | a41b2ff2 | pbrook | ret = rtl8139_Cfg9346_read(s); |
2326 | a41b2ff2 | pbrook | break;
|
2327 | a41b2ff2 | pbrook | case Config0:
|
2328 | a41b2ff2 | pbrook | ret = rtl8139_Config0_read(s); |
2329 | a41b2ff2 | pbrook | break;
|
2330 | a41b2ff2 | pbrook | case Config1:
|
2331 | a41b2ff2 | pbrook | ret = rtl8139_Config1_read(s); |
2332 | a41b2ff2 | pbrook | break;
|
2333 | a41b2ff2 | pbrook | case Config3:
|
2334 | a41b2ff2 | pbrook | ret = rtl8139_Config3_read(s); |
2335 | a41b2ff2 | pbrook | break;
|
2336 | a41b2ff2 | pbrook | case Config4:
|
2337 | a41b2ff2 | pbrook | ret = rtl8139_Config4_read(s); |
2338 | a41b2ff2 | pbrook | break;
|
2339 | a41b2ff2 | pbrook | case Config5:
|
2340 | a41b2ff2 | pbrook | ret = rtl8139_Config5_read(s); |
2341 | a41b2ff2 | pbrook | break;
|
2342 | a41b2ff2 | pbrook | |
2343 | a41b2ff2 | pbrook | case MediaStatus:
|
2344 | a41b2ff2 | pbrook | ret = 0xd0;
|
2345 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2346 | a41b2ff2 | pbrook | printf("RTL8139: MediaStatus read 0x%x\n", ret);
|
2347 | a41b2ff2 | pbrook | #endif
|
2348 | a41b2ff2 | pbrook | break;
|
2349 | a41b2ff2 | pbrook | |
2350 | a41b2ff2 | pbrook | case HltClk:
|
2351 | a41b2ff2 | pbrook | ret = s->clock_enabled; |
2352 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2353 | a41b2ff2 | pbrook | printf("RTL8139: HltClk read 0x%x\n", ret);
|
2354 | a41b2ff2 | pbrook | #endif
|
2355 | a41b2ff2 | pbrook | break;
|
2356 | a41b2ff2 | pbrook | |
2357 | a41b2ff2 | pbrook | case PCIRevisionID:
|
2358 | a41b2ff2 | pbrook | ret = 0x10;
|
2359 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2360 | a41b2ff2 | pbrook | printf("RTL8139: PCI Revision ID read 0x%x\n", ret);
|
2361 | a41b2ff2 | pbrook | #endif
|
2362 | a41b2ff2 | pbrook | break;
|
2363 | a41b2ff2 | pbrook | |
2364 | a41b2ff2 | pbrook | case TxThresh:
|
2365 | a41b2ff2 | pbrook | ret = s->TxThresh; |
2366 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2367 | a41b2ff2 | pbrook | printf("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret);
|
2368 | a41b2ff2 | pbrook | #endif
|
2369 | a41b2ff2 | pbrook | break;
|
2370 | a41b2ff2 | pbrook | |
2371 | a41b2ff2 | pbrook | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
2372 | a41b2ff2 | pbrook | ret = s->TxConfig >> 24;
|
2373 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2374 | a41b2ff2 | pbrook | printf("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
|
2375 | a41b2ff2 | pbrook | #endif
|
2376 | a41b2ff2 | pbrook | break;
|
2377 | a41b2ff2 | pbrook | |
2378 | a41b2ff2 | pbrook | default:
|
2379 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2380 | a41b2ff2 | pbrook | printf("RTL8139: not implemented read(b) addr=0x%x\n", addr);
|
2381 | a41b2ff2 | pbrook | #endif
|
2382 | a41b2ff2 | pbrook | ret = 0;
|
2383 | a41b2ff2 | pbrook | break;
|
2384 | a41b2ff2 | pbrook | } |
2385 | a41b2ff2 | pbrook | |
2386 | a41b2ff2 | pbrook | return ret;
|
2387 | a41b2ff2 | pbrook | } |
2388 | a41b2ff2 | pbrook | |
2389 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
2390 | a41b2ff2 | pbrook | { |
2391 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2392 | a41b2ff2 | pbrook | uint32_t ret; |
2393 | a41b2ff2 | pbrook | |
2394 | a41b2ff2 | pbrook | addr &= 0xfe; /* mask lower bit */ |
2395 | a41b2ff2 | pbrook | |
2396 | a41b2ff2 | pbrook | switch (addr)
|
2397 | a41b2ff2 | pbrook | { |
2398 | a41b2ff2 | pbrook | case IntrMask:
|
2399 | a41b2ff2 | pbrook | ret = rtl8139_IntrMask_read(s); |
2400 | a41b2ff2 | pbrook | break;
|
2401 | a41b2ff2 | pbrook | |
2402 | a41b2ff2 | pbrook | case IntrStatus:
|
2403 | a41b2ff2 | pbrook | ret = rtl8139_IntrStatus_read(s); |
2404 | a41b2ff2 | pbrook | break;
|
2405 | a41b2ff2 | pbrook | |
2406 | a41b2ff2 | pbrook | case MultiIntr:
|
2407 | a41b2ff2 | pbrook | ret = rtl8139_MultiIntr_read(s); |
2408 | a41b2ff2 | pbrook | break;
|
2409 | a41b2ff2 | pbrook | |
2410 | a41b2ff2 | pbrook | case RxBufPtr:
|
2411 | a41b2ff2 | pbrook | ret = rtl8139_RxBufPtr_read(s); |
2412 | a41b2ff2 | pbrook | break;
|
2413 | a41b2ff2 | pbrook | |
2414 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2415 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeCtrl_read(s); |
2416 | a41b2ff2 | pbrook | break;
|
2417 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2418 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeStatus_read(s); |
2419 | a41b2ff2 | pbrook | break;
|
2420 | a41b2ff2 | pbrook | case NWayAdvert:
|
2421 | a41b2ff2 | pbrook | ret = s->NWayAdvert; |
2422 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2423 | a41b2ff2 | pbrook | printf("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret);
|
2424 | a41b2ff2 | pbrook | #endif
|
2425 | a41b2ff2 | pbrook | break;
|
2426 | a41b2ff2 | pbrook | case NWayLPAR:
|
2427 | a41b2ff2 | pbrook | ret = s->NWayLPAR; |
2428 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2429 | a41b2ff2 | pbrook | printf("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret);
|
2430 | a41b2ff2 | pbrook | #endif
|
2431 | a41b2ff2 | pbrook | break;
|
2432 | a41b2ff2 | pbrook | case NWayExpansion:
|
2433 | a41b2ff2 | pbrook | ret = s->NWayExpansion; |
2434 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2435 | a41b2ff2 | pbrook | printf("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret);
|
2436 | a41b2ff2 | pbrook | #endif
|
2437 | a41b2ff2 | pbrook | break;
|
2438 | a41b2ff2 | pbrook | |
2439 | a41b2ff2 | pbrook | case CpCmd:
|
2440 | a41b2ff2 | pbrook | ret = rtl8139_CpCmd_read(s); |
2441 | a41b2ff2 | pbrook | break;
|
2442 | a41b2ff2 | pbrook | |
2443 | a41b2ff2 | pbrook | case TxSummary:
|
2444 | a41b2ff2 | pbrook | ret = rtl8139_TSAD_read(s); |
2445 | a41b2ff2 | pbrook | break;
|
2446 | a41b2ff2 | pbrook | |
2447 | a41b2ff2 | pbrook | case CSCR:
|
2448 | a41b2ff2 | pbrook | ret = rtl8139_CSCR_read(s); |
2449 | a41b2ff2 | pbrook | break;
|
2450 | a41b2ff2 | pbrook | |
2451 | a41b2ff2 | pbrook | default:
|
2452 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2453 | a41b2ff2 | pbrook | printf("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr);
|
2454 | a41b2ff2 | pbrook | #endif
|
2455 | a41b2ff2 | pbrook | |
2456 | a41b2ff2 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
2457 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr) << 8;
|
2458 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1);
|
2459 | a41b2ff2 | pbrook | #else
|
2460 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
2461 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
2462 | a41b2ff2 | pbrook | #endif
|
2463 | a41b2ff2 | pbrook | |
2464 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2465 | a41b2ff2 | pbrook | printf("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
|
2466 | a41b2ff2 | pbrook | #endif
|
2467 | a41b2ff2 | pbrook | break;
|
2468 | a41b2ff2 | pbrook | } |
2469 | a41b2ff2 | pbrook | |
2470 | a41b2ff2 | pbrook | return ret;
|
2471 | a41b2ff2 | pbrook | } |
2472 | a41b2ff2 | pbrook | |
2473 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
2474 | a41b2ff2 | pbrook | { |
2475 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2476 | a41b2ff2 | pbrook | uint32_t ret; |
2477 | a41b2ff2 | pbrook | |
2478 | a41b2ff2 | pbrook | addr &= 0xfc; /* also mask low 2 bits */ |
2479 | a41b2ff2 | pbrook | |
2480 | a41b2ff2 | pbrook | switch (addr)
|
2481 | a41b2ff2 | pbrook | { |
2482 | a41b2ff2 | pbrook | case RxMissed:
|
2483 | a41b2ff2 | pbrook | ret = s->RxMissed; |
2484 | a41b2ff2 | pbrook | |
2485 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2486 | a41b2ff2 | pbrook | printf("RTL8139: RxMissed read val=0x%08x\n", ret);
|
2487 | a41b2ff2 | pbrook | #endif
|
2488 | a41b2ff2 | pbrook | break;
|
2489 | a41b2ff2 | pbrook | |
2490 | a41b2ff2 | pbrook | case TxConfig:
|
2491 | a41b2ff2 | pbrook | ret = rtl8139_TxConfig_read(s); |
2492 | a41b2ff2 | pbrook | break;
|
2493 | a41b2ff2 | pbrook | |
2494 | a41b2ff2 | pbrook | case RxConfig:
|
2495 | a41b2ff2 | pbrook | ret = rtl8139_RxConfig_read(s); |
2496 | a41b2ff2 | pbrook | break;
|
2497 | a41b2ff2 | pbrook | |
2498 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
2499 | a41b2ff2 | pbrook | ret = rtl8139_TxStatus_read(s, addr-TxStatus0); |
2500 | a41b2ff2 | pbrook | break;
|
2501 | a41b2ff2 | pbrook | |
2502 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
2503 | a41b2ff2 | pbrook | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
2504 | a41b2ff2 | pbrook | break;
|
2505 | a41b2ff2 | pbrook | |
2506 | a41b2ff2 | pbrook | case RxBuf:
|
2507 | a41b2ff2 | pbrook | ret = rtl8139_RxBuf_read(s); |
2508 | a41b2ff2 | pbrook | break;
|
2509 | a41b2ff2 | pbrook | |
2510 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
2511 | a41b2ff2 | pbrook | ret = s->RxRingAddrLO; |
2512 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2513 | a41b2ff2 | pbrook | printf("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret);
|
2514 | a41b2ff2 | pbrook | #endif
|
2515 | a41b2ff2 | pbrook | break;
|
2516 | a41b2ff2 | pbrook | |
2517 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
2518 | a41b2ff2 | pbrook | ret = s->RxRingAddrHI; |
2519 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2520 | a41b2ff2 | pbrook | printf("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret);
|
2521 | a41b2ff2 | pbrook | #endif
|
2522 | a41b2ff2 | pbrook | break;
|
2523 | a41b2ff2 | pbrook | |
2524 | a41b2ff2 | pbrook | default:
|
2525 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2526 | a41b2ff2 | pbrook | printf("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr);
|
2527 | a41b2ff2 | pbrook | #endif
|
2528 | a41b2ff2 | pbrook | |
2529 | a41b2ff2 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
2530 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr) << 24;
|
2531 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 16; |
2532 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 2) << 8; |
2533 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 3);
|
2534 | a41b2ff2 | pbrook | #else
|
2535 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
2536 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
2537 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
2538 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
2539 | a41b2ff2 | pbrook | #endif
|
2540 | a41b2ff2 | pbrook | |
2541 | a41b2ff2 | pbrook | #ifdef DEBUG_RTL8139
|
2542 | a41b2ff2 | pbrook | printf("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret);
|
2543 | a41b2ff2 | pbrook | #endif
|
2544 | a41b2ff2 | pbrook | break;
|
2545 | a41b2ff2 | pbrook | } |
2546 | a41b2ff2 | pbrook | |
2547 | a41b2ff2 | pbrook | return ret;
|
2548 | a41b2ff2 | pbrook | } |
2549 | a41b2ff2 | pbrook | |
2550 | a41b2ff2 | pbrook | /* */
|
2551 | a41b2ff2 | pbrook | |
2552 | a41b2ff2 | pbrook | static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
2553 | a41b2ff2 | pbrook | { |
2554 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
2555 | a41b2ff2 | pbrook | } |
2556 | a41b2ff2 | pbrook | |
2557 | a41b2ff2 | pbrook | static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
2558 | a41b2ff2 | pbrook | { |
2559 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
2560 | a41b2ff2 | pbrook | } |
2561 | a41b2ff2 | pbrook | |
2562 | a41b2ff2 | pbrook | static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
2563 | a41b2ff2 | pbrook | { |
2564 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
2565 | a41b2ff2 | pbrook | } |
2566 | a41b2ff2 | pbrook | |
2567 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
2568 | a41b2ff2 | pbrook | { |
2569 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
2570 | a41b2ff2 | pbrook | } |
2571 | a41b2ff2 | pbrook | |
2572 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
2573 | a41b2ff2 | pbrook | { |
2574 | a41b2ff2 | pbrook | return rtl8139_io_readw(opaque, addr & 0xFF); |
2575 | a41b2ff2 | pbrook | } |
2576 | a41b2ff2 | pbrook | |
2577 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
2578 | a41b2ff2 | pbrook | { |
2579 | a41b2ff2 | pbrook | return rtl8139_io_readl(opaque, addr & 0xFF); |
2580 | a41b2ff2 | pbrook | } |
2581 | a41b2ff2 | pbrook | |
2582 | a41b2ff2 | pbrook | /* */
|
2583 | a41b2ff2 | pbrook | |
2584 | a41b2ff2 | pbrook | static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
2585 | a41b2ff2 | pbrook | { |
2586 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
2587 | a41b2ff2 | pbrook | } |
2588 | a41b2ff2 | pbrook | |
2589 | a41b2ff2 | pbrook | static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
2590 | a41b2ff2 | pbrook | { |
2591 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
2592 | a41b2ff2 | pbrook | } |
2593 | a41b2ff2 | pbrook | |
2594 | a41b2ff2 | pbrook | static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
2595 | a41b2ff2 | pbrook | { |
2596 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
2597 | a41b2ff2 | pbrook | } |
2598 | a41b2ff2 | pbrook | |
2599 | a41b2ff2 | pbrook | static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
2600 | a41b2ff2 | pbrook | { |
2601 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
2602 | a41b2ff2 | pbrook | } |
2603 | a41b2ff2 | pbrook | |
2604 | a41b2ff2 | pbrook | static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
2605 | a41b2ff2 | pbrook | { |
2606 | a41b2ff2 | pbrook | return rtl8139_io_readw(opaque, addr & 0xFF); |
2607 | a41b2ff2 | pbrook | } |
2608 | a41b2ff2 | pbrook | |
2609 | a41b2ff2 | pbrook | static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
2610 | a41b2ff2 | pbrook | { |
2611 | a41b2ff2 | pbrook | return rtl8139_io_readl(opaque, addr & 0xFF); |
2612 | a41b2ff2 | pbrook | } |
2613 | a41b2ff2 | pbrook | |
2614 | a41b2ff2 | pbrook | /* */
|
2615 | a41b2ff2 | pbrook | |
2616 | a41b2ff2 | pbrook | static void rtl8139_save(QEMUFile* f,void* opaque) |
2617 | a41b2ff2 | pbrook | { |
2618 | a41b2ff2 | pbrook | RTL8139State* s=(RTL8139State*)opaque; |
2619 | a41b2ff2 | pbrook | int i;
|
2620 | a41b2ff2 | pbrook | |
2621 | a41b2ff2 | pbrook | qemu_put_buffer(f, s->phys, 6);
|
2622 | a41b2ff2 | pbrook | qemu_put_buffer(f, s->mult, 8);
|
2623 | a41b2ff2 | pbrook | |
2624 | a41b2ff2 | pbrook | for (i=0; i<4; ++i) |
2625 | a41b2ff2 | pbrook | { |
2626 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
|
2627 | a41b2ff2 | pbrook | } |
2628 | a41b2ff2 | pbrook | for (i=0; i<4; ++i) |
2629 | a41b2ff2 | pbrook | { |
2630 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
|
2631 | a41b2ff2 | pbrook | } |
2632 | a41b2ff2 | pbrook | |
2633 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
|
2634 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
|
2635 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxBufPtr); |
2636 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxBufAddr); |
2637 | a41b2ff2 | pbrook | |
2638 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->IntrStatus); |
2639 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->IntrMask); |
2640 | a41b2ff2 | pbrook | |
2641 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->TxConfig); |
2642 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxConfig); |
2643 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxMissed); |
2644 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->CSCR); |
2645 | a41b2ff2 | pbrook | |
2646 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Cfg9346); |
2647 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Config0); |
2648 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Config1); |
2649 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Config3); |
2650 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Config4); |
2651 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->Config5); |
2652 | a41b2ff2 | pbrook | |
2653 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->clock_enabled); |
2654 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->bChipCmdState); |
2655 | a41b2ff2 | pbrook | |
2656 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->MultiIntr); |
2657 | a41b2ff2 | pbrook | |
2658 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->BasicModeCtrl); |
2659 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->BasicModeStatus); |
2660 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->NWayAdvert); |
2661 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->NWayLPAR); |
2662 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->NWayExpansion); |
2663 | a41b2ff2 | pbrook | |
2664 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->CpCmd); |
2665 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->TxThresh); |
2666 | a41b2ff2 | pbrook | |
2667 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->irq); |
2668 | a41b2ff2 | pbrook | qemu_put_buffer(f, s->macaddr, 6);
|
2669 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->rtl8139_mmio_io_addr); |
2670 | a41b2ff2 | pbrook | |
2671 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->currTxDesc); |
2672 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->currCPlusRxDesc); |
2673 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->currCPlusTxDesc); |
2674 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxRingAddrLO); |
2675 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->RxRingAddrHI); |
2676 | a41b2ff2 | pbrook | |
2677 | a41b2ff2 | pbrook | for (i=0; i<EEPROM_9346_SIZE; ++i) |
2678 | a41b2ff2 | pbrook | { |
2679 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->eeprom.contents[i]); |
2680 | a41b2ff2 | pbrook | } |
2681 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->eeprom.mode); |
2682 | a41b2ff2 | pbrook | qemu_put_be32s(f, &s->eeprom.tick); |
2683 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->eeprom.address); |
2684 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->eeprom.input); |
2685 | a41b2ff2 | pbrook | qemu_put_be16s(f, &s->eeprom.output); |
2686 | a41b2ff2 | pbrook | |
2687 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->eeprom.eecs); |
2688 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->eeprom.eesk); |
2689 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->eeprom.eedi); |
2690 | a41b2ff2 | pbrook | qemu_put_8s(f, &s->eeprom.eedo); |
2691 | a41b2ff2 | pbrook | } |
2692 | a41b2ff2 | pbrook | |
2693 | a41b2ff2 | pbrook | static int rtl8139_load(QEMUFile* f,void* opaque,int version_id) |
2694 | a41b2ff2 | pbrook | { |
2695 | a41b2ff2 | pbrook | RTL8139State* s=(RTL8139State*)opaque; |
2696 | a41b2ff2 | pbrook | int i;
|
2697 | a41b2ff2 | pbrook | |
2698 | a41b2ff2 | pbrook | if (version_id != 1) |
2699 | a41b2ff2 | pbrook | return -EINVAL;
|
2700 | a41b2ff2 | pbrook | |
2701 | a41b2ff2 | pbrook | qemu_get_buffer(f, s->phys, 6);
|
2702 | a41b2ff2 | pbrook | qemu_get_buffer(f, s->mult, 8);
|
2703 | a41b2ff2 | pbrook | |
2704 | a41b2ff2 | pbrook | for (i=0; i<4; ++i) |
2705 | a41b2ff2 | pbrook | { |
2706 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
|
2707 | a41b2ff2 | pbrook | } |
2708 | a41b2ff2 | pbrook | for (i=0; i<4; ++i) |
2709 | a41b2ff2 | pbrook | { |
2710 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
|
2711 | a41b2ff2 | pbrook | } |
2712 | a41b2ff2 | pbrook | |
2713 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
|
2714 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
|
2715 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxBufPtr); |
2716 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxBufAddr); |
2717 | a41b2ff2 | pbrook | |
2718 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->IntrStatus); |
2719 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->IntrMask); |
2720 | a41b2ff2 | pbrook | |
2721 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->TxConfig); |
2722 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxConfig); |
2723 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxMissed); |
2724 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->CSCR); |
2725 | a41b2ff2 | pbrook | |
2726 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Cfg9346); |
2727 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Config0); |
2728 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Config1); |
2729 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Config3); |
2730 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Config4); |
2731 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->Config5); |
2732 | a41b2ff2 | pbrook | |
2733 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->clock_enabled); |
2734 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->bChipCmdState); |
2735 | a41b2ff2 | pbrook | |
2736 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->MultiIntr); |
2737 | a41b2ff2 | pbrook | |
2738 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->BasicModeCtrl); |
2739 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->BasicModeStatus); |
2740 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->NWayAdvert); |
2741 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->NWayLPAR); |
2742 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->NWayExpansion); |
2743 | a41b2ff2 | pbrook | |
2744 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->CpCmd); |
2745 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->TxThresh); |
2746 | a41b2ff2 | pbrook | |
2747 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->irq); |
2748 | a41b2ff2 | pbrook | qemu_get_buffer(f, s->macaddr, 6);
|
2749 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->rtl8139_mmio_io_addr); |
2750 | a41b2ff2 | pbrook | |
2751 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->currTxDesc); |
2752 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->currCPlusRxDesc); |
2753 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->currCPlusTxDesc); |
2754 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxRingAddrLO); |
2755 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->RxRingAddrHI); |
2756 | a41b2ff2 | pbrook | |
2757 | a41b2ff2 | pbrook | for (i=0; i<EEPROM_9346_SIZE; ++i) |
2758 | a41b2ff2 | pbrook | { |
2759 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->eeprom.contents[i]); |
2760 | a41b2ff2 | pbrook | } |
2761 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->eeprom.mode); |
2762 | a41b2ff2 | pbrook | qemu_get_be32s(f, &s->eeprom.tick); |
2763 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->eeprom.address); |
2764 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->eeprom.input); |
2765 | a41b2ff2 | pbrook | qemu_get_be16s(f, &s->eeprom.output); |
2766 | a41b2ff2 | pbrook | |
2767 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->eeprom.eecs); |
2768 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->eeprom.eesk); |
2769 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->eeprom.eedi); |
2770 | a41b2ff2 | pbrook | qemu_get_8s(f, &s->eeprom.eedo); |
2771 | a41b2ff2 | pbrook | |
2772 | a41b2ff2 | pbrook | return 0; |
2773 | a41b2ff2 | pbrook | } |
2774 | a41b2ff2 | pbrook | |
2775 | a41b2ff2 | pbrook | /***********************************************************/
|
2776 | a41b2ff2 | pbrook | /* PCI RTL8139 definitions */
|
2777 | a41b2ff2 | pbrook | |
2778 | a41b2ff2 | pbrook | typedef struct PCIRTL8139State { |
2779 | a41b2ff2 | pbrook | PCIDevice dev; |
2780 | a41b2ff2 | pbrook | RTL8139State rtl8139; |
2781 | a41b2ff2 | pbrook | } PCIRTL8139State; |
2782 | a41b2ff2 | pbrook | |
2783 | a41b2ff2 | pbrook | static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num, |
2784 | a41b2ff2 | pbrook | uint32_t addr, uint32_t size, int type)
|
2785 | a41b2ff2 | pbrook | { |
2786 | a41b2ff2 | pbrook | PCIRTL8139State *d = (PCIRTL8139State *)pci_dev; |
2787 | a41b2ff2 | pbrook | RTL8139State *s = &d->rtl8139; |
2788 | a41b2ff2 | pbrook | |
2789 | a41b2ff2 | pbrook | cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr); |
2790 | a41b2ff2 | pbrook | } |
2791 | a41b2ff2 | pbrook | |
2792 | a41b2ff2 | pbrook | static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, |
2793 | a41b2ff2 | pbrook | uint32_t addr, uint32_t size, int type)
|
2794 | a41b2ff2 | pbrook | { |
2795 | a41b2ff2 | pbrook | PCIRTL8139State *d = (PCIRTL8139State *)pci_dev; |
2796 | a41b2ff2 | pbrook | RTL8139State *s = &d->rtl8139; |
2797 | a41b2ff2 | pbrook | |
2798 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); |
2799 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); |
2800 | a41b2ff2 | pbrook | |
2801 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); |
2802 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); |
2803 | a41b2ff2 | pbrook | |
2804 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); |
2805 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); |
2806 | a41b2ff2 | pbrook | } |
2807 | a41b2ff2 | pbrook | |
2808 | a41b2ff2 | pbrook | static CPUReadMemoryFunc *rtl8139_mmio_read[3] = { |
2809 | a41b2ff2 | pbrook | rtl8139_mmio_readb, |
2810 | a41b2ff2 | pbrook | rtl8139_mmio_readw, |
2811 | a41b2ff2 | pbrook | rtl8139_mmio_readl, |
2812 | a41b2ff2 | pbrook | }; |
2813 | a41b2ff2 | pbrook | |
2814 | a41b2ff2 | pbrook | static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = { |
2815 | a41b2ff2 | pbrook | rtl8139_mmio_writeb, |
2816 | a41b2ff2 | pbrook | rtl8139_mmio_writew, |
2817 | a41b2ff2 | pbrook | rtl8139_mmio_writel, |
2818 | a41b2ff2 | pbrook | }; |
2819 | a41b2ff2 | pbrook | |
2820 | a41b2ff2 | pbrook | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd)
|
2821 | a41b2ff2 | pbrook | { |
2822 | a41b2ff2 | pbrook | PCIRTL8139State *d; |
2823 | a41b2ff2 | pbrook | RTL8139State *s; |
2824 | a41b2ff2 | pbrook | uint8_t *pci_conf; |
2825 | a41b2ff2 | pbrook | |
2826 | a41b2ff2 | pbrook | d = (PCIRTL8139State *)pci_register_device(bus, |
2827 | a41b2ff2 | pbrook | "RTL8139", sizeof(PCIRTL8139State), |
2828 | a41b2ff2 | pbrook | -1,
|
2829 | a41b2ff2 | pbrook | NULL, NULL); |
2830 | a41b2ff2 | pbrook | pci_conf = d->dev.config; |
2831 | a41b2ff2 | pbrook | pci_conf[0x00] = 0xec; /* Realtek 8139 */ |
2832 | a41b2ff2 | pbrook | pci_conf[0x01] = 0x10; |
2833 | a41b2ff2 | pbrook | pci_conf[0x02] = 0x39; |
2834 | a41b2ff2 | pbrook | pci_conf[0x03] = 0x81; |
2835 | a41b2ff2 | pbrook | pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ |
2836 | a41b2ff2 | pbrook | pci_conf[0x08] = 0x20; /* 0x10 */ /* PCI revision ID; >=0x20 is for 8139C+ */ |
2837 | a41b2ff2 | pbrook | pci_conf[0x0a] = 0x00; /* ethernet network controller */ |
2838 | a41b2ff2 | pbrook | pci_conf[0x0b] = 0x02; |
2839 | a41b2ff2 | pbrook | pci_conf[0x0e] = 0x00; /* header_type */ |
2840 | a41b2ff2 | pbrook | pci_conf[0x3d] = 1; /* interrupt pin 0 */ |
2841 | a41b2ff2 | pbrook | pci_conf[0x34] = 0xdc; |
2842 | a41b2ff2 | pbrook | |
2843 | a41b2ff2 | pbrook | s = &d->rtl8139; |
2844 | a41b2ff2 | pbrook | |
2845 | a41b2ff2 | pbrook | /* I/O handler for memory-mapped I/O */
|
2846 | a41b2ff2 | pbrook | s->rtl8139_mmio_io_addr = |
2847 | a41b2ff2 | pbrook | cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
|
2848 | a41b2ff2 | pbrook | |
2849 | a41b2ff2 | pbrook | pci_register_io_region(&d->dev, 0, 0x100, |
2850 | a41b2ff2 | pbrook | PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map); |
2851 | a41b2ff2 | pbrook | |
2852 | a41b2ff2 | pbrook | pci_register_io_region(&d->dev, 1, 0x100, |
2853 | a41b2ff2 | pbrook | PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map); |
2854 | a41b2ff2 | pbrook | |
2855 | a41b2ff2 | pbrook | s->irq = 16; /* PCI interrupt */ |
2856 | a41b2ff2 | pbrook | s->pci_dev = (PCIDevice *)d; |
2857 | a41b2ff2 | pbrook | memcpy(s->macaddr, nd->macaddr, 6);
|
2858 | a41b2ff2 | pbrook | rtl8139_reset(s); |
2859 | a41b2ff2 | pbrook | s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive, |
2860 | a41b2ff2 | pbrook | rtl8139_can_receive, s); |
2861 | a41b2ff2 | pbrook | |
2862 | a41b2ff2 | pbrook | snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
2863 | a41b2ff2 | pbrook | "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
2864 | a41b2ff2 | pbrook | s->macaddr[0],
|
2865 | a41b2ff2 | pbrook | s->macaddr[1],
|
2866 | a41b2ff2 | pbrook | s->macaddr[2],
|
2867 | a41b2ff2 | pbrook | s->macaddr[3],
|
2868 | a41b2ff2 | pbrook | s->macaddr[4],
|
2869 | a41b2ff2 | pbrook | s->macaddr[5]);
|
2870 | a41b2ff2 | pbrook | |
2871 | a41b2ff2 | pbrook | /* XXX: instance number ? */
|
2872 | a41b2ff2 | pbrook | register_savevm("rtl8139", 0, 1, rtl8139_save, rtl8139_load, s); |
2873 | a41b2ff2 | pbrook | register_savevm("rtl8139_pci", 0, 1, generic_pci_save, generic_pci_load, |
2874 | a41b2ff2 | pbrook | &d->dev); |
2875 | a41b2ff2 | pbrook | } |