root / hw / pl190.c @ 0986ac3b
History | View | Annotate | Download (6.5 kB)
1 |
/*
|
---|---|
2 |
* Arm PrimeCell PL190 Vector Interrupt Controller
|
3 |
*
|
4 |
* Copyright (c) 2006 CodeSourcery.
|
5 |
* Written by Paul Brook
|
6 |
*
|
7 |
* This code is licenced under the GPL.
|
8 |
*/
|
9 |
|
10 |
#include "vl.h" |
11 |
#include "arm_pic.h" |
12 |
|
13 |
/* The number of virtual priority levels. 16 user vectors plus the
|
14 |
unvectored IRQ. Chained interrupts would require an additional level
|
15 |
if implemented. */
|
16 |
|
17 |
#define PL190_NUM_PRIO 17 |
18 |
|
19 |
typedef struct { |
20 |
arm_pic_handler handler; |
21 |
uint32_t base; |
22 |
DisplayState *ds; |
23 |
uint32_t level; |
24 |
uint32_t soft_level; |
25 |
uint32_t irq_enable; |
26 |
uint32_t fiq_select; |
27 |
uint32_t default_addr; |
28 |
uint8_t vect_control[16];
|
29 |
uint32_t vect_addr[PL190_NUM_PRIO]; |
30 |
/* Mask containing interrupts with higher priority than this one. */
|
31 |
uint32_t prio_mask[PL190_NUM_PRIO + 1];
|
32 |
int protected;
|
33 |
/* Current priority level. */
|
34 |
int priority;
|
35 |
int prev_prio[PL190_NUM_PRIO];
|
36 |
void *parent;
|
37 |
int irq;
|
38 |
int fiq;
|
39 |
} pl190_state; |
40 |
|
41 |
static const unsigned char pl190_id[] = |
42 |
{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; |
43 |
|
44 |
static inline uint32_t pl190_irq_level(pl190_state *s) |
45 |
{ |
46 |
return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
|
47 |
} |
48 |
|
49 |
/* Update interrupts. */
|
50 |
static void pl190_update(pl190_state *s) |
51 |
{ |
52 |
uint32_t level = pl190_irq_level(s); |
53 |
int set;
|
54 |
|
55 |
set = (level & s->prio_mask[s->priority]) != 0;
|
56 |
pic_set_irq_new(s->parent, s->irq, set); |
57 |
set = ((s->level | s->soft_level) & s->fiq_select) != 0;
|
58 |
pic_set_irq_new(s->parent, s->fiq, set); |
59 |
} |
60 |
|
61 |
static void pl190_set_irq(void *opaque, int irq, int level) |
62 |
{ |
63 |
pl190_state *s = (pl190_state *)opaque; |
64 |
|
65 |
if (level)
|
66 |
s->level |= 1u << irq;
|
67 |
else
|
68 |
s->level &= ~(1u << irq);
|
69 |
pl190_update(s); |
70 |
} |
71 |
|
72 |
static void pl190_update_vectors(pl190_state *s) |
73 |
{ |
74 |
uint32_t mask; |
75 |
int i;
|
76 |
int n;
|
77 |
|
78 |
mask = 0;
|
79 |
for (i = 0; i < 16; i++) |
80 |
{ |
81 |
s->prio_mask[i] = mask; |
82 |
if (s->vect_control[i] & 0x20) |
83 |
{ |
84 |
n = s->vect_control[i] & 0x1f;
|
85 |
mask |= 1 << n;
|
86 |
} |
87 |
} |
88 |
s->prio_mask[16] = mask;
|
89 |
pl190_update(s); |
90 |
} |
91 |
|
92 |
static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) |
93 |
{ |
94 |
pl190_state *s = (pl190_state *)opaque; |
95 |
int i;
|
96 |
|
97 |
offset -= s->base; |
98 |
if (offset >= 0xfe0 && offset < 0x1000) { |
99 |
return pl190_id[(offset - 0xfe0) >> 2]; |
100 |
} |
101 |
if (offset >= 0x100 && offset < 0x140) { |
102 |
return s->vect_addr[(offset - 0x100) >> 2]; |
103 |
} |
104 |
if (offset >= 0x200 && offset < 0x240) { |
105 |
return s->vect_control[(offset - 0x200) >> 2]; |
106 |
} |
107 |
switch (offset >> 2) { |
108 |
case 0: /* IRQSTATUS */ |
109 |
return pl190_irq_level(s);
|
110 |
case 1: /* FIQSATUS */ |
111 |
return (s->level | s->soft_level) & s->fiq_select;
|
112 |
case 2: /* RAWINTR */ |
113 |
return s->level | s->soft_level;
|
114 |
case 3: /* INTSELECT */ |
115 |
return s->fiq_select;
|
116 |
case 4: /* INTENABLE */ |
117 |
return s->irq_enable;
|
118 |
case 6: /* SOFTINT */ |
119 |
return s->soft_level;
|
120 |
case 8: /* PROTECTION */ |
121 |
return s->protected;
|
122 |
case 12: /* VECTADDR */ |
123 |
/* Read vector address at the start of an ISR. Increases the
|
124 |
current priority level to that of the current interrupt. */
|
125 |
for (i = 0; i < s->priority; i++) |
126 |
{ |
127 |
if ((s->level | s->soft_level) & s->prio_mask[i])
|
128 |
break;
|
129 |
} |
130 |
/* Reading this value with no pending interrupts is undefined.
|
131 |
We return the default address. */
|
132 |
if (i == PL190_NUM_PRIO)
|
133 |
return s->vect_addr[16]; |
134 |
if (i < s->priority)
|
135 |
{ |
136 |
s->prev_prio[i] = s->priority; |
137 |
s->priority = i; |
138 |
pl190_update(s); |
139 |
} |
140 |
return s->vect_addr[s->priority];
|
141 |
case 13: /* DEFVECTADDR */ |
142 |
return s->vect_addr[16]; |
143 |
default:
|
144 |
cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset);
|
145 |
return 0; |
146 |
} |
147 |
} |
148 |
|
149 |
static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val) |
150 |
{ |
151 |
pl190_state *s = (pl190_state *)opaque; |
152 |
|
153 |
offset -= s->base; |
154 |
if (offset >= 0x100 && offset < 0x140) { |
155 |
s->vect_addr[(offset - 0x100) >> 2] = val; |
156 |
pl190_update_vectors(s); |
157 |
return;
|
158 |
} |
159 |
if (offset >= 0x200 && offset < 0x240) { |
160 |
s->vect_control[(offset - 0x200) >> 2] = val; |
161 |
pl190_update_vectors(s); |
162 |
return;
|
163 |
} |
164 |
switch (offset >> 2) { |
165 |
case 0: /* SELECT */ |
166 |
/* This is a readonly register, but linux tries to write to it
|
167 |
anyway. Ignore the write. */
|
168 |
break;
|
169 |
case 3: /* INTSELECT */ |
170 |
s->fiq_select = val; |
171 |
break;
|
172 |
case 4: /* INTENABLE */ |
173 |
s->irq_enable |= val; |
174 |
break;
|
175 |
case 5: /* INTENCLEAR */ |
176 |
s->irq_enable &= ~val; |
177 |
break;
|
178 |
case 6: /* SOFTINT */ |
179 |
s->soft_level |= val; |
180 |
break;
|
181 |
case 7: /* SOFTINTCLEAR */ |
182 |
s->soft_level &= ~val; |
183 |
break;
|
184 |
case 8: /* PROTECTION */ |
185 |
/* TODO: Protection (supervisor only access) is not implemented. */
|
186 |
s->protected = val & 1;
|
187 |
break;
|
188 |
case 12: /* VECTADDR */ |
189 |
/* Restore the previous priority level. The value written is
|
190 |
ignored. */
|
191 |
if (s->priority < PL190_NUM_PRIO)
|
192 |
s->priority = s->prev_prio[s->priority]; |
193 |
break;
|
194 |
case 13: /* DEFVECTADDR */ |
195 |
s->default_addr = val; |
196 |
break;
|
197 |
case 0xc0: /* ITCR */ |
198 |
if (val)
|
199 |
cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
|
200 |
break;
|
201 |
default:
|
202 |
cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset);
|
203 |
return;
|
204 |
} |
205 |
pl190_update(s); |
206 |
} |
207 |
|
208 |
static CPUReadMemoryFunc *pl190_readfn[] = {
|
209 |
pl190_read, |
210 |
pl190_read, |
211 |
pl190_read |
212 |
}; |
213 |
|
214 |
static CPUWriteMemoryFunc *pl190_writefn[] = {
|
215 |
pl190_write, |
216 |
pl190_write, |
217 |
pl190_write |
218 |
}; |
219 |
|
220 |
void pl190_reset(pl190_state *s)
|
221 |
{ |
222 |
int i;
|
223 |
|
224 |
for (i = 0; i < 16; i++) |
225 |
{ |
226 |
s->vect_addr[i] = 0;
|
227 |
s->vect_control[i] = 0;
|
228 |
} |
229 |
s->vect_addr[16] = 0; |
230 |
s->prio_mask[17] = 0xffffffff; |
231 |
s->priority = PL190_NUM_PRIO; |
232 |
pl190_update_vectors(s); |
233 |
} |
234 |
|
235 |
void *pl190_init(uint32_t base, void *parent, int irq, int fiq) |
236 |
{ |
237 |
pl190_state *s; |
238 |
int iomemtype;
|
239 |
|
240 |
s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
|
241 |
iomemtype = cpu_register_io_memory(0, pl190_readfn,
|
242 |
pl190_writefn, s); |
243 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
244 |
s->handler = pl190_set_irq; |
245 |
s->base = base; |
246 |
s->parent = parent; |
247 |
s->irq = irq; |
248 |
s->fiq = fiq; |
249 |
pl190_reset(s); |
250 |
/* ??? Save/restore. */
|
251 |
return s;
|
252 |
} |