root / hw / slavio_misc.c @ 09b26c5e
History | View | Annotate | Download (6.6 kB)
1 | 3475187d | bellard | /*
|
---|---|---|---|
2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
|
3 | 3475187d | bellard | *
|
4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
|
5 | 3475187d | bellard | *
|
6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
|
12 | 3475187d | bellard | *
|
13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 3475187d | bellard | * all copies or substantial portions of the Software.
|
15 | 3475187d | bellard | *
|
16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 3475187d | bellard | * THE SOFTWARE.
|
23 | 3475187d | bellard | */
|
24 | 3475187d | bellard | #include "vl.h" |
25 | 3475187d | bellard | /* debug misc */
|
26 | 3475187d | bellard | //#define DEBUG_MISC
|
27 | 3475187d | bellard | |
28 | 3475187d | bellard | /*
|
29 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
|
30 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
|
31 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
32 | 3475187d | bellard | *
|
33 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
|
34 | 3475187d | bellard | */
|
35 | 3475187d | bellard | |
36 | 3475187d | bellard | #ifdef DEBUG_MISC
|
37 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...) \
|
38 | 3475187d | bellard | do { printf("MISC: " fmt , ##args); } while (0) |
39 | 3475187d | bellard | #else
|
40 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...)
|
41 | 3475187d | bellard | #endif
|
42 | 3475187d | bellard | |
43 | 3475187d | bellard | typedef struct MiscState { |
44 | 3475187d | bellard | int irq;
|
45 | 3475187d | bellard | uint8_t config; |
46 | 3475187d | bellard | uint8_t aux1, aux2; |
47 | 4e3b1ea1 | bellard | uint8_t diag, mctrl, sysctrl; |
48 | 3475187d | bellard | } MiscState; |
49 | 3475187d | bellard | |
50 | 3475187d | bellard | #define MISC_MAXADDR 1 |
51 | 3475187d | bellard | |
52 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
53 | 3475187d | bellard | { |
54 | 3475187d | bellard | MiscState *s = opaque; |
55 | 3475187d | bellard | |
56 | 3475187d | bellard | if ((s->aux2 & 0x4) && (s->config & 0x8)) { |
57 | 3475187d | bellard | pic_set_irq(s->irq, 1);
|
58 | 3475187d | bellard | } else {
|
59 | 3475187d | bellard | pic_set_irq(s->irq, 0);
|
60 | 3475187d | bellard | } |
61 | 3475187d | bellard | } |
62 | 3475187d | bellard | |
63 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
64 | 3475187d | bellard | { |
65 | 3475187d | bellard | MiscState *s = opaque; |
66 | 3475187d | bellard | |
67 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
|
68 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
|
69 | 3475187d | bellard | } |
70 | 3475187d | bellard | |
71 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
72 | 3475187d | bellard | { |
73 | 3475187d | bellard | MiscState *s = opaque; |
74 | 3475187d | bellard | |
75 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
|
76 | 3475187d | bellard | if (power_failing && (s->config & 0x8)) { |
77 | 3475187d | bellard | s->aux2 |= 0x4;
|
78 | 3475187d | bellard | } else {
|
79 | 3475187d | bellard | s->aux2 &= ~0x4;
|
80 | 3475187d | bellard | } |
81 | 3475187d | bellard | slavio_misc_update_irq(s); |
82 | 3475187d | bellard | } |
83 | 3475187d | bellard | |
84 | 3475187d | bellard | static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
85 | 3475187d | bellard | { |
86 | 3475187d | bellard | MiscState *s = opaque; |
87 | 3475187d | bellard | |
88 | 3475187d | bellard | switch (addr & 0xfff0000) { |
89 | 3475187d | bellard | case 0x1800000: |
90 | 3475187d | bellard | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
91 | 3475187d | bellard | s->config = val & 0xff;
|
92 | 3475187d | bellard | slavio_misc_update_irq(s); |
93 | 3475187d | bellard | break;
|
94 | 3475187d | bellard | case 0x1900000: |
95 | 3475187d | bellard | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
96 | 3475187d | bellard | s->aux1 = val & 0xff;
|
97 | 3475187d | bellard | break;
|
98 | 3475187d | bellard | case 0x1910000: |
99 | 3475187d | bellard | val &= 0x3;
|
100 | 3475187d | bellard | MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
101 | 3475187d | bellard | val |= s->aux2 & 0x4;
|
102 | 3475187d | bellard | if (val & 0x2) // Clear Power Fail int |
103 | 3475187d | bellard | val &= 0x1;
|
104 | 3475187d | bellard | s->aux2 = val; |
105 | 3475187d | bellard | if (val & 1) |
106 | 3475187d | bellard | qemu_system_shutdown_request(); |
107 | 3475187d | bellard | slavio_misc_update_irq(s); |
108 | 3475187d | bellard | break;
|
109 | 3475187d | bellard | case 0x1a00000: |
110 | 3475187d | bellard | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
111 | 3475187d | bellard | s->diag = val & 0xff;
|
112 | 3475187d | bellard | break;
|
113 | 3475187d | bellard | case 0x1b00000: |
114 | 3475187d | bellard | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
115 | 3475187d | bellard | s->mctrl = val & 0xff;
|
116 | 3475187d | bellard | break;
|
117 | 3475187d | bellard | case 0x1f00000: |
118 | 3475187d | bellard | MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); |
119 | 4e3b1ea1 | bellard | if (val & 1) { |
120 | 4e3b1ea1 | bellard | s->sysctrl = 0x2;
|
121 | 3475187d | bellard | qemu_system_reset_request(); |
122 | 4e3b1ea1 | bellard | } |
123 | 3475187d | bellard | break;
|
124 | 3475187d | bellard | case 0xa000000: |
125 | 3475187d | bellard | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
126 | 3475187d | bellard | #if 0
|
127 | ba3c64fb | bellard | // XXX almost works
|
128 | ba3c64fb | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
|
129 | 3475187d | bellard | #endif
|
130 | 3475187d | bellard | break;
|
131 | 3475187d | bellard | } |
132 | 3475187d | bellard | } |
133 | 3475187d | bellard | |
134 | 3475187d | bellard | static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
135 | 3475187d | bellard | { |
136 | 3475187d | bellard | MiscState *s = opaque; |
137 | 3475187d | bellard | uint32_t ret = 0;
|
138 | 3475187d | bellard | |
139 | 3475187d | bellard | switch (addr & 0xfff0000) { |
140 | 3475187d | bellard | case 0x1800000: |
141 | 3475187d | bellard | ret = s->config; |
142 | 3475187d | bellard | MISC_DPRINTF("Read config %2.2x\n", ret);
|
143 | 3475187d | bellard | break;
|
144 | 3475187d | bellard | case 0x1900000: |
145 | 3475187d | bellard | ret = s->aux1; |
146 | 3475187d | bellard | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
147 | 3475187d | bellard | break;
|
148 | 3475187d | bellard | case 0x1910000: |
149 | 3475187d | bellard | ret = s->aux2; |
150 | 3475187d | bellard | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
151 | 3475187d | bellard | break;
|
152 | 3475187d | bellard | case 0x1a00000: |
153 | 3475187d | bellard | ret = s->diag; |
154 | 3475187d | bellard | MISC_DPRINTF("Read diag %2.2x\n", ret);
|
155 | 3475187d | bellard | break;
|
156 | 3475187d | bellard | case 0x1b00000: |
157 | 3475187d | bellard | ret = s->mctrl; |
158 | 3475187d | bellard | MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
159 | 3475187d | bellard | break;
|
160 | 3475187d | bellard | case 0x1f00000: |
161 | 3475187d | bellard | MISC_DPRINTF("Read system control %2.2x\n", ret);
|
162 | 4e3b1ea1 | bellard | ret = s->sysctrl; |
163 | 3475187d | bellard | break;
|
164 | 3475187d | bellard | case 0xa000000: |
165 | 3475187d | bellard | MISC_DPRINTF("Read power management %2.2x\n", ret);
|
166 | 3475187d | bellard | break;
|
167 | 3475187d | bellard | } |
168 | 3475187d | bellard | return ret;
|
169 | 3475187d | bellard | } |
170 | 3475187d | bellard | |
171 | 3475187d | bellard | static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { |
172 | 3475187d | bellard | slavio_misc_mem_readb, |
173 | 3475187d | bellard | slavio_misc_mem_readb, |
174 | 3475187d | bellard | slavio_misc_mem_readb, |
175 | 3475187d | bellard | }; |
176 | 3475187d | bellard | |
177 | 3475187d | bellard | static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { |
178 | 3475187d | bellard | slavio_misc_mem_writeb, |
179 | 3475187d | bellard | slavio_misc_mem_writeb, |
180 | 3475187d | bellard | slavio_misc_mem_writeb, |
181 | 3475187d | bellard | }; |
182 | 3475187d | bellard | |
183 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
184 | 3475187d | bellard | { |
185 | 3475187d | bellard | MiscState *s = opaque; |
186 | 3475187d | bellard | |
187 | 3475187d | bellard | qemu_put_be32s(f, &s->irq); |
188 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
189 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
190 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
191 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
192 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
193 | 4e3b1ea1 | bellard | qemu_put_8s(f, &s->sysctrl); |
194 | 3475187d | bellard | } |
195 | 3475187d | bellard | |
196 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
197 | 3475187d | bellard | { |
198 | 3475187d | bellard | MiscState *s = opaque; |
199 | 3475187d | bellard | |
200 | 3475187d | bellard | if (version_id != 1) |
201 | 3475187d | bellard | return -EINVAL;
|
202 | 3475187d | bellard | |
203 | 3475187d | bellard | qemu_get_be32s(f, &s->irq); |
204 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
205 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
206 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
207 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
208 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
209 | 4e3b1ea1 | bellard | qemu_get_8s(f, &s->sysctrl); |
210 | 3475187d | bellard | return 0; |
211 | 3475187d | bellard | } |
212 | 3475187d | bellard | |
213 | 3475187d | bellard | void *slavio_misc_init(uint32_t base, int irq) |
214 | 3475187d | bellard | { |
215 | 3475187d | bellard | int slavio_misc_io_memory;
|
216 | 3475187d | bellard | MiscState *s; |
217 | 3475187d | bellard | |
218 | 3475187d | bellard | s = qemu_mallocz(sizeof(MiscState));
|
219 | 3475187d | bellard | if (!s)
|
220 | 3475187d | bellard | return NULL; |
221 | 3475187d | bellard | |
222 | 3475187d | bellard | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
|
223 | 3475187d | bellard | // Slavio control
|
224 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);
|
225 | 3475187d | bellard | // AUX 1
|
226 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);
|
227 | 3475187d | bellard | // AUX 2
|
228 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);
|
229 | 3475187d | bellard | // Diagnostics
|
230 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);
|
231 | 3475187d | bellard | // Modem control
|
232 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);
|
233 | 3475187d | bellard | // System control
|
234 | 3475187d | bellard | cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
|
235 | 3475187d | bellard | // Power management
|
236 | 3475187d | bellard | cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
|
237 | 3475187d | bellard | |
238 | 3475187d | bellard | s->irq = irq; |
239 | 3475187d | bellard | |
240 | 3475187d | bellard | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s); |
241 | 3475187d | bellard | qemu_register_reset(slavio_misc_reset, s); |
242 | 3475187d | bellard | slavio_misc_reset(s); |
243 | 3475187d | bellard | return s;
|
244 | 3475187d | bellard | } |