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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>
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18 | 574bbf7b | bellard | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "pc.h" |
21 | 54c96da7 | Michael S. Tsirkin | #include "pci.h" |
22 | 54c96da7 | Michael S. Tsirkin | #include "msix.h" |
23 | 87ecb68b | pbrook | #include "qemu-timer.h" |
24 | bb7e7293 | aurel32 | #include "host-utils.h" |
25 | 8d2ba1fb | Jan Kiszka | #include "kvm.h" |
26 | 574bbf7b | bellard | |
27 | 574bbf7b | bellard | //#define DEBUG_APIC
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28 | 574bbf7b | bellard | |
29 | 574bbf7b | bellard | /* APIC Local Vector Table */
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30 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
31 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
32 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
33 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
34 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
35 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
36 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
37 | 574bbf7b | bellard | |
38 | 574bbf7b | bellard | /* APIC delivery modes */
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39 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
40 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
41 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
42 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
43 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
44 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
45 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
46 | 574bbf7b | bellard | |
47 | d592d303 | bellard | /* APIC destination mode */
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48 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
49 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
50 | d592d303 | bellard | |
51 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
52 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
53 | 574bbf7b | bellard | |
54 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
55 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
56 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
57 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
58 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
59 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
60 | 574bbf7b | bellard | |
61 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
62 | 574bbf7b | bellard | |
63 | 574bbf7b | bellard | #define APIC_SV_ENABLE (1 << 8) |
64 | 574bbf7b | bellard | |
65 | d3e9db93 | bellard | #define MAX_APICS 255 |
66 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
67 | d3e9db93 | bellard | |
68 | 54c96da7 | Michael S. Tsirkin | /* Intel APIC constants: from include/asm/msidef.h */
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69 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_SHIFT 0 |
70 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_VECTOR_MASK 0x000000ff |
71 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
72 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_TRIGGER_SHIFT 15 |
73 | 54c96da7 | Michael S. Tsirkin | #define MSI_DATA_LEVEL_SHIFT 14 |
74 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_MODE_SHIFT 2 |
75 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_SHIFT 12 |
76 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
77 | 54c96da7 | Michael S. Tsirkin | |
78 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_BASE 0xfee00000 |
79 | 54c96da7 | Michael S. Tsirkin | #define MSI_ADDR_SIZE 0x100000 |
80 | 54c96da7 | Michael S. Tsirkin | |
81 | 574bbf7b | bellard | typedef struct APICState { |
82 | 574bbf7b | bellard | CPUState *cpu_env; |
83 | 574bbf7b | bellard | uint32_t apicbase; |
84 | 574bbf7b | bellard | uint8_t id; |
85 | d592d303 | bellard | uint8_t arb_id; |
86 | 574bbf7b | bellard | uint8_t tpr; |
87 | 574bbf7b | bellard | uint32_t spurious_vec; |
88 | d592d303 | bellard | uint8_t log_dest; |
89 | d592d303 | bellard | uint8_t dest_mode; |
90 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
91 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
92 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
93 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
94 | 574bbf7b | bellard | uint32_t esr; /* error register */
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95 | 574bbf7b | bellard | uint32_t icr[2];
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96 | 574bbf7b | bellard | |
97 | 574bbf7b | bellard | uint32_t divide_conf; |
98 | 574bbf7b | bellard | int count_shift;
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99 | 574bbf7b | bellard | uint32_t initial_count; |
100 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
101 | 678e12cc | Gleb Natapov | uint32_t idx; |
102 | 574bbf7b | bellard | QEMUTimer *timer; |
103 | b09ea7d5 | Gleb Natapov | int sipi_vector;
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104 | b09ea7d5 | Gleb Natapov | int wait_for_sipi;
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105 | 574bbf7b | bellard | } APICState; |
106 | 574bbf7b | bellard | |
107 | 574bbf7b | bellard | static int apic_io_memory; |
108 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
109 | 678e12cc | Gleb Natapov | static int last_apic_idx = 0; |
110 | 73822ec8 | aliguori | static int apic_irq_delivered; |
111 | 73822ec8 | aliguori | |
112 | d592d303 | bellard | |
113 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
114 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
115 | 610626af | aliguori | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
116 | 610626af | aliguori | uint8_t dest, uint8_t dest_mode); |
117 | d592d303 | bellard | |
118 | 3b63c04e | aurel32 | /* Find first bit starting from msb */
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119 | 3b63c04e | aurel32 | static int fls_bit(uint32_t value) |
120 | 3b63c04e | aurel32 | { |
121 | 3b63c04e | aurel32 | return 31 - clz32(value); |
122 | 3b63c04e | aurel32 | } |
123 | 3b63c04e | aurel32 | |
124 | e95f5491 | aurel32 | /* Find first bit starting from lsb */
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125 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
126 | d3e9db93 | bellard | { |
127 | bb7e7293 | aurel32 | return ctz32(value);
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128 | d3e9db93 | bellard | } |
129 | d3e9db93 | bellard | |
130 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
131 | d3e9db93 | bellard | { |
132 | d3e9db93 | bellard | int i, mask;
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133 | d3e9db93 | bellard | i = index >> 5;
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134 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
135 | d3e9db93 | bellard | tab[i] |= mask; |
136 | d3e9db93 | bellard | } |
137 | d3e9db93 | bellard | |
138 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
139 | d3e9db93 | bellard | { |
140 | d3e9db93 | bellard | int i, mask;
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141 | d3e9db93 | bellard | i = index >> 5;
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142 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
143 | d3e9db93 | bellard | tab[i] &= ~mask; |
144 | d3e9db93 | bellard | } |
145 | d3e9db93 | bellard | |
146 | 73822ec8 | aliguori | static inline int get_bit(uint32_t *tab, int index) |
147 | 73822ec8 | aliguori | { |
148 | 73822ec8 | aliguori | int i, mask;
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149 | 73822ec8 | aliguori | i = index >> 5;
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150 | 73822ec8 | aliguori | mask = 1 << (index & 0x1f); |
151 | 73822ec8 | aliguori | return !!(tab[i] & mask);
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152 | 73822ec8 | aliguori | } |
153 | 73822ec8 | aliguori | |
154 | 1a7de94a | aurel32 | static void apic_local_deliver(CPUState *env, int vector) |
155 | a5b38b51 | aurel32 | { |
156 | a5b38b51 | aurel32 | APICState *s = env->apic_state; |
157 | a5b38b51 | aurel32 | uint32_t lvt = s->lvt[vector]; |
158 | a5b38b51 | aurel32 | int trigger_mode;
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159 | a5b38b51 | aurel32 | |
160 | a5b38b51 | aurel32 | if (lvt & APIC_LVT_MASKED)
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161 | a5b38b51 | aurel32 | return;
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162 | a5b38b51 | aurel32 | |
163 | a5b38b51 | aurel32 | switch ((lvt >> 8) & 7) { |
164 | a5b38b51 | aurel32 | case APIC_DM_SMI:
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165 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_SMI); |
166 | a5b38b51 | aurel32 | break;
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167 | a5b38b51 | aurel32 | |
168 | a5b38b51 | aurel32 | case APIC_DM_NMI:
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169 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_NMI); |
170 | a5b38b51 | aurel32 | break;
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171 | a5b38b51 | aurel32 | |
172 | a5b38b51 | aurel32 | case APIC_DM_EXTINT:
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173 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
174 | a5b38b51 | aurel32 | break;
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175 | a5b38b51 | aurel32 | |
176 | a5b38b51 | aurel32 | case APIC_DM_FIXED:
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177 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_EDGE; |
178 | a5b38b51 | aurel32 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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179 | a5b38b51 | aurel32 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
180 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_LEVEL; |
181 | a5b38b51 | aurel32 | apic_set_irq(s, lvt & 0xff, trigger_mode);
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182 | a5b38b51 | aurel32 | } |
183 | a5b38b51 | aurel32 | } |
184 | a5b38b51 | aurel32 | |
185 | 1a7de94a | aurel32 | void apic_deliver_pic_intr(CPUState *env, int level) |
186 | 1a7de94a | aurel32 | { |
187 | 1a7de94a | aurel32 | if (level)
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188 | 1a7de94a | aurel32 | apic_local_deliver(env, APIC_LVT_LINT0); |
189 | 1a7de94a | aurel32 | else {
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190 | 1a7de94a | aurel32 | APICState *s = env->apic_state; |
191 | 1a7de94a | aurel32 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
192 | 1a7de94a | aurel32 | |
193 | 1a7de94a | aurel32 | switch ((lvt >> 8) & 7) { |
194 | 1a7de94a | aurel32 | case APIC_DM_FIXED:
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195 | 1a7de94a | aurel32 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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196 | 1a7de94a | aurel32 | break;
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197 | 1a7de94a | aurel32 | reset_bit(s->irr, lvt & 0xff);
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198 | 1a7de94a | aurel32 | /* fall through */
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199 | 1a7de94a | aurel32 | case APIC_DM_EXTINT:
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200 | 1a7de94a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
201 | 1a7de94a | aurel32 | break;
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202 | 1a7de94a | aurel32 | } |
203 | 1a7de94a | aurel32 | } |
204 | 1a7de94a | aurel32 | } |
205 | 1a7de94a | aurel32 | |
206 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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207 | d3e9db93 | bellard | {\ |
208 | d3e9db93 | bellard | int __i, __j, __mask;\
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209 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
210 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
211 | d3e9db93 | bellard | if (__mask) {\
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212 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
213 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
214 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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215 | d3e9db93 | bellard | if (apic) {\
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216 | d3e9db93 | bellard | code;\ |
217 | d3e9db93 | bellard | }\ |
218 | d3e9db93 | bellard | }\ |
219 | d3e9db93 | bellard | }\ |
220 | d3e9db93 | bellard | }\ |
221 | d3e9db93 | bellard | }\ |
222 | d3e9db93 | bellard | } |
223 | d3e9db93 | bellard | |
224 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
225 | d3e9db93 | bellard | uint8_t delivery_mode, |
226 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
227 | d592d303 | bellard | uint8_t trigger_mode) |
228 | d592d303 | bellard | { |
229 | d592d303 | bellard | APICState *apic_iter; |
230 | d592d303 | bellard | |
231 | d592d303 | bellard | switch (delivery_mode) {
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232 | d592d303 | bellard | case APIC_DM_LOWPRI:
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233 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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234 | d3e9db93 | bellard | { |
235 | d3e9db93 | bellard | int i, d;
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236 | d3e9db93 | bellard | d = -1;
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237 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
238 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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239 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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240 | d3e9db93 | bellard | break;
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241 | d3e9db93 | bellard | } |
242 | d3e9db93 | bellard | } |
243 | d3e9db93 | bellard | if (d >= 0) { |
244 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
245 | d3e9db93 | bellard | if (apic_iter) {
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246 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
247 | d3e9db93 | bellard | } |
248 | d3e9db93 | bellard | } |
249 | 8dd69b8f | bellard | } |
250 | d3e9db93 | bellard | return;
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251 | 8dd69b8f | bellard | |
252 | d592d303 | bellard | case APIC_DM_FIXED:
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253 | d592d303 | bellard | break;
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254 | d592d303 | bellard | |
255 | d592d303 | bellard | case APIC_DM_SMI:
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256 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
257 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
258 | e2eb9d3e | aurel32 | return;
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259 | e2eb9d3e | aurel32 | |
260 | d592d303 | bellard | case APIC_DM_NMI:
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261 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
262 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
263 | e2eb9d3e | aurel32 | return;
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264 | d592d303 | bellard | |
265 | d592d303 | bellard | case APIC_DM_INIT:
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266 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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267 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
268 | b09ea7d5 | Gleb Natapov | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
269 | d592d303 | bellard | return;
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270 | 3b46e624 | ths | |
271 | d592d303 | bellard | case APIC_DM_EXTINT:
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272 | b1fc0348 | bellard | /* handled in I/O APIC code */
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273 | d592d303 | bellard | break;
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274 | d592d303 | bellard | |
275 | d592d303 | bellard | default:
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276 | d592d303 | bellard | return;
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277 | d592d303 | bellard | } |
278 | d592d303 | bellard | |
279 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
280 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
281 | d592d303 | bellard | } |
282 | 574bbf7b | bellard | |
283 | 610626af | aliguori | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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284 | 610626af | aliguori | uint8_t delivery_mode, uint8_t vector_num, |
285 | 610626af | aliguori | uint8_t polarity, uint8_t trigger_mode) |
286 | 610626af | aliguori | { |
287 | 610626af | aliguori | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
288 | 610626af | aliguori | |
289 | 610626af | aliguori | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
290 | 610626af | aliguori | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
291 | 610626af | aliguori | trigger_mode); |
292 | 610626af | aliguori | } |
293 | 610626af | aliguori | |
294 | 574bbf7b | bellard | void cpu_set_apic_base(CPUState *env, uint64_t val)
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295 | 574bbf7b | bellard | { |
296 | 574bbf7b | bellard | APICState *s = env->apic_state; |
297 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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298 | 26a76461 | bellard | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
299 | 574bbf7b | bellard | #endif
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300 | 2c7c13d4 | aurel32 | if (!s)
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301 | 2c7c13d4 | aurel32 | return;
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302 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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303 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
304 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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305 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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306 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
307 | 574bbf7b | bellard | env->cpuid_features &= ~CPUID_APIC; |
308 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
309 | 574bbf7b | bellard | } |
310 | 574bbf7b | bellard | } |
311 | 574bbf7b | bellard | |
312 | 574bbf7b | bellard | uint64_t cpu_get_apic_base(CPUState *env) |
313 | 574bbf7b | bellard | { |
314 | 574bbf7b | bellard | APICState *s = env->apic_state; |
315 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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316 | 2c7c13d4 | aurel32 | printf("cpu_get_apic_base: %016" PRIx64 "\n", |
317 | 2c7c13d4 | aurel32 | s ? (uint64_t)s->apicbase: 0);
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318 | 574bbf7b | bellard | #endif
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319 | 2c7c13d4 | aurel32 | return s ? s->apicbase : 0; |
320 | 574bbf7b | bellard | } |
321 | 574bbf7b | bellard | |
322 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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323 | 9230e66e | bellard | { |
324 | 9230e66e | bellard | APICState *s = env->apic_state; |
325 | 2c7c13d4 | aurel32 | if (!s)
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326 | 2c7c13d4 | aurel32 | return;
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327 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
328 | d592d303 | bellard | apic_update_irq(s); |
329 | 9230e66e | bellard | } |
330 | 9230e66e | bellard | |
331 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env) |
332 | 9230e66e | bellard | { |
333 | 9230e66e | bellard | APICState *s = env->apic_state; |
334 | 2c7c13d4 | aurel32 | return s ? s->tpr >> 4 : 0; |
335 | 9230e66e | bellard | } |
336 | 9230e66e | bellard | |
337 | d592d303 | bellard | /* return -1 if no bit is set */
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338 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
339 | d592d303 | bellard | { |
340 | d592d303 | bellard | int i;
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341 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
342 | d592d303 | bellard | if (tab[i] != 0) { |
343 | 3b63c04e | aurel32 | return i * 32 + fls_bit(tab[i]); |
344 | d592d303 | bellard | } |
345 | d592d303 | bellard | } |
346 | d592d303 | bellard | return -1; |
347 | d592d303 | bellard | } |
348 | d592d303 | bellard | |
349 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
350 | 574bbf7b | bellard | { |
351 | 574bbf7b | bellard | int tpr, isrv, ppr;
|
352 | 574bbf7b | bellard | |
353 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
|
354 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
355 | 574bbf7b | bellard | if (isrv < 0) |
356 | 574bbf7b | bellard | isrv = 0;
|
357 | 574bbf7b | bellard | isrv >>= 4;
|
358 | 574bbf7b | bellard | if (tpr >= isrv)
|
359 | 574bbf7b | bellard | ppr = s->tpr; |
360 | 574bbf7b | bellard | else
|
361 | 574bbf7b | bellard | ppr = isrv << 4;
|
362 | 574bbf7b | bellard | return ppr;
|
363 | 574bbf7b | bellard | } |
364 | 574bbf7b | bellard | |
365 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
366 | d592d303 | bellard | { |
367 | d592d303 | bellard | /* XXX: arbitration */
|
368 | d592d303 | bellard | return 0; |
369 | d592d303 | bellard | } |
370 | d592d303 | bellard | |
371 | 574bbf7b | bellard | /* signal the CPU if an irq is pending */
|
372 | 574bbf7b | bellard | static void apic_update_irq(APICState *s) |
373 | 574bbf7b | bellard | { |
374 | d592d303 | bellard | int irrv, ppr;
|
375 | d592d303 | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
376 | d592d303 | bellard | return;
|
377 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
378 | 574bbf7b | bellard | if (irrv < 0) |
379 | 574bbf7b | bellard | return;
|
380 | d592d303 | bellard | ppr = apic_get_ppr(s); |
381 | d592d303 | bellard | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
382 | 574bbf7b | bellard | return;
|
383 | 574bbf7b | bellard | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
384 | 574bbf7b | bellard | } |
385 | 574bbf7b | bellard | |
386 | 73822ec8 | aliguori | void apic_reset_irq_delivered(void) |
387 | 73822ec8 | aliguori | { |
388 | 73822ec8 | aliguori | apic_irq_delivered = 0;
|
389 | 73822ec8 | aliguori | } |
390 | 73822ec8 | aliguori | |
391 | 73822ec8 | aliguori | int apic_get_irq_delivered(void) |
392 | 73822ec8 | aliguori | { |
393 | 73822ec8 | aliguori | return apic_irq_delivered;
|
394 | 73822ec8 | aliguori | } |
395 | 73822ec8 | aliguori | |
396 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
397 | 574bbf7b | bellard | { |
398 | 73822ec8 | aliguori | apic_irq_delivered += !get_bit(s->irr, vector_num); |
399 | 73822ec8 | aliguori | |
400 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
401 | 574bbf7b | bellard | if (trigger_mode)
|
402 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
403 | 574bbf7b | bellard | else
|
404 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
405 | 574bbf7b | bellard | apic_update_irq(s); |
406 | 574bbf7b | bellard | } |
407 | 574bbf7b | bellard | |
408 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
409 | 574bbf7b | bellard | { |
410 | 574bbf7b | bellard | int isrv;
|
411 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
412 | 574bbf7b | bellard | if (isrv < 0) |
413 | 574bbf7b | bellard | return;
|
414 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
415 | d592d303 | bellard | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
416 | d592d303 | bellard | set the remote IRR bit for level triggered interrupts. */
|
417 | 574bbf7b | bellard | apic_update_irq(s); |
418 | 574bbf7b | bellard | } |
419 | 574bbf7b | bellard | |
420 | 678e12cc | Gleb Natapov | static int apic_find_dest(uint8_t dest) |
421 | 678e12cc | Gleb Natapov | { |
422 | 678e12cc | Gleb Natapov | APICState *apic = local_apics[dest]; |
423 | 678e12cc | Gleb Natapov | int i;
|
424 | 678e12cc | Gleb Natapov | |
425 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
426 | 678e12cc | Gleb Natapov | return dest; /* shortcut in case apic->id == apic->idx */ |
427 | 678e12cc | Gleb Natapov | |
428 | 678e12cc | Gleb Natapov | for (i = 0; i < MAX_APICS; i++) { |
429 | 678e12cc | Gleb Natapov | apic = local_apics[i]; |
430 | 678e12cc | Gleb Natapov | if (apic && apic->id == dest)
|
431 | 678e12cc | Gleb Natapov | return i;
|
432 | 678e12cc | Gleb Natapov | } |
433 | 678e12cc | Gleb Natapov | |
434 | 678e12cc | Gleb Natapov | return -1; |
435 | 678e12cc | Gleb Natapov | } |
436 | 678e12cc | Gleb Natapov | |
437 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
438 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
439 | d592d303 | bellard | { |
440 | d592d303 | bellard | APICState *apic_iter; |
441 | d3e9db93 | bellard | int i;
|
442 | d592d303 | bellard | |
443 | d592d303 | bellard | if (dest_mode == 0) { |
444 | d3e9db93 | bellard | if (dest == 0xff) { |
445 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
446 | d3e9db93 | bellard | } else {
|
447 | 678e12cc | Gleb Natapov | int idx = apic_find_dest(dest);
|
448 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
449 | 678e12cc | Gleb Natapov | if (idx >= 0) |
450 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, idx); |
451 | d3e9db93 | bellard | } |
452 | d592d303 | bellard | } else {
|
453 | d592d303 | bellard | /* XXX: cluster mode */
|
454 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
455 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
456 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
457 | d3e9db93 | bellard | if (apic_iter) {
|
458 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
459 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
460 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
461 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
462 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
463 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
464 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
465 | d3e9db93 | bellard | } |
466 | d3e9db93 | bellard | } |
467 | d3e9db93 | bellard | } |
468 | d592d303 | bellard | } |
469 | d592d303 | bellard | } |
470 | d592d303 | bellard | } |
471 | d592d303 | bellard | |
472 | d592d303 | bellard | |
473 | b09ea7d5 | Gleb Natapov | void apic_init_reset(CPUState *env)
|
474 | d592d303 | bellard | { |
475 | b09ea7d5 | Gleb Natapov | APICState *s = env->apic_state; |
476 | d592d303 | bellard | int i;
|
477 | d592d303 | bellard | |
478 | b09ea7d5 | Gleb Natapov | if (!s)
|
479 | b09ea7d5 | Gleb Natapov | return;
|
480 | b09ea7d5 | Gleb Natapov | |
481 | d592d303 | bellard | s->tpr = 0;
|
482 | d592d303 | bellard | s->spurious_vec = 0xff;
|
483 | d592d303 | bellard | s->log_dest = 0;
|
484 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
485 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
486 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
487 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
488 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
489 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
490 | d592d303 | bellard | s->esr = 0;
|
491 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
492 | d592d303 | bellard | s->divide_conf = 0;
|
493 | d592d303 | bellard | s->count_shift = 0;
|
494 | d592d303 | bellard | s->initial_count = 0;
|
495 | d592d303 | bellard | s->initial_count_load_time = 0;
|
496 | d592d303 | bellard | s->next_time = 0;
|
497 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 1;
|
498 | 3003b8bb | aurel32 | |
499 | b09ea7d5 | Gleb Natapov | env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
500 | d592d303 | bellard | } |
501 | d592d303 | bellard | |
502 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
503 | e0fd8781 | bellard | { |
504 | b09ea7d5 | Gleb Natapov | s->sipi_vector = vector_num; |
505 | b09ea7d5 | Gleb Natapov | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
506 | b09ea7d5 | Gleb Natapov | } |
507 | b09ea7d5 | Gleb Natapov | |
508 | b09ea7d5 | Gleb Natapov | void apic_sipi(CPUState *env)
|
509 | b09ea7d5 | Gleb Natapov | { |
510 | b09ea7d5 | Gleb Natapov | APICState *s = env->apic_state; |
511 | b09ea7d5 | Gleb Natapov | |
512 | b09ea7d5 | Gleb Natapov | cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); |
513 | b09ea7d5 | Gleb Natapov | |
514 | b09ea7d5 | Gleb Natapov | if (!s->wait_for_sipi)
|
515 | e0fd8781 | bellard | return;
|
516 | b09ea7d5 | Gleb Natapov | |
517 | e0fd8781 | bellard | env->eip = 0;
|
518 | b09ea7d5 | Gleb Natapov | cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
519 | e0fd8781 | bellard | 0xffff, 0); |
520 | ce5232c5 | bellard | env->halted = 0;
|
521 | b09ea7d5 | Gleb Natapov | s->wait_for_sipi = 0;
|
522 | e0fd8781 | bellard | } |
523 | e0fd8781 | bellard | |
524 | d592d303 | bellard | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
525 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
526 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
527 | d592d303 | bellard | { |
528 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
529 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
530 | d592d303 | bellard | APICState *apic_iter; |
531 | d592d303 | bellard | |
532 | e0fd8781 | bellard | switch (dest_shorthand) {
|
533 | d3e9db93 | bellard | case 0: |
534 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
535 | d3e9db93 | bellard | break;
|
536 | d3e9db93 | bellard | case 1: |
537 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
538 | 678e12cc | Gleb Natapov | set_bit(deliver_bitmask, s->idx); |
539 | d3e9db93 | bellard | break;
|
540 | d3e9db93 | bellard | case 2: |
541 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
542 | d3e9db93 | bellard | break;
|
543 | d3e9db93 | bellard | case 3: |
544 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
545 | 678e12cc | Gleb Natapov | reset_bit(deliver_bitmask, s->idx); |
546 | d3e9db93 | bellard | break;
|
547 | e0fd8781 | bellard | } |
548 | e0fd8781 | bellard | |
549 | d592d303 | bellard | switch (delivery_mode) {
|
550 | d592d303 | bellard | case APIC_DM_INIT:
|
551 | d592d303 | bellard | { |
552 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
553 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
554 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
555 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
556 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
557 | d592d303 | bellard | return;
|
558 | d592d303 | bellard | } |
559 | d592d303 | bellard | } |
560 | d592d303 | bellard | break;
|
561 | d592d303 | bellard | |
562 | d592d303 | bellard | case APIC_DM_SIPI:
|
563 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
564 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
565 | d592d303 | bellard | return;
|
566 | d592d303 | bellard | } |
567 | d592d303 | bellard | |
568 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
569 | d592d303 | bellard | trigger_mode); |
570 | d592d303 | bellard | } |
571 | d592d303 | bellard | |
572 | 574bbf7b | bellard | int apic_get_interrupt(CPUState *env)
|
573 | 574bbf7b | bellard | { |
574 | 574bbf7b | bellard | APICState *s = env->apic_state; |
575 | 574bbf7b | bellard | int intno;
|
576 | 574bbf7b | bellard | |
577 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
578 | 574bbf7b | bellard | IRQs */
|
579 | 574bbf7b | bellard | if (!s)
|
580 | 574bbf7b | bellard | return -1; |
581 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
582 | 574bbf7b | bellard | return -1; |
583 | 3b46e624 | ths | |
584 | 574bbf7b | bellard | /* XXX: spurious IRQ handling */
|
585 | 574bbf7b | bellard | intno = get_highest_priority_int(s->irr); |
586 | 574bbf7b | bellard | if (intno < 0) |
587 | 574bbf7b | bellard | return -1; |
588 | d592d303 | bellard | if (s->tpr && intno <= s->tpr)
|
589 | d592d303 | bellard | return s->spurious_vec & 0xff; |
590 | b4511723 | bellard | reset_bit(s->irr, intno); |
591 | 574bbf7b | bellard | set_bit(s->isr, intno); |
592 | 574bbf7b | bellard | apic_update_irq(s); |
593 | 574bbf7b | bellard | return intno;
|
594 | 574bbf7b | bellard | } |
595 | 574bbf7b | bellard | |
596 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env)
|
597 | 0e21e12b | ths | { |
598 | 0e21e12b | ths | APICState *s = env->apic_state; |
599 | 0e21e12b | ths | uint32_t lvt0; |
600 | 0e21e12b | ths | |
601 | 0e21e12b | ths | if (!s)
|
602 | 0e21e12b | ths | return -1; |
603 | 0e21e12b | ths | |
604 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
605 | 0e21e12b | ths | |
606 | a5b38b51 | aurel32 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
607 | a5b38b51 | aurel32 | (lvt0 & APIC_LVT_MASKED) == 0)
|
608 | 0e21e12b | ths | return 1; |
609 | 0e21e12b | ths | |
610 | 0e21e12b | ths | return 0; |
611 | 0e21e12b | ths | } |
612 | 0e21e12b | ths | |
613 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
614 | 574bbf7b | bellard | { |
615 | 574bbf7b | bellard | int64_t d; |
616 | 574bbf7b | bellard | uint32_t val; |
617 | 5fafdf24 | ths | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
618 | 574bbf7b | bellard | s->count_shift; |
619 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
620 | 574bbf7b | bellard | /* periodic */
|
621 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
622 | 574bbf7b | bellard | } else {
|
623 | 574bbf7b | bellard | if (d >= s->initial_count)
|
624 | 574bbf7b | bellard | val = 0;
|
625 | 574bbf7b | bellard | else
|
626 | 574bbf7b | bellard | val = s->initial_count - d; |
627 | 574bbf7b | bellard | } |
628 | 574bbf7b | bellard | return val;
|
629 | 574bbf7b | bellard | } |
630 | 574bbf7b | bellard | |
631 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
632 | 574bbf7b | bellard | { |
633 | 574bbf7b | bellard | int64_t next_time, d; |
634 | 3b46e624 | ths | |
635 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
636 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
637 | 574bbf7b | bellard | s->count_shift; |
638 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
639 | 681f8c29 | aliguori | if (!s->initial_count)
|
640 | 681f8c29 | aliguori | goto no_timer;
|
641 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
642 | 574bbf7b | bellard | } else {
|
643 | 574bbf7b | bellard | if (d >= s->initial_count)
|
644 | 574bbf7b | bellard | goto no_timer;
|
645 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
646 | 574bbf7b | bellard | } |
647 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
648 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
649 | 574bbf7b | bellard | s->next_time = next_time; |
650 | 574bbf7b | bellard | } else {
|
651 | 574bbf7b | bellard | no_timer:
|
652 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
653 | 574bbf7b | bellard | } |
654 | 574bbf7b | bellard | } |
655 | 574bbf7b | bellard | |
656 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
657 | 574bbf7b | bellard | { |
658 | 574bbf7b | bellard | APICState *s = opaque; |
659 | 574bbf7b | bellard | |
660 | a5b38b51 | aurel32 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
661 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
662 | 574bbf7b | bellard | } |
663 | 574bbf7b | bellard | |
664 | 574bbf7b | bellard | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
665 | 574bbf7b | bellard | { |
666 | 574bbf7b | bellard | return 0; |
667 | 574bbf7b | bellard | } |
668 | 574bbf7b | bellard | |
669 | 574bbf7b | bellard | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
670 | 574bbf7b | bellard | { |
671 | 574bbf7b | bellard | return 0; |
672 | 574bbf7b | bellard | } |
673 | 574bbf7b | bellard | |
674 | 574bbf7b | bellard | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
675 | 574bbf7b | bellard | { |
676 | 574bbf7b | bellard | } |
677 | 574bbf7b | bellard | |
678 | 574bbf7b | bellard | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
679 | 574bbf7b | bellard | { |
680 | 574bbf7b | bellard | } |
681 | 574bbf7b | bellard | |
682 | 574bbf7b | bellard | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
683 | 574bbf7b | bellard | { |
684 | 574bbf7b | bellard | CPUState *env; |
685 | 574bbf7b | bellard | APICState *s; |
686 | 574bbf7b | bellard | uint32_t val; |
687 | 574bbf7b | bellard | int index;
|
688 | 574bbf7b | bellard | |
689 | 574bbf7b | bellard | env = cpu_single_env; |
690 | 574bbf7b | bellard | if (!env)
|
691 | 574bbf7b | bellard | return 0; |
692 | 574bbf7b | bellard | s = env->apic_state; |
693 | 574bbf7b | bellard | |
694 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
695 | 574bbf7b | bellard | switch(index) {
|
696 | 574bbf7b | bellard | case 0x02: /* id */ |
697 | 574bbf7b | bellard | val = s->id << 24;
|
698 | 574bbf7b | bellard | break;
|
699 | 574bbf7b | bellard | case 0x03: /* version */ |
700 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
701 | 574bbf7b | bellard | break;
|
702 | 574bbf7b | bellard | case 0x08: |
703 | 574bbf7b | bellard | val = s->tpr; |
704 | 574bbf7b | bellard | break;
|
705 | d592d303 | bellard | case 0x09: |
706 | d592d303 | bellard | val = apic_get_arb_pri(s); |
707 | d592d303 | bellard | break;
|
708 | 574bbf7b | bellard | case 0x0a: |
709 | 574bbf7b | bellard | /* ppr */
|
710 | 574bbf7b | bellard | val = apic_get_ppr(s); |
711 | 574bbf7b | bellard | break;
|
712 | b237db36 | aurel32 | case 0x0b: |
713 | b237db36 | aurel32 | val = 0;
|
714 | b237db36 | aurel32 | break;
|
715 | d592d303 | bellard | case 0x0d: |
716 | d592d303 | bellard | val = s->log_dest << 24;
|
717 | d592d303 | bellard | break;
|
718 | d592d303 | bellard | case 0x0e: |
719 | d592d303 | bellard | val = s->dest_mode << 28;
|
720 | d592d303 | bellard | break;
|
721 | 574bbf7b | bellard | case 0x0f: |
722 | 574bbf7b | bellard | val = s->spurious_vec; |
723 | 574bbf7b | bellard | break;
|
724 | 574bbf7b | bellard | case 0x10 ... 0x17: |
725 | 574bbf7b | bellard | val = s->isr[index & 7];
|
726 | 574bbf7b | bellard | break;
|
727 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
728 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
729 | 574bbf7b | bellard | break;
|
730 | 574bbf7b | bellard | case 0x20 ... 0x27: |
731 | 574bbf7b | bellard | val = s->irr[index & 7];
|
732 | 574bbf7b | bellard | break;
|
733 | 574bbf7b | bellard | case 0x28: |
734 | 574bbf7b | bellard | val = s->esr; |
735 | 574bbf7b | bellard | break;
|
736 | 574bbf7b | bellard | case 0x30: |
737 | 574bbf7b | bellard | case 0x31: |
738 | 574bbf7b | bellard | val = s->icr[index & 1];
|
739 | 574bbf7b | bellard | break;
|
740 | e0fd8781 | bellard | case 0x32 ... 0x37: |
741 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
742 | e0fd8781 | bellard | break;
|
743 | 574bbf7b | bellard | case 0x38: |
744 | 574bbf7b | bellard | val = s->initial_count; |
745 | 574bbf7b | bellard | break;
|
746 | 574bbf7b | bellard | case 0x39: |
747 | 574bbf7b | bellard | val = apic_get_current_count(s); |
748 | 574bbf7b | bellard | break;
|
749 | 574bbf7b | bellard | case 0x3e: |
750 | 574bbf7b | bellard | val = s->divide_conf; |
751 | 574bbf7b | bellard | break;
|
752 | 574bbf7b | bellard | default:
|
753 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
754 | 574bbf7b | bellard | val = 0;
|
755 | 574bbf7b | bellard | break;
|
756 | 574bbf7b | bellard | } |
757 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
758 | 574bbf7b | bellard | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
759 | 574bbf7b | bellard | #endif
|
760 | 574bbf7b | bellard | return val;
|
761 | 574bbf7b | bellard | } |
762 | 574bbf7b | bellard | |
763 | 54c96da7 | Michael S. Tsirkin | static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
764 | 54c96da7 | Michael S. Tsirkin | { |
765 | 54c96da7 | Michael S. Tsirkin | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
766 | 54c96da7 | Michael S. Tsirkin | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
767 | 54c96da7 | Michael S. Tsirkin | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
768 | 54c96da7 | Michael S. Tsirkin | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
769 | 54c96da7 | Michael S. Tsirkin | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
770 | 54c96da7 | Michael S. Tsirkin | /* XXX: Ignore redirection hint. */
|
771 | 54c96da7 | Michael S. Tsirkin | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
772 | 54c96da7 | Michael S. Tsirkin | } |
773 | 54c96da7 | Michael S. Tsirkin | |
774 | 574bbf7b | bellard | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
775 | 574bbf7b | bellard | { |
776 | 574bbf7b | bellard | CPUState *env; |
777 | 574bbf7b | bellard | APICState *s; |
778 | 54c96da7 | Michael S. Tsirkin | int index = (addr >> 4) & 0xff; |
779 | 54c96da7 | Michael S. Tsirkin | if (addr > 0xfff || !index) { |
780 | 54c96da7 | Michael S. Tsirkin | /* MSI and MMIO APIC are at the same memory location,
|
781 | 54c96da7 | Michael S. Tsirkin | * but actually not on the global bus: MSI is on PCI bus
|
782 | 54c96da7 | Michael S. Tsirkin | * APIC is connected directly to the CPU.
|
783 | 54c96da7 | Michael S. Tsirkin | * Mapping them on the global bus happens to work because
|
784 | 54c96da7 | Michael S. Tsirkin | * MSI registers are reserved in APIC MMIO and vice versa. */
|
785 | 54c96da7 | Michael S. Tsirkin | apic_send_msi(addr, val); |
786 | 54c96da7 | Michael S. Tsirkin | return;
|
787 | 54c96da7 | Michael S. Tsirkin | } |
788 | 574bbf7b | bellard | |
789 | 574bbf7b | bellard | env = cpu_single_env; |
790 | 574bbf7b | bellard | if (!env)
|
791 | 574bbf7b | bellard | return;
|
792 | 574bbf7b | bellard | s = env->apic_state; |
793 | 574bbf7b | bellard | |
794 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
795 | 574bbf7b | bellard | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
796 | 574bbf7b | bellard | #endif
|
797 | 574bbf7b | bellard | |
798 | 574bbf7b | bellard | switch(index) {
|
799 | 574bbf7b | bellard | case 0x02: |
800 | 574bbf7b | bellard | s->id = (val >> 24);
|
801 | 574bbf7b | bellard | break;
|
802 | e0fd8781 | bellard | case 0x03: |
803 | e0fd8781 | bellard | break;
|
804 | 574bbf7b | bellard | case 0x08: |
805 | 574bbf7b | bellard | s->tpr = val; |
806 | d592d303 | bellard | apic_update_irq(s); |
807 | 574bbf7b | bellard | break;
|
808 | e0fd8781 | bellard | case 0x09: |
809 | e0fd8781 | bellard | case 0x0a: |
810 | e0fd8781 | bellard | break;
|
811 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
812 | 574bbf7b | bellard | apic_eoi(s); |
813 | 574bbf7b | bellard | break;
|
814 | d592d303 | bellard | case 0x0d: |
815 | d592d303 | bellard | s->log_dest = val >> 24;
|
816 | d592d303 | bellard | break;
|
817 | d592d303 | bellard | case 0x0e: |
818 | d592d303 | bellard | s->dest_mode = val >> 28;
|
819 | d592d303 | bellard | break;
|
820 | 574bbf7b | bellard | case 0x0f: |
821 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
822 | d592d303 | bellard | apic_update_irq(s); |
823 | 574bbf7b | bellard | break;
|
824 | e0fd8781 | bellard | case 0x10 ... 0x17: |
825 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
826 | e0fd8781 | bellard | case 0x20 ... 0x27: |
827 | e0fd8781 | bellard | case 0x28: |
828 | e0fd8781 | bellard | break;
|
829 | 574bbf7b | bellard | case 0x30: |
830 | d592d303 | bellard | s->icr[0] = val;
|
831 | d592d303 | bellard | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
832 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
833 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
834 | d592d303 | bellard | break;
|
835 | 574bbf7b | bellard | case 0x31: |
836 | d592d303 | bellard | s->icr[1] = val;
|
837 | 574bbf7b | bellard | break;
|
838 | 574bbf7b | bellard | case 0x32 ... 0x37: |
839 | 574bbf7b | bellard | { |
840 | 574bbf7b | bellard | int n = index - 0x32; |
841 | 574bbf7b | bellard | s->lvt[n] = val; |
842 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
843 | 574bbf7b | bellard | apic_timer_update(s, qemu_get_clock(vm_clock)); |
844 | 574bbf7b | bellard | } |
845 | 574bbf7b | bellard | break;
|
846 | 574bbf7b | bellard | case 0x38: |
847 | 574bbf7b | bellard | s->initial_count = val; |
848 | 574bbf7b | bellard | s->initial_count_load_time = qemu_get_clock(vm_clock); |
849 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
850 | 574bbf7b | bellard | break;
|
851 | e0fd8781 | bellard | case 0x39: |
852 | e0fd8781 | bellard | break;
|
853 | 574bbf7b | bellard | case 0x3e: |
854 | 574bbf7b | bellard | { |
855 | 574bbf7b | bellard | int v;
|
856 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
857 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
858 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
859 | 574bbf7b | bellard | } |
860 | 574bbf7b | bellard | break;
|
861 | 574bbf7b | bellard | default:
|
862 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
863 | 574bbf7b | bellard | break;
|
864 | 574bbf7b | bellard | } |
865 | 574bbf7b | bellard | } |
866 | 574bbf7b | bellard | |
867 | 695dcf71 | Juan Quintela | /* This function is only used for old state version 1 and 2 */
|
868 | 695dcf71 | Juan Quintela | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
869 | d592d303 | bellard | { |
870 | d592d303 | bellard | APICState *s = opaque; |
871 | d592d303 | bellard | int i;
|
872 | d592d303 | bellard | |
873 | e6cf6a8c | bellard | if (version_id > 2) |
874 | d592d303 | bellard | return -EINVAL;
|
875 | d592d303 | bellard | |
876 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
877 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
878 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
879 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
880 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
881 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
882 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
883 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
884 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
885 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
886 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
887 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
888 | d592d303 | bellard | } |
889 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
890 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
891 | d592d303 | bellard | } |
892 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
893 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
894 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
895 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
896 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
897 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
898 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
899 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
900 | e6cf6a8c | bellard | |
901 | e6cf6a8c | bellard | if (version_id >= 2) |
902 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
903 | d592d303 | bellard | return 0; |
904 | d592d303 | bellard | } |
905 | 574bbf7b | bellard | |
906 | 695dcf71 | Juan Quintela | static const VMStateDescription vmstate_apic = { |
907 | 695dcf71 | Juan Quintela | .name = "apic",
|
908 | 695dcf71 | Juan Quintela | .version_id = 3,
|
909 | 695dcf71 | Juan Quintela | .minimum_version_id = 3,
|
910 | 695dcf71 | Juan Quintela | .minimum_version_id_old = 1,
|
911 | 695dcf71 | Juan Quintela | .load_state_old = apic_load_old, |
912 | 695dcf71 | Juan Quintela | .fields = (VMStateField []) { |
913 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(apicbase, APICState), |
914 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(id, APICState), |
915 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(arb_id, APICState), |
916 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(tpr, APICState), |
917 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(spurious_vec, APICState), |
918 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(log_dest, APICState), |
919 | 695dcf71 | Juan Quintela | VMSTATE_UINT8(dest_mode, APICState), |
920 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
921 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
922 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
923 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
924 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(esr, APICState), |
925 | 695dcf71 | Juan Quintela | VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
926 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(divide_conf, APICState), |
927 | 695dcf71 | Juan Quintela | VMSTATE_INT32(count_shift, APICState), |
928 | 695dcf71 | Juan Quintela | VMSTATE_UINT32(initial_count, APICState), |
929 | 695dcf71 | Juan Quintela | VMSTATE_INT64(initial_count_load_time, APICState), |
930 | 695dcf71 | Juan Quintela | VMSTATE_INT64(next_time, APICState), |
931 | 695dcf71 | Juan Quintela | VMSTATE_TIMER(timer, APICState), |
932 | 695dcf71 | Juan Quintela | VMSTATE_END_OF_LIST() |
933 | 695dcf71 | Juan Quintela | } |
934 | 695dcf71 | Juan Quintela | }; |
935 | 695dcf71 | Juan Quintela | |
936 | d592d303 | bellard | static void apic_reset(void *opaque) |
937 | d592d303 | bellard | { |
938 | d592d303 | bellard | APICState *s = opaque; |
939 | 4c0960c0 | Avi Kivity | int bsp;
|
940 | fec5fa02 | aurel32 | |
941 | 4c0960c0 | Avi Kivity | cpu_synchronize_state(s->cpu_env); |
942 | 4c0960c0 | Avi Kivity | |
943 | 4c0960c0 | Avi Kivity | bsp = cpu_is_bsp(s->cpu_env); |
944 | fec5fa02 | aurel32 | s->apicbase = 0xfee00000 |
|
945 | 678e12cc | Gleb Natapov | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
946 | fec5fa02 | aurel32 | |
947 | b09ea7d5 | Gleb Natapov | cpu_reset(s->cpu_env); |
948 | b09ea7d5 | Gleb Natapov | apic_init_reset(s->cpu_env); |
949 | 0e21e12b | ths | |
950 | 678e12cc | Gleb Natapov | if (bsp) {
|
951 | a5b38b51 | aurel32 | /*
|
952 | a5b38b51 | aurel32 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
953 | a5b38b51 | aurel32 | * time typically by BIOS, so PIC interrupt can be delivered to the
|
954 | a5b38b51 | aurel32 | * processor when local APIC is enabled.
|
955 | a5b38b51 | aurel32 | */
|
956 | a5b38b51 | aurel32 | s->lvt[APIC_LVT_LINT0] = 0x700;
|
957 | a5b38b51 | aurel32 | } |
958 | d592d303 | bellard | } |
959 | 574bbf7b | bellard | |
960 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
961 | 574bbf7b | bellard | apic_mem_readb, |
962 | 574bbf7b | bellard | apic_mem_readw, |
963 | 574bbf7b | bellard | apic_mem_readl, |
964 | 574bbf7b | bellard | }; |
965 | 574bbf7b | bellard | |
966 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
967 | 574bbf7b | bellard | apic_mem_writeb, |
968 | 574bbf7b | bellard | apic_mem_writew, |
969 | 574bbf7b | bellard | apic_mem_writel, |
970 | 574bbf7b | bellard | }; |
971 | 574bbf7b | bellard | |
972 | 574bbf7b | bellard | int apic_init(CPUState *env)
|
973 | 574bbf7b | bellard | { |
974 | 574bbf7b | bellard | APICState *s; |
975 | 574bbf7b | bellard | |
976 | 678e12cc | Gleb Natapov | if (last_apic_idx >= MAX_APICS)
|
977 | d3e9db93 | bellard | return -1; |
978 | d592d303 | bellard | s = qemu_mallocz(sizeof(APICState));
|
979 | 574bbf7b | bellard | env->apic_state = s; |
980 | 678e12cc | Gleb Natapov | s->idx = last_apic_idx++; |
981 | 678e12cc | Gleb Natapov | s->id = env->cpuid_apic_id; |
982 | 574bbf7b | bellard | s->cpu_env = env; |
983 | 574bbf7b | bellard | |
984 | a5b38b51 | aurel32 | apic_reset(s); |
985 | 54c96da7 | Michael S. Tsirkin | msix_supported = 1;
|
986 | 0e21e12b | ths | |
987 | d592d303 | bellard | /* XXX: mapping more APICs at the same memory location */
|
988 | 574bbf7b | bellard | if (apic_io_memory == 0) { |
989 | 574bbf7b | bellard | /* NOTE: the APIC is directly connected to the CPU - it is not
|
990 | 574bbf7b | bellard | on the global memory bus. */
|
991 | 1eed09cb | Avi Kivity | apic_io_memory = cpu_register_io_memory(apic_mem_read, |
992 | 574bbf7b | bellard | apic_mem_write, NULL);
|
993 | 54c96da7 | Michael S. Tsirkin | /* XXX: what if the base changes? */
|
994 | 54c96da7 | Michael S. Tsirkin | cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, |
995 | d592d303 | bellard | apic_io_memory); |
996 | 574bbf7b | bellard | } |
997 | 574bbf7b | bellard | s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
998 | d592d303 | bellard | |
999 | 695dcf71 | Juan Quintela | vmstate_register(s->idx, &vmstate_apic, s); |
1000 | a08d4367 | Jan Kiszka | qemu_register_reset(apic_reset, s); |
1001 | 3b46e624 | ths | |
1002 | 678e12cc | Gleb Natapov | local_apics[s->idx] = s; |
1003 | d592d303 | bellard | return 0; |
1004 | d592d303 | bellard | } |