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1 | 8977f3c1 | bellard | /*
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2 | 890fa6be | bellard | * QEMU Floppy disk emulator (Intel 82078)
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003, 2007 Jocelyn Mayer
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5 | 65cef780 | blueswir1 | * Copyright (c) 2008 Herv? Poussineau
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6 | 5fafdf24 | ths | *
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7 | 8977f3c1 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 8977f3c1 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 8977f3c1 | bellard | * in the Software without restriction, including without limitation the rights
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10 | 8977f3c1 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 8977f3c1 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 8977f3c1 | bellard | * furnished to do so, subject to the following conditions:
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13 | 8977f3c1 | bellard | *
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14 | 8977f3c1 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 8977f3c1 | bellard | * all copies or substantial portions of the Software.
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16 | 8977f3c1 | bellard | *
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17 | 8977f3c1 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 8977f3c1 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 8977f3c1 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 8977f3c1 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 8977f3c1 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 8977f3c1 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 8977f3c1 | bellard | * THE SOFTWARE.
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24 | 8977f3c1 | bellard | */
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25 | e80cfcfc | bellard | /*
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26 | e80cfcfc | bellard | * The controller is used in Sun4m systems in a slightly different
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27 | e80cfcfc | bellard | * way. There are changes in DOR register and DMA is not available.
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28 | e80cfcfc | bellard | */
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29 | f64ab228 | Blue Swirl | |
30 | 87ecb68b | pbrook | #include "hw.h" |
31 | 87ecb68b | pbrook | #include "fdc.h" |
32 | 87ecb68b | pbrook | #include "block.h" |
33 | 87ecb68b | pbrook | #include "qemu-timer.h" |
34 | 87ecb68b | pbrook | #include "isa.h" |
35 | f64ab228 | Blue Swirl | #include "sysbus.h" |
36 | e8133762 | Blue Swirl | #include "qdev-addr.h" |
37 | 8977f3c1 | bellard | |
38 | 8977f3c1 | bellard | /********************************************************/
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39 | 8977f3c1 | bellard | /* debug Floppy devices */
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40 | 8977f3c1 | bellard | //#define DEBUG_FLOPPY
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41 | 8977f3c1 | bellard | |
42 | 8977f3c1 | bellard | #ifdef DEBUG_FLOPPY
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43 | 001faf32 | Blue Swirl | #define FLOPPY_DPRINTF(fmt, ...) \
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44 | 001faf32 | Blue Swirl | do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) |
45 | 8977f3c1 | bellard | #else
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46 | 001faf32 | Blue Swirl | #define FLOPPY_DPRINTF(fmt, ...)
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47 | 8977f3c1 | bellard | #endif
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48 | 8977f3c1 | bellard | |
49 | 001faf32 | Blue Swirl | #define FLOPPY_ERROR(fmt, ...) \
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50 | 001faf32 | Blue Swirl | do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
51 | 8977f3c1 | bellard | |
52 | 8977f3c1 | bellard | /********************************************************/
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53 | 8977f3c1 | bellard | /* Floppy drive emulation */
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54 | 8977f3c1 | bellard | |
55 | cefec4f5 | blueswir1 | #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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56 | cefec4f5 | blueswir1 | #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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57 | cefec4f5 | blueswir1 | |
58 | 8977f3c1 | bellard | /* Will always be a fixed parameter for us */
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59 | f2d81b33 | blueswir1 | #define FD_SECTOR_LEN 512 |
60 | f2d81b33 | blueswir1 | #define FD_SECTOR_SC 2 /* Sector size code */ |
61 | f2d81b33 | blueswir1 | #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ |
62 | 8977f3c1 | bellard | |
63 | 8977f3c1 | bellard | /* Floppy disk drive emulation */
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64 | 8977f3c1 | bellard | typedef enum fdisk_type_t { |
65 | 8977f3c1 | bellard | FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */ |
66 | 8977f3c1 | bellard | FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */ |
67 | 8977f3c1 | bellard | FDRIVE_DISK_720 = 0x03, /* 720 kB disk */ |
68 | baca51fa | bellard | FDRIVE_DISK_USER = 0x04, /* User defined geometry */ |
69 | baca51fa | bellard | FDRIVE_DISK_NONE = 0x05, /* No disk */ |
70 | 8977f3c1 | bellard | } fdisk_type_t; |
71 | 8977f3c1 | bellard | |
72 | 8977f3c1 | bellard | typedef enum fdrive_type_t { |
73 | 8977f3c1 | bellard | FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */ |
74 | 8977f3c1 | bellard | FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */ |
75 | 8977f3c1 | bellard | FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */ |
76 | 8977f3c1 | bellard | FDRIVE_DRV_NONE = 0x03, /* No drive connected */ |
77 | 8977f3c1 | bellard | } fdrive_type_t; |
78 | 8977f3c1 | bellard | |
79 | baca51fa | bellard | typedef enum fdisk_flags_t { |
80 | baca51fa | bellard | FDISK_DBL_SIDES = 0x01,
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81 | baca51fa | bellard | } fdisk_flags_t; |
82 | baca51fa | bellard | |
83 | 8977f3c1 | bellard | typedef struct fdrive_t { |
84 | 8977f3c1 | bellard | BlockDriverState *bs; |
85 | 8977f3c1 | bellard | /* Drive status */
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86 | 8977f3c1 | bellard | fdrive_type_t drive; |
87 | 8977f3c1 | bellard | uint8_t perpendicular; /* 2.88 MB access mode */
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88 | 8977f3c1 | bellard | /* Position */
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89 | 8977f3c1 | bellard | uint8_t head; |
90 | 8977f3c1 | bellard | uint8_t track; |
91 | 8977f3c1 | bellard | uint8_t sect; |
92 | 8977f3c1 | bellard | /* Media */
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93 | baca51fa | bellard | fdisk_flags_t flags; |
94 | 8977f3c1 | bellard | uint8_t last_sect; /* Nb sector per track */
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95 | 8977f3c1 | bellard | uint8_t max_track; /* Nb of tracks */
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96 | baca51fa | bellard | uint16_t bps; /* Bytes per sector */
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97 | 8977f3c1 | bellard | uint8_t ro; /* Is read-only */
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98 | 8977f3c1 | bellard | } fdrive_t; |
99 | 8977f3c1 | bellard | |
100 | caed8802 | bellard | static void fd_init (fdrive_t *drv, BlockDriverState *bs) |
101 | 8977f3c1 | bellard | { |
102 | 8977f3c1 | bellard | /* Drive */
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103 | caed8802 | bellard | drv->bs = bs; |
104 | b939777c | bellard | drv->drive = FDRIVE_DRV_NONE; |
105 | 8977f3c1 | bellard | drv->perpendicular = 0;
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106 | 8977f3c1 | bellard | /* Disk */
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107 | baca51fa | bellard | drv->last_sect = 0;
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108 | 8977f3c1 | bellard | drv->max_track = 0;
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109 | 8977f3c1 | bellard | } |
110 | 8977f3c1 | bellard | |
111 | 8977f3c1 | bellard | static int _fd_sector (uint8_t head, uint8_t track, |
112 | 4f431960 | j_mayer | uint8_t sect, uint8_t last_sect) |
113 | 8977f3c1 | bellard | { |
114 | 8977f3c1 | bellard | return (((track * 2) + head) * last_sect) + sect - 1; |
115 | 8977f3c1 | bellard | } |
116 | 8977f3c1 | bellard | |
117 | 8977f3c1 | bellard | /* Returns current position, in sectors, for given drive */
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118 | 8977f3c1 | bellard | static int fd_sector (fdrive_t *drv) |
119 | 8977f3c1 | bellard | { |
120 | 8977f3c1 | bellard | return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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121 | 8977f3c1 | bellard | } |
122 | 8977f3c1 | bellard | |
123 | 77370520 | blueswir1 | /* Seek to a new position:
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124 | 77370520 | blueswir1 | * returns 0 if already on right track
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125 | 77370520 | blueswir1 | * returns 1 if track changed
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126 | 77370520 | blueswir1 | * returns 2 if track is invalid
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127 | 77370520 | blueswir1 | * returns 3 if sector is invalid
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128 | 77370520 | blueswir1 | * returns 4 if seek is disabled
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129 | 77370520 | blueswir1 | */
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130 | 8977f3c1 | bellard | static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect, |
131 | 8977f3c1 | bellard | int enable_seek)
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132 | 8977f3c1 | bellard | { |
133 | 8977f3c1 | bellard | uint32_t sector; |
134 | baca51fa | bellard | int ret;
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135 | baca51fa | bellard | |
136 | baca51fa | bellard | if (track > drv->max_track ||
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137 | 4f431960 | j_mayer | (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
138 | ed5fd2cc | bellard | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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139 | ed5fd2cc | bellard | head, track, sect, 1,
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140 | ed5fd2cc | bellard | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
141 | ed5fd2cc | bellard | drv->max_track, drv->last_sect); |
142 | 8977f3c1 | bellard | return 2; |
143 | 8977f3c1 | bellard | } |
144 | 8977f3c1 | bellard | if (sect > drv->last_sect) {
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145 | ed5fd2cc | bellard | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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146 | ed5fd2cc | bellard | head, track, sect, 1,
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147 | ed5fd2cc | bellard | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
148 | ed5fd2cc | bellard | drv->max_track, drv->last_sect); |
149 | 8977f3c1 | bellard | return 3; |
150 | 8977f3c1 | bellard | } |
151 | 8977f3c1 | bellard | sector = _fd_sector(head, track, sect, drv->last_sect); |
152 | baca51fa | bellard | ret = 0;
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153 | 8977f3c1 | bellard | if (sector != fd_sector(drv)) {
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154 | 8977f3c1 | bellard | #if 0
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155 | 8977f3c1 | bellard | if (!enable_seek) {
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156 | 8977f3c1 | bellard | FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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157 | 8977f3c1 | bellard | head, track, sect, 1, drv->max_track, drv->last_sect);
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158 | 8977f3c1 | bellard | return 4;
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159 | 8977f3c1 | bellard | }
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160 | 8977f3c1 | bellard | #endif
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161 | 8977f3c1 | bellard | drv->head = head; |
162 | 4f431960 | j_mayer | if (drv->track != track)
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163 | 4f431960 | j_mayer | ret = 1;
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164 | 8977f3c1 | bellard | drv->track = track; |
165 | 8977f3c1 | bellard | drv->sect = sect; |
166 | 8977f3c1 | bellard | } |
167 | 8977f3c1 | bellard | |
168 | baca51fa | bellard | return ret;
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169 | 8977f3c1 | bellard | } |
170 | 8977f3c1 | bellard | |
171 | 8977f3c1 | bellard | /* Set drive back to track 0 */
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172 | 8977f3c1 | bellard | static void fd_recalibrate (fdrive_t *drv) |
173 | 8977f3c1 | bellard | { |
174 | 8977f3c1 | bellard | FLOPPY_DPRINTF("recalibrate\n");
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175 | 8977f3c1 | bellard | drv->head = 0;
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176 | 8977f3c1 | bellard | drv->track = 0;
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177 | 8977f3c1 | bellard | drv->sect = 1;
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178 | 8977f3c1 | bellard | } |
179 | 8977f3c1 | bellard | |
180 | a541f297 | bellard | /* Recognize floppy formats */
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181 | a541f297 | bellard | typedef struct fd_format_t { |
182 | a541f297 | bellard | fdrive_type_t drive; |
183 | a541f297 | bellard | fdisk_type_t disk; |
184 | a541f297 | bellard | uint8_t last_sect; |
185 | a541f297 | bellard | uint8_t max_track; |
186 | a541f297 | bellard | uint8_t max_head; |
187 | 60fe76f3 | ths | const char *str; |
188 | a541f297 | bellard | } fd_format_t; |
189 | a541f297 | bellard | |
190 | 51a65271 | blueswir1 | static const fd_format_t fd_formats[] = { |
191 | a541f297 | bellard | /* First entry is default format */
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192 | a541f297 | bellard | /* 1.44 MB 3"1/2 floppy disks */
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193 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", }, |
194 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", }, |
195 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", }, |
196 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", }, |
197 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", }, |
198 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", }, |
199 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", }, |
200 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", }, |
201 | a541f297 | bellard | /* 2.88 MB 3"1/2 floppy disks */
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202 | a541f297 | bellard | { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", }, |
203 | a541f297 | bellard | { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", }, |
204 | a541f297 | bellard | { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", }, |
205 | a541f297 | bellard | { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", }, |
206 | a541f297 | bellard | { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", }, |
207 | a541f297 | bellard | /* 720 kB 3"1/2 floppy disks */
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208 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", }, |
209 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", }, |
210 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", }, |
211 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", }, |
212 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", }, |
213 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", }, |
214 | a541f297 | bellard | /* 1.2 MB 5"1/4 floppy disks */
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215 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", }, |
216 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", }, |
217 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", }, |
218 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", }, |
219 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", }, |
220 | a541f297 | bellard | /* 720 kB 5"1/4 floppy disks */
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221 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", }, |
222 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", }, |
223 | a541f297 | bellard | /* 360 kB 5"1/4 floppy disks */
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224 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", }, |
225 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", }, |
226 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", }, |
227 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", }, |
228 | 5fafdf24 | ths | /* 320 kB 5"1/4 floppy disks */
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229 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", }, |
230 | a541f297 | bellard | { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", }, |
231 | a541f297 | bellard | /* 360 kB must match 5"1/4 better than 3"1/2... */
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232 | a541f297 | bellard | { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", }, |
233 | a541f297 | bellard | /* end */
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234 | a541f297 | bellard | { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, }, |
235 | a541f297 | bellard | }; |
236 | a541f297 | bellard | |
237 | 8977f3c1 | bellard | /* Revalidate a disk drive after a disk change */
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238 | caed8802 | bellard | static void fd_revalidate (fdrive_t *drv) |
239 | 8977f3c1 | bellard | { |
240 | 51a65271 | blueswir1 | const fd_format_t *parse;
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241 | 96b8f136 | ths | uint64_t nb_sectors, size; |
242 | a541f297 | bellard | int i, first_match, match;
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243 | baca51fa | bellard | int nb_heads, max_track, last_sect, ro;
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244 | 8977f3c1 | bellard | |
245 | 8977f3c1 | bellard | FLOPPY_DPRINTF("revalidate\n");
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246 | a541f297 | bellard | if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { |
247 | 4f431960 | j_mayer | ro = bdrv_is_read_only(drv->bs); |
248 | 4f431960 | j_mayer | bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect); |
249 | 4f431960 | j_mayer | if (nb_heads != 0 && max_track != 0 && last_sect != 0) { |
250 | 4f431960 | j_mayer | FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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251 | ed5fd2cc | bellard | nb_heads - 1, max_track, last_sect);
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252 | 4f431960 | j_mayer | } else {
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253 | 4f431960 | j_mayer | bdrv_get_geometry(drv->bs, &nb_sectors); |
254 | 4f431960 | j_mayer | match = -1;
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255 | 4f431960 | j_mayer | first_match = -1;
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256 | 4f431960 | j_mayer | for (i = 0;; i++) { |
257 | 4f431960 | j_mayer | parse = &fd_formats[i]; |
258 | 4f431960 | j_mayer | if (parse->drive == FDRIVE_DRV_NONE)
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259 | 4f431960 | j_mayer | break;
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260 | 4f431960 | j_mayer | if (drv->drive == parse->drive ||
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261 | 4f431960 | j_mayer | drv->drive == FDRIVE_DRV_NONE) { |
262 | 4f431960 | j_mayer | size = (parse->max_head + 1) * parse->max_track *
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263 | 4f431960 | j_mayer | parse->last_sect; |
264 | 4f431960 | j_mayer | if (nb_sectors == size) {
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265 | 4f431960 | j_mayer | match = i; |
266 | 4f431960 | j_mayer | break;
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267 | 4f431960 | j_mayer | } |
268 | 4f431960 | j_mayer | if (first_match == -1) |
269 | 4f431960 | j_mayer | first_match = i; |
270 | 4f431960 | j_mayer | } |
271 | 4f431960 | j_mayer | } |
272 | 4f431960 | j_mayer | if (match == -1) { |
273 | 4f431960 | j_mayer | if (first_match == -1) |
274 | 4f431960 | j_mayer | match = 1;
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275 | 4f431960 | j_mayer | else
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276 | 4f431960 | j_mayer | match = first_match; |
277 | 4f431960 | j_mayer | parse = &fd_formats[match]; |
278 | 4f431960 | j_mayer | } |
279 | 4f431960 | j_mayer | nb_heads = parse->max_head + 1;
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280 | 4f431960 | j_mayer | max_track = parse->max_track; |
281 | 4f431960 | j_mayer | last_sect = parse->last_sect; |
282 | 4f431960 | j_mayer | drv->drive = parse->drive; |
283 | 4f431960 | j_mayer | FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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284 | ed5fd2cc | bellard | nb_heads, max_track, last_sect, ro ? "ro" : "rw"); |
285 | 4f431960 | j_mayer | } |
286 | 4f431960 | j_mayer | if (nb_heads == 1) { |
287 | 4f431960 | j_mayer | drv->flags &= ~FDISK_DBL_SIDES; |
288 | 4f431960 | j_mayer | } else {
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289 | 4f431960 | j_mayer | drv->flags |= FDISK_DBL_SIDES; |
290 | 4f431960 | j_mayer | } |
291 | 4f431960 | j_mayer | drv->max_track = max_track; |
292 | 4f431960 | j_mayer | drv->last_sect = last_sect; |
293 | 4f431960 | j_mayer | drv->ro = ro; |
294 | 8977f3c1 | bellard | } else {
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295 | 4f431960 | j_mayer | FLOPPY_DPRINTF("No disk in drive\n");
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296 | baca51fa | bellard | drv->last_sect = 0;
|
297 | 4f431960 | j_mayer | drv->max_track = 0;
|
298 | 4f431960 | j_mayer | drv->flags &= ~FDISK_DBL_SIDES; |
299 | 8977f3c1 | bellard | } |
300 | caed8802 | bellard | } |
301 | caed8802 | bellard | |
302 | 8977f3c1 | bellard | /********************************************************/
|
303 | 4b19ec0c | bellard | /* Intel 82078 floppy disk controller emulation */
|
304 | 8977f3c1 | bellard | |
305 | baca51fa | bellard | static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq); |
306 | baca51fa | bellard | static void fdctrl_reset_fifo (fdctrl_t *fdctrl); |
307 | 85571bc7 | bellard | static int fdctrl_transfer_handler (void *opaque, int nchan, |
308 | 85571bc7 | bellard | int dma_pos, int dma_len); |
309 | 77370520 | blueswir1 | static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0); |
310 | baca51fa | bellard | |
311 | 8c6a4d77 | blueswir1 | static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
|
312 | baca51fa | bellard | static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
|
313 | baca51fa | bellard | static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
|
314 | baca51fa | bellard | static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value); |
315 | baca51fa | bellard | static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
|
316 | baca51fa | bellard | static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value); |
317 | baca51fa | bellard | static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
|
318 | baca51fa | bellard | static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value); |
319 | baca51fa | bellard | static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
|
320 | baca51fa | bellard | static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value); |
321 | baca51fa | bellard | static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
|
322 | 8977f3c1 | bellard | |
323 | 8977f3c1 | bellard | enum {
|
324 | 8977f3c1 | bellard | FD_DIR_WRITE = 0,
|
325 | 8977f3c1 | bellard | FD_DIR_READ = 1,
|
326 | 8977f3c1 | bellard | FD_DIR_SCANE = 2,
|
327 | 8977f3c1 | bellard | FD_DIR_SCANL = 3,
|
328 | 8977f3c1 | bellard | FD_DIR_SCANH = 4,
|
329 | 8977f3c1 | bellard | }; |
330 | 8977f3c1 | bellard | |
331 | 8977f3c1 | bellard | enum {
|
332 | b9b3d225 | blueswir1 | FD_STATE_MULTI = 0x01, /* multi track flag */ |
333 | b9b3d225 | blueswir1 | FD_STATE_FORMAT = 0x02, /* format flag */ |
334 | b9b3d225 | blueswir1 | FD_STATE_SEEK = 0x04, /* seek flag */ |
335 | 8977f3c1 | bellard | }; |
336 | 8977f3c1 | bellard | |
337 | 9fea808a | blueswir1 | enum {
|
338 | 8c6a4d77 | blueswir1 | FD_REG_SRA = 0x00,
|
339 | 8c6a4d77 | blueswir1 | FD_REG_SRB = 0x01,
|
340 | 9fea808a | blueswir1 | FD_REG_DOR = 0x02,
|
341 | 9fea808a | blueswir1 | FD_REG_TDR = 0x03,
|
342 | 9fea808a | blueswir1 | FD_REG_MSR = 0x04,
|
343 | 9fea808a | blueswir1 | FD_REG_DSR = 0x04,
|
344 | 9fea808a | blueswir1 | FD_REG_FIFO = 0x05,
|
345 | 9fea808a | blueswir1 | FD_REG_DIR = 0x07,
|
346 | 9fea808a | blueswir1 | }; |
347 | 9fea808a | blueswir1 | |
348 | 9fea808a | blueswir1 | enum {
|
349 | 65cef780 | blueswir1 | FD_CMD_READ_TRACK = 0x02,
|
350 | 9fea808a | blueswir1 | FD_CMD_SPECIFY = 0x03,
|
351 | 9fea808a | blueswir1 | FD_CMD_SENSE_DRIVE_STATUS = 0x04,
|
352 | 65cef780 | blueswir1 | FD_CMD_WRITE = 0x05,
|
353 | 65cef780 | blueswir1 | FD_CMD_READ = 0x06,
|
354 | 9fea808a | blueswir1 | FD_CMD_RECALIBRATE = 0x07,
|
355 | 9fea808a | blueswir1 | FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
|
356 | 65cef780 | blueswir1 | FD_CMD_WRITE_DELETED = 0x09,
|
357 | 65cef780 | blueswir1 | FD_CMD_READ_ID = 0x0a,
|
358 | 65cef780 | blueswir1 | FD_CMD_READ_DELETED = 0x0c,
|
359 | 65cef780 | blueswir1 | FD_CMD_FORMAT_TRACK = 0x0d,
|
360 | 9fea808a | blueswir1 | FD_CMD_DUMPREG = 0x0e,
|
361 | 9fea808a | blueswir1 | FD_CMD_SEEK = 0x0f,
|
362 | 9fea808a | blueswir1 | FD_CMD_VERSION = 0x10,
|
363 | 65cef780 | blueswir1 | FD_CMD_SCAN_EQUAL = 0x11,
|
364 | 9fea808a | blueswir1 | FD_CMD_PERPENDICULAR_MODE = 0x12,
|
365 | 9fea808a | blueswir1 | FD_CMD_CONFIGURE = 0x13,
|
366 | 65cef780 | blueswir1 | FD_CMD_LOCK = 0x14,
|
367 | 65cef780 | blueswir1 | FD_CMD_VERIFY = 0x16,
|
368 | 9fea808a | blueswir1 | FD_CMD_POWERDOWN_MODE = 0x17,
|
369 | 9fea808a | blueswir1 | FD_CMD_PART_ID = 0x18,
|
370 | 65cef780 | blueswir1 | FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
|
371 | 65cef780 | blueswir1 | FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
|
372 | 9fea808a | blueswir1 | FD_CMD_SAVE = 0x2c,
|
373 | 9fea808a | blueswir1 | FD_CMD_OPTION = 0x33,
|
374 | 9fea808a | blueswir1 | FD_CMD_RESTORE = 0x4c,
|
375 | 9fea808a | blueswir1 | FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
|
376 | 9fea808a | blueswir1 | FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
|
377 | 9fea808a | blueswir1 | FD_CMD_FORMAT_AND_WRITE = 0xcd,
|
378 | 9fea808a | blueswir1 | FD_CMD_RELATIVE_SEEK_IN = 0xcf,
|
379 | 9fea808a | blueswir1 | }; |
380 | 9fea808a | blueswir1 | |
381 | 9fea808a | blueswir1 | enum {
|
382 | 9fea808a | blueswir1 | FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ |
383 | 9fea808a | blueswir1 | FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ |
384 | 9fea808a | blueswir1 | FD_CONFIG_POLL = 0x10, /* Poll enabled */ |
385 | 9fea808a | blueswir1 | FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ |
386 | 9fea808a | blueswir1 | FD_CONFIG_EIS = 0x40, /* No implied seeks */ |
387 | 9fea808a | blueswir1 | }; |
388 | 9fea808a | blueswir1 | |
389 | 9fea808a | blueswir1 | enum {
|
390 | 9fea808a | blueswir1 | FD_SR0_EQPMT = 0x10,
|
391 | 9fea808a | blueswir1 | FD_SR0_SEEK = 0x20,
|
392 | 9fea808a | blueswir1 | FD_SR0_ABNTERM = 0x40,
|
393 | 9fea808a | blueswir1 | FD_SR0_INVCMD = 0x80,
|
394 | 9fea808a | blueswir1 | FD_SR0_RDYCHG = 0xc0,
|
395 | 9fea808a | blueswir1 | }; |
396 | 9fea808a | blueswir1 | |
397 | 9fea808a | blueswir1 | enum {
|
398 | 77370520 | blueswir1 | FD_SR1_EC = 0x80, /* End of cylinder */ |
399 | 77370520 | blueswir1 | }; |
400 | 77370520 | blueswir1 | |
401 | 77370520 | blueswir1 | enum {
|
402 | 77370520 | blueswir1 | FD_SR2_SNS = 0x04, /* Scan not satisfied */ |
403 | 77370520 | blueswir1 | FD_SR2_SEH = 0x08, /* Scan equal hit */ |
404 | 77370520 | blueswir1 | }; |
405 | 77370520 | blueswir1 | |
406 | 77370520 | blueswir1 | enum {
|
407 | 8c6a4d77 | blueswir1 | FD_SRA_DIR = 0x01,
|
408 | 8c6a4d77 | blueswir1 | FD_SRA_nWP = 0x02,
|
409 | 8c6a4d77 | blueswir1 | FD_SRA_nINDX = 0x04,
|
410 | 8c6a4d77 | blueswir1 | FD_SRA_HDSEL = 0x08,
|
411 | 8c6a4d77 | blueswir1 | FD_SRA_nTRK0 = 0x10,
|
412 | 8c6a4d77 | blueswir1 | FD_SRA_STEP = 0x20,
|
413 | 8c6a4d77 | blueswir1 | FD_SRA_nDRV2 = 0x40,
|
414 | 8c6a4d77 | blueswir1 | FD_SRA_INTPEND = 0x80,
|
415 | 8c6a4d77 | blueswir1 | }; |
416 | 8c6a4d77 | blueswir1 | |
417 | 8c6a4d77 | blueswir1 | enum {
|
418 | 8c6a4d77 | blueswir1 | FD_SRB_MTR0 = 0x01,
|
419 | 8c6a4d77 | blueswir1 | FD_SRB_MTR1 = 0x02,
|
420 | 8c6a4d77 | blueswir1 | FD_SRB_WGATE = 0x04,
|
421 | 8c6a4d77 | blueswir1 | FD_SRB_RDATA = 0x08,
|
422 | 8c6a4d77 | blueswir1 | FD_SRB_WDATA = 0x10,
|
423 | 8c6a4d77 | blueswir1 | FD_SRB_DR0 = 0x20,
|
424 | 8c6a4d77 | blueswir1 | }; |
425 | 8c6a4d77 | blueswir1 | |
426 | 8c6a4d77 | blueswir1 | enum {
|
427 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
428 | 78ae820c | blueswir1 | FD_DOR_SELMASK = 0x03,
|
429 | 78ae820c | blueswir1 | #else
|
430 | 9fea808a | blueswir1 | FD_DOR_SELMASK = 0x01,
|
431 | 78ae820c | blueswir1 | #endif
|
432 | 9fea808a | blueswir1 | FD_DOR_nRESET = 0x04,
|
433 | 9fea808a | blueswir1 | FD_DOR_DMAEN = 0x08,
|
434 | 9fea808a | blueswir1 | FD_DOR_MOTEN0 = 0x10,
|
435 | 9fea808a | blueswir1 | FD_DOR_MOTEN1 = 0x20,
|
436 | 9fea808a | blueswir1 | FD_DOR_MOTEN2 = 0x40,
|
437 | 9fea808a | blueswir1 | FD_DOR_MOTEN3 = 0x80,
|
438 | 9fea808a | blueswir1 | }; |
439 | 9fea808a | blueswir1 | |
440 | 9fea808a | blueswir1 | enum {
|
441 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
442 | 9fea808a | blueswir1 | FD_TDR_BOOTSEL = 0x0c,
|
443 | 78ae820c | blueswir1 | #else
|
444 | 78ae820c | blueswir1 | FD_TDR_BOOTSEL = 0x04,
|
445 | 78ae820c | blueswir1 | #endif
|
446 | 9fea808a | blueswir1 | }; |
447 | 9fea808a | blueswir1 | |
448 | 9fea808a | blueswir1 | enum {
|
449 | 9fea808a | blueswir1 | FD_DSR_DRATEMASK= 0x03,
|
450 | 9fea808a | blueswir1 | FD_DSR_PWRDOWN = 0x40,
|
451 | 9fea808a | blueswir1 | FD_DSR_SWRESET = 0x80,
|
452 | 9fea808a | blueswir1 | }; |
453 | 9fea808a | blueswir1 | |
454 | 9fea808a | blueswir1 | enum {
|
455 | 9fea808a | blueswir1 | FD_MSR_DRV0BUSY = 0x01,
|
456 | 9fea808a | blueswir1 | FD_MSR_DRV1BUSY = 0x02,
|
457 | 9fea808a | blueswir1 | FD_MSR_DRV2BUSY = 0x04,
|
458 | 9fea808a | blueswir1 | FD_MSR_DRV3BUSY = 0x08,
|
459 | 9fea808a | blueswir1 | FD_MSR_CMDBUSY = 0x10,
|
460 | 9fea808a | blueswir1 | FD_MSR_NONDMA = 0x20,
|
461 | 9fea808a | blueswir1 | FD_MSR_DIO = 0x40,
|
462 | 9fea808a | blueswir1 | FD_MSR_RQM = 0x80,
|
463 | 9fea808a | blueswir1 | }; |
464 | 9fea808a | blueswir1 | |
465 | 9fea808a | blueswir1 | enum {
|
466 | 9fea808a | blueswir1 | FD_DIR_DSKCHG = 0x80,
|
467 | 9fea808a | blueswir1 | }; |
468 | 9fea808a | blueswir1 | |
469 | 8977f3c1 | bellard | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
|
470 | 8977f3c1 | bellard | #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
|
471 | baca51fa | bellard | #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
|
472 | 8977f3c1 | bellard | |
473 | baca51fa | bellard | struct fdctrl_t {
|
474 | 4b19ec0c | bellard | /* Controller's identification */
|
475 | 8977f3c1 | bellard | uint8_t version; |
476 | 8977f3c1 | bellard | /* HW */
|
477 | d537cf6c | pbrook | qemu_irq irq; |
478 | 8977f3c1 | bellard | int dma_chann;
|
479 | 4b19ec0c | bellard | /* Controller state */
|
480 | ed5fd2cc | bellard | QEMUTimer *result_timer; |
481 | 8c6a4d77 | blueswir1 | uint8_t sra; |
482 | 8c6a4d77 | blueswir1 | uint8_t srb; |
483 | 368df94d | blueswir1 | uint8_t dor; |
484 | 46d3233b | blueswir1 | uint8_t tdr; |
485 | b9b3d225 | blueswir1 | uint8_t dsr; |
486 | 368df94d | blueswir1 | uint8_t msr; |
487 | 8977f3c1 | bellard | uint8_t cur_drv; |
488 | 77370520 | blueswir1 | uint8_t status0; |
489 | 77370520 | blueswir1 | uint8_t status1; |
490 | 77370520 | blueswir1 | uint8_t status2; |
491 | 8977f3c1 | bellard | /* Command FIFO */
|
492 | 33f00271 | balrog | uint8_t *fifo; |
493 | 8977f3c1 | bellard | uint32_t data_pos; |
494 | 8977f3c1 | bellard | uint32_t data_len; |
495 | 8977f3c1 | bellard | uint8_t data_state; |
496 | 8977f3c1 | bellard | uint8_t data_dir; |
497 | 890fa6be | bellard | uint8_t eot; /* last wanted sector */
|
498 | 8977f3c1 | bellard | /* States kept only to be returned back */
|
499 | 8977f3c1 | bellard | /* Timers state */
|
500 | 8977f3c1 | bellard | uint8_t timer0; |
501 | 8977f3c1 | bellard | uint8_t timer1; |
502 | 8977f3c1 | bellard | /* precompensation */
|
503 | 8977f3c1 | bellard | uint8_t precomp_trk; |
504 | 8977f3c1 | bellard | uint8_t config; |
505 | 8977f3c1 | bellard | uint8_t lock; |
506 | 8977f3c1 | bellard | /* Power down config (also with status regB access mode */
|
507 | 8977f3c1 | bellard | uint8_t pwrd; |
508 | 741402f9 | blueswir1 | /* Sun4m quirks? */
|
509 | a06e5a3c | blueswir1 | int sun4m;
|
510 | 8977f3c1 | bellard | /* Floppy drives */
|
511 | 78ae820c | blueswir1 | fdrive_t drives[MAX_FD]; |
512 | f2d81b33 | blueswir1 | int reset_sensei;
|
513 | baca51fa | bellard | }; |
514 | baca51fa | bellard | |
515 | 8baf73ad | Gerd Hoffmann | typedef struct fdctrl_sysbus_t { |
516 | 8baf73ad | Gerd Hoffmann | SysBusDevice busdev; |
517 | 8baf73ad | Gerd Hoffmann | struct fdctrl_t state;
|
518 | 8baf73ad | Gerd Hoffmann | } fdctrl_sysbus_t; |
519 | 8baf73ad | Gerd Hoffmann | |
520 | 8baf73ad | Gerd Hoffmann | typedef struct fdctrl_isabus_t { |
521 | 8baf73ad | Gerd Hoffmann | ISADevice busdev; |
522 | 8baf73ad | Gerd Hoffmann | struct fdctrl_t state;
|
523 | 8baf73ad | Gerd Hoffmann | } fdctrl_isabus_t; |
524 | 8baf73ad | Gerd Hoffmann | |
525 | baca51fa | bellard | static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
526 | baca51fa | bellard | { |
527 | baca51fa | bellard | fdctrl_t *fdctrl = opaque; |
528 | baca51fa | bellard | uint32_t retval; |
529 | baca51fa | bellard | |
530 | e64d7d59 | blueswir1 | switch (reg) {
|
531 | 8c6a4d77 | blueswir1 | case FD_REG_SRA:
|
532 | 8c6a4d77 | blueswir1 | retval = fdctrl_read_statusA(fdctrl); |
533 | 4f431960 | j_mayer | break;
|
534 | 8c6a4d77 | blueswir1 | case FD_REG_SRB:
|
535 | 4f431960 | j_mayer | retval = fdctrl_read_statusB(fdctrl); |
536 | 4f431960 | j_mayer | break;
|
537 | 9fea808a | blueswir1 | case FD_REG_DOR:
|
538 | 4f431960 | j_mayer | retval = fdctrl_read_dor(fdctrl); |
539 | 4f431960 | j_mayer | break;
|
540 | 9fea808a | blueswir1 | case FD_REG_TDR:
|
541 | baca51fa | bellard | retval = fdctrl_read_tape(fdctrl); |
542 | 4f431960 | j_mayer | break;
|
543 | 9fea808a | blueswir1 | case FD_REG_MSR:
|
544 | baca51fa | bellard | retval = fdctrl_read_main_status(fdctrl); |
545 | 4f431960 | j_mayer | break;
|
546 | 9fea808a | blueswir1 | case FD_REG_FIFO:
|
547 | baca51fa | bellard | retval = fdctrl_read_data(fdctrl); |
548 | 4f431960 | j_mayer | break;
|
549 | 9fea808a | blueswir1 | case FD_REG_DIR:
|
550 | baca51fa | bellard | retval = fdctrl_read_dir(fdctrl); |
551 | 4f431960 | j_mayer | break;
|
552 | a541f297 | bellard | default:
|
553 | 4f431960 | j_mayer | retval = (uint32_t)(-1);
|
554 | 4f431960 | j_mayer | break;
|
555 | a541f297 | bellard | } |
556 | ed5fd2cc | bellard | FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
557 | baca51fa | bellard | |
558 | baca51fa | bellard | return retval;
|
559 | baca51fa | bellard | } |
560 | baca51fa | bellard | |
561 | baca51fa | bellard | static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) |
562 | baca51fa | bellard | { |
563 | baca51fa | bellard | fdctrl_t *fdctrl = opaque; |
564 | baca51fa | bellard | |
565 | ed5fd2cc | bellard | FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
566 | ed5fd2cc | bellard | |
567 | e64d7d59 | blueswir1 | switch (reg) {
|
568 | 9fea808a | blueswir1 | case FD_REG_DOR:
|
569 | 4f431960 | j_mayer | fdctrl_write_dor(fdctrl, value); |
570 | 4f431960 | j_mayer | break;
|
571 | 9fea808a | blueswir1 | case FD_REG_TDR:
|
572 | baca51fa | bellard | fdctrl_write_tape(fdctrl, value); |
573 | 4f431960 | j_mayer | break;
|
574 | 9fea808a | blueswir1 | case FD_REG_DSR:
|
575 | baca51fa | bellard | fdctrl_write_rate(fdctrl, value); |
576 | 4f431960 | j_mayer | break;
|
577 | 9fea808a | blueswir1 | case FD_REG_FIFO:
|
578 | baca51fa | bellard | fdctrl_write_data(fdctrl, value); |
579 | 4f431960 | j_mayer | break;
|
580 | a541f297 | bellard | default:
|
581 | 4f431960 | j_mayer | break;
|
582 | a541f297 | bellard | } |
583 | baca51fa | bellard | } |
584 | baca51fa | bellard | |
585 | e64d7d59 | blueswir1 | static uint32_t fdctrl_read_port (void *opaque, uint32_t reg) |
586 | e64d7d59 | blueswir1 | { |
587 | e64d7d59 | blueswir1 | return fdctrl_read(opaque, reg & 7); |
588 | e64d7d59 | blueswir1 | } |
589 | e64d7d59 | blueswir1 | |
590 | e64d7d59 | blueswir1 | static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) |
591 | e64d7d59 | blueswir1 | { |
592 | e64d7d59 | blueswir1 | fdctrl_write(opaque, reg & 7, value);
|
593 | e64d7d59 | blueswir1 | } |
594 | e64d7d59 | blueswir1 | |
595 | 62a46c61 | bellard | static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
596 | 62a46c61 | bellard | { |
597 | 5dcb6b91 | blueswir1 | return fdctrl_read(opaque, (uint32_t)reg);
|
598 | 62a46c61 | bellard | } |
599 | 62a46c61 | bellard | |
600 | 5fafdf24 | ths | static void fdctrl_write_mem (void *opaque, |
601 | 62a46c61 | bellard | target_phys_addr_t reg, uint32_t value) |
602 | 62a46c61 | bellard | { |
603 | 5dcb6b91 | blueswir1 | fdctrl_write(opaque, (uint32_t)reg, value); |
604 | 62a46c61 | bellard | } |
605 | 62a46c61 | bellard | |
606 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const fdctrl_mem_read[3] = { |
607 | 62a46c61 | bellard | fdctrl_read_mem, |
608 | 62a46c61 | bellard | fdctrl_read_mem, |
609 | 62a46c61 | bellard | fdctrl_read_mem, |
610 | e80cfcfc | bellard | }; |
611 | e80cfcfc | bellard | |
612 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = { |
613 | 62a46c61 | bellard | fdctrl_write_mem, |
614 | 62a46c61 | bellard | fdctrl_write_mem, |
615 | 62a46c61 | bellard | fdctrl_write_mem, |
616 | e80cfcfc | bellard | }; |
617 | e80cfcfc | bellard | |
618 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = { |
619 | 7c560456 | blueswir1 | fdctrl_read_mem, |
620 | 7c560456 | blueswir1 | NULL,
|
621 | 7c560456 | blueswir1 | NULL,
|
622 | 7c560456 | blueswir1 | }; |
623 | 7c560456 | blueswir1 | |
624 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = { |
625 | 7c560456 | blueswir1 | fdctrl_write_mem, |
626 | 7c560456 | blueswir1 | NULL,
|
627 | 7c560456 | blueswir1 | NULL,
|
628 | 7c560456 | blueswir1 | }; |
629 | 7c560456 | blueswir1 | |
630 | 3ccacc4a | blueswir1 | static void fd_save (QEMUFile *f, fdrive_t *fd) |
631 | 3ccacc4a | blueswir1 | { |
632 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &fd->head); |
633 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &fd->track); |
634 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &fd->sect); |
635 | 3ccacc4a | blueswir1 | } |
636 | 3ccacc4a | blueswir1 | |
637 | 3ccacc4a | blueswir1 | static void fdc_save (QEMUFile *f, void *opaque) |
638 | 3ccacc4a | blueswir1 | { |
639 | 3ccacc4a | blueswir1 | fdctrl_t *s = opaque; |
640 | 78ae820c | blueswir1 | uint8_t tmp; |
641 | 78ae820c | blueswir1 | int i;
|
642 | cefec4f5 | blueswir1 | uint8_t dor = s->dor | GET_CUR_DRV(s); |
643 | 3ccacc4a | blueswir1 | |
644 | 8c6a4d77 | blueswir1 | /* Controller state */
|
645 | 8c6a4d77 | blueswir1 | qemu_put_8s(f, &s->sra); |
646 | 8c6a4d77 | blueswir1 | qemu_put_8s(f, &s->srb); |
647 | cefec4f5 | blueswir1 | qemu_put_8s(f, &dor); |
648 | 46d3233b | blueswir1 | qemu_put_8s(f, &s->tdr); |
649 | 77370520 | blueswir1 | qemu_put_8s(f, &s->dsr); |
650 | 77370520 | blueswir1 | qemu_put_8s(f, &s->msr); |
651 | 77370520 | blueswir1 | qemu_put_8s(f, &s->status0); |
652 | 77370520 | blueswir1 | qemu_put_8s(f, &s->status1); |
653 | 77370520 | blueswir1 | qemu_put_8s(f, &s->status2); |
654 | 77370520 | blueswir1 | /* Command FIFO */
|
655 | 3ccacc4a | blueswir1 | qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN); |
656 | 3ccacc4a | blueswir1 | qemu_put_be32s(f, &s->data_pos); |
657 | 3ccacc4a | blueswir1 | qemu_put_be32s(f, &s->data_len); |
658 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->data_state); |
659 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->data_dir); |
660 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->eot); |
661 | 77370520 | blueswir1 | /* States kept only to be returned back */
|
662 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->timer0); |
663 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->timer1); |
664 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->precomp_trk); |
665 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->config); |
666 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->lock); |
667 | 3ccacc4a | blueswir1 | qemu_put_8s(f, &s->pwrd); |
668 | 78ae820c | blueswir1 | |
669 | 78ae820c | blueswir1 | tmp = MAX_FD; |
670 | 78ae820c | blueswir1 | qemu_put_8s(f, &tmp); |
671 | 78ae820c | blueswir1 | for (i = 0; i < MAX_FD; i++) |
672 | 78ae820c | blueswir1 | fd_save(f, &s->drives[i]); |
673 | 3ccacc4a | blueswir1 | } |
674 | 3ccacc4a | blueswir1 | |
675 | 3ccacc4a | blueswir1 | static int fd_load (QEMUFile *f, fdrive_t *fd) |
676 | 3ccacc4a | blueswir1 | { |
677 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &fd->head); |
678 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &fd->track); |
679 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &fd->sect); |
680 | 3ccacc4a | blueswir1 | |
681 | 3ccacc4a | blueswir1 | return 0; |
682 | 3ccacc4a | blueswir1 | } |
683 | 3ccacc4a | blueswir1 | |
684 | 3ccacc4a | blueswir1 | static int fdc_load (QEMUFile *f, void *opaque, int version_id) |
685 | 3ccacc4a | blueswir1 | { |
686 | 3ccacc4a | blueswir1 | fdctrl_t *s = opaque; |
687 | 78ae820c | blueswir1 | int i, ret = 0; |
688 | 78ae820c | blueswir1 | uint8_t n; |
689 | 3ccacc4a | blueswir1 | |
690 | 77370520 | blueswir1 | if (version_id != 2) |
691 | 3ccacc4a | blueswir1 | return -EINVAL;
|
692 | 3ccacc4a | blueswir1 | |
693 | 8c6a4d77 | blueswir1 | /* Controller state */
|
694 | 8c6a4d77 | blueswir1 | qemu_get_8s(f, &s->sra); |
695 | 8c6a4d77 | blueswir1 | qemu_get_8s(f, &s->srb); |
696 | cefec4f5 | blueswir1 | qemu_get_8s(f, &s->dor); |
697 | cefec4f5 | blueswir1 | SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK); |
698 | cefec4f5 | blueswir1 | s->dor &= ~FD_DOR_SELMASK; |
699 | 46d3233b | blueswir1 | qemu_get_8s(f, &s->tdr); |
700 | 77370520 | blueswir1 | qemu_get_8s(f, &s->dsr); |
701 | 77370520 | blueswir1 | qemu_get_8s(f, &s->msr); |
702 | 77370520 | blueswir1 | qemu_get_8s(f, &s->status0); |
703 | 77370520 | blueswir1 | qemu_get_8s(f, &s->status1); |
704 | 77370520 | blueswir1 | qemu_get_8s(f, &s->status2); |
705 | 77370520 | blueswir1 | /* Command FIFO */
|
706 | 3ccacc4a | blueswir1 | qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN); |
707 | 3ccacc4a | blueswir1 | qemu_get_be32s(f, &s->data_pos); |
708 | 3ccacc4a | blueswir1 | qemu_get_be32s(f, &s->data_len); |
709 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->data_state); |
710 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->data_dir); |
711 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->eot); |
712 | 77370520 | blueswir1 | /* States kept only to be returned back */
|
713 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->timer0); |
714 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->timer1); |
715 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->precomp_trk); |
716 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->config); |
717 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->lock); |
718 | 3ccacc4a | blueswir1 | qemu_get_8s(f, &s->pwrd); |
719 | 78ae820c | blueswir1 | qemu_get_8s(f, &n); |
720 | 3ccacc4a | blueswir1 | |
721 | 78ae820c | blueswir1 | if (n > MAX_FD)
|
722 | 78ae820c | blueswir1 | return -EINVAL;
|
723 | 78ae820c | blueswir1 | |
724 | 78ae820c | blueswir1 | for (i = 0; i < n; i++) { |
725 | 78ae820c | blueswir1 | ret = fd_load(f, &s->drives[i]); |
726 | 78ae820c | blueswir1 | if (ret != 0) |
727 | 78ae820c | blueswir1 | break;
|
728 | 78ae820c | blueswir1 | } |
729 | 3ccacc4a | blueswir1 | |
730 | 3ccacc4a | blueswir1 | return ret;
|
731 | 3ccacc4a | blueswir1 | } |
732 | 3ccacc4a | blueswir1 | |
733 | 3ccacc4a | blueswir1 | static void fdctrl_external_reset(void *opaque) |
734 | 3ccacc4a | blueswir1 | { |
735 | 3ccacc4a | blueswir1 | fdctrl_t *s = opaque; |
736 | 3ccacc4a | blueswir1 | |
737 | 3ccacc4a | blueswir1 | fdctrl_reset(s, 0);
|
738 | 3ccacc4a | blueswir1 | } |
739 | 3ccacc4a | blueswir1 | |
740 | 2be17ebd | blueswir1 | static void fdctrl_handle_tc(void *opaque, int irq, int level) |
741 | 2be17ebd | blueswir1 | { |
742 | 2be17ebd | blueswir1 | //fdctrl_t *s = opaque;
|
743 | 2be17ebd | blueswir1 | |
744 | 2be17ebd | blueswir1 | if (level) {
|
745 | 2be17ebd | blueswir1 | // XXX
|
746 | 2be17ebd | blueswir1 | FLOPPY_DPRINTF("TC pulsed\n");
|
747 | 2be17ebd | blueswir1 | } |
748 | 2be17ebd | blueswir1 | } |
749 | 2be17ebd | blueswir1 | |
750 | baca51fa | bellard | /* XXX: may change if moved to bdrv */
|
751 | baca51fa | bellard | int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num) |
752 | caed8802 | bellard | { |
753 | baca51fa | bellard | return fdctrl->drives[drive_num].drive;
|
754 | 8977f3c1 | bellard | } |
755 | 8977f3c1 | bellard | |
756 | 8977f3c1 | bellard | /* Change IRQ state */
|
757 | baca51fa | bellard | static void fdctrl_reset_irq (fdctrl_t *fdctrl) |
758 | 8977f3c1 | bellard | { |
759 | 8c6a4d77 | blueswir1 | if (!(fdctrl->sra & FD_SRA_INTPEND))
|
760 | 8c6a4d77 | blueswir1 | return;
|
761 | ed5fd2cc | bellard | FLOPPY_DPRINTF("Reset interrupt\n");
|
762 | d537cf6c | pbrook | qemu_set_irq(fdctrl->irq, 0);
|
763 | 8c6a4d77 | blueswir1 | fdctrl->sra &= ~FD_SRA_INTPEND; |
764 | 8977f3c1 | bellard | } |
765 | 8977f3c1 | bellard | |
766 | 77370520 | blueswir1 | static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0) |
767 | 8977f3c1 | bellard | { |
768 | b9b3d225 | blueswir1 | /* Sparc mutation */
|
769 | b9b3d225 | blueswir1 | if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
|
770 | b9b3d225 | blueswir1 | /* XXX: not sure */
|
771 | b9b3d225 | blueswir1 | fdctrl->msr &= ~FD_MSR_CMDBUSY; |
772 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
773 | 77370520 | blueswir1 | fdctrl->status0 = status0; |
774 | 4f431960 | j_mayer | return;
|
775 | 6f7e9aec | bellard | } |
776 | 8c6a4d77 | blueswir1 | if (!(fdctrl->sra & FD_SRA_INTPEND)) {
|
777 | d537cf6c | pbrook | qemu_set_irq(fdctrl->irq, 1);
|
778 | 8c6a4d77 | blueswir1 | fdctrl->sra |= FD_SRA_INTPEND; |
779 | 8977f3c1 | bellard | } |
780 | f2d81b33 | blueswir1 | fdctrl->reset_sensei = 0;
|
781 | 77370520 | blueswir1 | fdctrl->status0 = status0; |
782 | 77370520 | blueswir1 | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
|
783 | 8977f3c1 | bellard | } |
784 | 8977f3c1 | bellard | |
785 | 4b19ec0c | bellard | /* Reset controller */
|
786 | baca51fa | bellard | static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq) |
787 | 8977f3c1 | bellard | { |
788 | 8977f3c1 | bellard | int i;
|
789 | 8977f3c1 | bellard | |
790 | 4b19ec0c | bellard | FLOPPY_DPRINTF("reset controller\n");
|
791 | baca51fa | bellard | fdctrl_reset_irq(fdctrl); |
792 | 4b19ec0c | bellard | /* Initialise controller */
|
793 | 8c6a4d77 | blueswir1 | fdctrl->sra = 0;
|
794 | 8c6a4d77 | blueswir1 | fdctrl->srb = 0xc0;
|
795 | 8c6a4d77 | blueswir1 | if (!fdctrl->drives[1].bs) |
796 | 8c6a4d77 | blueswir1 | fdctrl->sra |= FD_SRA_nDRV2; |
797 | baca51fa | bellard | fdctrl->cur_drv = 0;
|
798 | 1c346df2 | blueswir1 | fdctrl->dor = FD_DOR_nRESET; |
799 | 368df94d | blueswir1 | fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
800 | b9b3d225 | blueswir1 | fdctrl->msr = FD_MSR_RQM; |
801 | 8977f3c1 | bellard | /* FIFO state */
|
802 | baca51fa | bellard | fdctrl->data_pos = 0;
|
803 | baca51fa | bellard | fdctrl->data_len = 0;
|
804 | b9b3d225 | blueswir1 | fdctrl->data_state = 0;
|
805 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_WRITE; |
806 | 8977f3c1 | bellard | for (i = 0; i < MAX_FD; i++) |
807 | 1c346df2 | blueswir1 | fd_recalibrate(&fdctrl->drives[i]); |
808 | baca51fa | bellard | fdctrl_reset_fifo(fdctrl); |
809 | 77370520 | blueswir1 | if (do_irq) {
|
810 | 9fea808a | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG); |
811 | f2d81b33 | blueswir1 | fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
812 | 77370520 | blueswir1 | } |
813 | baca51fa | bellard | } |
814 | baca51fa | bellard | |
815 | baca51fa | bellard | static inline fdrive_t *drv0 (fdctrl_t *fdctrl) |
816 | baca51fa | bellard | { |
817 | 46d3233b | blueswir1 | return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
818 | baca51fa | bellard | } |
819 | baca51fa | bellard | |
820 | baca51fa | bellard | static inline fdrive_t *drv1 (fdctrl_t *fdctrl) |
821 | baca51fa | bellard | { |
822 | 46d3233b | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
823 | 46d3233b | blueswir1 | return &fdctrl->drives[1]; |
824 | 46d3233b | blueswir1 | else
|
825 | 46d3233b | blueswir1 | return &fdctrl->drives[0]; |
826 | baca51fa | bellard | } |
827 | baca51fa | bellard | |
828 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
829 | 78ae820c | blueswir1 | static inline fdrive_t *drv2 (fdctrl_t *fdctrl) |
830 | 78ae820c | blueswir1 | { |
831 | 78ae820c | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) |
832 | 78ae820c | blueswir1 | return &fdctrl->drives[2]; |
833 | 78ae820c | blueswir1 | else
|
834 | 78ae820c | blueswir1 | return &fdctrl->drives[1]; |
835 | 78ae820c | blueswir1 | } |
836 | 78ae820c | blueswir1 | |
837 | 78ae820c | blueswir1 | static inline fdrive_t *drv3 (fdctrl_t *fdctrl) |
838 | 78ae820c | blueswir1 | { |
839 | 78ae820c | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) |
840 | 78ae820c | blueswir1 | return &fdctrl->drives[3]; |
841 | 78ae820c | blueswir1 | else
|
842 | 78ae820c | blueswir1 | return &fdctrl->drives[2]; |
843 | 78ae820c | blueswir1 | } |
844 | 78ae820c | blueswir1 | #endif
|
845 | 78ae820c | blueswir1 | |
846 | baca51fa | bellard | static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
|
847 | baca51fa | bellard | { |
848 | 78ae820c | blueswir1 | switch (fdctrl->cur_drv) {
|
849 | 78ae820c | blueswir1 | case 0: return drv0(fdctrl); |
850 | 78ae820c | blueswir1 | case 1: return drv1(fdctrl); |
851 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
852 | 78ae820c | blueswir1 | case 2: return drv2(fdctrl); |
853 | 78ae820c | blueswir1 | case 3: return drv3(fdctrl); |
854 | 78ae820c | blueswir1 | #endif
|
855 | 78ae820c | blueswir1 | default: return NULL; |
856 | 78ae820c | blueswir1 | } |
857 | 8977f3c1 | bellard | } |
858 | 8977f3c1 | bellard | |
859 | 8c6a4d77 | blueswir1 | /* Status A register : 0x00 (read-only) */
|
860 | 8c6a4d77 | blueswir1 | static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
|
861 | 8c6a4d77 | blueswir1 | { |
862 | 8c6a4d77 | blueswir1 | uint32_t retval = fdctrl->sra; |
863 | 8c6a4d77 | blueswir1 | |
864 | 8c6a4d77 | blueswir1 | FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
|
865 | 8c6a4d77 | blueswir1 | |
866 | 8c6a4d77 | blueswir1 | return retval;
|
867 | 8c6a4d77 | blueswir1 | } |
868 | 8c6a4d77 | blueswir1 | |
869 | 8977f3c1 | bellard | /* Status B register : 0x01 (read-only) */
|
870 | baca51fa | bellard | static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
|
871 | 8977f3c1 | bellard | { |
872 | 8c6a4d77 | blueswir1 | uint32_t retval = fdctrl->srb; |
873 | 8c6a4d77 | blueswir1 | |
874 | 8c6a4d77 | blueswir1 | FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
|
875 | 8c6a4d77 | blueswir1 | |
876 | 8c6a4d77 | blueswir1 | return retval;
|
877 | 8977f3c1 | bellard | } |
878 | 8977f3c1 | bellard | |
879 | 8977f3c1 | bellard | /* Digital output register : 0x02 */
|
880 | baca51fa | bellard | static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
|
881 | 8977f3c1 | bellard | { |
882 | 1c346df2 | blueswir1 | uint32_t retval = fdctrl->dor; |
883 | 8977f3c1 | bellard | |
884 | 8977f3c1 | bellard | /* Selected drive */
|
885 | baca51fa | bellard | retval |= fdctrl->cur_drv; |
886 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
|
887 | 8977f3c1 | bellard | |
888 | 8977f3c1 | bellard | return retval;
|
889 | 8977f3c1 | bellard | } |
890 | 8977f3c1 | bellard | |
891 | baca51fa | bellard | static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value) |
892 | 8977f3c1 | bellard | { |
893 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
|
894 | 8c6a4d77 | blueswir1 | |
895 | 8c6a4d77 | blueswir1 | /* Motors */
|
896 | 8c6a4d77 | blueswir1 | if (value & FD_DOR_MOTEN0)
|
897 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_MTR0; |
898 | 8c6a4d77 | blueswir1 | else
|
899 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_MTR0; |
900 | 8c6a4d77 | blueswir1 | if (value & FD_DOR_MOTEN1)
|
901 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_MTR1; |
902 | 8c6a4d77 | blueswir1 | else
|
903 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_MTR1; |
904 | 8c6a4d77 | blueswir1 | |
905 | 8c6a4d77 | blueswir1 | /* Drive */
|
906 | 8c6a4d77 | blueswir1 | if (value & 1) |
907 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_DR0; |
908 | 8c6a4d77 | blueswir1 | else
|
909 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_DR0; |
910 | 8c6a4d77 | blueswir1 | |
911 | 8977f3c1 | bellard | /* Reset */
|
912 | 9fea808a | blueswir1 | if (!(value & FD_DOR_nRESET)) {
|
913 | 1c346df2 | blueswir1 | if (fdctrl->dor & FD_DOR_nRESET) {
|
914 | 4b19ec0c | bellard | FLOPPY_DPRINTF("controller enter RESET state\n");
|
915 | 8977f3c1 | bellard | } |
916 | 8977f3c1 | bellard | } else {
|
917 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
918 | 4b19ec0c | bellard | FLOPPY_DPRINTF("controller out of RESET state\n");
|
919 | fb6cf1d0 | bellard | fdctrl_reset(fdctrl, 1);
|
920 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
921 | 8977f3c1 | bellard | } |
922 | 8977f3c1 | bellard | } |
923 | 8977f3c1 | bellard | /* Selected drive */
|
924 | 9fea808a | blueswir1 | fdctrl->cur_drv = value & FD_DOR_SELMASK; |
925 | 368df94d | blueswir1 | |
926 | 368df94d | blueswir1 | fdctrl->dor = value; |
927 | 8977f3c1 | bellard | } |
928 | 8977f3c1 | bellard | |
929 | 8977f3c1 | bellard | /* Tape drive register : 0x03 */
|
930 | baca51fa | bellard | static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
|
931 | 8977f3c1 | bellard | { |
932 | 46d3233b | blueswir1 | uint32_t retval = fdctrl->tdr; |
933 | 8977f3c1 | bellard | |
934 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
|
935 | 8977f3c1 | bellard | |
936 | 8977f3c1 | bellard | return retval;
|
937 | 8977f3c1 | bellard | } |
938 | 8977f3c1 | bellard | |
939 | baca51fa | bellard | static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value) |
940 | 8977f3c1 | bellard | { |
941 | 8977f3c1 | bellard | /* Reset mode */
|
942 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
943 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
944 | 8977f3c1 | bellard | return;
|
945 | 8977f3c1 | bellard | } |
946 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
|
947 | 8977f3c1 | bellard | /* Disk boot selection indicator */
|
948 | 46d3233b | blueswir1 | fdctrl->tdr = value & FD_TDR_BOOTSEL; |
949 | 8977f3c1 | bellard | /* Tape indicators: never allow */
|
950 | 8977f3c1 | bellard | } |
951 | 8977f3c1 | bellard | |
952 | 8977f3c1 | bellard | /* Main status register : 0x04 (read) */
|
953 | baca51fa | bellard | static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
|
954 | 8977f3c1 | bellard | { |
955 | b9b3d225 | blueswir1 | uint32_t retval = fdctrl->msr; |
956 | 8977f3c1 | bellard | |
957 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
958 | 1c346df2 | blueswir1 | fdctrl->dor |= FD_DOR_nRESET; |
959 | b9b3d225 | blueswir1 | |
960 | 8977f3c1 | bellard | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
|
961 | 8977f3c1 | bellard | |
962 | 8977f3c1 | bellard | return retval;
|
963 | 8977f3c1 | bellard | } |
964 | 8977f3c1 | bellard | |
965 | 8977f3c1 | bellard | /* Data select rate register : 0x04 (write) */
|
966 | baca51fa | bellard | static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value) |
967 | 8977f3c1 | bellard | { |
968 | 8977f3c1 | bellard | /* Reset mode */
|
969 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
970 | 4f431960 | j_mayer | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
971 | 4f431960 | j_mayer | return;
|
972 | 4f431960 | j_mayer | } |
973 | 8977f3c1 | bellard | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
|
974 | 8977f3c1 | bellard | /* Reset: autoclear */
|
975 | 9fea808a | blueswir1 | if (value & FD_DSR_SWRESET) {
|
976 | 1c346df2 | blueswir1 | fdctrl->dor &= ~FD_DOR_nRESET; |
977 | baca51fa | bellard | fdctrl_reset(fdctrl, 1);
|
978 | 1c346df2 | blueswir1 | fdctrl->dor |= FD_DOR_nRESET; |
979 | 8977f3c1 | bellard | } |
980 | 9fea808a | blueswir1 | if (value & FD_DSR_PWRDOWN) {
|
981 | baca51fa | bellard | fdctrl_reset(fdctrl, 1);
|
982 | 8977f3c1 | bellard | } |
983 | b9b3d225 | blueswir1 | fdctrl->dsr = value; |
984 | 8977f3c1 | bellard | } |
985 | 8977f3c1 | bellard | |
986 | ea185bbd | bellard | static int fdctrl_media_changed(fdrive_t *drv) |
987 | ea185bbd | bellard | { |
988 | ea185bbd | bellard | int ret;
|
989 | 4f431960 | j_mayer | |
990 | 5fafdf24 | ths | if (!drv->bs)
|
991 | ea185bbd | bellard | return 0; |
992 | ea185bbd | bellard | ret = bdrv_media_changed(drv->bs); |
993 | ea185bbd | bellard | if (ret) {
|
994 | ea185bbd | bellard | fd_revalidate(drv); |
995 | ea185bbd | bellard | } |
996 | ea185bbd | bellard | return ret;
|
997 | ea185bbd | bellard | } |
998 | ea185bbd | bellard | |
999 | 8977f3c1 | bellard | /* Digital input register : 0x07 (read-only) */
|
1000 | baca51fa | bellard | static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
|
1001 | 8977f3c1 | bellard | { |
1002 | 8977f3c1 | bellard | uint32_t retval = 0;
|
1003 | 8977f3c1 | bellard | |
1004 | 78ae820c | blueswir1 | if (fdctrl_media_changed(drv0(fdctrl))
|
1005 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv1(fdctrl)) |
1006 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1007 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv2(fdctrl)) |
1008 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv3(fdctrl)) |
1009 | 78ae820c | blueswir1 | #endif
|
1010 | 78ae820c | blueswir1 | ) |
1011 | 9fea808a | blueswir1 | retval |= FD_DIR_DSKCHG; |
1012 | 8977f3c1 | bellard | if (retval != 0) |
1013 | baca51fa | bellard | FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
|
1014 | 8977f3c1 | bellard | |
1015 | 8977f3c1 | bellard | return retval;
|
1016 | 8977f3c1 | bellard | } |
1017 | 8977f3c1 | bellard | |
1018 | 8977f3c1 | bellard | /* FIFO state control */
|
1019 | baca51fa | bellard | static void fdctrl_reset_fifo (fdctrl_t *fdctrl) |
1020 | 8977f3c1 | bellard | { |
1021 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_WRITE; |
1022 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1023 | b9b3d225 | blueswir1 | fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
1024 | 8977f3c1 | bellard | } |
1025 | 8977f3c1 | bellard | |
1026 | 8977f3c1 | bellard | /* Set FIFO status for the host to read */
|
1027 | baca51fa | bellard | static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq) |
1028 | 8977f3c1 | bellard | { |
1029 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_READ; |
1030 | baca51fa | bellard | fdctrl->data_len = fifo_len; |
1031 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1032 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
1033 | 8977f3c1 | bellard | if (do_irq)
|
1034 | baca51fa | bellard | fdctrl_raise_irq(fdctrl, 0x00);
|
1035 | 8977f3c1 | bellard | } |
1036 | 8977f3c1 | bellard | |
1037 | 8977f3c1 | bellard | /* Set an error: unimplemented/unknown command */
|
1038 | 65cef780 | blueswir1 | static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction) |
1039 | 8977f3c1 | bellard | { |
1040 | 77370520 | blueswir1 | FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); |
1041 | 9fea808a | blueswir1 | fdctrl->fifo[0] = FD_SR0_INVCMD;
|
1042 | baca51fa | bellard | fdctrl_set_fifo(fdctrl, 1, 0); |
1043 | 8977f3c1 | bellard | } |
1044 | 8977f3c1 | bellard | |
1045 | 746d6de7 | blueswir1 | /* Seek to next sector */
|
1046 | 746d6de7 | blueswir1 | static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv) |
1047 | 746d6de7 | blueswir1 | { |
1048 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
1049 | 746d6de7 | blueswir1 | cur_drv->head, cur_drv->track, cur_drv->sect, |
1050 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
1051 | 746d6de7 | blueswir1 | /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
|
1052 | 746d6de7 | blueswir1 | error in fact */
|
1053 | 746d6de7 | blueswir1 | if (cur_drv->sect >= cur_drv->last_sect ||
|
1054 | 746d6de7 | blueswir1 | cur_drv->sect == fdctrl->eot) { |
1055 | 746d6de7 | blueswir1 | cur_drv->sect = 1;
|
1056 | 746d6de7 | blueswir1 | if (FD_MULTI_TRACK(fdctrl->data_state)) {
|
1057 | 746d6de7 | blueswir1 | if (cur_drv->head == 0 && |
1058 | 746d6de7 | blueswir1 | (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
|
1059 | 746d6de7 | blueswir1 | cur_drv->head = 1;
|
1060 | 746d6de7 | blueswir1 | } else {
|
1061 | 746d6de7 | blueswir1 | cur_drv->head = 0;
|
1062 | 746d6de7 | blueswir1 | cur_drv->track++; |
1063 | 746d6de7 | blueswir1 | if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) |
1064 | 746d6de7 | blueswir1 | return 0; |
1065 | 746d6de7 | blueswir1 | } |
1066 | 746d6de7 | blueswir1 | } else {
|
1067 | 746d6de7 | blueswir1 | cur_drv->track++; |
1068 | 746d6de7 | blueswir1 | return 0; |
1069 | 746d6de7 | blueswir1 | } |
1070 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
|
1071 | 746d6de7 | blueswir1 | cur_drv->head, cur_drv->track, |
1072 | 746d6de7 | blueswir1 | cur_drv->sect, fd_sector(cur_drv)); |
1073 | 746d6de7 | blueswir1 | } else {
|
1074 | 746d6de7 | blueswir1 | cur_drv->sect++; |
1075 | 746d6de7 | blueswir1 | } |
1076 | 746d6de7 | blueswir1 | return 1; |
1077 | 746d6de7 | blueswir1 | } |
1078 | 746d6de7 | blueswir1 | |
1079 | 8977f3c1 | bellard | /* Callback for transfer end (stop or abort) */
|
1080 | baca51fa | bellard | static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0, |
1081 | 4f431960 | j_mayer | uint8_t status1, uint8_t status2) |
1082 | 8977f3c1 | bellard | { |
1083 | baca51fa | bellard | fdrive_t *cur_drv; |
1084 | 8977f3c1 | bellard | |
1085 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1086 | 8977f3c1 | bellard | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
|
1087 | 8977f3c1 | bellard | status0, status1, status2, |
1088 | cefec4f5 | blueswir1 | status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
|
1089 | cefec4f5 | blueswir1 | fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
1090 | baca51fa | bellard | fdctrl->fifo[1] = status1;
|
1091 | baca51fa | bellard | fdctrl->fifo[2] = status2;
|
1092 | baca51fa | bellard | fdctrl->fifo[3] = cur_drv->track;
|
1093 | baca51fa | bellard | fdctrl->fifo[4] = cur_drv->head;
|
1094 | baca51fa | bellard | fdctrl->fifo[5] = cur_drv->sect;
|
1095 | baca51fa | bellard | fdctrl->fifo[6] = FD_SECTOR_SC;
|
1096 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_READ; |
1097 | 368df94d | blueswir1 | if (!(fdctrl->msr & FD_MSR_NONDMA)) {
|
1098 | baca51fa | bellard | DMA_release_DREQ(fdctrl->dma_chann); |
1099 | ed5fd2cc | bellard | } |
1100 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
1101 | 368df94d | blueswir1 | fdctrl->msr &= ~FD_MSR_NONDMA; |
1102 | baca51fa | bellard | fdctrl_set_fifo(fdctrl, 7, 1); |
1103 | 8977f3c1 | bellard | } |
1104 | 8977f3c1 | bellard | |
1105 | 8977f3c1 | bellard | /* Prepare a data transfer (either DMA or FIFO) */
|
1106 | baca51fa | bellard | static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction) |
1107 | 8977f3c1 | bellard | { |
1108 | baca51fa | bellard | fdrive_t *cur_drv; |
1109 | 8977f3c1 | bellard | uint8_t kh, kt, ks; |
1110 | 77370520 | blueswir1 | int did_seek = 0; |
1111 | 8977f3c1 | bellard | |
1112 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1113 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1114 | baca51fa | bellard | kt = fdctrl->fifo[2];
|
1115 | baca51fa | bellard | kh = fdctrl->fifo[3];
|
1116 | baca51fa | bellard | ks = fdctrl->fifo[4];
|
1117 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
|
1118 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
1119 | 8977f3c1 | bellard | _fd_sector(kh, kt, ks, cur_drv->last_sect)); |
1120 | 77370520 | blueswir1 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1121 | 8977f3c1 | bellard | case 2: |
1122 | 8977f3c1 | bellard | /* sect too big */
|
1123 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1124 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1125 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1126 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1127 | 8977f3c1 | bellard | return;
|
1128 | 8977f3c1 | bellard | case 3: |
1129 | 8977f3c1 | bellard | /* track too big */
|
1130 | 77370520 | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1131 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1132 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1133 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1134 | 8977f3c1 | bellard | return;
|
1135 | 8977f3c1 | bellard | case 4: |
1136 | 8977f3c1 | bellard | /* No seek enabled */
|
1137 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1138 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1139 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1140 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1141 | 8977f3c1 | bellard | return;
|
1142 | 8977f3c1 | bellard | case 1: |
1143 | 8977f3c1 | bellard | did_seek = 1;
|
1144 | 8977f3c1 | bellard | break;
|
1145 | 8977f3c1 | bellard | default:
|
1146 | 8977f3c1 | bellard | break;
|
1147 | 8977f3c1 | bellard | } |
1148 | b9b3d225 | blueswir1 | |
1149 | 8977f3c1 | bellard | /* Set the FIFO state */
|
1150 | baca51fa | bellard | fdctrl->data_dir = direction; |
1151 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1152 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_CMDBUSY; |
1153 | baca51fa | bellard | if (fdctrl->fifo[0] & 0x80) |
1154 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_MULTI; |
1155 | baca51fa | bellard | else
|
1156 | baca51fa | bellard | fdctrl->data_state &= ~FD_STATE_MULTI; |
1157 | 8977f3c1 | bellard | if (did_seek)
|
1158 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_SEEK; |
1159 | baca51fa | bellard | else
|
1160 | baca51fa | bellard | fdctrl->data_state &= ~FD_STATE_SEEK; |
1161 | baca51fa | bellard | if (fdctrl->fifo[5] == 00) { |
1162 | baca51fa | bellard | fdctrl->data_len = fdctrl->fifo[8];
|
1163 | baca51fa | bellard | } else {
|
1164 | 4f431960 | j_mayer | int tmp;
|
1165 | 3bcb80f1 | ths | fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
1166 | 771effeb | blueswir1 | tmp = (fdctrl->fifo[6] - ks + 1); |
1167 | baca51fa | bellard | if (fdctrl->fifo[0] & 0x80) |
1168 | 771effeb | blueswir1 | tmp += fdctrl->fifo[6];
|
1169 | 4f431960 | j_mayer | fdctrl->data_len *= tmp; |
1170 | baca51fa | bellard | } |
1171 | 890fa6be | bellard | fdctrl->eot = fdctrl->fifo[6];
|
1172 | 368df94d | blueswir1 | if (fdctrl->dor & FD_DOR_DMAEN) {
|
1173 | 8977f3c1 | bellard | int dma_mode;
|
1174 | 8977f3c1 | bellard | /* DMA transfer are enabled. Check if DMA channel is well programmed */
|
1175 | baca51fa | bellard | dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
1176 | 8977f3c1 | bellard | dma_mode = (dma_mode >> 2) & 3; |
1177 | baca51fa | bellard | FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
|
1178 | 4f431960 | j_mayer | dma_mode, direction, |
1179 | baca51fa | bellard | (128 << fdctrl->fifo[5]) * |
1180 | 4f431960 | j_mayer | (cur_drv->last_sect - ks + 1), fdctrl->data_len);
|
1181 | 8977f3c1 | bellard | if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
|
1182 | 8977f3c1 | bellard | direction == FD_DIR_SCANH) && dma_mode == 0) ||
|
1183 | 8977f3c1 | bellard | (direction == FD_DIR_WRITE && dma_mode == 2) ||
|
1184 | 8977f3c1 | bellard | (direction == FD_DIR_READ && dma_mode == 1)) {
|
1185 | 8977f3c1 | bellard | /* No access is allowed until DMA transfer has completed */
|
1186 | b9b3d225 | blueswir1 | fdctrl->msr &= ~FD_MSR_RQM; |
1187 | 4b19ec0c | bellard | /* Now, we just have to wait for the DMA controller to
|
1188 | 8977f3c1 | bellard | * recall us...
|
1189 | 8977f3c1 | bellard | */
|
1190 | baca51fa | bellard | DMA_hold_DREQ(fdctrl->dma_chann); |
1191 | baca51fa | bellard | DMA_schedule(fdctrl->dma_chann); |
1192 | 8977f3c1 | bellard | return;
|
1193 | baca51fa | bellard | } else {
|
1194 | 4f431960 | j_mayer | FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
|
1195 | 8977f3c1 | bellard | } |
1196 | 8977f3c1 | bellard | } |
1197 | 8977f3c1 | bellard | FLOPPY_DPRINTF("start non-DMA transfer\n");
|
1198 | 368df94d | blueswir1 | fdctrl->msr |= FD_MSR_NONDMA; |
1199 | b9b3d225 | blueswir1 | if (direction != FD_DIR_WRITE)
|
1200 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_DIO; |
1201 | 8977f3c1 | bellard | /* IO based transfer: calculate len */
|
1202 | baca51fa | bellard | fdctrl_raise_irq(fdctrl, 0x00);
|
1203 | 8977f3c1 | bellard | |
1204 | 8977f3c1 | bellard | return;
|
1205 | 8977f3c1 | bellard | } |
1206 | 8977f3c1 | bellard | |
1207 | 8977f3c1 | bellard | /* Prepare a transfer of deleted data */
|
1208 | baca51fa | bellard | static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction) |
1209 | 8977f3c1 | bellard | { |
1210 | 77370520 | blueswir1 | FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
|
1211 | 77370520 | blueswir1 | |
1212 | 8977f3c1 | bellard | /* We don't handle deleted data,
|
1213 | 8977f3c1 | bellard | * so we don't return *ANYTHING*
|
1214 | 8977f3c1 | bellard | */
|
1215 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1216 | 8977f3c1 | bellard | } |
1217 | 8977f3c1 | bellard | |
1218 | 8977f3c1 | bellard | /* handlers for DMA transfers */
|
1219 | 85571bc7 | bellard | static int fdctrl_transfer_handler (void *opaque, int nchan, |
1220 | 85571bc7 | bellard | int dma_pos, int dma_len) |
1221 | 8977f3c1 | bellard | { |
1222 | baca51fa | bellard | fdctrl_t *fdctrl; |
1223 | baca51fa | bellard | fdrive_t *cur_drv; |
1224 | baca51fa | bellard | int len, start_pos, rel_pos;
|
1225 | 8977f3c1 | bellard | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
1226 | 8977f3c1 | bellard | |
1227 | baca51fa | bellard | fdctrl = opaque; |
1228 | b9b3d225 | blueswir1 | if (fdctrl->msr & FD_MSR_RQM) {
|
1229 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
|
1230 | 8977f3c1 | bellard | return 0; |
1231 | 8977f3c1 | bellard | } |
1232 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1233 | baca51fa | bellard | if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
|
1234 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANH) |
1235 | 77370520 | blueswir1 | status2 = FD_SR2_SNS; |
1236 | 85571bc7 | bellard | if (dma_len > fdctrl->data_len)
|
1237 | 85571bc7 | bellard | dma_len = fdctrl->data_len; |
1238 | 890fa6be | bellard | if (cur_drv->bs == NULL) { |
1239 | 4f431960 | j_mayer | if (fdctrl->data_dir == FD_DIR_WRITE)
|
1240 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1241 | 4f431960 | j_mayer | else
|
1242 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1243 | 4f431960 | j_mayer | len = 0;
|
1244 | 890fa6be | bellard | goto transfer_error;
|
1245 | 890fa6be | bellard | } |
1246 | baca51fa | bellard | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1247 | 85571bc7 | bellard | for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
|
1248 | 85571bc7 | bellard | len = dma_len - fdctrl->data_pos; |
1249 | baca51fa | bellard | if (len + rel_pos > FD_SECTOR_LEN)
|
1250 | baca51fa | bellard | len = FD_SECTOR_LEN - rel_pos; |
1251 | 6f7e9aec | bellard | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
|
1252 | 6f7e9aec | bellard | "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
|
1253 | cefec4f5 | blueswir1 | fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
1254 | baca51fa | bellard | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
1255 | 9fea808a | blueswir1 | fd_sector(cur_drv) * FD_SECTOR_LEN); |
1256 | baca51fa | bellard | if (fdctrl->data_dir != FD_DIR_WRITE ||
|
1257 | 4f431960 | j_mayer | len < FD_SECTOR_LEN || rel_pos != 0) {
|
1258 | baca51fa | bellard | /* READ & SCAN commands and realign to a sector for WRITE */
|
1259 | baca51fa | bellard | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
|
1260 | 4f431960 | j_mayer | fdctrl->fifo, 1) < 0) { |
1261 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
|
1262 | 8977f3c1 | bellard | fd_sector(cur_drv)); |
1263 | 8977f3c1 | bellard | /* Sure, image size is too small... */
|
1264 | baca51fa | bellard | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1265 | 8977f3c1 | bellard | } |
1266 | 890fa6be | bellard | } |
1267 | 4f431960 | j_mayer | switch (fdctrl->data_dir) {
|
1268 | 4f431960 | j_mayer | case FD_DIR_READ:
|
1269 | 4f431960 | j_mayer | /* READ commands */
|
1270 | 85571bc7 | bellard | DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
1271 | 85571bc7 | bellard | fdctrl->data_pos, len); |
1272 | 4f431960 | j_mayer | break;
|
1273 | 4f431960 | j_mayer | case FD_DIR_WRITE:
|
1274 | baca51fa | bellard | /* WRITE commands */
|
1275 | 85571bc7 | bellard | DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
1276 | 85571bc7 | bellard | fdctrl->data_pos, len); |
1277 | baca51fa | bellard | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
|
1278 | 4f431960 | j_mayer | fdctrl->fifo, 1) < 0) { |
1279 | 77370520 | blueswir1 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1280 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1281 | baca51fa | bellard | goto transfer_error;
|
1282 | 890fa6be | bellard | } |
1283 | 4f431960 | j_mayer | break;
|
1284 | 4f431960 | j_mayer | default:
|
1285 | 4f431960 | j_mayer | /* SCAN commands */
|
1286 | baca51fa | bellard | { |
1287 | 4f431960 | j_mayer | uint8_t tmpbuf[FD_SECTOR_LEN]; |
1288 | baca51fa | bellard | int ret;
|
1289 | 85571bc7 | bellard | DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
1290 | baca51fa | bellard | ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
1291 | 8977f3c1 | bellard | if (ret == 0) { |
1292 | 77370520 | blueswir1 | status2 = FD_SR2_SEH; |
1293 | 8977f3c1 | bellard | goto end_transfer;
|
1294 | 8977f3c1 | bellard | } |
1295 | baca51fa | bellard | if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1296 | baca51fa | bellard | (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
|
1297 | 8977f3c1 | bellard | status2 = 0x00;
|
1298 | 8977f3c1 | bellard | goto end_transfer;
|
1299 | 8977f3c1 | bellard | } |
1300 | 8977f3c1 | bellard | } |
1301 | 4f431960 | j_mayer | break;
|
1302 | 8977f3c1 | bellard | } |
1303 | 4f431960 | j_mayer | fdctrl->data_pos += len; |
1304 | 4f431960 | j_mayer | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1305 | baca51fa | bellard | if (rel_pos == 0) { |
1306 | 8977f3c1 | bellard | /* Seek to next sector */
|
1307 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
|
1308 | 746d6de7 | blueswir1 | break;
|
1309 | 8977f3c1 | bellard | } |
1310 | 8977f3c1 | bellard | } |
1311 | 4f431960 | j_mayer | end_transfer:
|
1312 | baca51fa | bellard | len = fdctrl->data_pos - start_pos; |
1313 | baca51fa | bellard | FLOPPY_DPRINTF("end transfer %d %d %d\n",
|
1314 | 4f431960 | j_mayer | fdctrl->data_pos, len, fdctrl->data_len); |
1315 | baca51fa | bellard | if (fdctrl->data_dir == FD_DIR_SCANE ||
|
1316 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANL || |
1317 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANH) |
1318 | 77370520 | blueswir1 | status2 = FD_SR2_SEH; |
1319 | baca51fa | bellard | if (FD_DID_SEEK(fdctrl->data_state))
|
1320 | 9fea808a | blueswir1 | status0 |= FD_SR0_SEEK; |
1321 | baca51fa | bellard | fdctrl->data_len -= len; |
1322 | 890fa6be | bellard | fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
1323 | 4f431960 | j_mayer | transfer_error:
|
1324 | 8977f3c1 | bellard | |
1325 | baca51fa | bellard | return len;
|
1326 | 8977f3c1 | bellard | } |
1327 | 8977f3c1 | bellard | |
1328 | 8977f3c1 | bellard | /* Data register : 0x05 */
|
1329 | baca51fa | bellard | static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
|
1330 | 8977f3c1 | bellard | { |
1331 | baca51fa | bellard | fdrive_t *cur_drv; |
1332 | 8977f3c1 | bellard | uint32_t retval = 0;
|
1333 | 746d6de7 | blueswir1 | int pos;
|
1334 | 8977f3c1 | bellard | |
1335 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1336 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1337 | b9b3d225 | blueswir1 | if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
|
1338 | b9b3d225 | blueswir1 | FLOPPY_ERROR("controller not ready for reading\n");
|
1339 | 8977f3c1 | bellard | return 0; |
1340 | 8977f3c1 | bellard | } |
1341 | baca51fa | bellard | pos = fdctrl->data_pos; |
1342 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1343 | 8977f3c1 | bellard | pos %= FD_SECTOR_LEN; |
1344 | 8977f3c1 | bellard | if (pos == 0) { |
1345 | 746d6de7 | blueswir1 | if (fdctrl->data_pos != 0) |
1346 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1347 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1348 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
1349 | 746d6de7 | blueswir1 | return 0; |
1350 | 746d6de7 | blueswir1 | } |
1351 | 77370520 | blueswir1 | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1352 | 77370520 | blueswir1 | FLOPPY_DPRINTF("error getting sector %d\n",
|
1353 | 77370520 | blueswir1 | fd_sector(cur_drv)); |
1354 | 77370520 | blueswir1 | /* Sure, image size is too small... */
|
1355 | 77370520 | blueswir1 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1356 | 77370520 | blueswir1 | } |
1357 | 8977f3c1 | bellard | } |
1358 | 8977f3c1 | bellard | } |
1359 | baca51fa | bellard | retval = fdctrl->fifo[pos]; |
1360 | baca51fa | bellard | if (++fdctrl->data_pos == fdctrl->data_len) {
|
1361 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1362 | 890fa6be | bellard | /* Switch from transfer mode to status mode
|
1363 | 8977f3c1 | bellard | * then from status mode to command mode
|
1364 | 8977f3c1 | bellard | */
|
1365 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1366 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1367 | ed5fd2cc | bellard | } else {
|
1368 | baca51fa | bellard | fdctrl_reset_fifo(fdctrl); |
1369 | ed5fd2cc | bellard | fdctrl_reset_irq(fdctrl); |
1370 | ed5fd2cc | bellard | } |
1371 | 8977f3c1 | bellard | } |
1372 | 8977f3c1 | bellard | FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
|
1373 | 8977f3c1 | bellard | |
1374 | 8977f3c1 | bellard | return retval;
|
1375 | 8977f3c1 | bellard | } |
1376 | 8977f3c1 | bellard | |
1377 | baca51fa | bellard | static void fdctrl_format_sector (fdctrl_t *fdctrl) |
1378 | 8977f3c1 | bellard | { |
1379 | baca51fa | bellard | fdrive_t *cur_drv; |
1380 | baca51fa | bellard | uint8_t kh, kt, ks; |
1381 | 8977f3c1 | bellard | |
1382 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1383 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1384 | baca51fa | bellard | kt = fdctrl->fifo[6];
|
1385 | baca51fa | bellard | kh = fdctrl->fifo[7];
|
1386 | baca51fa | bellard | ks = fdctrl->fifo[8];
|
1387 | baca51fa | bellard | FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
|
1388 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
1389 | baca51fa | bellard | _fd_sector(kh, kt, ks, cur_drv->last_sect)); |
1390 | 9fea808a | blueswir1 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1391 | baca51fa | bellard | case 2: |
1392 | baca51fa | bellard | /* sect too big */
|
1393 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1394 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1395 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1396 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1397 | baca51fa | bellard | return;
|
1398 | baca51fa | bellard | case 3: |
1399 | baca51fa | bellard | /* track too big */
|
1400 | 77370520 | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1401 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1402 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1403 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1404 | baca51fa | bellard | return;
|
1405 | baca51fa | bellard | case 4: |
1406 | baca51fa | bellard | /* No seek enabled */
|
1407 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1408 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1409 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1410 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1411 | baca51fa | bellard | return;
|
1412 | baca51fa | bellard | case 1: |
1413 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_SEEK; |
1414 | baca51fa | bellard | break;
|
1415 | baca51fa | bellard | default:
|
1416 | baca51fa | bellard | break;
|
1417 | baca51fa | bellard | } |
1418 | baca51fa | bellard | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1419 | baca51fa | bellard | if (cur_drv->bs == NULL || |
1420 | baca51fa | bellard | bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1421 | 37a4c539 | ths | FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
|
1422 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1423 | baca51fa | bellard | } else {
|
1424 | 4f431960 | j_mayer | if (cur_drv->sect == cur_drv->last_sect) {
|
1425 | 4f431960 | j_mayer | fdctrl->data_state &= ~FD_STATE_FORMAT; |
1426 | 4f431960 | j_mayer | /* Last sector done */
|
1427 | 4f431960 | j_mayer | if (FD_DID_SEEK(fdctrl->data_state))
|
1428 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1429 | 4f431960 | j_mayer | else
|
1430 | 4f431960 | j_mayer | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1431 | 4f431960 | j_mayer | } else {
|
1432 | 4f431960 | j_mayer | /* More to do */
|
1433 | 4f431960 | j_mayer | fdctrl->data_pos = 0;
|
1434 | 4f431960 | j_mayer | fdctrl->data_len = 4;
|
1435 | 4f431960 | j_mayer | } |
1436 | baca51fa | bellard | } |
1437 | baca51fa | bellard | } |
1438 | baca51fa | bellard | |
1439 | 65cef780 | blueswir1 | static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction) |
1440 | 65cef780 | blueswir1 | { |
1441 | 65cef780 | blueswir1 | fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; |
1442 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->lock << 4; |
1443 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
|
1444 | 65cef780 | blueswir1 | } |
1445 | 65cef780 | blueswir1 | |
1446 | 65cef780 | blueswir1 | static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction) |
1447 | 65cef780 | blueswir1 | { |
1448 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1449 | 65cef780 | blueswir1 | |
1450 | 65cef780 | blueswir1 | /* Drives position */
|
1451 | 65cef780 | blueswir1 | fdctrl->fifo[0] = drv0(fdctrl)->track;
|
1452 | 65cef780 | blueswir1 | fdctrl->fifo[1] = drv1(fdctrl)->track;
|
1453 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1454 | 78ae820c | blueswir1 | fdctrl->fifo[2] = drv2(fdctrl)->track;
|
1455 | 78ae820c | blueswir1 | fdctrl->fifo[3] = drv3(fdctrl)->track;
|
1456 | 78ae820c | blueswir1 | #else
|
1457 | 65cef780 | blueswir1 | fdctrl->fifo[2] = 0; |
1458 | 65cef780 | blueswir1 | fdctrl->fifo[3] = 0; |
1459 | 78ae820c | blueswir1 | #endif
|
1460 | 65cef780 | blueswir1 | /* timers */
|
1461 | 65cef780 | blueswir1 | fdctrl->fifo[4] = fdctrl->timer0;
|
1462 | 368df94d | blueswir1 | fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
1463 | 65cef780 | blueswir1 | fdctrl->fifo[6] = cur_drv->last_sect;
|
1464 | 65cef780 | blueswir1 | fdctrl->fifo[7] = (fdctrl->lock << 7) | |
1465 | 65cef780 | blueswir1 | (cur_drv->perpendicular << 2);
|
1466 | 65cef780 | blueswir1 | fdctrl->fifo[8] = fdctrl->config;
|
1467 | 65cef780 | blueswir1 | fdctrl->fifo[9] = fdctrl->precomp_trk;
|
1468 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 10, 0); |
1469 | 65cef780 | blueswir1 | } |
1470 | 65cef780 | blueswir1 | |
1471 | 65cef780 | blueswir1 | static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction) |
1472 | 65cef780 | blueswir1 | { |
1473 | 65cef780 | blueswir1 | /* Controller's version */
|
1474 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->version;
|
1475 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1476 | 65cef780 | blueswir1 | } |
1477 | 65cef780 | blueswir1 | |
1478 | 65cef780 | blueswir1 | static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction) |
1479 | 65cef780 | blueswir1 | { |
1480 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0x41; /* Stepping 1 */ |
1481 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 0); |
1482 | 65cef780 | blueswir1 | } |
1483 | 65cef780 | blueswir1 | |
1484 | 65cef780 | blueswir1 | static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction) |
1485 | 65cef780 | blueswir1 | { |
1486 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1487 | 65cef780 | blueswir1 | |
1488 | 65cef780 | blueswir1 | /* Drives position */
|
1489 | 65cef780 | blueswir1 | drv0(fdctrl)->track = fdctrl->fifo[3];
|
1490 | 65cef780 | blueswir1 | drv1(fdctrl)->track = fdctrl->fifo[4];
|
1491 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1492 | 78ae820c | blueswir1 | drv2(fdctrl)->track = fdctrl->fifo[5];
|
1493 | 78ae820c | blueswir1 | drv3(fdctrl)->track = fdctrl->fifo[6];
|
1494 | 78ae820c | blueswir1 | #endif
|
1495 | 65cef780 | blueswir1 | /* timers */
|
1496 | 65cef780 | blueswir1 | fdctrl->timer0 = fdctrl->fifo[7];
|
1497 | 65cef780 | blueswir1 | fdctrl->timer1 = fdctrl->fifo[8];
|
1498 | 65cef780 | blueswir1 | cur_drv->last_sect = fdctrl->fifo[9];
|
1499 | 65cef780 | blueswir1 | fdctrl->lock = fdctrl->fifo[10] >> 7; |
1500 | 65cef780 | blueswir1 | cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; |
1501 | 65cef780 | blueswir1 | fdctrl->config = fdctrl->fifo[11];
|
1502 | 65cef780 | blueswir1 | fdctrl->precomp_trk = fdctrl->fifo[12];
|
1503 | 65cef780 | blueswir1 | fdctrl->pwrd = fdctrl->fifo[13];
|
1504 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1505 | 65cef780 | blueswir1 | } |
1506 | 65cef780 | blueswir1 | |
1507 | 65cef780 | blueswir1 | static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction) |
1508 | 65cef780 | blueswir1 | { |
1509 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1510 | 65cef780 | blueswir1 | |
1511 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0; |
1512 | 65cef780 | blueswir1 | fdctrl->fifo[1] = 0; |
1513 | 65cef780 | blueswir1 | /* Drives position */
|
1514 | 65cef780 | blueswir1 | fdctrl->fifo[2] = drv0(fdctrl)->track;
|
1515 | 65cef780 | blueswir1 | fdctrl->fifo[3] = drv1(fdctrl)->track;
|
1516 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1517 | 78ae820c | blueswir1 | fdctrl->fifo[4] = drv2(fdctrl)->track;
|
1518 | 78ae820c | blueswir1 | fdctrl->fifo[5] = drv3(fdctrl)->track;
|
1519 | 78ae820c | blueswir1 | #else
|
1520 | 65cef780 | blueswir1 | fdctrl->fifo[4] = 0; |
1521 | 65cef780 | blueswir1 | fdctrl->fifo[5] = 0; |
1522 | 78ae820c | blueswir1 | #endif
|
1523 | 65cef780 | blueswir1 | /* timers */
|
1524 | 65cef780 | blueswir1 | fdctrl->fifo[6] = fdctrl->timer0;
|
1525 | 65cef780 | blueswir1 | fdctrl->fifo[7] = fdctrl->timer1;
|
1526 | 65cef780 | blueswir1 | fdctrl->fifo[8] = cur_drv->last_sect;
|
1527 | 65cef780 | blueswir1 | fdctrl->fifo[9] = (fdctrl->lock << 7) | |
1528 | 65cef780 | blueswir1 | (cur_drv->perpendicular << 2);
|
1529 | 65cef780 | blueswir1 | fdctrl->fifo[10] = fdctrl->config;
|
1530 | 65cef780 | blueswir1 | fdctrl->fifo[11] = fdctrl->precomp_trk;
|
1531 | 65cef780 | blueswir1 | fdctrl->fifo[12] = fdctrl->pwrd;
|
1532 | 65cef780 | blueswir1 | fdctrl->fifo[13] = 0; |
1533 | 65cef780 | blueswir1 | fdctrl->fifo[14] = 0; |
1534 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 15, 1); |
1535 | 65cef780 | blueswir1 | } |
1536 | 65cef780 | blueswir1 | |
1537 | 65cef780 | blueswir1 | static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction) |
1538 | 65cef780 | blueswir1 | { |
1539 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1540 | 65cef780 | blueswir1 | |
1541 | 65cef780 | blueswir1 | /* XXX: should set main status register to busy */
|
1542 | 65cef780 | blueswir1 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1543 | 65cef780 | blueswir1 | qemu_mod_timer(fdctrl->result_timer, |
1544 | 65cef780 | blueswir1 | qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
|
1545 | 65cef780 | blueswir1 | } |
1546 | 65cef780 | blueswir1 | |
1547 | 65cef780 | blueswir1 | static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction) |
1548 | 65cef780 | blueswir1 | { |
1549 | 65cef780 | blueswir1 | fdrive_t *cur_drv; |
1550 | 65cef780 | blueswir1 | |
1551 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1552 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1553 | 65cef780 | blueswir1 | fdctrl->data_state |= FD_STATE_FORMAT; |
1554 | 65cef780 | blueswir1 | if (fdctrl->fifo[0] & 0x80) |
1555 | 65cef780 | blueswir1 | fdctrl->data_state |= FD_STATE_MULTI; |
1556 | 65cef780 | blueswir1 | else
|
1557 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_MULTI; |
1558 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_SEEK; |
1559 | 65cef780 | blueswir1 | cur_drv->bps = |
1560 | 65cef780 | blueswir1 | fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; |
1561 | 65cef780 | blueswir1 | #if 0
|
1562 | 65cef780 | blueswir1 | cur_drv->last_sect =
|
1563 | 65cef780 | blueswir1 | cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
|
1564 | 65cef780 | blueswir1 | fdctrl->fifo[3] / 2;
|
1565 | 65cef780 | blueswir1 | #else
|
1566 | 65cef780 | blueswir1 | cur_drv->last_sect = fdctrl->fifo[3];
|
1567 | 65cef780 | blueswir1 | #endif
|
1568 | 65cef780 | blueswir1 | /* TODO: implement format using DMA expected by the Bochs BIOS
|
1569 | 65cef780 | blueswir1 | * and Linux fdformat (read 3 bytes per sector via DMA and fill
|
1570 | 65cef780 | blueswir1 | * the sector with the specified fill byte
|
1571 | 65cef780 | blueswir1 | */
|
1572 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_FORMAT; |
1573 | 65cef780 | blueswir1 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1574 | 65cef780 | blueswir1 | } |
1575 | 65cef780 | blueswir1 | |
1576 | 65cef780 | blueswir1 | static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction) |
1577 | 65cef780 | blueswir1 | { |
1578 | 65cef780 | blueswir1 | fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; |
1579 | 65cef780 | blueswir1 | fdctrl->timer1 = fdctrl->fifo[2] >> 1; |
1580 | 368df94d | blueswir1 | if (fdctrl->fifo[2] & 1) |
1581 | 368df94d | blueswir1 | fdctrl->dor &= ~FD_DOR_DMAEN; |
1582 | 368df94d | blueswir1 | else
|
1583 | 368df94d | blueswir1 | fdctrl->dor |= FD_DOR_DMAEN; |
1584 | 65cef780 | blueswir1 | /* No result back */
|
1585 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1586 | 65cef780 | blueswir1 | } |
1587 | 65cef780 | blueswir1 | |
1588 | 65cef780 | blueswir1 | static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction) |
1589 | 65cef780 | blueswir1 | { |
1590 | 65cef780 | blueswir1 | fdrive_t *cur_drv; |
1591 | 65cef780 | blueswir1 | |
1592 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1593 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1594 | 65cef780 | blueswir1 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1595 | 65cef780 | blueswir1 | /* 1 Byte status back */
|
1596 | 65cef780 | blueswir1 | fdctrl->fifo[0] = (cur_drv->ro << 6) | |
1597 | 65cef780 | blueswir1 | (cur_drv->track == 0 ? 0x10 : 0x00) | |
1598 | 65cef780 | blueswir1 | (cur_drv->head << 2) |
|
1599 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl) | |
1600 | 65cef780 | blueswir1 | 0x28;
|
1601 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 0); |
1602 | 65cef780 | blueswir1 | } |
1603 | 65cef780 | blueswir1 | |
1604 | 65cef780 | blueswir1 | static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction) |
1605 | 65cef780 | blueswir1 | { |
1606 | 65cef780 | blueswir1 | fdrive_t *cur_drv; |
1607 | 65cef780 | blueswir1 | |
1608 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1609 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1610 | 65cef780 | blueswir1 | fd_recalibrate(cur_drv); |
1611 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1612 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1613 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1614 | 65cef780 | blueswir1 | } |
1615 | 65cef780 | blueswir1 | |
1616 | 65cef780 | blueswir1 | static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction) |
1617 | 65cef780 | blueswir1 | { |
1618 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1619 | 65cef780 | blueswir1 | |
1620 | f2d81b33 | blueswir1 | if(fdctrl->reset_sensei > 0) { |
1621 | f2d81b33 | blueswir1 | fdctrl->fifo[0] =
|
1622 | f2d81b33 | blueswir1 | FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; |
1623 | f2d81b33 | blueswir1 | fdctrl->reset_sensei--; |
1624 | f2d81b33 | blueswir1 | } else {
|
1625 | f2d81b33 | blueswir1 | /* XXX: status0 handling is broken for read/write
|
1626 | f2d81b33 | blueswir1 | commands, so we do this hack. It should be suppressed
|
1627 | f2d81b33 | blueswir1 | ASAP */
|
1628 | f2d81b33 | blueswir1 | fdctrl->fifo[0] =
|
1629 | f2d81b33 | blueswir1 | FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1630 | f2d81b33 | blueswir1 | } |
1631 | f2d81b33 | blueswir1 | |
1632 | 65cef780 | blueswir1 | fdctrl->fifo[1] = cur_drv->track;
|
1633 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 2, 0); |
1634 | 65cef780 | blueswir1 | fdctrl_reset_irq(fdctrl); |
1635 | 77370520 | blueswir1 | fdctrl->status0 = FD_SR0_RDYCHG; |
1636 | 65cef780 | blueswir1 | } |
1637 | 65cef780 | blueswir1 | |
1638 | 65cef780 | blueswir1 | static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction) |
1639 | 65cef780 | blueswir1 | { |
1640 | 65cef780 | blueswir1 | fdrive_t *cur_drv; |
1641 | 65cef780 | blueswir1 | |
1642 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1643 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1644 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1645 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] > cur_drv->max_track) { |
1646 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK); |
1647 | 65cef780 | blueswir1 | } else {
|
1648 | 65cef780 | blueswir1 | cur_drv->track = fdctrl->fifo[2];
|
1649 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1650 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1651 | 65cef780 | blueswir1 | } |
1652 | 65cef780 | blueswir1 | } |
1653 | 65cef780 | blueswir1 | |
1654 | 65cef780 | blueswir1 | static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction) |
1655 | 65cef780 | blueswir1 | { |
1656 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1657 | 65cef780 | blueswir1 | |
1658 | 65cef780 | blueswir1 | if (fdctrl->fifo[1] & 0x80) |
1659 | 65cef780 | blueswir1 | cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; |
1660 | 65cef780 | blueswir1 | /* No result back */
|
1661 | 1c346df2 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1662 | 65cef780 | blueswir1 | } |
1663 | 65cef780 | blueswir1 | |
1664 | 65cef780 | blueswir1 | static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction) |
1665 | 65cef780 | blueswir1 | { |
1666 | 65cef780 | blueswir1 | fdctrl->config = fdctrl->fifo[2];
|
1667 | 65cef780 | blueswir1 | fdctrl->precomp_trk = fdctrl->fifo[3];
|
1668 | 65cef780 | blueswir1 | /* No result back */
|
1669 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1670 | 65cef780 | blueswir1 | } |
1671 | 65cef780 | blueswir1 | |
1672 | 65cef780 | blueswir1 | static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction) |
1673 | 65cef780 | blueswir1 | { |
1674 | 65cef780 | blueswir1 | fdctrl->pwrd = fdctrl->fifo[1];
|
1675 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
1676 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1677 | 65cef780 | blueswir1 | } |
1678 | 65cef780 | blueswir1 | |
1679 | 65cef780 | blueswir1 | static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction) |
1680 | 65cef780 | blueswir1 | { |
1681 | 65cef780 | blueswir1 | /* No result back */
|
1682 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1683 | 65cef780 | blueswir1 | } |
1684 | 65cef780 | blueswir1 | |
1685 | 65cef780 | blueswir1 | static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction) |
1686 | 65cef780 | blueswir1 | { |
1687 | 65cef780 | blueswir1 | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1688 | 65cef780 | blueswir1 | |
1689 | 65cef780 | blueswir1 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { |
1690 | 65cef780 | blueswir1 | /* Command parameters done */
|
1691 | 65cef780 | blueswir1 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { |
1692 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
1693 | 65cef780 | blueswir1 | fdctrl->fifo[2] = 0; |
1694 | 65cef780 | blueswir1 | fdctrl->fifo[3] = 0; |
1695 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 4, 1); |
1696 | 65cef780 | blueswir1 | } else {
|
1697 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1698 | 65cef780 | blueswir1 | } |
1699 | 65cef780 | blueswir1 | } else if (fdctrl->data_len > 7) { |
1700 | 65cef780 | blueswir1 | /* ERROR */
|
1701 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0x80 | |
1702 | cefec4f5 | blueswir1 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1703 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1704 | 65cef780 | blueswir1 | } |
1705 | 65cef780 | blueswir1 | } |
1706 | 65cef780 | blueswir1 | |
1707 | 65cef780 | blueswir1 | static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction) |
1708 | 65cef780 | blueswir1 | { |
1709 | 77370520 | blueswir1 | fdrive_t *cur_drv; |
1710 | 65cef780 | blueswir1 | |
1711 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1712 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1713 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
1714 | 65cef780 | blueswir1 | cur_drv->track = cur_drv->max_track - 1;
|
1715 | 65cef780 | blueswir1 | } else {
|
1716 | 65cef780 | blueswir1 | cur_drv->track += fdctrl->fifo[2];
|
1717 | 65cef780 | blueswir1 | } |
1718 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1719 | 77370520 | blueswir1 | /* Raise Interrupt */
|
1720 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1721 | 65cef780 | blueswir1 | } |
1722 | 65cef780 | blueswir1 | |
1723 | 65cef780 | blueswir1 | static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction) |
1724 | 65cef780 | blueswir1 | { |
1725 | 77370520 | blueswir1 | fdrive_t *cur_drv; |
1726 | 65cef780 | blueswir1 | |
1727 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1728 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1729 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] > cur_drv->track) { |
1730 | 65cef780 | blueswir1 | cur_drv->track = 0;
|
1731 | 65cef780 | blueswir1 | } else {
|
1732 | 65cef780 | blueswir1 | cur_drv->track -= fdctrl->fifo[2];
|
1733 | 65cef780 | blueswir1 | } |
1734 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1735 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1736 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1737 | 65cef780 | blueswir1 | } |
1738 | 65cef780 | blueswir1 | |
1739 | 678803ab | blueswir1 | static const struct { |
1740 | 678803ab | blueswir1 | uint8_t value; |
1741 | 678803ab | blueswir1 | uint8_t mask; |
1742 | 678803ab | blueswir1 | const char* name; |
1743 | 678803ab | blueswir1 | int parameters;
|
1744 | 678803ab | blueswir1 | void (*handler)(fdctrl_t *fdctrl, int direction); |
1745 | 678803ab | blueswir1 | int direction;
|
1746 | 678803ab | blueswir1 | } handlers[] = { |
1747 | 678803ab | blueswir1 | { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1748 | 678803ab | blueswir1 | { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, |
1749 | 678803ab | blueswir1 | { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, |
1750 | 678803ab | blueswir1 | { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, |
1751 | 678803ab | blueswir1 | { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, |
1752 | 678803ab | blueswir1 | { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, |
1753 | 678803ab | blueswir1 | { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1754 | 678803ab | blueswir1 | { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ |
1755 | 678803ab | blueswir1 | { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ |
1756 | 678803ab | blueswir1 | { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, |
1757 | 678803ab | blueswir1 | { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, |
1758 | 678803ab | blueswir1 | { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented }, |
1759 | 678803ab | blueswir1 | { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, |
1760 | 678803ab | blueswir1 | { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, |
1761 | 678803ab | blueswir1 | { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, |
1762 | 678803ab | blueswir1 | { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, |
1763 | 678803ab | blueswir1 | { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, |
1764 | 678803ab | blueswir1 | { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, |
1765 | 678803ab | blueswir1 | { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, |
1766 | 678803ab | blueswir1 | { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, |
1767 | 678803ab | blueswir1 | { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, |
1768 | 678803ab | blueswir1 | { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, |
1769 | 678803ab | blueswir1 | { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, |
1770 | 678803ab | blueswir1 | { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, |
1771 | 678803ab | blueswir1 | { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, |
1772 | 678803ab | blueswir1 | { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, |
1773 | 678803ab | blueswir1 | { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, |
1774 | 678803ab | blueswir1 | { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, |
1775 | 678803ab | blueswir1 | { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, |
1776 | 678803ab | blueswir1 | { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, |
1777 | 678803ab | blueswir1 | { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ |
1778 | 678803ab | blueswir1 | { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ |
1779 | 678803ab | blueswir1 | }; |
1780 | 678803ab | blueswir1 | /* Associate command to an index in the 'handlers' array */
|
1781 | 678803ab | blueswir1 | static uint8_t command_to_handler[256]; |
1782 | 678803ab | blueswir1 | |
1783 | baca51fa | bellard | static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value) |
1784 | baca51fa | bellard | { |
1785 | baca51fa | bellard | fdrive_t *cur_drv; |
1786 | 65cef780 | blueswir1 | int pos;
|
1787 | baca51fa | bellard | |
1788 | 8977f3c1 | bellard | /* Reset mode */
|
1789 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
1790 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
1791 | 8977f3c1 | bellard | return;
|
1792 | 8977f3c1 | bellard | } |
1793 | b9b3d225 | blueswir1 | if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
|
1794 | b9b3d225 | blueswir1 | FLOPPY_ERROR("controller not ready for writing\n");
|
1795 | 8977f3c1 | bellard | return;
|
1796 | 8977f3c1 | bellard | } |
1797 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1798 | 8977f3c1 | bellard | /* Is it write command time ? */
|
1799 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1800 | 8977f3c1 | bellard | /* FIFO data write */
|
1801 | b3bc1540 | blueswir1 | pos = fdctrl->data_pos++; |
1802 | b3bc1540 | blueswir1 | pos %= FD_SECTOR_LEN; |
1803 | b3bc1540 | blueswir1 | fdctrl->fifo[pos] = value; |
1804 | b3bc1540 | blueswir1 | if (pos == FD_SECTOR_LEN - 1 || |
1805 | baca51fa | bellard | fdctrl->data_pos == fdctrl->data_len) { |
1806 | 77370520 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1807 | 77370520 | blueswir1 | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1808 | 77370520 | blueswir1 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1809 | 77370520 | blueswir1 | return;
|
1810 | 77370520 | blueswir1 | } |
1811 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1812 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1813 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
1814 | 746d6de7 | blueswir1 | return;
|
1815 | 746d6de7 | blueswir1 | } |
1816 | 8977f3c1 | bellard | } |
1817 | 890fa6be | bellard | /* Switch from transfer mode to status mode
|
1818 | 8977f3c1 | bellard | * then from status mode to command mode
|
1819 | 8977f3c1 | bellard | */
|
1820 | b9b3d225 | blueswir1 | if (fdctrl->data_pos == fdctrl->data_len)
|
1821 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1822 | 8977f3c1 | bellard | return;
|
1823 | 8977f3c1 | bellard | } |
1824 | baca51fa | bellard | if (fdctrl->data_pos == 0) { |
1825 | 8977f3c1 | bellard | /* Command */
|
1826 | 678803ab | blueswir1 | pos = command_to_handler[value & 0xff];
|
1827 | 678803ab | blueswir1 | FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
|
1828 | 678803ab | blueswir1 | fdctrl->data_len = handlers[pos].parameters + 1;
|
1829 | 8977f3c1 | bellard | } |
1830 | 678803ab | blueswir1 | |
1831 | baca51fa | bellard | FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
|
1832 | 77370520 | blueswir1 | fdctrl->fifo[fdctrl->data_pos++] = value; |
1833 | 77370520 | blueswir1 | if (fdctrl->data_pos == fdctrl->data_len) {
|
1834 | 8977f3c1 | bellard | /* We now have all parameters
|
1835 | 8977f3c1 | bellard | * and will be able to treat the command
|
1836 | 8977f3c1 | bellard | */
|
1837 | 4f431960 | j_mayer | if (fdctrl->data_state & FD_STATE_FORMAT) {
|
1838 | 4f431960 | j_mayer | fdctrl_format_sector(fdctrl); |
1839 | 8977f3c1 | bellard | return;
|
1840 | 8977f3c1 | bellard | } |
1841 | 65cef780 | blueswir1 | |
1842 | 678803ab | blueswir1 | pos = command_to_handler[fdctrl->fifo[0] & 0xff]; |
1843 | 678803ab | blueswir1 | FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
|
1844 | 678803ab | blueswir1 | (*handlers[pos].handler)(fdctrl, handlers[pos].direction); |
1845 | 8977f3c1 | bellard | } |
1846 | 8977f3c1 | bellard | } |
1847 | ed5fd2cc | bellard | |
1848 | ed5fd2cc | bellard | static void fdctrl_result_timer(void *opaque) |
1849 | ed5fd2cc | bellard | { |
1850 | ed5fd2cc | bellard | fdctrl_t *fdctrl = opaque; |
1851 | b7ffa3b1 | ths | fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1852 | 4f431960 | j_mayer | |
1853 | b7ffa3b1 | ths | /* Pretend we are spinning.
|
1854 | b7ffa3b1 | ths | * This is needed for Coherent, which uses READ ID to check for
|
1855 | b7ffa3b1 | ths | * sector interleaving.
|
1856 | b7ffa3b1 | ths | */
|
1857 | b7ffa3b1 | ths | if (cur_drv->last_sect != 0) { |
1858 | b7ffa3b1 | ths | cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
|
1859 | b7ffa3b1 | ths | } |
1860 | ed5fd2cc | bellard | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1861 | ed5fd2cc | bellard | } |
1862 | 678803ab | blueswir1 | |
1863 | 678803ab | blueswir1 | /* Init functions */
|
1864 | 12a71a02 | Blue Swirl | static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds) |
1865 | 678803ab | blueswir1 | { |
1866 | 12a71a02 | Blue Swirl | unsigned int i; |
1867 | 678803ab | blueswir1 | |
1868 | 678803ab | blueswir1 | for (i = 0; i < MAX_FD; i++) { |
1869 | 678803ab | blueswir1 | fd_init(&fdctrl->drives[i], fds[i]); |
1870 | 678803ab | blueswir1 | fd_revalidate(&fdctrl->drives[i]); |
1871 | 678803ab | blueswir1 | } |
1872 | 678803ab | blueswir1 | } |
1873 | 678803ab | blueswir1 | |
1874 | 2091ba23 | Gerd Hoffmann | fdctrl_t *fdctrl_init_isa(int isairq, int dma_chann, |
1875 | 2091ba23 | Gerd Hoffmann | uint32_t io_base, |
1876 | 2091ba23 | Gerd Hoffmann | BlockDriverState **fds) |
1877 | 678803ab | blueswir1 | { |
1878 | 678803ab | blueswir1 | fdctrl_t *fdctrl; |
1879 | 2091ba23 | Gerd Hoffmann | ISADevice *dev; |
1880 | 678803ab | blueswir1 | |
1881 | e8935eef | Gerd Hoffmann | dev = isa_create_simple("isa-fdc", io_base, 0, isairq, -1); |
1882 | 2091ba23 | Gerd Hoffmann | fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state); |
1883 | 8baf73ad | Gerd Hoffmann | |
1884 | 2091ba23 | Gerd Hoffmann | fdctrl->dma_chann = dma_chann; |
1885 | 2091ba23 | Gerd Hoffmann | DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); |
1886 | 8baf73ad | Gerd Hoffmann | |
1887 | 2091ba23 | Gerd Hoffmann | fdctrl_connect_drives(fdctrl, fds); |
1888 | 2091ba23 | Gerd Hoffmann | |
1889 | 2091ba23 | Gerd Hoffmann | return fdctrl;
|
1890 | 2091ba23 | Gerd Hoffmann | } |
1891 | 2091ba23 | Gerd Hoffmann | |
1892 | 2091ba23 | Gerd Hoffmann | fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
|
1893 | 2091ba23 | Gerd Hoffmann | target_phys_addr_t mmio_base, |
1894 | 2091ba23 | Gerd Hoffmann | BlockDriverState **fds) |
1895 | 2091ba23 | Gerd Hoffmann | { |
1896 | 2091ba23 | Gerd Hoffmann | fdctrl_t *fdctrl; |
1897 | 2091ba23 | Gerd Hoffmann | DeviceState *dev; |
1898 | 2091ba23 | Gerd Hoffmann | fdctrl_sysbus_t *sys; |
1899 | 2091ba23 | Gerd Hoffmann | |
1900 | 2091ba23 | Gerd Hoffmann | dev = qdev_create(NULL, "sysbus-fdc"); |
1901 | 2091ba23 | Gerd Hoffmann | qdev_init(dev); |
1902 | 2091ba23 | Gerd Hoffmann | sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); |
1903 | 2091ba23 | Gerd Hoffmann | fdctrl = &sys->state; |
1904 | 2091ba23 | Gerd Hoffmann | sysbus_connect_irq(&sys->busdev, 0, irq);
|
1905 | 2091ba23 | Gerd Hoffmann | sysbus_mmio_map(&sys->busdev, 0, mmio_base);
|
1906 | 8baf73ad | Gerd Hoffmann | |
1907 | 12a71a02 | Blue Swirl | fdctrl->dma_chann = dma_chann; |
1908 | 12a71a02 | Blue Swirl | DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); |
1909 | 12a71a02 | Blue Swirl | fdctrl_connect_drives(fdctrl, fds); |
1910 | f64ab228 | Blue Swirl | |
1911 | 678803ab | blueswir1 | return fdctrl;
|
1912 | 678803ab | blueswir1 | } |
1913 | 678803ab | blueswir1 | |
1914 | 678803ab | blueswir1 | fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, |
1915 | 678803ab | blueswir1 | BlockDriverState **fds, qemu_irq *fdc_tc) |
1916 | 678803ab | blueswir1 | { |
1917 | f64ab228 | Blue Swirl | DeviceState *dev; |
1918 | 8baf73ad | Gerd Hoffmann | fdctrl_sysbus_t *sys; |
1919 | 678803ab | blueswir1 | fdctrl_t *fdctrl; |
1920 | 678803ab | blueswir1 | |
1921 | 12a71a02 | Blue Swirl | dev = qdev_create(NULL, "SUNW,fdtwo"); |
1922 | f64ab228 | Blue Swirl | qdev_init(dev); |
1923 | 8baf73ad | Gerd Hoffmann | sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); |
1924 | 8baf73ad | Gerd Hoffmann | fdctrl = &sys->state; |
1925 | 8baf73ad | Gerd Hoffmann | sysbus_connect_irq(&sys->busdev, 0, irq);
|
1926 | 8baf73ad | Gerd Hoffmann | sysbus_mmio_map(&sys->busdev, 0, io_base);
|
1927 | f64ab228 | Blue Swirl | *fdc_tc = qdev_get_gpio_in(dev, 0);
|
1928 | f64ab228 | Blue Swirl | |
1929 | 12a71a02 | Blue Swirl | fdctrl->dma_chann = -1;
|
1930 | 12a71a02 | Blue Swirl | |
1931 | 12a71a02 | Blue Swirl | fdctrl_connect_drives(fdctrl, fds); |
1932 | 678803ab | blueswir1 | |
1933 | 678803ab | blueswir1 | return fdctrl;
|
1934 | 678803ab | blueswir1 | } |
1935 | f64ab228 | Blue Swirl | |
1936 | 81a322d4 | Gerd Hoffmann | static int fdctrl_init_common(fdctrl_t *fdctrl) |
1937 | f64ab228 | Blue Swirl | { |
1938 | 12a71a02 | Blue Swirl | int i, j;
|
1939 | 12a71a02 | Blue Swirl | static int command_tables_inited = 0; |
1940 | f64ab228 | Blue Swirl | |
1941 | 12a71a02 | Blue Swirl | /* Fill 'command_to_handler' lookup table */
|
1942 | 12a71a02 | Blue Swirl | if (!command_tables_inited) {
|
1943 | 12a71a02 | Blue Swirl | command_tables_inited = 1;
|
1944 | 12a71a02 | Blue Swirl | for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { |
1945 | 12a71a02 | Blue Swirl | for (j = 0; j < sizeof(command_to_handler); j++) { |
1946 | 12a71a02 | Blue Swirl | if ((j & handlers[i].mask) == handlers[i].value) {
|
1947 | 12a71a02 | Blue Swirl | command_to_handler[j] = i; |
1948 | 12a71a02 | Blue Swirl | } |
1949 | 12a71a02 | Blue Swirl | } |
1950 | 12a71a02 | Blue Swirl | } |
1951 | 12a71a02 | Blue Swirl | } |
1952 | 12a71a02 | Blue Swirl | |
1953 | 12a71a02 | Blue Swirl | FLOPPY_DPRINTF("init controller\n");
|
1954 | 12a71a02 | Blue Swirl | fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
|
1955 | 12a71a02 | Blue Swirl | fdctrl->result_timer = qemu_new_timer(vm_clock, |
1956 | 12a71a02 | Blue Swirl | fdctrl_result_timer, fdctrl); |
1957 | 12a71a02 | Blue Swirl | |
1958 | 12a71a02 | Blue Swirl | fdctrl->version = 0x90; /* Intel 82078 controller */ |
1959 | 12a71a02 | Blue Swirl | fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
|
1960 | 12a71a02 | Blue Swirl | |
1961 | 12a71a02 | Blue Swirl | fdctrl_external_reset(fdctrl); |
1962 | 12a71a02 | Blue Swirl | register_savevm("fdc", -1, 2, fdc_save, fdc_load, fdctrl); |
1963 | 12a71a02 | Blue Swirl | qemu_register_reset(fdctrl_external_reset, fdctrl); |
1964 | 81a322d4 | Gerd Hoffmann | return 0; |
1965 | f64ab228 | Blue Swirl | } |
1966 | f64ab228 | Blue Swirl | |
1967 | 81a322d4 | Gerd Hoffmann | static int isabus_fdc_init1(ISADevice *dev) |
1968 | 8baf73ad | Gerd Hoffmann | { |
1969 | 8baf73ad | Gerd Hoffmann | fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev); |
1970 | 8baf73ad | Gerd Hoffmann | fdctrl_t *fdctrl = &isa->state; |
1971 | 8baf73ad | Gerd Hoffmann | |
1972 | 8baf73ad | Gerd Hoffmann | register_ioport_read(isa->busdev.iobase[0] + 0x01, 5, 1, |
1973 | 8baf73ad | Gerd Hoffmann | &fdctrl_read_port, fdctrl); |
1974 | 8baf73ad | Gerd Hoffmann | register_ioport_read(isa->busdev.iobase[0] + 0x07, 1, 1, |
1975 | 8baf73ad | Gerd Hoffmann | &fdctrl_read_port, fdctrl); |
1976 | 8baf73ad | Gerd Hoffmann | register_ioport_write(isa->busdev.iobase[0] + 0x01, 5, 1, |
1977 | 8baf73ad | Gerd Hoffmann | &fdctrl_write_port, fdctrl); |
1978 | 8baf73ad | Gerd Hoffmann | register_ioport_write(isa->busdev.iobase[0] + 0x07, 1, 1, |
1979 | 8baf73ad | Gerd Hoffmann | &fdctrl_write_port, fdctrl); |
1980 | 8baf73ad | Gerd Hoffmann | isa_init_irq(&isa->busdev, &fdctrl->irq); |
1981 | 8baf73ad | Gerd Hoffmann | |
1982 | 81a322d4 | Gerd Hoffmann | return fdctrl_init_common(fdctrl);
|
1983 | 8baf73ad | Gerd Hoffmann | } |
1984 | 8baf73ad | Gerd Hoffmann | |
1985 | 81a322d4 | Gerd Hoffmann | static int sysbus_fdc_init1(SysBusDevice *dev) |
1986 | 12a71a02 | Blue Swirl | { |
1987 | 8baf73ad | Gerd Hoffmann | fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); |
1988 | 12a71a02 | Blue Swirl | int io;
|
1989 | 12a71a02 | Blue Swirl | |
1990 | 12a71a02 | Blue Swirl | io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl); |
1991 | 8baf73ad | Gerd Hoffmann | sysbus_init_mmio(dev, 0x08, io);
|
1992 | 8baf73ad | Gerd Hoffmann | sysbus_init_irq(dev, &fdctrl->irq); |
1993 | 8baf73ad | Gerd Hoffmann | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
1994 | 8baf73ad | Gerd Hoffmann | |
1995 | 81a322d4 | Gerd Hoffmann | return fdctrl_init_common(fdctrl);
|
1996 | 12a71a02 | Blue Swirl | } |
1997 | 12a71a02 | Blue Swirl | |
1998 | 81a322d4 | Gerd Hoffmann | static int sun4m_fdc_init1(SysBusDevice *dev) |
1999 | 12a71a02 | Blue Swirl | { |
2000 | 8baf73ad | Gerd Hoffmann | fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); |
2001 | 12a71a02 | Blue Swirl | int io;
|
2002 | 12a71a02 | Blue Swirl | |
2003 | 12a71a02 | Blue Swirl | io = cpu_register_io_memory(fdctrl_mem_read_strict, |
2004 | 12a71a02 | Blue Swirl | fdctrl_mem_write_strict, fdctrl); |
2005 | 8baf73ad | Gerd Hoffmann | sysbus_init_mmio(dev, 0x08, io);
|
2006 | 8baf73ad | Gerd Hoffmann | sysbus_init_irq(dev, &fdctrl->irq); |
2007 | 8baf73ad | Gerd Hoffmann | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
2008 | 8baf73ad | Gerd Hoffmann | |
2009 | 8baf73ad | Gerd Hoffmann | fdctrl->sun4m = 1;
|
2010 | 81a322d4 | Gerd Hoffmann | return fdctrl_init_common(fdctrl);
|
2011 | 12a71a02 | Blue Swirl | } |
2012 | f64ab228 | Blue Swirl | |
2013 | 8baf73ad | Gerd Hoffmann | static ISADeviceInfo isa_fdc_info = {
|
2014 | 8baf73ad | Gerd Hoffmann | .init = isabus_fdc_init1, |
2015 | 8baf73ad | Gerd Hoffmann | .qdev.name = "isa-fdc",
|
2016 | 8baf73ad | Gerd Hoffmann | .qdev.size = sizeof(fdctrl_isabus_t),
|
2017 | 8baf73ad | Gerd Hoffmann | }; |
2018 | 8baf73ad | Gerd Hoffmann | |
2019 | 8baf73ad | Gerd Hoffmann | static SysBusDeviceInfo sysbus_fdc_info = {
|
2020 | 8baf73ad | Gerd Hoffmann | .init = sysbus_fdc_init1, |
2021 | 8baf73ad | Gerd Hoffmann | .qdev.name = "sysbus-fdc",
|
2022 | 8baf73ad | Gerd Hoffmann | .qdev.size = sizeof(fdctrl_sysbus_t),
|
2023 | 12a71a02 | Blue Swirl | }; |
2024 | 12a71a02 | Blue Swirl | |
2025 | 12a71a02 | Blue Swirl | static SysBusDeviceInfo sun4m_fdc_info = {
|
2026 | 12a71a02 | Blue Swirl | .init = sun4m_fdc_init1, |
2027 | 12a71a02 | Blue Swirl | .qdev.name = "SUNW,fdtwo",
|
2028 | 8baf73ad | Gerd Hoffmann | .qdev.size = sizeof(fdctrl_sysbus_t),
|
2029 | f64ab228 | Blue Swirl | }; |
2030 | f64ab228 | Blue Swirl | |
2031 | f64ab228 | Blue Swirl | static void fdc_register_devices(void) |
2032 | f64ab228 | Blue Swirl | { |
2033 | 8baf73ad | Gerd Hoffmann | isa_qdev_register(&isa_fdc_info); |
2034 | 8baf73ad | Gerd Hoffmann | sysbus_register_withprop(&sysbus_fdc_info); |
2035 | 12a71a02 | Blue Swirl | sysbus_register_withprop(&sun4m_fdc_info); |
2036 | f64ab228 | Blue Swirl | } |
2037 | f64ab228 | Blue Swirl | |
2038 | f64ab228 | Blue Swirl | device_init(fdc_register_devices) |