root / hw / unin_pci.c @ 0abaa7c1
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU Uninorth PCI host (for all Mac99 and newer machines)
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc_mac.h" |
26 | 87ecb68b | pbrook | #include "pci.h" |
27 | 87ecb68b | pbrook | |
28 | f3902383 | blueswir1 | /* debug UniNorth */
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29 | f3902383 | blueswir1 | //#define DEBUG_UNIN
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30 | f3902383 | blueswir1 | |
31 | f3902383 | blueswir1 | #ifdef DEBUG_UNIN
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32 | 001faf32 | Blue Swirl | #define UNIN_DPRINTF(fmt, ...) \
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33 | 001faf32 | Blue Swirl | do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) |
34 | f3902383 | blueswir1 | #else
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35 | 001faf32 | Blue Swirl | #define UNIN_DPRINTF(fmt, ...)
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36 | f3902383 | blueswir1 | #endif
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37 | f3902383 | blueswir1 | |
38 | 502a5395 | pbrook | typedef target_phys_addr_t pci_addr_t;
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39 | 502a5395 | pbrook | #include "pci_host.h" |
40 | 502a5395 | pbrook | |
41 | 2e29bd04 | Blue Swirl | typedef struct UNINState { |
42 | 2e29bd04 | Blue Swirl | SysBusDevice busdev; |
43 | 2e29bd04 | Blue Swirl | PCIHostState host_state; |
44 | 2e29bd04 | Blue Swirl | } UNINState; |
45 | 502a5395 | pbrook | |
46 | 502a5395 | pbrook | static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
47 | 502a5395 | pbrook | uint32_t val) |
48 | 502a5395 | pbrook | { |
49 | 502a5395 | pbrook | UNINState *s = opaque; |
50 | 502a5395 | pbrook | |
51 | f3902383 | blueswir1 | UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val); |
52 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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53 | 502a5395 | pbrook | val = bswap32(val); |
54 | 502a5395 | pbrook | #endif
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55 | 502a5395 | pbrook | |
56 | 2e29bd04 | Blue Swirl | s->host_state.config_reg = val; |
57 | 502a5395 | pbrook | } |
58 | 502a5395 | pbrook | |
59 | 502a5395 | pbrook | static uint32_t pci_unin_main_config_readl (void *opaque, |
60 | 502a5395 | pbrook | target_phys_addr_t addr) |
61 | 502a5395 | pbrook | { |
62 | 502a5395 | pbrook | UNINState *s = opaque; |
63 | 502a5395 | pbrook | uint32_t val; |
64 | 502a5395 | pbrook | |
65 | 2e29bd04 | Blue Swirl | val = s->host_state.config_reg; |
66 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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67 | 502a5395 | pbrook | val = bswap32(val); |
68 | 502a5395 | pbrook | #endif
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69 | f3902383 | blueswir1 | UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val); |
70 | 502a5395 | pbrook | |
71 | 502a5395 | pbrook | return val;
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72 | 502a5395 | pbrook | } |
73 | 502a5395 | pbrook | |
74 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = { |
75 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
76 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
77 | 502a5395 | pbrook | &pci_unin_main_config_writel, |
78 | 502a5395 | pbrook | }; |
79 | 502a5395 | pbrook | |
80 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_unin_main_config_read[] = { |
81 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
82 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
83 | 502a5395 | pbrook | &pci_unin_main_config_readl, |
84 | 502a5395 | pbrook | }; |
85 | 502a5395 | pbrook | |
86 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_unin_main_write[] = { |
87 | 502a5395 | pbrook | &pci_host_data_writeb, |
88 | 502a5395 | pbrook | &pci_host_data_writew, |
89 | 502a5395 | pbrook | &pci_host_data_writel, |
90 | 502a5395 | pbrook | }; |
91 | 502a5395 | pbrook | |
92 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_unin_main_read[] = { |
93 | 502a5395 | pbrook | &pci_host_data_readb, |
94 | 502a5395 | pbrook | &pci_host_data_readw, |
95 | 502a5395 | pbrook | &pci_host_data_readl, |
96 | 502a5395 | pbrook | }; |
97 | 502a5395 | pbrook | |
98 | 502a5395 | pbrook | static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
99 | 502a5395 | pbrook | uint32_t val) |
100 | 502a5395 | pbrook | { |
101 | 502a5395 | pbrook | UNINState *s = opaque; |
102 | 502a5395 | pbrook | |
103 | 2e29bd04 | Blue Swirl | s->host_state.config_reg = val; |
104 | 502a5395 | pbrook | } |
105 | 502a5395 | pbrook | |
106 | 502a5395 | pbrook | static uint32_t pci_unin_config_readl (void *opaque, |
107 | 502a5395 | pbrook | target_phys_addr_t addr) |
108 | 502a5395 | pbrook | { |
109 | 502a5395 | pbrook | UNINState *s = opaque; |
110 | 502a5395 | pbrook | |
111 | 2e29bd04 | Blue Swirl | return s->host_state.config_reg;
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112 | 502a5395 | pbrook | } |
113 | 502a5395 | pbrook | |
114 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_unin_config_write[] = { |
115 | 502a5395 | pbrook | &pci_unin_config_writel, |
116 | 502a5395 | pbrook | &pci_unin_config_writel, |
117 | 502a5395 | pbrook | &pci_unin_config_writel, |
118 | 502a5395 | pbrook | }; |
119 | 502a5395 | pbrook | |
120 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_unin_config_read[] = { |
121 | 502a5395 | pbrook | &pci_unin_config_readl, |
122 | 502a5395 | pbrook | &pci_unin_config_readl, |
123 | 502a5395 | pbrook | &pci_unin_config_readl, |
124 | 502a5395 | pbrook | }; |
125 | 502a5395 | pbrook | |
126 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_unin_write[] = { |
127 | 2e29bd04 | Blue Swirl | &pci_host_data_writeb, |
128 | 2e29bd04 | Blue Swirl | &pci_host_data_writew, |
129 | 2e29bd04 | Blue Swirl | &pci_host_data_writel, |
130 | 502a5395 | pbrook | }; |
131 | 502a5395 | pbrook | |
132 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_unin_read[] = { |
133 | 2e29bd04 | Blue Swirl | &pci_host_data_readb, |
134 | 2e29bd04 | Blue Swirl | &pci_host_data_readw, |
135 | 2e29bd04 | Blue Swirl | &pci_host_data_readl, |
136 | 502a5395 | pbrook | }; |
137 | 502a5395 | pbrook | |
138 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
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139 | d2b59317 | pbrook | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
140 | 502a5395 | pbrook | { |
141 | d2b59317 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
142 | d2b59317 | pbrook | } |
143 | d2b59317 | pbrook | |
144 | d537cf6c | pbrook | static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level) |
145 | d2b59317 | pbrook | { |
146 | d537cf6c | pbrook | qemu_set_irq(pic[irq_num + 8], level);
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147 | 502a5395 | pbrook | } |
148 | 502a5395 | pbrook | |
149 | f3902383 | blueswir1 | static void pci_unin_save(QEMUFile* f, void *opaque) |
150 | f3902383 | blueswir1 | { |
151 | f3902383 | blueswir1 | PCIDevice *d = opaque; |
152 | f3902383 | blueswir1 | |
153 | f3902383 | blueswir1 | pci_device_save(d, f); |
154 | f3902383 | blueswir1 | } |
155 | f3902383 | blueswir1 | |
156 | f3902383 | blueswir1 | static int pci_unin_load(QEMUFile* f, void *opaque, int version_id) |
157 | f3902383 | blueswir1 | { |
158 | f3902383 | blueswir1 | PCIDevice *d = opaque; |
159 | f3902383 | blueswir1 | |
160 | f3902383 | blueswir1 | if (version_id != 1) |
161 | f3902383 | blueswir1 | return -EINVAL;
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162 | f3902383 | blueswir1 | |
163 | f3902383 | blueswir1 | return pci_device_load(d, f);
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164 | f3902383 | blueswir1 | } |
165 | f3902383 | blueswir1 | |
166 | f3902383 | blueswir1 | static void pci_unin_reset(void *opaque) |
167 | f3902383 | blueswir1 | { |
168 | f3902383 | blueswir1 | } |
169 | f3902383 | blueswir1 | |
170 | 81a322d4 | Gerd Hoffmann | static int pci_unin_main_init_device(SysBusDevice *dev) |
171 | 502a5395 | pbrook | { |
172 | 502a5395 | pbrook | UNINState *s; |
173 | 502a5395 | pbrook | int pci_mem_config, pci_mem_data;
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174 | 502a5395 | pbrook | |
175 | 502a5395 | pbrook | /* Use values found on a real PowerMac */
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176 | 502a5395 | pbrook | /* Uninorth main bus */
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177 | 2e29bd04 | Blue Swirl | s = FROM_SYSBUS(UNINState, dev); |
178 | 502a5395 | pbrook | |
179 | 1eed09cb | Avi Kivity | pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read, |
180 | 502a5395 | pbrook | pci_unin_main_config_write, s); |
181 | 1eed09cb | Avi Kivity | pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
182 | 2e29bd04 | Blue Swirl | pci_unin_main_write, &s->host_state); |
183 | 2e29bd04 | Blue Swirl | |
184 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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185 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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186 | 2e29bd04 | Blue Swirl | |
187 | 2e29bd04 | Blue Swirl | register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state); |
188 | 2e29bd04 | Blue Swirl | qemu_register_reset(pci_unin_reset, &s->host_state); |
189 | 2e29bd04 | Blue Swirl | pci_unin_reset(&s->host_state); |
190 | 81a322d4 | Gerd Hoffmann | return 0; |
191 | 2e29bd04 | Blue Swirl | } |
192 | 2e29bd04 | Blue Swirl | |
193 | 81a322d4 | Gerd Hoffmann | static int pci_dec_21154_init_device(SysBusDevice *dev) |
194 | 2e29bd04 | Blue Swirl | { |
195 | 2e29bd04 | Blue Swirl | UNINState *s; |
196 | 2e29bd04 | Blue Swirl | int pci_mem_config, pci_mem_data;
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197 | 2e29bd04 | Blue Swirl | |
198 | 2e29bd04 | Blue Swirl | /* Uninorth bridge */
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199 | 2e29bd04 | Blue Swirl | s = FROM_SYSBUS(UNINState, dev); |
200 | 2e29bd04 | Blue Swirl | |
201 | 2e29bd04 | Blue Swirl | // XXX: s = &pci_bridge[2];
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202 | 2e29bd04 | Blue Swirl | pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
203 | 2e29bd04 | Blue Swirl | pci_unin_config_write, s); |
204 | 2e29bd04 | Blue Swirl | pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
205 | 2e29bd04 | Blue Swirl | pci_unin_main_write, &s->host_state); |
206 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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207 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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208 | 81a322d4 | Gerd Hoffmann | return 0; |
209 | 2e29bd04 | Blue Swirl | } |
210 | 2e29bd04 | Blue Swirl | |
211 | 81a322d4 | Gerd Hoffmann | static int pci_unin_agp_init_device(SysBusDevice *dev) |
212 | 2e29bd04 | Blue Swirl | { |
213 | 2e29bd04 | Blue Swirl | UNINState *s; |
214 | 2e29bd04 | Blue Swirl | int pci_mem_config, pci_mem_data;
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215 | 2e29bd04 | Blue Swirl | |
216 | 2e29bd04 | Blue Swirl | /* Uninorth AGP bus */
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217 | 2e29bd04 | Blue Swirl | s = FROM_SYSBUS(UNINState, dev); |
218 | 2e29bd04 | Blue Swirl | |
219 | 2e29bd04 | Blue Swirl | pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
220 | 2e29bd04 | Blue Swirl | pci_unin_config_write, s); |
221 | 2e29bd04 | Blue Swirl | pci_mem_data = cpu_register_io_memory(pci_unin_main_read, |
222 | 2e29bd04 | Blue Swirl | pci_unin_main_write, &s->host_state); |
223 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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224 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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225 | 81a322d4 | Gerd Hoffmann | return 0; |
226 | 2e29bd04 | Blue Swirl | } |
227 | 2e29bd04 | Blue Swirl | |
228 | 81a322d4 | Gerd Hoffmann | static int pci_unin_internal_init_device(SysBusDevice *dev) |
229 | 2e29bd04 | Blue Swirl | { |
230 | 2e29bd04 | Blue Swirl | UNINState *s; |
231 | 2e29bd04 | Blue Swirl | int pci_mem_config, pci_mem_data;
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232 | 2e29bd04 | Blue Swirl | |
233 | 2e29bd04 | Blue Swirl | /* Uninorth internal bus */
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234 | 2e29bd04 | Blue Swirl | s = FROM_SYSBUS(UNINState, dev); |
235 | 2e29bd04 | Blue Swirl | |
236 | 2e29bd04 | Blue Swirl | pci_mem_config = cpu_register_io_memory(pci_unin_config_read, |
237 | 2e29bd04 | Blue Swirl | pci_unin_config_write, s); |
238 | 2e29bd04 | Blue Swirl | pci_mem_data = cpu_register_io_memory(pci_unin_read, |
239 | 2e29bd04 | Blue Swirl | pci_unin_write, s); |
240 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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241 | 2e29bd04 | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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242 | 81a322d4 | Gerd Hoffmann | return 0; |
243 | 2e29bd04 | Blue Swirl | } |
244 | 2e29bd04 | Blue Swirl | |
245 | 2e29bd04 | Blue Swirl | PCIBus *pci_pmac_init(qemu_irq *pic) |
246 | 2e29bd04 | Blue Swirl | { |
247 | 2e29bd04 | Blue Swirl | DeviceState *dev; |
248 | 2e29bd04 | Blue Swirl | SysBusDevice *s; |
249 | 2e29bd04 | Blue Swirl | UNINState *d; |
250 | 2e29bd04 | Blue Swirl | |
251 | 2e29bd04 | Blue Swirl | /* Use values found on a real PowerMac */
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252 | 2e29bd04 | Blue Swirl | /* Uninorth main bus */
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253 | 2e29bd04 | Blue Swirl | dev = qdev_create(NULL, "Uni-north main"); |
254 | 2e29bd04 | Blue Swirl | qdev_init(dev); |
255 | 2e29bd04 | Blue Swirl | s = sysbus_from_qdev(dev); |
256 | 2e29bd04 | Blue Swirl | d = FROM_SYSBUS(UNINState, s); |
257 | 2e29bd04 | Blue Swirl | d->host_state.bus = pci_register_bus(NULL, "pci", |
258 | 2e29bd04 | Blue Swirl | pci_unin_set_irq, pci_unin_map_irq, |
259 | 2e29bd04 | Blue Swirl | pic, 11 << 3, 4); |
260 | 2e29bd04 | Blue Swirl | |
261 | 2e29bd04 | Blue Swirl | pci_create_simple(d->host_state.bus, 11 << 3, "Uni-north main"); |
262 | 2e29bd04 | Blue Swirl | |
263 | 2e29bd04 | Blue Swirl | sysbus_mmio_map(s, 0, 0xf2800000); |
264 | 2e29bd04 | Blue Swirl | sysbus_mmio_map(s, 1, 0xf2c00000); |
265 | 2e29bd04 | Blue Swirl | |
266 | 2e29bd04 | Blue Swirl | /* DEC 21154 bridge */
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267 | 2e29bd04 | Blue Swirl | #if 0
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268 | 2e29bd04 | Blue Swirl | /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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269 | 2e29bd04 | Blue Swirl | pci_create_simple(d->host_state.bus, 12 << 3, "DEC 21154");
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270 | 2e29bd04 | Blue Swirl | #endif
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271 | 2e29bd04 | Blue Swirl | |
272 | 2e29bd04 | Blue Swirl | /* Uninorth AGP bus */
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273 | 2e29bd04 | Blue Swirl | pci_create_simple(d->host_state.bus, 13 << 3, "Uni-north AGP"); |
274 | 2e29bd04 | Blue Swirl | |
275 | 2e29bd04 | Blue Swirl | /* Uninorth internal bus */
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276 | 2e29bd04 | Blue Swirl | #if 0
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277 | 2e29bd04 | Blue Swirl | /* XXX: not needed for now */
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278 | 2e29bd04 | Blue Swirl | pci_create_simple(d->host_state.bus, 14 << 3, "Uni-north internal");
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279 | 2e29bd04 | Blue Swirl | #endif
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280 | 2e29bd04 | Blue Swirl | |
281 | 2e29bd04 | Blue Swirl | return d->host_state.bus;
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282 | 2e29bd04 | Blue Swirl | } |
283 | 2e29bd04 | Blue Swirl | |
284 | 81a322d4 | Gerd Hoffmann | static int unin_main_pci_host_init(PCIDevice *d) |
285 | 2e29bd04 | Blue Swirl | { |
286 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
287 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI); |
288 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
289 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
290 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
291 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
292 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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293 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer |
294 | 81a322d4 | Gerd Hoffmann | return 0; |
295 | 2e29bd04 | Blue Swirl | } |
296 | 502a5395 | pbrook | |
297 | 81a322d4 | Gerd Hoffmann | static int dec_21154_pci_host_init(PCIDevice *d) |
298 | 2e29bd04 | Blue Swirl | { |
299 | 502a5395 | pbrook | /* pci-to-pci bridge */
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300 | 4ebcf884 | blueswir1 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); |
301 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); |
302 | 502a5395 | pbrook | d->config[0x08] = 0x05; // revision |
303 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
304 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
305 | 502a5395 | pbrook | d->config[0x0D] = 0x20; // latency_timer |
306 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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307 | 502a5395 | pbrook | |
308 | 502a5395 | pbrook | d->config[0x18] = 0x01; // primary_bus |
309 | 502a5395 | pbrook | d->config[0x19] = 0x02; // secondary_bus |
310 | 502a5395 | pbrook | d->config[0x1A] = 0x02; // subordinate_bus |
311 | 502a5395 | pbrook | d->config[0x1B] = 0x20; // secondary_latency_timer |
312 | 502a5395 | pbrook | d->config[0x1C] = 0x11; // io_base |
313 | 502a5395 | pbrook | d->config[0x1D] = 0x01; // io_limit |
314 | 502a5395 | pbrook | d->config[0x20] = 0x00; // memory_base |
315 | 502a5395 | pbrook | d->config[0x21] = 0x80; |
316 | 502a5395 | pbrook | d->config[0x22] = 0x00; // memory_limit |
317 | 502a5395 | pbrook | d->config[0x23] = 0x80; |
318 | 502a5395 | pbrook | d->config[0x24] = 0x01; // prefetchable_memory_base |
319 | 502a5395 | pbrook | d->config[0x25] = 0x80; |
320 | 502a5395 | pbrook | d->config[0x26] = 0xF1; // prefectchable_memory_limit |
321 | 502a5395 | pbrook | d->config[0x27] = 0x7F; |
322 | 502a5395 | pbrook | // d->config[0x34] = 0xdc // capabilities_pointer
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323 | 81a322d4 | Gerd Hoffmann | return 0; |
324 | 2e29bd04 | Blue Swirl | } |
325 | 502a5395 | pbrook | |
326 | 81a322d4 | Gerd Hoffmann | static int unin_agp_pci_host_init(PCIDevice *d) |
327 | 2e29bd04 | Blue Swirl | { |
328 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
329 | deb54399 | aliguori | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); |
330 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
331 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
332 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
333 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
334 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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335 | 502a5395 | pbrook | // d->config[0x34] = 0x80; // capabilities_pointer
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336 | 81a322d4 | Gerd Hoffmann | return 0; |
337 | 2e29bd04 | Blue Swirl | } |
338 | 502a5395 | pbrook | |
339 | 81a322d4 | Gerd Hoffmann | static int unin_internal_pci_host_init(PCIDevice *d) |
340 | 2e29bd04 | Blue Swirl | { |
341 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
342 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI); |
343 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
344 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
345 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
346 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
347 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
348 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer |
349 | 81a322d4 | Gerd Hoffmann | return 0; |
350 | 2e29bd04 | Blue Swirl | } |
351 | 2e29bd04 | Blue Swirl | |
352 | 2e29bd04 | Blue Swirl | static PCIDeviceInfo unin_main_pci_host_info = {
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353 | 2e29bd04 | Blue Swirl | .qdev.name = "Uni-north main",
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354 | 2e29bd04 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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355 | 2e29bd04 | Blue Swirl | .init = unin_main_pci_host_init, |
356 | 2e29bd04 | Blue Swirl | }; |
357 | 2e29bd04 | Blue Swirl | |
358 | 2e29bd04 | Blue Swirl | static PCIDeviceInfo dec_21154_pci_host_info = {
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359 | 2e29bd04 | Blue Swirl | .qdev.name = "DEC 21154",
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360 | 2e29bd04 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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361 | 2e29bd04 | Blue Swirl | .init = dec_21154_pci_host_init, |
362 | 2e29bd04 | Blue Swirl | }; |
363 | f3902383 | blueswir1 | |
364 | 2e29bd04 | Blue Swirl | static PCIDeviceInfo unin_agp_pci_host_info = {
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365 | 2e29bd04 | Blue Swirl | .qdev.name = "Uni-north AGP",
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366 | 2e29bd04 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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367 | 2e29bd04 | Blue Swirl | .init = unin_agp_pci_host_init, |
368 | 2e29bd04 | Blue Swirl | }; |
369 | 2e29bd04 | Blue Swirl | |
370 | 2e29bd04 | Blue Swirl | static PCIDeviceInfo unin_internal_pci_host_info = {
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371 | 2e29bd04 | Blue Swirl | .qdev.name = "Uni-north internal",
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372 | 2e29bd04 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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373 | 2e29bd04 | Blue Swirl | .init = unin_internal_pci_host_init, |
374 | 2e29bd04 | Blue Swirl | }; |
375 | 2e29bd04 | Blue Swirl | |
376 | 2e29bd04 | Blue Swirl | static void unin_register_devices(void) |
377 | 2e29bd04 | Blue Swirl | { |
378 | 2e29bd04 | Blue Swirl | sysbus_register_dev("Uni-north main", sizeof(UNINState), |
379 | 2e29bd04 | Blue Swirl | pci_unin_main_init_device); |
380 | 2e29bd04 | Blue Swirl | pci_qdev_register(&unin_main_pci_host_info); |
381 | 2e29bd04 | Blue Swirl | sysbus_register_dev("DEC 21154", sizeof(UNINState), |
382 | 2e29bd04 | Blue Swirl | pci_dec_21154_init_device); |
383 | 2e29bd04 | Blue Swirl | pci_qdev_register(&dec_21154_pci_host_info); |
384 | 2e29bd04 | Blue Swirl | sysbus_register_dev("Uni-north AGP", sizeof(UNINState), |
385 | 2e29bd04 | Blue Swirl | pci_unin_agp_init_device); |
386 | 2e29bd04 | Blue Swirl | pci_qdev_register(&unin_agp_pci_host_info); |
387 | 2e29bd04 | Blue Swirl | sysbus_register_dev("Uni-north internal", sizeof(UNINState), |
388 | 2e29bd04 | Blue Swirl | pci_unin_internal_init_device); |
389 | 2e29bd04 | Blue Swirl | pci_qdev_register(&unin_internal_pci_host_info); |
390 | 502a5395 | pbrook | } |
391 | 2e29bd04 | Blue Swirl | |
392 | 2e29bd04 | Blue Swirl | device_init(unin_register_devices) |