root / target-arm / helper.c @ 0b03bdfc
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "gdbstub.h" |
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#include "helper.h" |
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#include "qemu-common.h" |
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#include "host-utils.h" |
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#if !defined(CONFIG_USER_ONLY)
|
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#include "hw/loader.h" |
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#endif
|
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#include "sysemu.h" |
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|
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static uint32_t cortexa15_cp15_c0_c1[8] = { |
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0x00001131, 0x00011011, 0x02010555, 0x00000000, |
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0x10201105, 0x20000000, 0x01240000, 0x02102211 |
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}; |
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|
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static uint32_t cortexa15_cp15_c0_c2[8] = { |
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0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0 |
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}; |
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|
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static uint32_t cortexa9_cp15_c0_c1[8] = |
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{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 }; |
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|
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static uint32_t cortexa9_cp15_c0_c2[8] = |
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{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 }; |
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|
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static uint32_t cortexa8_cp15_c0_c1[8] = |
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{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; |
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|
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static uint32_t cortexa8_cp15_c0_c2[8] = |
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{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; |
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|
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static uint32_t mpcore_cp15_c0_c1[8] = |
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{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; |
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|
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static uint32_t mpcore_cp15_c0_c2[8] = |
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{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; |
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|
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static uint32_t arm1136_cp15_c0_c1[8] = |
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{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; |
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|
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static uint32_t arm1136_cp15_c0_c2[8] = |
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{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; |
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|
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static uint32_t arm1176_cp15_c0_c1[8] = |
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{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 }; |
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|
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static uint32_t arm1176_cp15_c0_c2[8] = |
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{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; |
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|
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static uint32_t cpu_arm_find_by_name(const char *name); |
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|
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1u << feature;
|
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} |
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|
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static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
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{ |
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env->cp15.c0_cpuid = id; |
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switch (id) {
|
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case ARM_CPUID_ARM926:
|
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set_feature(env, ARM_FEATURE_V5); |
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set_feature(env, ARM_FEATURE_VFP); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00090078;
|
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break;
|
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case ARM_CPUID_ARM946:
|
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set_feature(env, ARM_FEATURE_V5); |
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set_feature(env, ARM_FEATURE_MPU); |
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env->cp15.c0_cachetype = 0x0f004006;
|
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env->cp15.c1_sys = 0x00000078;
|
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break;
|
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case ARM_CPUID_ARM1026:
|
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set_feature(env, ARM_FEATURE_V5); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00090078;
|
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break;
|
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case ARM_CPUID_ARM1136:
|
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/* This is the 1136 r1, which is a v6K core */
|
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set_feature(env, ARM_FEATURE_V6K); |
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/* Fall through */
|
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case ARM_CPUID_ARM1136_R2:
|
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
|
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* older core than plain "arm1136". In particular this does not
|
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* have the v6K features.
|
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*/
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_VFP); |
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/* These ID register values are correct for 1136 but may be wrong
|
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* for 1136_r2 (in particular r0p2 does not actually implement most
|
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* of the ID registers).
|
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*/
|
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
|
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memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00050078;
|
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break;
|
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case ARM_CPUID_ARM1176:
|
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_VAPA); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
|
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memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00050078;
|
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break;
|
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case ARM_CPUID_ARM11MPCORE:
|
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_VAPA); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
|
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memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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break;
|
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case ARM_CPUID_CORTEXA8:
|
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set_feature(env, ARM_FEATURE_V7); |
134 |
set_feature(env, ARM_FEATURE_VFP3); |
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set_feature(env, ARM_FEATURE_NEON); |
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set_feature(env, ARM_FEATURE_THUMB2EE); |
137 |
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
|
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memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x82048004;
|
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env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; |
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env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ |
145 |
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ |
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env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ |
147 |
env->cp15.c1_sys = 0x00c50078;
|
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break;
|
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case ARM_CPUID_CORTEXA9:
|
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_VFP3); |
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set_feature(env, ARM_FEATURE_VFP_FP16); |
153 |
set_feature(env, ARM_FEATURE_NEON); |
154 |
set_feature(env, ARM_FEATURE_THUMB2EE); |
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/* Note that A9 supports the MP extensions even for
|
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* A9UP and single-core A9MP (which are both different
|
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* and valid configurations; we don't model A9UP).
|
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*/
|
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set_feature(env, ARM_FEATURE_V7MP); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */ |
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
|
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memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); |
164 |
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x80038003;
|
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env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; |
167 |
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ |
168 |
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ |
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env->cp15.c1_sys = 0x00c50078;
|
170 |
break;
|
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case ARM_CPUID_CORTEXA15:
|
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set_feature(env, ARM_FEATURE_V7); |
173 |
set_feature(env, ARM_FEATURE_VFP4); |
174 |
set_feature(env, ARM_FEATURE_VFP_FP16); |
175 |
set_feature(env, ARM_FEATURE_NEON); |
176 |
set_feature(env, ARM_FEATURE_THUMB2EE); |
177 |
set_feature(env, ARM_FEATURE_ARM_DIV); |
178 |
set_feature(env, ARM_FEATURE_V7MP); |
179 |
set_feature(env, ARM_FEATURE_GENERIC_TIMER); |
180 |
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
|
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memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); |
184 |
memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); |
185 |
env->cp15.c0_cachetype = 0x8444c004;
|
186 |
env->cp15.c0_clid = 0x0a200023;
|
187 |
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ |
188 |
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ |
189 |
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
190 |
env->cp15.c1_sys = 0x00c50078;
|
191 |
break;
|
192 |
case ARM_CPUID_CORTEXM3:
|
193 |
set_feature(env, ARM_FEATURE_V7); |
194 |
set_feature(env, ARM_FEATURE_M); |
195 |
break;
|
196 |
case ARM_CPUID_ANY: /* For userspace emulation. */ |
197 |
set_feature(env, ARM_FEATURE_V7); |
198 |
set_feature(env, ARM_FEATURE_VFP4); |
199 |
set_feature(env, ARM_FEATURE_VFP_FP16); |
200 |
set_feature(env, ARM_FEATURE_NEON); |
201 |
set_feature(env, ARM_FEATURE_THUMB2EE); |
202 |
set_feature(env, ARM_FEATURE_ARM_DIV); |
203 |
set_feature(env, ARM_FEATURE_V7MP); |
204 |
break;
|
205 |
case ARM_CPUID_TI915T:
|
206 |
case ARM_CPUID_TI925T:
|
207 |
set_feature(env, ARM_FEATURE_V4T); |
208 |
set_feature(env, ARM_FEATURE_OMAPCP); |
209 |
env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
|
210 |
env->cp15.c0_cachetype = 0x5109149;
|
211 |
env->cp15.c1_sys = 0x00000070;
|
212 |
env->cp15.c15_i_max = 0x000;
|
213 |
env->cp15.c15_i_min = 0xff0;
|
214 |
break;
|
215 |
case ARM_CPUID_PXA250:
|
216 |
case ARM_CPUID_PXA255:
|
217 |
case ARM_CPUID_PXA260:
|
218 |
case ARM_CPUID_PXA261:
|
219 |
case ARM_CPUID_PXA262:
|
220 |
set_feature(env, ARM_FEATURE_V5); |
221 |
set_feature(env, ARM_FEATURE_XSCALE); |
222 |
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
223 |
env->cp15.c0_cachetype = 0xd172172;
|
224 |
env->cp15.c1_sys = 0x00000078;
|
225 |
break;
|
226 |
case ARM_CPUID_PXA270_A0:
|
227 |
case ARM_CPUID_PXA270_A1:
|
228 |
case ARM_CPUID_PXA270_B0:
|
229 |
case ARM_CPUID_PXA270_B1:
|
230 |
case ARM_CPUID_PXA270_C0:
|
231 |
case ARM_CPUID_PXA270_C5:
|
232 |
set_feature(env, ARM_FEATURE_V5); |
233 |
set_feature(env, ARM_FEATURE_XSCALE); |
234 |
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
235 |
set_feature(env, ARM_FEATURE_IWMMXT); |
236 |
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
237 |
env->cp15.c0_cachetype = 0xd172172;
|
238 |
env->cp15.c1_sys = 0x00000078;
|
239 |
break;
|
240 |
case ARM_CPUID_SA1100:
|
241 |
case ARM_CPUID_SA1110:
|
242 |
set_feature(env, ARM_FEATURE_STRONGARM); |
243 |
env->cp15.c1_sys = 0x00000070;
|
244 |
break;
|
245 |
default:
|
246 |
cpu_abort(env, "Bad CPU ID: %x\n", id);
|
247 |
break;
|
248 |
} |
249 |
|
250 |
/* Some features automatically imply others: */
|
251 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
252 |
set_feature(env, ARM_FEATURE_VAPA); |
253 |
set_feature(env, ARM_FEATURE_THUMB2); |
254 |
if (!arm_feature(env, ARM_FEATURE_M)) {
|
255 |
set_feature(env, ARM_FEATURE_V6K); |
256 |
} else {
|
257 |
set_feature(env, ARM_FEATURE_V6); |
258 |
} |
259 |
} |
260 |
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
261 |
set_feature(env, ARM_FEATURE_V6); |
262 |
} |
263 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
264 |
set_feature(env, ARM_FEATURE_V5); |
265 |
if (!arm_feature(env, ARM_FEATURE_M)) {
|
266 |
set_feature(env, ARM_FEATURE_AUXCR); |
267 |
} |
268 |
} |
269 |
if (arm_feature(env, ARM_FEATURE_V5)) {
|
270 |
set_feature(env, ARM_FEATURE_V4T); |
271 |
} |
272 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
273 |
set_feature(env, ARM_FEATURE_THUMB_DIV); |
274 |
} |
275 |
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
276 |
set_feature(env, ARM_FEATURE_THUMB_DIV); |
277 |
} |
278 |
if (arm_feature(env, ARM_FEATURE_VFP4)) {
|
279 |
set_feature(env, ARM_FEATURE_VFP3); |
280 |
} |
281 |
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
282 |
set_feature(env, ARM_FEATURE_VFP); |
283 |
} |
284 |
} |
285 |
|
286 |
void cpu_reset(CPUARMState *env)
|
287 |
{ |
288 |
uint32_t id; |
289 |
uint32_t tmp = 0;
|
290 |
|
291 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
292 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
293 |
log_cpu_state(env, 0);
|
294 |
} |
295 |
|
296 |
id = env->cp15.c0_cpuid; |
297 |
tmp = env->cp15.c15_config_base_address; |
298 |
memset(env, 0, offsetof(CPUARMState, breakpoints));
|
299 |
if (id)
|
300 |
cpu_reset_model_id(env, id); |
301 |
env->cp15.c15_config_base_address = tmp; |
302 |
#if defined (CONFIG_USER_ONLY)
|
303 |
env->uncached_cpsr = ARM_CPU_MODE_USR; |
304 |
/* For user mode we must enable access to coprocessors */
|
305 |
env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
306 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
307 |
env->cp15.c15_cpar = 3;
|
308 |
} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
309 |
env->cp15.c15_cpar = 1;
|
310 |
} |
311 |
#else
|
312 |
/* SVC mode with interrupts disabled. */
|
313 |
env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
314 |
/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
|
315 |
clear at reset. Initial SP and PC are loaded from ROM. */
|
316 |
if (IS_M(env)) {
|
317 |
uint32_t pc; |
318 |
uint8_t *rom; |
319 |
env->uncached_cpsr &= ~CPSR_I; |
320 |
rom = rom_ptr(0);
|
321 |
if (rom) {
|
322 |
/* We should really use ldl_phys here, in case the guest
|
323 |
modified flash and reset itself. However images
|
324 |
loaded via -kernel have not been copied yet, so load the
|
325 |
values directly from there. */
|
326 |
env->regs[13] = ldl_p(rom);
|
327 |
pc = ldl_p(rom + 4);
|
328 |
env->thumb = pc & 1;
|
329 |
env->regs[15] = pc & ~1; |
330 |
} |
331 |
} |
332 |
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
|
333 |
env->cp15.c2_base_mask = 0xffffc000u;
|
334 |
/* v7 performance monitor control register: same implementor
|
335 |
* field as main ID register, and we implement no event counters.
|
336 |
*/
|
337 |
env->cp15.c9_pmcr = (id & 0xff000000);
|
338 |
#endif
|
339 |
set_flush_to_zero(1, &env->vfp.standard_fp_status);
|
340 |
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
|
341 |
set_default_nan_mode(1, &env->vfp.standard_fp_status);
|
342 |
set_float_detect_tininess(float_tininess_before_rounding, |
343 |
&env->vfp.fp_status); |
344 |
set_float_detect_tininess(float_tininess_before_rounding, |
345 |
&env->vfp.standard_fp_status); |
346 |
tlb_flush(env, 1);
|
347 |
} |
348 |
|
349 |
static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg) |
350 |
{ |
351 |
int nregs;
|
352 |
|
353 |
/* VFP data registers are always little-endian. */
|
354 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
355 |
if (reg < nregs) {
|
356 |
stfq_le_p(buf, env->vfp.regs[reg]); |
357 |
return 8; |
358 |
} |
359 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
360 |
/* Aliases for Q regs. */
|
361 |
nregs += 16;
|
362 |
if (reg < nregs) {
|
363 |
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); |
364 |
stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); |
365 |
return 16; |
366 |
} |
367 |
} |
368 |
switch (reg - nregs) {
|
369 |
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; |
370 |
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; |
371 |
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
372 |
} |
373 |
return 0; |
374 |
} |
375 |
|
376 |
static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) |
377 |
{ |
378 |
int nregs;
|
379 |
|
380 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
381 |
if (reg < nregs) {
|
382 |
env->vfp.regs[reg] = ldfq_le_p(buf); |
383 |
return 8; |
384 |
} |
385 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
386 |
nregs += 16;
|
387 |
if (reg < nregs) {
|
388 |
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); |
389 |
env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); |
390 |
return 16; |
391 |
} |
392 |
} |
393 |
switch (reg - nregs) {
|
394 |
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
395 |
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; |
396 |
case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
397 |
} |
398 |
return 0; |
399 |
} |
400 |
|
401 |
CPUARMState *cpu_arm_init(const char *cpu_model) |
402 |
{ |
403 |
CPUARMState *env; |
404 |
uint32_t id; |
405 |
static int inited = 0; |
406 |
|
407 |
id = cpu_arm_find_by_name(cpu_model); |
408 |
if (id == 0) |
409 |
return NULL; |
410 |
env = g_malloc0(sizeof(CPUARMState));
|
411 |
cpu_exec_init(env); |
412 |
if (tcg_enabled() && !inited) {
|
413 |
inited = 1;
|
414 |
arm_translate_init(); |
415 |
} |
416 |
|
417 |
env->cpu_model_str = cpu_model; |
418 |
env->cp15.c0_cpuid = id; |
419 |
cpu_reset(env); |
420 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
421 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
422 |
51, "arm-neon.xml", 0); |
423 |
} else if (arm_feature(env, ARM_FEATURE_VFP3)) { |
424 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
425 |
35, "arm-vfp3.xml", 0); |
426 |
} else if (arm_feature(env, ARM_FEATURE_VFP)) { |
427 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
428 |
19, "arm-vfp.xml", 0); |
429 |
} |
430 |
qemu_init_vcpu(env); |
431 |
return env;
|
432 |
} |
433 |
|
434 |
struct arm_cpu_t {
|
435 |
uint32_t id; |
436 |
const char *name; |
437 |
}; |
438 |
|
439 |
static const struct arm_cpu_t arm_cpu_names[] = { |
440 |
{ ARM_CPUID_ARM926, "arm926"},
|
441 |
{ ARM_CPUID_ARM946, "arm946"},
|
442 |
{ ARM_CPUID_ARM1026, "arm1026"},
|
443 |
{ ARM_CPUID_ARM1136, "arm1136"},
|
444 |
{ ARM_CPUID_ARM1136_R2, "arm1136-r2"},
|
445 |
{ ARM_CPUID_ARM1176, "arm1176"},
|
446 |
{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
|
447 |
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
|
448 |
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
|
449 |
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
|
450 |
{ ARM_CPUID_CORTEXA15, "cortex-a15" },
|
451 |
{ ARM_CPUID_TI925T, "ti925t" },
|
452 |
{ ARM_CPUID_PXA250, "pxa250" },
|
453 |
{ ARM_CPUID_SA1100, "sa1100" },
|
454 |
{ ARM_CPUID_SA1110, "sa1110" },
|
455 |
{ ARM_CPUID_PXA255, "pxa255" },
|
456 |
{ ARM_CPUID_PXA260, "pxa260" },
|
457 |
{ ARM_CPUID_PXA261, "pxa261" },
|
458 |
{ ARM_CPUID_PXA262, "pxa262" },
|
459 |
{ ARM_CPUID_PXA270, "pxa270" },
|
460 |
{ ARM_CPUID_PXA270_A0, "pxa270-a0" },
|
461 |
{ ARM_CPUID_PXA270_A1, "pxa270-a1" },
|
462 |
{ ARM_CPUID_PXA270_B0, "pxa270-b0" },
|
463 |
{ ARM_CPUID_PXA270_B1, "pxa270-b1" },
|
464 |
{ ARM_CPUID_PXA270_C0, "pxa270-c0" },
|
465 |
{ ARM_CPUID_PXA270_C5, "pxa270-c5" },
|
466 |
{ ARM_CPUID_ANY, "any"},
|
467 |
{ 0, NULL} |
468 |
}; |
469 |
|
470 |
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
471 |
{ |
472 |
int i;
|
473 |
|
474 |
(*cpu_fprintf)(f, "Available CPUs:\n");
|
475 |
for (i = 0; arm_cpu_names[i].name; i++) { |
476 |
(*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
|
477 |
} |
478 |
} |
479 |
|
480 |
/* return 0 if not found */
|
481 |
static uint32_t cpu_arm_find_by_name(const char *name) |
482 |
{ |
483 |
int i;
|
484 |
uint32_t id; |
485 |
|
486 |
id = 0;
|
487 |
for (i = 0; arm_cpu_names[i].name; i++) { |
488 |
if (strcmp(name, arm_cpu_names[i].name) == 0) { |
489 |
id = arm_cpu_names[i].id; |
490 |
break;
|
491 |
} |
492 |
} |
493 |
return id;
|
494 |
} |
495 |
|
496 |
void cpu_arm_close(CPUARMState *env)
|
497 |
{ |
498 |
g_free(env); |
499 |
} |
500 |
|
501 |
static int bad_mode_switch(CPUState *env, int mode) |
502 |
{ |
503 |
/* Return true if it is not valid for us to switch to
|
504 |
* this CPU mode (ie all the UNPREDICTABLE cases in
|
505 |
* the ARM ARM CPSRWriteByInstr pseudocode).
|
506 |
*/
|
507 |
switch (mode) {
|
508 |
case ARM_CPU_MODE_USR:
|
509 |
case ARM_CPU_MODE_SYS:
|
510 |
case ARM_CPU_MODE_SVC:
|
511 |
case ARM_CPU_MODE_ABT:
|
512 |
case ARM_CPU_MODE_UND:
|
513 |
case ARM_CPU_MODE_IRQ:
|
514 |
case ARM_CPU_MODE_FIQ:
|
515 |
return 0; |
516 |
default:
|
517 |
return 1; |
518 |
} |
519 |
} |
520 |
|
521 |
uint32_t cpsr_read(CPUARMState *env) |
522 |
{ |
523 |
int ZF;
|
524 |
ZF = (env->ZF == 0);
|
525 |
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | |
526 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
527 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
528 |
| ((env->condexec_bits & 0xfc) << 8) |
529 |
| (env->GE << 16);
|
530 |
} |
531 |
|
532 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
533 |
{ |
534 |
if (mask & CPSR_NZCV) {
|
535 |
env->ZF = (~val) & CPSR_Z; |
536 |
env->NF = val; |
537 |
env->CF = (val >> 29) & 1; |
538 |
env->VF = (val << 3) & 0x80000000; |
539 |
} |
540 |
if (mask & CPSR_Q)
|
541 |
env->QF = ((val & CPSR_Q) != 0);
|
542 |
if (mask & CPSR_T)
|
543 |
env->thumb = ((val & CPSR_T) != 0);
|
544 |
if (mask & CPSR_IT_0_1) {
|
545 |
env->condexec_bits &= ~3;
|
546 |
env->condexec_bits |= (val >> 25) & 3; |
547 |
} |
548 |
if (mask & CPSR_IT_2_7) {
|
549 |
env->condexec_bits &= 3;
|
550 |
env->condexec_bits |= (val >> 8) & 0xfc; |
551 |
} |
552 |
if (mask & CPSR_GE) {
|
553 |
env->GE = (val >> 16) & 0xf; |
554 |
} |
555 |
|
556 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
557 |
if (bad_mode_switch(env, val & CPSR_M)) {
|
558 |
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
|
559 |
* We choose to ignore the attempt and leave the CPSR M field
|
560 |
* untouched.
|
561 |
*/
|
562 |
mask &= ~CPSR_M; |
563 |
} else {
|
564 |
switch_mode(env, val & CPSR_M); |
565 |
} |
566 |
} |
567 |
mask &= ~CACHED_CPSR_BITS; |
568 |
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
569 |
} |
570 |
|
571 |
/* Sign/zero extend */
|
572 |
uint32_t HELPER(sxtb16)(uint32_t x) |
573 |
{ |
574 |
uint32_t res; |
575 |
res = (uint16_t)(int8_t)x; |
576 |
res |= (uint32_t)(int8_t)(x >> 16) << 16; |
577 |
return res;
|
578 |
} |
579 |
|
580 |
uint32_t HELPER(uxtb16)(uint32_t x) |
581 |
{ |
582 |
uint32_t res; |
583 |
res = (uint16_t)(uint8_t)x; |
584 |
res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
585 |
return res;
|
586 |
} |
587 |
|
588 |
uint32_t HELPER(clz)(uint32_t x) |
589 |
{ |
590 |
return clz32(x);
|
591 |
} |
592 |
|
593 |
int32_t HELPER(sdiv)(int32_t num, int32_t den) |
594 |
{ |
595 |
if (den == 0) |
596 |
return 0; |
597 |
if (num == INT_MIN && den == -1) |
598 |
return INT_MIN;
|
599 |
return num / den;
|
600 |
} |
601 |
|
602 |
uint32_t HELPER(udiv)(uint32_t num, uint32_t den) |
603 |
{ |
604 |
if (den == 0) |
605 |
return 0; |
606 |
return num / den;
|
607 |
} |
608 |
|
609 |
uint32_t HELPER(rbit)(uint32_t x) |
610 |
{ |
611 |
x = ((x & 0xff000000) >> 24) |
612 |
| ((x & 0x00ff0000) >> 8) |
613 |
| ((x & 0x0000ff00) << 8) |
614 |
| ((x & 0x000000ff) << 24); |
615 |
x = ((x & 0xf0f0f0f0) >> 4) |
616 |
| ((x & 0x0f0f0f0f) << 4); |
617 |
x = ((x & 0x88888888) >> 3) |
618 |
| ((x & 0x44444444) >> 1) |
619 |
| ((x & 0x22222222) << 1) |
620 |
| ((x & 0x11111111) << 3); |
621 |
return x;
|
622 |
} |
623 |
|
624 |
uint32_t HELPER(abs)(uint32_t x) |
625 |
{ |
626 |
return ((int32_t)x < 0) ? -x : x; |
627 |
} |
628 |
|
629 |
#if defined(CONFIG_USER_ONLY)
|
630 |
|
631 |
void do_interrupt (CPUState *env)
|
632 |
{ |
633 |
env->exception_index = -1;
|
634 |
} |
635 |
|
636 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
637 |
int mmu_idx)
|
638 |
{ |
639 |
if (rw == 2) { |
640 |
env->exception_index = EXCP_PREFETCH_ABORT; |
641 |
env->cp15.c6_insn = address; |
642 |
} else {
|
643 |
env->exception_index = EXCP_DATA_ABORT; |
644 |
env->cp15.c6_data = address; |
645 |
} |
646 |
return 1; |
647 |
} |
648 |
|
649 |
/* These should probably raise undefined insn exceptions. */
|
650 |
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
651 |
{ |
652 |
int op1 = (insn >> 8) & 0xf; |
653 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
654 |
return;
|
655 |
} |
656 |
|
657 |
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
658 |
{ |
659 |
int op1 = (insn >> 8) & 0xf; |
660 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
661 |
return 0; |
662 |
} |
663 |
|
664 |
void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
665 |
{ |
666 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
667 |
} |
668 |
|
669 |
uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
670 |
{ |
671 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
672 |
} |
673 |
|
674 |
/* These should probably raise undefined insn exceptions. */
|
675 |
void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
676 |
{ |
677 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
678 |
} |
679 |
|
680 |
uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
681 |
{ |
682 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
683 |
return 0; |
684 |
} |
685 |
|
686 |
void switch_mode(CPUState *env, int mode) |
687 |
{ |
688 |
if (mode != ARM_CPU_MODE_USR)
|
689 |
cpu_abort(env, "Tried to switch out of user mode\n");
|
690 |
} |
691 |
|
692 |
void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
693 |
{ |
694 |
cpu_abort(env, "banked r13 write\n");
|
695 |
} |
696 |
|
697 |
uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
698 |
{ |
699 |
cpu_abort(env, "banked r13 read\n");
|
700 |
return 0; |
701 |
} |
702 |
|
703 |
#else
|
704 |
|
705 |
/* Map CPU modes onto saved register banks. */
|
706 |
static inline int bank_number(CPUState *env, int mode) |
707 |
{ |
708 |
switch (mode) {
|
709 |
case ARM_CPU_MODE_USR:
|
710 |
case ARM_CPU_MODE_SYS:
|
711 |
return 0; |
712 |
case ARM_CPU_MODE_SVC:
|
713 |
return 1; |
714 |
case ARM_CPU_MODE_ABT:
|
715 |
return 2; |
716 |
case ARM_CPU_MODE_UND:
|
717 |
return 3; |
718 |
case ARM_CPU_MODE_IRQ:
|
719 |
return 4; |
720 |
case ARM_CPU_MODE_FIQ:
|
721 |
return 5; |
722 |
} |
723 |
cpu_abort(env, "Bad mode %x\n", mode);
|
724 |
return -1; |
725 |
} |
726 |
|
727 |
void switch_mode(CPUState *env, int mode) |
728 |
{ |
729 |
int old_mode;
|
730 |
int i;
|
731 |
|
732 |
old_mode = env->uncached_cpsr & CPSR_M; |
733 |
if (mode == old_mode)
|
734 |
return;
|
735 |
|
736 |
if (old_mode == ARM_CPU_MODE_FIQ) {
|
737 |
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
738 |
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
739 |
} else if (mode == ARM_CPU_MODE_FIQ) { |
740 |
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
741 |
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
742 |
} |
743 |
|
744 |
i = bank_number(env, old_mode); |
745 |
env->banked_r13[i] = env->regs[13];
|
746 |
env->banked_r14[i] = env->regs[14];
|
747 |
env->banked_spsr[i] = env->spsr; |
748 |
|
749 |
i = bank_number(env, mode); |
750 |
env->regs[13] = env->banked_r13[i];
|
751 |
env->regs[14] = env->banked_r14[i];
|
752 |
env->spsr = env->banked_spsr[i]; |
753 |
} |
754 |
|
755 |
static void v7m_push(CPUARMState *env, uint32_t val) |
756 |
{ |
757 |
env->regs[13] -= 4; |
758 |
stl_phys(env->regs[13], val);
|
759 |
} |
760 |
|
761 |
static uint32_t v7m_pop(CPUARMState *env)
|
762 |
{ |
763 |
uint32_t val; |
764 |
val = ldl_phys(env->regs[13]);
|
765 |
env->regs[13] += 4; |
766 |
return val;
|
767 |
} |
768 |
|
769 |
/* Switch to V7M main or process stack pointer. */
|
770 |
static void switch_v7m_sp(CPUARMState *env, int process) |
771 |
{ |
772 |
uint32_t tmp; |
773 |
if (env->v7m.current_sp != process) {
|
774 |
tmp = env->v7m.other_sp; |
775 |
env->v7m.other_sp = env->regs[13];
|
776 |
env->regs[13] = tmp;
|
777 |
env->v7m.current_sp = process; |
778 |
} |
779 |
} |
780 |
|
781 |
static void do_v7m_exception_exit(CPUARMState *env) |
782 |
{ |
783 |
uint32_t type; |
784 |
uint32_t xpsr; |
785 |
|
786 |
type = env->regs[15];
|
787 |
if (env->v7m.exception != 0) |
788 |
armv7m_nvic_complete_irq(env->nvic, env->v7m.exception); |
789 |
|
790 |
/* Switch to the target stack. */
|
791 |
switch_v7m_sp(env, (type & 4) != 0); |
792 |
/* Pop registers. */
|
793 |
env->regs[0] = v7m_pop(env);
|
794 |
env->regs[1] = v7m_pop(env);
|
795 |
env->regs[2] = v7m_pop(env);
|
796 |
env->regs[3] = v7m_pop(env);
|
797 |
env->regs[12] = v7m_pop(env);
|
798 |
env->regs[14] = v7m_pop(env);
|
799 |
env->regs[15] = v7m_pop(env);
|
800 |
xpsr = v7m_pop(env); |
801 |
xpsr_write(env, xpsr, 0xfffffdff);
|
802 |
/* Undo stack alignment. */
|
803 |
if (xpsr & 0x200) |
804 |
env->regs[13] |= 4; |
805 |
/* ??? The exception return type specifies Thread/Handler mode. However
|
806 |
this is also implied by the xPSR value. Not sure what to do
|
807 |
if there is a mismatch. */
|
808 |
/* ??? Likewise for mismatches between the CONTROL register and the stack
|
809 |
pointer. */
|
810 |
} |
811 |
|
812 |
static void do_interrupt_v7m(CPUARMState *env) |
813 |
{ |
814 |
uint32_t xpsr = xpsr_read(env); |
815 |
uint32_t lr; |
816 |
uint32_t addr; |
817 |
|
818 |
lr = 0xfffffff1;
|
819 |
if (env->v7m.current_sp)
|
820 |
lr |= 4;
|
821 |
if (env->v7m.exception == 0) |
822 |
lr |= 8;
|
823 |
|
824 |
/* For exceptions we just mark as pending on the NVIC, and let that
|
825 |
handle it. */
|
826 |
/* TODO: Need to escalate if the current priority is higher than the
|
827 |
one we're raising. */
|
828 |
switch (env->exception_index) {
|
829 |
case EXCP_UDEF:
|
830 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
831 |
return;
|
832 |
case EXCP_SWI:
|
833 |
env->regs[15] += 2; |
834 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
835 |
return;
|
836 |
case EXCP_PREFETCH_ABORT:
|
837 |
case EXCP_DATA_ABORT:
|
838 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
839 |
return;
|
840 |
case EXCP_BKPT:
|
841 |
if (semihosting_enabled) {
|
842 |
int nr;
|
843 |
nr = lduw_code(env->regs[15]) & 0xff; |
844 |
if (nr == 0xab) { |
845 |
env->regs[15] += 2; |
846 |
env->regs[0] = do_arm_semihosting(env);
|
847 |
return;
|
848 |
} |
849 |
} |
850 |
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
851 |
return;
|
852 |
case EXCP_IRQ:
|
853 |
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); |
854 |
break;
|
855 |
case EXCP_EXCEPTION_EXIT:
|
856 |
do_v7m_exception_exit(env); |
857 |
return;
|
858 |
default:
|
859 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
860 |
return; /* Never happens. Keep compiler happy. */ |
861 |
} |
862 |
|
863 |
/* Align stack pointer. */
|
864 |
/* ??? Should only do this if Configuration Control Register
|
865 |
STACKALIGN bit is set. */
|
866 |
if (env->regs[13] & 4) { |
867 |
env->regs[13] -= 4; |
868 |
xpsr |= 0x200;
|
869 |
} |
870 |
/* Switch to the handler mode. */
|
871 |
v7m_push(env, xpsr); |
872 |
v7m_push(env, env->regs[15]);
|
873 |
v7m_push(env, env->regs[14]);
|
874 |
v7m_push(env, env->regs[12]);
|
875 |
v7m_push(env, env->regs[3]);
|
876 |
v7m_push(env, env->regs[2]);
|
877 |
v7m_push(env, env->regs[1]);
|
878 |
v7m_push(env, env->regs[0]);
|
879 |
switch_v7m_sp(env, 0);
|
880 |
env->uncached_cpsr &= ~CPSR_IT; |
881 |
env->regs[14] = lr;
|
882 |
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
|
883 |
env->regs[15] = addr & 0xfffffffe; |
884 |
env->thumb = addr & 1;
|
885 |
} |
886 |
|
887 |
/* Handle a CPU exception. */
|
888 |
void do_interrupt(CPUARMState *env)
|
889 |
{ |
890 |
uint32_t addr; |
891 |
uint32_t mask; |
892 |
int new_mode;
|
893 |
uint32_t offset; |
894 |
|
895 |
if (IS_M(env)) {
|
896 |
do_interrupt_v7m(env); |
897 |
return;
|
898 |
} |
899 |
/* TODO: Vectored interrupt controller. */
|
900 |
switch (env->exception_index) {
|
901 |
case EXCP_UDEF:
|
902 |
new_mode = ARM_CPU_MODE_UND; |
903 |
addr = 0x04;
|
904 |
mask = CPSR_I; |
905 |
if (env->thumb)
|
906 |
offset = 2;
|
907 |
else
|
908 |
offset = 4;
|
909 |
break;
|
910 |
case EXCP_SWI:
|
911 |
if (semihosting_enabled) {
|
912 |
/* Check for semihosting interrupt. */
|
913 |
if (env->thumb) {
|
914 |
mask = lduw_code(env->regs[15] - 2) & 0xff; |
915 |
} else {
|
916 |
mask = ldl_code(env->regs[15] - 4) & 0xffffff; |
917 |
} |
918 |
/* Only intercept calls from privileged modes, to provide some
|
919 |
semblance of security. */
|
920 |
if (((mask == 0x123456 && !env->thumb) |
921 |
|| (mask == 0xab && env->thumb))
|
922 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
923 |
env->regs[0] = do_arm_semihosting(env);
|
924 |
return;
|
925 |
} |
926 |
} |
927 |
new_mode = ARM_CPU_MODE_SVC; |
928 |
addr = 0x08;
|
929 |
mask = CPSR_I; |
930 |
/* The PC already points to the next instruction. */
|
931 |
offset = 0;
|
932 |
break;
|
933 |
case EXCP_BKPT:
|
934 |
/* See if this is a semihosting syscall. */
|
935 |
if (env->thumb && semihosting_enabled) {
|
936 |
mask = lduw_code(env->regs[15]) & 0xff; |
937 |
if (mask == 0xab |
938 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
939 |
env->regs[15] += 2; |
940 |
env->regs[0] = do_arm_semihosting(env);
|
941 |
return;
|
942 |
} |
943 |
} |
944 |
env->cp15.c5_insn = 2;
|
945 |
/* Fall through to prefetch abort. */
|
946 |
case EXCP_PREFETCH_ABORT:
|
947 |
new_mode = ARM_CPU_MODE_ABT; |
948 |
addr = 0x0c;
|
949 |
mask = CPSR_A | CPSR_I; |
950 |
offset = 4;
|
951 |
break;
|
952 |
case EXCP_DATA_ABORT:
|
953 |
new_mode = ARM_CPU_MODE_ABT; |
954 |
addr = 0x10;
|
955 |
mask = CPSR_A | CPSR_I; |
956 |
offset = 8;
|
957 |
break;
|
958 |
case EXCP_IRQ:
|
959 |
new_mode = ARM_CPU_MODE_IRQ; |
960 |
addr = 0x18;
|
961 |
/* Disable IRQ and imprecise data aborts. */
|
962 |
mask = CPSR_A | CPSR_I; |
963 |
offset = 4;
|
964 |
break;
|
965 |
case EXCP_FIQ:
|
966 |
new_mode = ARM_CPU_MODE_FIQ; |
967 |
addr = 0x1c;
|
968 |
/* Disable FIQ, IRQ and imprecise data aborts. */
|
969 |
mask = CPSR_A | CPSR_I | CPSR_F; |
970 |
offset = 4;
|
971 |
break;
|
972 |
default:
|
973 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
974 |
return; /* Never happens. Keep compiler happy. */ |
975 |
} |
976 |
/* High vectors. */
|
977 |
if (env->cp15.c1_sys & (1 << 13)) { |
978 |
addr += 0xffff0000;
|
979 |
} |
980 |
switch_mode (env, new_mode); |
981 |
env->spsr = cpsr_read(env); |
982 |
/* Clear IT bits. */
|
983 |
env->condexec_bits = 0;
|
984 |
/* Switch to the new mode, and to the correct instruction set. */
|
985 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
986 |
env->uncached_cpsr |= mask; |
987 |
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
|
988 |
* and we should just guard the thumb mode on V4 */
|
989 |
if (arm_feature(env, ARM_FEATURE_V4T)) {
|
990 |
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
991 |
} |
992 |
env->regs[14] = env->regs[15] + offset; |
993 |
env->regs[15] = addr;
|
994 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
995 |
} |
996 |
|
997 |
/* Check section/page access permissions.
|
998 |
Returns the page protection flags, or zero if the access is not
|
999 |
permitted. */
|
1000 |
static inline int check_ap(CPUState *env, int ap, int domain_prot, |
1001 |
int access_type, int is_user) |
1002 |
{ |
1003 |
int prot_ro;
|
1004 |
|
1005 |
if (domain_prot == 3) { |
1006 |
return PAGE_READ | PAGE_WRITE;
|
1007 |
} |
1008 |
|
1009 |
if (access_type == 1) |
1010 |
prot_ro = 0;
|
1011 |
else
|
1012 |
prot_ro = PAGE_READ; |
1013 |
|
1014 |
switch (ap) {
|
1015 |
case 0: |
1016 |
if (access_type == 1) |
1017 |
return 0; |
1018 |
switch ((env->cp15.c1_sys >> 8) & 3) { |
1019 |
case 1: |
1020 |
return is_user ? 0 : PAGE_READ; |
1021 |
case 2: |
1022 |
return PAGE_READ;
|
1023 |
default:
|
1024 |
return 0; |
1025 |
} |
1026 |
case 1: |
1027 |
return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
1028 |
case 2: |
1029 |
if (is_user)
|
1030 |
return prot_ro;
|
1031 |
else
|
1032 |
return PAGE_READ | PAGE_WRITE;
|
1033 |
case 3: |
1034 |
return PAGE_READ | PAGE_WRITE;
|
1035 |
case 4: /* Reserved. */ |
1036 |
return 0; |
1037 |
case 5: |
1038 |
return is_user ? 0 : prot_ro; |
1039 |
case 6: |
1040 |
return prot_ro;
|
1041 |
case 7: |
1042 |
if (!arm_feature (env, ARM_FEATURE_V6K))
|
1043 |
return 0; |
1044 |
return prot_ro;
|
1045 |
default:
|
1046 |
abort(); |
1047 |
} |
1048 |
} |
1049 |
|
1050 |
static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
|
1051 |
{ |
1052 |
uint32_t table; |
1053 |
|
1054 |
if (address & env->cp15.c2_mask)
|
1055 |
table = env->cp15.c2_base1 & 0xffffc000;
|
1056 |
else
|
1057 |
table = env->cp15.c2_base0 & env->cp15.c2_base_mask; |
1058 |
|
1059 |
table |= (address >> 18) & 0x3ffc; |
1060 |
return table;
|
1061 |
} |
1062 |
|
1063 |
static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, |
1064 |
int is_user, uint32_t *phys_ptr, int *prot, |
1065 |
target_ulong *page_size) |
1066 |
{ |
1067 |
int code;
|
1068 |
uint32_t table; |
1069 |
uint32_t desc; |
1070 |
int type;
|
1071 |
int ap;
|
1072 |
int domain;
|
1073 |
int domain_prot;
|
1074 |
uint32_t phys_addr; |
1075 |
|
1076 |
/* Pagetable walk. */
|
1077 |
/* Lookup l1 descriptor. */
|
1078 |
table = get_level1_table_address(env, address); |
1079 |
desc = ldl_phys(table); |
1080 |
type = (desc & 3);
|
1081 |
domain = (desc >> 5) & 0x0f; |
1082 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
1083 |
if (type == 0) { |
1084 |
/* Section translation fault. */
|
1085 |
code = 5;
|
1086 |
goto do_fault;
|
1087 |
} |
1088 |
if (domain_prot == 0 || domain_prot == 2) { |
1089 |
if (type == 2) |
1090 |
code = 9; /* Section domain fault. */ |
1091 |
else
|
1092 |
code = 11; /* Page domain fault. */ |
1093 |
goto do_fault;
|
1094 |
} |
1095 |
if (type == 2) { |
1096 |
/* 1Mb section. */
|
1097 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
1098 |
ap = (desc >> 10) & 3; |
1099 |
code = 13;
|
1100 |
*page_size = 1024 * 1024; |
1101 |
} else {
|
1102 |
/* Lookup l2 entry. */
|
1103 |
if (type == 1) { |
1104 |
/* Coarse pagetable. */
|
1105 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
1106 |
} else {
|
1107 |
/* Fine pagetable. */
|
1108 |
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
1109 |
} |
1110 |
desc = ldl_phys(table); |
1111 |
switch (desc & 3) { |
1112 |
case 0: /* Page translation fault. */ |
1113 |
code = 7;
|
1114 |
goto do_fault;
|
1115 |
case 1: /* 64k page. */ |
1116 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
1117 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
1118 |
*page_size = 0x10000;
|
1119 |
break;
|
1120 |
case 2: /* 4k page. */ |
1121 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
1122 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
1123 |
*page_size = 0x1000;
|
1124 |
break;
|
1125 |
case 3: /* 1k page. */ |
1126 |
if (type == 1) { |
1127 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1128 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
1129 |
} else {
|
1130 |
/* Page translation fault. */
|
1131 |
code = 7;
|
1132 |
goto do_fault;
|
1133 |
} |
1134 |
} else {
|
1135 |
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
1136 |
} |
1137 |
ap = (desc >> 4) & 3; |
1138 |
*page_size = 0x400;
|
1139 |
break;
|
1140 |
default:
|
1141 |
/* Never happens, but compiler isn't smart enough to tell. */
|
1142 |
abort(); |
1143 |
} |
1144 |
code = 15;
|
1145 |
} |
1146 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
1147 |
if (!*prot) {
|
1148 |
/* Access permission fault. */
|
1149 |
goto do_fault;
|
1150 |
} |
1151 |
*prot |= PAGE_EXEC; |
1152 |
*phys_ptr = phys_addr; |
1153 |
return 0; |
1154 |
do_fault:
|
1155 |
return code | (domain << 4); |
1156 |
} |
1157 |
|
1158 |
static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, |
1159 |
int is_user, uint32_t *phys_ptr, int *prot, |
1160 |
target_ulong *page_size) |
1161 |
{ |
1162 |
int code;
|
1163 |
uint32_t table; |
1164 |
uint32_t desc; |
1165 |
uint32_t xn; |
1166 |
int type;
|
1167 |
int ap;
|
1168 |
int domain;
|
1169 |
int domain_prot;
|
1170 |
uint32_t phys_addr; |
1171 |
|
1172 |
/* Pagetable walk. */
|
1173 |
/* Lookup l1 descriptor. */
|
1174 |
table = get_level1_table_address(env, address); |
1175 |
desc = ldl_phys(table); |
1176 |
type = (desc & 3);
|
1177 |
if (type == 0) { |
1178 |
/* Section translation fault. */
|
1179 |
code = 5;
|
1180 |
domain = 0;
|
1181 |
goto do_fault;
|
1182 |
} else if (type == 2 && (desc & (1 << 18))) { |
1183 |
/* Supersection. */
|
1184 |
domain = 0;
|
1185 |
} else {
|
1186 |
/* Section or page. */
|
1187 |
domain = (desc >> 5) & 0x0f; |
1188 |
} |
1189 |
domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; |
1190 |
if (domain_prot == 0 || domain_prot == 2) { |
1191 |
if (type == 2) |
1192 |
code = 9; /* Section domain fault. */ |
1193 |
else
|
1194 |
code = 11; /* Page domain fault. */ |
1195 |
goto do_fault;
|
1196 |
} |
1197 |
if (type == 2) { |
1198 |
if (desc & (1 << 18)) { |
1199 |
/* Supersection. */
|
1200 |
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); |
1201 |
*page_size = 0x1000000;
|
1202 |
} else {
|
1203 |
/* Section. */
|
1204 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
1205 |
*page_size = 0x100000;
|
1206 |
} |
1207 |
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
1208 |
xn = desc & (1 << 4); |
1209 |
code = 13;
|
1210 |
} else {
|
1211 |
/* Lookup l2 entry. */
|
1212 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
1213 |
desc = ldl_phys(table); |
1214 |
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
1215 |
switch (desc & 3) { |
1216 |
case 0: /* Page translation fault. */ |
1217 |
code = 7;
|
1218 |
goto do_fault;
|
1219 |
case 1: /* 64k page. */ |
1220 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
1221 |
xn = desc & (1 << 15); |
1222 |
*page_size = 0x10000;
|
1223 |
break;
|
1224 |
case 2: case 3: /* 4k page. */ |
1225 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
1226 |
xn = desc & 1;
|
1227 |
*page_size = 0x1000;
|
1228 |
break;
|
1229 |
default:
|
1230 |
/* Never happens, but compiler isn't smart enough to tell. */
|
1231 |
abort(); |
1232 |
} |
1233 |
code = 15;
|
1234 |
} |
1235 |
if (domain_prot == 3) { |
1236 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1237 |
} else {
|
1238 |
if (xn && access_type == 2) |
1239 |
goto do_fault;
|
1240 |
|
1241 |
/* The simplified model uses AP[0] as an access control bit. */
|
1242 |
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { |
1243 |
/* Access flag fault. */
|
1244 |
code = (code == 15) ? 6 : 3; |
1245 |
goto do_fault;
|
1246 |
} |
1247 |
*prot = check_ap(env, ap, domain_prot, access_type, is_user); |
1248 |
if (!*prot) {
|
1249 |
/* Access permission fault. */
|
1250 |
goto do_fault;
|
1251 |
} |
1252 |
if (!xn) {
|
1253 |
*prot |= PAGE_EXEC; |
1254 |
} |
1255 |
} |
1256 |
*phys_ptr = phys_addr; |
1257 |
return 0; |
1258 |
do_fault:
|
1259 |
return code | (domain << 4); |
1260 |
} |
1261 |
|
1262 |
static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type, |
1263 |
int is_user, uint32_t *phys_ptr, int *prot) |
1264 |
{ |
1265 |
int n;
|
1266 |
uint32_t mask; |
1267 |
uint32_t base; |
1268 |
|
1269 |
*phys_ptr = address; |
1270 |
for (n = 7; n >= 0; n--) { |
1271 |
base = env->cp15.c6_region[n]; |
1272 |
if ((base & 1) == 0) |
1273 |
continue;
|
1274 |
mask = 1 << ((base >> 1) & 0x1f); |
1275 |
/* Keep this shift separate from the above to avoid an
|
1276 |
(undefined) << 32. */
|
1277 |
mask = (mask << 1) - 1; |
1278 |
if (((base ^ address) & ~mask) == 0) |
1279 |
break;
|
1280 |
} |
1281 |
if (n < 0) |
1282 |
return 2; |
1283 |
|
1284 |
if (access_type == 2) { |
1285 |
mask = env->cp15.c5_insn; |
1286 |
} else {
|
1287 |
mask = env->cp15.c5_data; |
1288 |
} |
1289 |
mask = (mask >> (n * 4)) & 0xf; |
1290 |
switch (mask) {
|
1291 |
case 0: |
1292 |
return 1; |
1293 |
case 1: |
1294 |
if (is_user)
|
1295 |
return 1; |
1296 |
*prot = PAGE_READ | PAGE_WRITE; |
1297 |
break;
|
1298 |
case 2: |
1299 |
*prot = PAGE_READ; |
1300 |
if (!is_user)
|
1301 |
*prot |= PAGE_WRITE; |
1302 |
break;
|
1303 |
case 3: |
1304 |
*prot = PAGE_READ | PAGE_WRITE; |
1305 |
break;
|
1306 |
case 5: |
1307 |
if (is_user)
|
1308 |
return 1; |
1309 |
*prot = PAGE_READ; |
1310 |
break;
|
1311 |
case 6: |
1312 |
*prot = PAGE_READ; |
1313 |
break;
|
1314 |
default:
|
1315 |
/* Bad permission. */
|
1316 |
return 1; |
1317 |
} |
1318 |
*prot |= PAGE_EXEC; |
1319 |
return 0; |
1320 |
} |
1321 |
|
1322 |
static inline int get_phys_addr(CPUState *env, uint32_t address, |
1323 |
int access_type, int is_user, |
1324 |
uint32_t *phys_ptr, int *prot,
|
1325 |
target_ulong *page_size) |
1326 |
{ |
1327 |
/* Fast Context Switch Extension. */
|
1328 |
if (address < 0x02000000) |
1329 |
address += env->cp15.c13_fcse; |
1330 |
|
1331 |
if ((env->cp15.c1_sys & 1) == 0) { |
1332 |
/* MMU/MPU disabled. */
|
1333 |
*phys_ptr = address; |
1334 |
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1335 |
*page_size = TARGET_PAGE_SIZE; |
1336 |
return 0; |
1337 |
} else if (arm_feature(env, ARM_FEATURE_MPU)) { |
1338 |
*page_size = TARGET_PAGE_SIZE; |
1339 |
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
|
1340 |
prot); |
1341 |
} else if (env->cp15.c1_sys & (1 << 23)) { |
1342 |
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
|
1343 |
prot, page_size); |
1344 |
} else {
|
1345 |
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
|
1346 |
prot, page_size); |
1347 |
} |
1348 |
} |
1349 |
|
1350 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
|
1351 |
int access_type, int mmu_idx) |
1352 |
{ |
1353 |
uint32_t phys_addr; |
1354 |
target_ulong page_size; |
1355 |
int prot;
|
1356 |
int ret, is_user;
|
1357 |
|
1358 |
is_user = mmu_idx == MMU_USER_IDX; |
1359 |
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot, |
1360 |
&page_size); |
1361 |
if (ret == 0) { |
1362 |
/* Map a single [sub]page. */
|
1363 |
phys_addr &= ~(uint32_t)0x3ff;
|
1364 |
address &= ~(uint32_t)0x3ff;
|
1365 |
tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); |
1366 |
return 0; |
1367 |
} |
1368 |
|
1369 |
if (access_type == 2) { |
1370 |
env->cp15.c5_insn = ret; |
1371 |
env->cp15.c6_insn = address; |
1372 |
env->exception_index = EXCP_PREFETCH_ABORT; |
1373 |
} else {
|
1374 |
env->cp15.c5_data = ret; |
1375 |
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
1376 |
env->cp15.c5_data |= (1 << 11); |
1377 |
env->cp15.c6_data = address; |
1378 |
env->exception_index = EXCP_DATA_ABORT; |
1379 |
} |
1380 |
return 1; |
1381 |
} |
1382 |
|
1383 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
1384 |
{ |
1385 |
uint32_t phys_addr; |
1386 |
target_ulong page_size; |
1387 |
int prot;
|
1388 |
int ret;
|
1389 |
|
1390 |
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size); |
1391 |
|
1392 |
if (ret != 0) |
1393 |
return -1; |
1394 |
|
1395 |
return phys_addr;
|
1396 |
} |
1397 |
|
1398 |
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
1399 |
{ |
1400 |
int cp_num = (insn >> 8) & 0xf; |
1401 |
int cp_info = (insn >> 5) & 7; |
1402 |
int src = (insn >> 16) & 0xf; |
1403 |
int operand = insn & 0xf; |
1404 |
|
1405 |
if (env->cp[cp_num].cp_write)
|
1406 |
env->cp[cp_num].cp_write(env->cp[cp_num].opaque, |
1407 |
cp_info, src, operand, val); |
1408 |
} |
1409 |
|
1410 |
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
1411 |
{ |
1412 |
int cp_num = (insn >> 8) & 0xf; |
1413 |
int cp_info = (insn >> 5) & 7; |
1414 |
int dest = (insn >> 16) & 0xf; |
1415 |
int operand = insn & 0xf; |
1416 |
|
1417 |
if (env->cp[cp_num].cp_read)
|
1418 |
return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
|
1419 |
cp_info, dest, operand); |
1420 |
return 0; |
1421 |
} |
1422 |
|
1423 |
/* Return basic MPU access permission bits. */
|
1424 |
static uint32_t simple_mpu_ap_bits(uint32_t val)
|
1425 |
{ |
1426 |
uint32_t ret; |
1427 |
uint32_t mask; |
1428 |
int i;
|
1429 |
ret = 0;
|
1430 |
mask = 3;
|
1431 |
for (i = 0; i < 16; i += 2) { |
1432 |
ret |= (val >> i) & mask; |
1433 |
mask <<= 2;
|
1434 |
} |
1435 |
return ret;
|
1436 |
} |
1437 |
|
1438 |
/* Pad basic MPU access permission bits to extended format. */
|
1439 |
static uint32_t extended_mpu_ap_bits(uint32_t val)
|
1440 |
{ |
1441 |
uint32_t ret; |
1442 |
uint32_t mask; |
1443 |
int i;
|
1444 |
ret = 0;
|
1445 |
mask = 3;
|
1446 |
for (i = 0; i < 16; i += 2) { |
1447 |
ret |= (val & mask) << i; |
1448 |
mask <<= 2;
|
1449 |
} |
1450 |
return ret;
|
1451 |
} |
1452 |
|
1453 |
void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
1454 |
{ |
1455 |
int op1;
|
1456 |
int op2;
|
1457 |
int crm;
|
1458 |
|
1459 |
op1 = (insn >> 21) & 7; |
1460 |
op2 = (insn >> 5) & 7; |
1461 |
crm = insn & 0xf;
|
1462 |
switch ((insn >> 16) & 0xf) { |
1463 |
case 0: |
1464 |
/* ID codes. */
|
1465 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1466 |
break;
|
1467 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1468 |
break;
|
1469 |
if (arm_feature(env, ARM_FEATURE_V7)
|
1470 |
&& op1 == 2 && crm == 0 && op2 == 0) { |
1471 |
env->cp15.c0_cssel = val & 0xf;
|
1472 |
break;
|
1473 |
} |
1474 |
goto bad_reg;
|
1475 |
case 1: /* System configuration. */ |
1476 |
if (arm_feature(env, ARM_FEATURE_V7)
|
1477 |
&& op1 == 0 && crm == 1 && op2 == 0) { |
1478 |
env->cp15.c1_scr = val; |
1479 |
break;
|
1480 |
} |
1481 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1482 |
op2 = 0;
|
1483 |
switch (op2) {
|
1484 |
case 0: |
1485 |
if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) |
1486 |
env->cp15.c1_sys = val; |
1487 |
/* ??? Lots of these bits are not implemented. */
|
1488 |
/* This may enable/disable the MMU, so do a TLB flush. */
|
1489 |
tlb_flush(env, 1);
|
1490 |
break;
|
1491 |
case 1: /* Auxiliary control register. */ |
1492 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1493 |
env->cp15.c1_xscaleauxcr = val; |
1494 |
break;
|
1495 |
} |
1496 |
/* Not implemented. */
|
1497 |
break;
|
1498 |
case 2: |
1499 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1500 |
goto bad_reg;
|
1501 |
if (env->cp15.c1_coproc != val) {
|
1502 |
env->cp15.c1_coproc = val; |
1503 |
/* ??? Is this safe when called from within a TB? */
|
1504 |
tb_flush(env); |
1505 |
} |
1506 |
break;
|
1507 |
default:
|
1508 |
goto bad_reg;
|
1509 |
} |
1510 |
break;
|
1511 |
case 2: /* MMU Page table control / MPU cache control. */ |
1512 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1513 |
switch (op2) {
|
1514 |
case 0: |
1515 |
env->cp15.c2_data = val; |
1516 |
break;
|
1517 |
case 1: |
1518 |
env->cp15.c2_insn = val; |
1519 |
break;
|
1520 |
default:
|
1521 |
goto bad_reg;
|
1522 |
} |
1523 |
} else {
|
1524 |
switch (op2) {
|
1525 |
case 0: |
1526 |
env->cp15.c2_base0 = val; |
1527 |
break;
|
1528 |
case 1: |
1529 |
env->cp15.c2_base1 = val; |
1530 |
break;
|
1531 |
case 2: |
1532 |
val &= 7;
|
1533 |
env->cp15.c2_control = val; |
1534 |
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
|
1535 |
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
|
1536 |
break;
|
1537 |
default:
|
1538 |
goto bad_reg;
|
1539 |
} |
1540 |
} |
1541 |
break;
|
1542 |
case 3: /* MMU Domain access control / MPU write buffer control. */ |
1543 |
env->cp15.c3 = val; |
1544 |
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
1545 |
break;
|
1546 |
case 4: /* Reserved. */ |
1547 |
goto bad_reg;
|
1548 |
case 5: /* MMU Fault status / MPU access permission. */ |
1549 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1550 |
op2 = 0;
|
1551 |
switch (op2) {
|
1552 |
case 0: |
1553 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1554 |
val = extended_mpu_ap_bits(val); |
1555 |
env->cp15.c5_data = val; |
1556 |
break;
|
1557 |
case 1: |
1558 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1559 |
val = extended_mpu_ap_bits(val); |
1560 |
env->cp15.c5_insn = val; |
1561 |
break;
|
1562 |
case 2: |
1563 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1564 |
goto bad_reg;
|
1565 |
env->cp15.c5_data = val; |
1566 |
break;
|
1567 |
case 3: |
1568 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1569 |
goto bad_reg;
|
1570 |
env->cp15.c5_insn = val; |
1571 |
break;
|
1572 |
default:
|
1573 |
goto bad_reg;
|
1574 |
} |
1575 |
break;
|
1576 |
case 6: /* MMU Fault address / MPU base/size. */ |
1577 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1578 |
if (crm >= 8) |
1579 |
goto bad_reg;
|
1580 |
env->cp15.c6_region[crm] = val; |
1581 |
} else {
|
1582 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1583 |
op2 = 0;
|
1584 |
switch (op2) {
|
1585 |
case 0: |
1586 |
env->cp15.c6_data = val; |
1587 |
break;
|
1588 |
case 1: /* ??? This is WFAR on armv6 */ |
1589 |
case 2: |
1590 |
env->cp15.c6_insn = val; |
1591 |
break;
|
1592 |
default:
|
1593 |
goto bad_reg;
|
1594 |
} |
1595 |
} |
1596 |
break;
|
1597 |
case 7: /* Cache control. */ |
1598 |
env->cp15.c15_i_max = 0x000;
|
1599 |
env->cp15.c15_i_min = 0xff0;
|
1600 |
if (op1 != 0) { |
1601 |
goto bad_reg;
|
1602 |
} |
1603 |
/* No cache, so nothing to do except VA->PA translations. */
|
1604 |
if (arm_feature(env, ARM_FEATURE_VAPA)) {
|
1605 |
switch (crm) {
|
1606 |
case 4: |
1607 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
1608 |
env->cp15.c7_par = val & 0xfffff6ff;
|
1609 |
} else {
|
1610 |
env->cp15.c7_par = val & 0xfffff1ff;
|
1611 |
} |
1612 |
break;
|
1613 |
case 8: { |
1614 |
uint32_t phys_addr; |
1615 |
target_ulong page_size; |
1616 |
int prot;
|
1617 |
int ret, is_user = op2 & 2; |
1618 |
int access_type = op2 & 1; |
1619 |
|
1620 |
if (op2 & 4) { |
1621 |
/* Other states are only available with TrustZone */
|
1622 |
goto bad_reg;
|
1623 |
} |
1624 |
ret = get_phys_addr(env, val, access_type, is_user, |
1625 |
&phys_addr, &prot, &page_size); |
1626 |
if (ret == 0) { |
1627 |
/* We do not set any attribute bits in the PAR */
|
1628 |
if (page_size == (1 << 24) |
1629 |
&& arm_feature(env, ARM_FEATURE_V7)) { |
1630 |
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; |
1631 |
} else {
|
1632 |
env->cp15.c7_par = phys_addr & 0xfffff000;
|
1633 |
} |
1634 |
} else {
|
1635 |
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | |
1636 |
((ret & (12 << 1)) >> 6) | |
1637 |
((ret & 0xf) << 1) | 1; |
1638 |
} |
1639 |
break;
|
1640 |
} |
1641 |
} |
1642 |
} |
1643 |
break;
|
1644 |
case 8: /* MMU TLB control. */ |
1645 |
switch (op2) {
|
1646 |
case 0: /* Invalidate all (TLBIALL) */ |
1647 |
tlb_flush(env, 1);
|
1648 |
break;
|
1649 |
case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ |
1650 |
tlb_flush_page(env, val & TARGET_PAGE_MASK); |
1651 |
break;
|
1652 |
case 2: /* Invalidate by ASID (TLBIASID) */ |
1653 |
tlb_flush(env, val == 0);
|
1654 |
break;
|
1655 |
case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ |
1656 |
tlb_flush_page(env, val & TARGET_PAGE_MASK); |
1657 |
break;
|
1658 |
default:
|
1659 |
goto bad_reg;
|
1660 |
} |
1661 |
break;
|
1662 |
case 9: |
1663 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1664 |
break;
|
1665 |
if (arm_feature(env, ARM_FEATURE_STRONGARM))
|
1666 |
break; /* Ignore ReadBuffer access */ |
1667 |
switch (crm) {
|
1668 |
case 0: /* Cache lockdown. */ |
1669 |
switch (op1) {
|
1670 |
case 0: /* L1 cache. */ |
1671 |
switch (op2) {
|
1672 |
case 0: |
1673 |
env->cp15.c9_data = val; |
1674 |
break;
|
1675 |
case 1: |
1676 |
env->cp15.c9_insn = val; |
1677 |
break;
|
1678 |
default:
|
1679 |
goto bad_reg;
|
1680 |
} |
1681 |
break;
|
1682 |
case 1: /* L2 cache. */ |
1683 |
/* Ignore writes to L2 lockdown/auxiliary registers. */
|
1684 |
break;
|
1685 |
default:
|
1686 |
goto bad_reg;
|
1687 |
} |
1688 |
break;
|
1689 |
case 1: /* TCM memory region registers. */ |
1690 |
/* Not implemented. */
|
1691 |
goto bad_reg;
|
1692 |
case 12: /* Performance monitor control */ |
1693 |
/* Performance monitors are implementation defined in v7,
|
1694 |
* but with an ARM recommended set of registers, which we
|
1695 |
* follow (although we don't actually implement any counters)
|
1696 |
*/
|
1697 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
1698 |
goto bad_reg;
|
1699 |
} |
1700 |
switch (op2) {
|
1701 |
case 0: /* performance monitor control register */ |
1702 |
/* only the DP, X, D and E bits are writable */
|
1703 |
env->cp15.c9_pmcr &= ~0x39;
|
1704 |
env->cp15.c9_pmcr |= (val & 0x39);
|
1705 |
break;
|
1706 |
case 1: /* Count enable set register */ |
1707 |
val &= (1 << 31); |
1708 |
env->cp15.c9_pmcnten |= val; |
1709 |
break;
|
1710 |
case 2: /* Count enable clear */ |
1711 |
val &= (1 << 31); |
1712 |
env->cp15.c9_pmcnten &= ~val; |
1713 |
break;
|
1714 |
case 3: /* Overflow flag status */ |
1715 |
env->cp15.c9_pmovsr &= ~val; |
1716 |
break;
|
1717 |
case 4: /* Software increment */ |
1718 |
/* RAZ/WI since we don't implement the software-count event */
|
1719 |
break;
|
1720 |
case 5: /* Event counter selection register */ |
1721 |
/* Since we don't implement any events, writing to this register
|
1722 |
* is actually UNPREDICTABLE. So we choose to RAZ/WI.
|
1723 |
*/
|
1724 |
break;
|
1725 |
default:
|
1726 |
goto bad_reg;
|
1727 |
} |
1728 |
break;
|
1729 |
case 13: /* Performance counters */ |
1730 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
1731 |
goto bad_reg;
|
1732 |
} |
1733 |
switch (op2) {
|
1734 |
case 0: /* Cycle count register: not implemented, so RAZ/WI */ |
1735 |
break;
|
1736 |
case 1: /* Event type select */ |
1737 |
env->cp15.c9_pmxevtyper = val & 0xff;
|
1738 |
break;
|
1739 |
case 2: /* Event count register */ |
1740 |
/* Unimplemented (we have no events), RAZ/WI */
|
1741 |
break;
|
1742 |
default:
|
1743 |
goto bad_reg;
|
1744 |
} |
1745 |
break;
|
1746 |
case 14: /* Performance monitor control */ |
1747 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
1748 |
goto bad_reg;
|
1749 |
} |
1750 |
switch (op2) {
|
1751 |
case 0: /* user enable */ |
1752 |
env->cp15.c9_pmuserenr = val & 1;
|
1753 |
/* changes access rights for cp registers, so flush tbs */
|
1754 |
tb_flush(env); |
1755 |
break;
|
1756 |
case 1: /* interrupt enable set */ |
1757 |
/* We have no event counters so only the C bit can be changed */
|
1758 |
val &= (1 << 31); |
1759 |
env->cp15.c9_pminten |= val; |
1760 |
break;
|
1761 |
case 2: /* interrupt enable clear */ |
1762 |
val &= (1 << 31); |
1763 |
env->cp15.c9_pminten &= ~val; |
1764 |
break;
|
1765 |
} |
1766 |
break;
|
1767 |
default:
|
1768 |
goto bad_reg;
|
1769 |
} |
1770 |
break;
|
1771 |
case 10: /* MMU TLB lockdown. */ |
1772 |
/* ??? TLB lockdown not implemented. */
|
1773 |
break;
|
1774 |
case 12: /* Reserved. */ |
1775 |
goto bad_reg;
|
1776 |
case 13: /* Process ID. */ |
1777 |
switch (op2) {
|
1778 |
case 0: |
1779 |
/* Unlike real hardware the qemu TLB uses virtual addresses,
|
1780 |
not modified virtual addresses, so this causes a TLB flush.
|
1781 |
*/
|
1782 |
if (env->cp15.c13_fcse != val)
|
1783 |
tlb_flush(env, 1);
|
1784 |
env->cp15.c13_fcse = val; |
1785 |
break;
|
1786 |
case 1: |
1787 |
/* This changes the ASID, so do a TLB flush. */
|
1788 |
if (env->cp15.c13_context != val
|
1789 |
&& !arm_feature(env, ARM_FEATURE_MPU)) |
1790 |
tlb_flush(env, 0);
|
1791 |
env->cp15.c13_context = val; |
1792 |
break;
|
1793 |
default:
|
1794 |
goto bad_reg;
|
1795 |
} |
1796 |
break;
|
1797 |
case 14: /* Generic timer */ |
1798 |
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
|
1799 |
/* Dummy implementation: RAZ/WI for all */
|
1800 |
break;
|
1801 |
} |
1802 |
goto bad_reg;
|
1803 |
case 15: /* Implementation specific. */ |
1804 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1805 |
if (op2 == 0 && crm == 1) { |
1806 |
if (env->cp15.c15_cpar != (val & 0x3fff)) { |
1807 |
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
1808 |
tb_flush(env); |
1809 |
env->cp15.c15_cpar = val & 0x3fff;
|
1810 |
} |
1811 |
break;
|
1812 |
} |
1813 |
goto bad_reg;
|
1814 |
} |
1815 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1816 |
switch (crm) {
|
1817 |
case 0: |
1818 |
break;
|
1819 |
case 1: /* Set TI925T configuration. */ |
1820 |
env->cp15.c15_ticonfig = val & 0xe7;
|
1821 |
env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */ |
1822 |
ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
1823 |
break;
|
1824 |
case 2: /* Set I_max. */ |
1825 |
env->cp15.c15_i_max = val; |
1826 |
break;
|
1827 |
case 3: /* Set I_min. */ |
1828 |
env->cp15.c15_i_min = val; |
1829 |
break;
|
1830 |
case 4: /* Set thread-ID. */ |
1831 |
env->cp15.c15_threadid = val & 0xffff;
|
1832 |
break;
|
1833 |
case 8: /* Wait-for-interrupt (deprecated). */ |
1834 |
cpu_interrupt(env, CPU_INTERRUPT_HALT); |
1835 |
break;
|
1836 |
default:
|
1837 |
goto bad_reg;
|
1838 |
} |
1839 |
} |
1840 |
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
|
1841 |
switch (crm) {
|
1842 |
case 0: |
1843 |
if ((op1 == 0) && (op2 == 0)) { |
1844 |
env->cp15.c15_power_control = val; |
1845 |
} else if ((op1 == 0) && (op2 == 1)) { |
1846 |
env->cp15.c15_diagnostic = val; |
1847 |
} else if ((op1 == 0) && (op2 == 2)) { |
1848 |
env->cp15.c15_power_diagnostic = val; |
1849 |
} |
1850 |
default:
|
1851 |
break;
|
1852 |
} |
1853 |
} |
1854 |
break;
|
1855 |
} |
1856 |
return;
|
1857 |
bad_reg:
|
1858 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
1859 |
cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
|
1860 |
(insn >> 16) & 0xf, crm, op1, op2); |
1861 |
} |
1862 |
|
1863 |
uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
1864 |
{ |
1865 |
int op1;
|
1866 |
int op2;
|
1867 |
int crm;
|
1868 |
|
1869 |
op1 = (insn >> 21) & 7; |
1870 |
op2 = (insn >> 5) & 7; |
1871 |
crm = insn & 0xf;
|
1872 |
switch ((insn >> 16) & 0xf) { |
1873 |
case 0: /* ID codes. */ |
1874 |
switch (op1) {
|
1875 |
case 0: |
1876 |
switch (crm) {
|
1877 |
case 0: |
1878 |
switch (op2) {
|
1879 |
case 0: /* Device ID. */ |
1880 |
return env->cp15.c0_cpuid;
|
1881 |
case 1: /* Cache Type. */ |
1882 |
return env->cp15.c0_cachetype;
|
1883 |
case 2: /* TCM status. */ |
1884 |
return 0; |
1885 |
case 3: /* TLB type register. */ |
1886 |
return 0; /* No lockable TLB entries. */ |
1887 |
case 5: /* MPIDR */ |
1888 |
/* The MPIDR was standardised in v7; prior to
|
1889 |
* this it was implemented only in the 11MPCore.
|
1890 |
* For all other pre-v7 cores it does not exist.
|
1891 |
*/
|
1892 |
if (arm_feature(env, ARM_FEATURE_V7) ||
|
1893 |
ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) { |
1894 |
int mpidr = env->cpu_index;
|
1895 |
/* We don't support setting cluster ID ([8..11])
|
1896 |
* so these bits always RAZ.
|
1897 |
*/
|
1898 |
if (arm_feature(env, ARM_FEATURE_V7MP)) {
|
1899 |
mpidr |= (1 << 31); |
1900 |
/* Cores which are uniprocessor (non-coherent)
|
1901 |
* but still implement the MP extensions set
|
1902 |
* bit 30. (For instance, A9UP.) However we do
|
1903 |
* not currently model any of those cores.
|
1904 |
*/
|
1905 |
} |
1906 |
return mpidr;
|
1907 |
} |
1908 |
/* otherwise fall through to the unimplemented-reg case */
|
1909 |
default:
|
1910 |
goto bad_reg;
|
1911 |
} |
1912 |
case 1: |
1913 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1914 |
goto bad_reg;
|
1915 |
return env->cp15.c0_c1[op2];
|
1916 |
case 2: |
1917 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1918 |
goto bad_reg;
|
1919 |
return env->cp15.c0_c2[op2];
|
1920 |
case 3: case 4: case 5: case 6: case 7: |
1921 |
return 0; |
1922 |
default:
|
1923 |
goto bad_reg;
|
1924 |
} |
1925 |
case 1: |
1926 |
/* These registers aren't documented on arm11 cores. However
|
1927 |
Linux looks at them anyway. */
|
1928 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1929 |
goto bad_reg;
|
1930 |
if (crm != 0) |
1931 |
goto bad_reg;
|
1932 |
if (!arm_feature(env, ARM_FEATURE_V7))
|
1933 |
return 0; |
1934 |
|
1935 |
switch (op2) {
|
1936 |
case 0: |
1937 |
return env->cp15.c0_ccsid[env->cp15.c0_cssel];
|
1938 |
case 1: |
1939 |
return env->cp15.c0_clid;
|
1940 |
case 7: |
1941 |
return 0; |
1942 |
} |
1943 |
goto bad_reg;
|
1944 |
case 2: |
1945 |
if (op2 != 0 || crm != 0) |
1946 |
goto bad_reg;
|
1947 |
return env->cp15.c0_cssel;
|
1948 |
default:
|
1949 |
goto bad_reg;
|
1950 |
} |
1951 |
case 1: /* System configuration. */ |
1952 |
if (arm_feature(env, ARM_FEATURE_V7)
|
1953 |
&& op1 == 0 && crm == 1 && op2 == 0) { |
1954 |
return env->cp15.c1_scr;
|
1955 |
} |
1956 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1957 |
op2 = 0;
|
1958 |
switch (op2) {
|
1959 |
case 0: /* Control register. */ |
1960 |
return env->cp15.c1_sys;
|
1961 |
case 1: /* Auxiliary control register. */ |
1962 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1963 |
return env->cp15.c1_xscaleauxcr;
|
1964 |
if (!arm_feature(env, ARM_FEATURE_AUXCR))
|
1965 |
goto bad_reg;
|
1966 |
switch (ARM_CPUID(env)) {
|
1967 |
case ARM_CPUID_ARM1026:
|
1968 |
return 1; |
1969 |
case ARM_CPUID_ARM1136:
|
1970 |
case ARM_CPUID_ARM1136_R2:
|
1971 |
case ARM_CPUID_ARM1176:
|
1972 |
return 7; |
1973 |
case ARM_CPUID_ARM11MPCORE:
|
1974 |
return 1; |
1975 |
case ARM_CPUID_CORTEXA8:
|
1976 |
return 2; |
1977 |
case ARM_CPUID_CORTEXA9:
|
1978 |
case ARM_CPUID_CORTEXA15:
|
1979 |
return 0; |
1980 |
default:
|
1981 |
goto bad_reg;
|
1982 |
} |
1983 |
case 2: /* Coprocessor access register. */ |
1984 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1985 |
goto bad_reg;
|
1986 |
return env->cp15.c1_coproc;
|
1987 |
default:
|
1988 |
goto bad_reg;
|
1989 |
} |
1990 |
case 2: /* MMU Page table control / MPU cache control. */ |
1991 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1992 |
switch (op2) {
|
1993 |
case 0: |
1994 |
return env->cp15.c2_data;
|
1995 |
break;
|
1996 |
case 1: |
1997 |
return env->cp15.c2_insn;
|
1998 |
break;
|
1999 |
default:
|
2000 |
goto bad_reg;
|
2001 |
} |
2002 |
} else {
|
2003 |
switch (op2) {
|
2004 |
case 0: |
2005 |
return env->cp15.c2_base0;
|
2006 |
case 1: |
2007 |
return env->cp15.c2_base1;
|
2008 |
case 2: |
2009 |
return env->cp15.c2_control;
|
2010 |
default:
|
2011 |
goto bad_reg;
|
2012 |
} |
2013 |
} |
2014 |
case 3: /* MMU Domain access control / MPU write buffer control. */ |
2015 |
return env->cp15.c3;
|
2016 |
case 4: /* Reserved. */ |
2017 |
goto bad_reg;
|
2018 |
case 5: /* MMU Fault status / MPU access permission. */ |
2019 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
2020 |
op2 = 0;
|
2021 |
switch (op2) {
|
2022 |
case 0: |
2023 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
2024 |
return simple_mpu_ap_bits(env->cp15.c5_data);
|
2025 |
return env->cp15.c5_data;
|
2026 |
case 1: |
2027 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
2028 |
return simple_mpu_ap_bits(env->cp15.c5_data);
|
2029 |
return env->cp15.c5_insn;
|
2030 |
case 2: |
2031 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
2032 |
goto bad_reg;
|
2033 |
return env->cp15.c5_data;
|
2034 |
case 3: |
2035 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
2036 |
goto bad_reg;
|
2037 |
return env->cp15.c5_insn;
|
2038 |
default:
|
2039 |
goto bad_reg;
|
2040 |
} |
2041 |
case 6: /* MMU Fault address. */ |
2042 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
2043 |
if (crm >= 8) |
2044 |
goto bad_reg;
|
2045 |
return env->cp15.c6_region[crm];
|
2046 |
} else {
|
2047 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
2048 |
op2 = 0;
|
2049 |
switch (op2) {
|
2050 |
case 0: |
2051 |
return env->cp15.c6_data;
|
2052 |
case 1: |
2053 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
2054 |
/* Watchpoint Fault Adrress. */
|
2055 |
return 0; /* Not implemented. */ |
2056 |
} else {
|
2057 |
/* Instruction Fault Adrress. */
|
2058 |
/* Arm9 doesn't have an IFAR, but implementing it anyway
|
2059 |
shouldn't do any harm. */
|
2060 |
return env->cp15.c6_insn;
|
2061 |
} |
2062 |
case 2: |
2063 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
2064 |
/* Instruction Fault Adrress. */
|
2065 |
return env->cp15.c6_insn;
|
2066 |
} else {
|
2067 |
goto bad_reg;
|
2068 |
} |
2069 |
default:
|
2070 |
goto bad_reg;
|
2071 |
} |
2072 |
} |
2073 |
case 7: /* Cache control. */ |
2074 |
if (crm == 4 && op1 == 0 && op2 == 0) { |
2075 |
return env->cp15.c7_par;
|
2076 |
} |
2077 |
/* FIXME: Should only clear Z flag if destination is r15. */
|
2078 |
env->ZF = 0;
|
2079 |
return 0; |
2080 |
case 8: /* MMU TLB control. */ |
2081 |
goto bad_reg;
|
2082 |
case 9: |
2083 |
switch (crm) {
|
2084 |
case 0: /* Cache lockdown */ |
2085 |
switch (op1) {
|
2086 |
case 0: /* L1 cache. */ |
2087 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
2088 |
return 0; |
2089 |
} |
2090 |
switch (op2) {
|
2091 |
case 0: |
2092 |
return env->cp15.c9_data;
|
2093 |
case 1: |
2094 |
return env->cp15.c9_insn;
|
2095 |
default:
|
2096 |
goto bad_reg;
|
2097 |
} |
2098 |
case 1: /* L2 cache */ |
2099 |
/* L2 Lockdown and Auxiliary control. */
|
2100 |
switch (op2) {
|
2101 |
case 0: |
2102 |
/* L2 cache lockdown (A8 only) */
|
2103 |
return 0; |
2104 |
case 2: |
2105 |
/* L2 cache auxiliary control (A8) or control (A15) */
|
2106 |
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
|
2107 |
/* Linux wants the number of processors from here.
|
2108 |
* Might as well set the interrupt-controller bit too.
|
2109 |
*/
|
2110 |
return ((smp_cpus - 1) << 24) | (1 << 23); |
2111 |
} |
2112 |
return 0; |
2113 |
case 3: |
2114 |
/* L2 cache extended control (A15) */
|
2115 |
return 0; |
2116 |
default:
|
2117 |
goto bad_reg;
|
2118 |
} |
2119 |
default:
|
2120 |
goto bad_reg;
|
2121 |
} |
2122 |
break;
|
2123 |
case 12: /* Performance monitor control */ |
2124 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
2125 |
goto bad_reg;
|
2126 |
} |
2127 |
switch (op2) {
|
2128 |
case 0: /* performance monitor control register */ |
2129 |
return env->cp15.c9_pmcr;
|
2130 |
case 1: /* count enable set */ |
2131 |
case 2: /* count enable clear */ |
2132 |
return env->cp15.c9_pmcnten;
|
2133 |
case 3: /* overflow flag status */ |
2134 |
return env->cp15.c9_pmovsr;
|
2135 |
case 4: /* software increment */ |
2136 |
case 5: /* event counter selection register */ |
2137 |
return 0; /* Unimplemented, RAZ/WI */ |
2138 |
default:
|
2139 |
goto bad_reg;
|
2140 |
} |
2141 |
case 13: /* Performance counters */ |
2142 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
2143 |
goto bad_reg;
|
2144 |
} |
2145 |
switch (op2) {
|
2146 |
case 1: /* Event type select */ |
2147 |
return env->cp15.c9_pmxevtyper;
|
2148 |
case 0: /* Cycle count register */ |
2149 |
case 2: /* Event count register */ |
2150 |
/* Unimplemented, so RAZ/WI */
|
2151 |
return 0; |
2152 |
default:
|
2153 |
goto bad_reg;
|
2154 |
} |
2155 |
case 14: /* Performance monitor control */ |
2156 |
if (!arm_feature(env, ARM_FEATURE_V7)) {
|
2157 |
goto bad_reg;
|
2158 |
} |
2159 |
switch (op2) {
|
2160 |
case 0: /* user enable */ |
2161 |
return env->cp15.c9_pmuserenr;
|
2162 |
case 1: /* interrupt enable set */ |
2163 |
case 2: /* interrupt enable clear */ |
2164 |
return env->cp15.c9_pminten;
|
2165 |
default:
|
2166 |
goto bad_reg;
|
2167 |
} |
2168 |
default:
|
2169 |
goto bad_reg;
|
2170 |
} |
2171 |
break;
|
2172 |
case 10: /* MMU TLB lockdown. */ |
2173 |
/* ??? TLB lockdown not implemented. */
|
2174 |
return 0; |
2175 |
case 11: /* TCM DMA control. */ |
2176 |
case 12: /* Reserved. */ |
2177 |
goto bad_reg;
|
2178 |
case 13: /* Process ID. */ |
2179 |
switch (op2) {
|
2180 |
case 0: |
2181 |
return env->cp15.c13_fcse;
|
2182 |
case 1: |
2183 |
return env->cp15.c13_context;
|
2184 |
default:
|
2185 |
goto bad_reg;
|
2186 |
} |
2187 |
case 14: /* Generic timer */ |
2188 |
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
|
2189 |
/* Dummy implementation: RAZ/WI for all */
|
2190 |
return 0; |
2191 |
} |
2192 |
goto bad_reg;
|
2193 |
case 15: /* Implementation specific. */ |
2194 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
2195 |
if (op2 == 0 && crm == 1) |
2196 |
return env->cp15.c15_cpar;
|
2197 |
|
2198 |
goto bad_reg;
|
2199 |
} |
2200 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
2201 |
switch (crm) {
|
2202 |
case 0: |
2203 |
return 0; |
2204 |
case 1: /* Read TI925T configuration. */ |
2205 |
return env->cp15.c15_ticonfig;
|
2206 |
case 2: /* Read I_max. */ |
2207 |
return env->cp15.c15_i_max;
|
2208 |
case 3: /* Read I_min. */ |
2209 |
return env->cp15.c15_i_min;
|
2210 |
case 4: /* Read thread-ID. */ |
2211 |
return env->cp15.c15_threadid;
|
2212 |
case 8: /* TI925T_status */ |
2213 |
return 0; |
2214 |
} |
2215 |
/* TODO: Peripheral port remap register:
|
2216 |
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
|
2217 |
* controller base address at $rn & ~0xfff and map size of
|
2218 |
* 0x200 << ($rn & 0xfff), when MMU is off. */
|
2219 |
goto bad_reg;
|
2220 |
} |
2221 |
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
|
2222 |
switch (crm) {
|
2223 |
case 0: |
2224 |
if ((op1 == 4) && (op2 == 0)) { |
2225 |
/* The config_base_address should hold the value of
|
2226 |
* the peripheral base. ARM should get this from a CPU
|
2227 |
* object property, but that support isn't available in
|
2228 |
* December 2011. Default to 0 for now and board models
|
2229 |
* that care can set it by a private hook */
|
2230 |
return env->cp15.c15_config_base_address;
|
2231 |
} else if ((op1 == 0) && (op2 == 0)) { |
2232 |
/* power_control should be set to maximum latency. Again,
|
2233 |
default to 0 and set by private hook */
|
2234 |
return env->cp15.c15_power_control;
|
2235 |
} else if ((op1 == 0) && (op2 == 1)) { |
2236 |
return env->cp15.c15_diagnostic;
|
2237 |
} else if ((op1 == 0) && (op2 == 2)) { |
2238 |
return env->cp15.c15_power_diagnostic;
|
2239 |
} |
2240 |
break;
|
2241 |
case 1: /* NEON Busy */ |
2242 |
return 0; |
2243 |
case 5: /* tlb lockdown */ |
2244 |
case 6: |
2245 |
case 7: |
2246 |
if ((op1 == 5) && (op2 == 2)) { |
2247 |
return 0; |
2248 |
} |
2249 |
break;
|
2250 |
default:
|
2251 |
break;
|
2252 |
} |
2253 |
goto bad_reg;
|
2254 |
} |
2255 |
return 0; |
2256 |
} |
2257 |
bad_reg:
|
2258 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
2259 |
cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
|
2260 |
(insn >> 16) & 0xf, crm, op1, op2); |
2261 |
return 0; |
2262 |
} |
2263 |
|
2264 |
void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
2265 |
{ |
2266 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
2267 |
env->regs[13] = val;
|
2268 |
} else {
|
2269 |
env->banked_r13[bank_number(env, mode)] = val; |
2270 |
} |
2271 |
} |
2272 |
|
2273 |
uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
2274 |
{ |
2275 |
if ((env->uncached_cpsr & CPSR_M) == mode) {
|
2276 |
return env->regs[13]; |
2277 |
} else {
|
2278 |
return env->banked_r13[bank_number(env, mode)];
|
2279 |
} |
2280 |
} |
2281 |
|
2282 |
uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
2283 |
{ |
2284 |
switch (reg) {
|
2285 |
case 0: /* APSR */ |
2286 |
return xpsr_read(env) & 0xf8000000; |
2287 |
case 1: /* IAPSR */ |
2288 |
return xpsr_read(env) & 0xf80001ff; |
2289 |
case 2: /* EAPSR */ |
2290 |
return xpsr_read(env) & 0xff00fc00; |
2291 |
case 3: /* xPSR */ |
2292 |
return xpsr_read(env) & 0xff00fdff; |
2293 |
case 5: /* IPSR */ |
2294 |
return xpsr_read(env) & 0x000001ff; |
2295 |
case 6: /* EPSR */ |
2296 |
return xpsr_read(env) & 0x0700fc00; |
2297 |
case 7: /* IEPSR */ |
2298 |
return xpsr_read(env) & 0x0700edff; |
2299 |
case 8: /* MSP */ |
2300 |
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; |
2301 |
case 9: /* PSP */ |
2302 |
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
2303 |
case 16: /* PRIMASK */ |
2304 |
return (env->uncached_cpsr & CPSR_I) != 0; |
2305 |
case 17: /* BASEPRI */ |
2306 |
case 18: /* BASEPRI_MAX */ |
2307 |
return env->v7m.basepri;
|
2308 |
case 19: /* FAULTMASK */ |
2309 |
return (env->uncached_cpsr & CPSR_F) != 0; |
2310 |
case 20: /* CONTROL */ |
2311 |
return env->v7m.control;
|
2312 |
default:
|
2313 |
/* ??? For debugging only. */
|
2314 |
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
|
2315 |
return 0; |
2316 |
} |
2317 |
} |
2318 |
|
2319 |
void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
2320 |
{ |
2321 |
switch (reg) {
|
2322 |
case 0: /* APSR */ |
2323 |
xpsr_write(env, val, 0xf8000000);
|
2324 |
break;
|
2325 |
case 1: /* IAPSR */ |
2326 |
xpsr_write(env, val, 0xf8000000);
|
2327 |
break;
|
2328 |
case 2: /* EAPSR */ |
2329 |
xpsr_write(env, val, 0xfe00fc00);
|
2330 |
break;
|
2331 |
case 3: /* xPSR */ |
2332 |
xpsr_write(env, val, 0xfe00fc00);
|
2333 |
break;
|
2334 |
case 5: /* IPSR */ |
2335 |
/* IPSR bits are readonly. */
|
2336 |
break;
|
2337 |
case 6: /* EPSR */ |
2338 |
xpsr_write(env, val, 0x0600fc00);
|
2339 |
break;
|
2340 |
case 7: /* IEPSR */ |
2341 |
xpsr_write(env, val, 0x0600fc00);
|
2342 |
break;
|
2343 |
case 8: /* MSP */ |
2344 |
if (env->v7m.current_sp)
|
2345 |
env->v7m.other_sp = val; |
2346 |
else
|
2347 |
env->regs[13] = val;
|
2348 |
break;
|
2349 |
case 9: /* PSP */ |
2350 |
if (env->v7m.current_sp)
|
2351 |
env->regs[13] = val;
|
2352 |
else
|
2353 |
env->v7m.other_sp = val; |
2354 |
break;
|
2355 |
case 16: /* PRIMASK */ |
2356 |
if (val & 1) |
2357 |
env->uncached_cpsr |= CPSR_I; |
2358 |
else
|
2359 |
env->uncached_cpsr &= ~CPSR_I; |
2360 |
break;
|
2361 |
case 17: /* BASEPRI */ |
2362 |
env->v7m.basepri = val & 0xff;
|
2363 |
break;
|
2364 |
case 18: /* BASEPRI_MAX */ |
2365 |
val &= 0xff;
|
2366 |
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) |
2367 |
env->v7m.basepri = val; |
2368 |
break;
|
2369 |
case 19: /* FAULTMASK */ |
2370 |
if (val & 1) |
2371 |
env->uncached_cpsr |= CPSR_F; |
2372 |
else
|
2373 |
env->uncached_cpsr &= ~CPSR_F; |
2374 |
break;
|
2375 |
case 20: /* CONTROL */ |
2376 |
env->v7m.control = val & 3;
|
2377 |
switch_v7m_sp(env, (val & 2) != 0); |
2378 |
break;
|
2379 |
default:
|
2380 |
/* ??? For debugging only. */
|
2381 |
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
|
2382 |
return;
|
2383 |
} |
2384 |
} |
2385 |
|
2386 |
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
2387 |
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
2388 |
void *opaque)
|
2389 |
{ |
2390 |
if (cpnum < 0 || cpnum > 14) { |
2391 |
cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
|
2392 |
return;
|
2393 |
} |
2394 |
|
2395 |
env->cp[cpnum].cp_read = cp_read; |
2396 |
env->cp[cpnum].cp_write = cp_write; |
2397 |
env->cp[cpnum].opaque = opaque; |
2398 |
} |
2399 |
|
2400 |
#endif
|
2401 |
|
2402 |
/* Note that signed overflow is undefined in C. The following routines are
|
2403 |
careful to use unsigned types where modulo arithmetic is required.
|
2404 |
Failure to do so _will_ break on newer gcc. */
|
2405 |
|
2406 |
/* Signed saturating arithmetic. */
|
2407 |
|
2408 |
/* Perform 16-bit signed saturating addition. */
|
2409 |
static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
2410 |
{ |
2411 |
uint16_t res; |
2412 |
|
2413 |
res = a + b; |
2414 |
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
2415 |
if (a & 0x8000) |
2416 |
res = 0x8000;
|
2417 |
else
|
2418 |
res = 0x7fff;
|
2419 |
} |
2420 |
return res;
|
2421 |
} |
2422 |
|
2423 |
/* Perform 8-bit signed saturating addition. */
|
2424 |
static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
2425 |
{ |
2426 |
uint8_t res; |
2427 |
|
2428 |
res = a + b; |
2429 |
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
2430 |
if (a & 0x80) |
2431 |
res = 0x80;
|
2432 |
else
|
2433 |
res = 0x7f;
|
2434 |
} |
2435 |
return res;
|
2436 |
} |
2437 |
|
2438 |
/* Perform 16-bit signed saturating subtraction. */
|
2439 |
static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
2440 |
{ |
2441 |
uint16_t res; |
2442 |
|
2443 |
res = a - b; |
2444 |
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
2445 |
if (a & 0x8000) |
2446 |
res = 0x8000;
|
2447 |
else
|
2448 |
res = 0x7fff;
|
2449 |
} |
2450 |
return res;
|
2451 |
} |
2452 |
|
2453 |
/* Perform 8-bit signed saturating subtraction. */
|
2454 |
static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
2455 |
{ |
2456 |
uint8_t res; |
2457 |
|
2458 |
res = a - b; |
2459 |
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
2460 |
if (a & 0x80) |
2461 |
res = 0x80;
|
2462 |
else
|
2463 |
res = 0x7f;
|
2464 |
} |
2465 |
return res;
|
2466 |
} |
2467 |
|
2468 |
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
2469 |
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
2470 |
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
2471 |
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
2472 |
#define PFX q
|
2473 |
|
2474 |
#include "op_addsub.h" |
2475 |
|
2476 |
/* Unsigned saturating arithmetic. */
|
2477 |
static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
2478 |
{ |
2479 |
uint16_t res; |
2480 |
res = a + b; |
2481 |
if (res < a)
|
2482 |
res = 0xffff;
|
2483 |
return res;
|
2484 |
} |
2485 |
|
2486 |
static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
2487 |
{ |
2488 |
if (a > b)
|
2489 |
return a - b;
|
2490 |
else
|
2491 |
return 0; |
2492 |
} |
2493 |
|
2494 |
static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
2495 |
{ |
2496 |
uint8_t res; |
2497 |
res = a + b; |
2498 |
if (res < a)
|
2499 |
res = 0xff;
|
2500 |
return res;
|
2501 |
} |
2502 |
|
2503 |
static inline uint8_t sub8_usat(uint8_t a, uint8_t b) |
2504 |
{ |
2505 |
if (a > b)
|
2506 |
return a - b;
|
2507 |
else
|
2508 |
return 0; |
2509 |
} |
2510 |
|
2511 |
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); |
2512 |
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); |
2513 |
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); |
2514 |
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); |
2515 |
#define PFX uq
|
2516 |
|
2517 |
#include "op_addsub.h" |
2518 |
|
2519 |
/* Signed modulo arithmetic. */
|
2520 |
#define SARITH16(a, b, n, op) do { \ |
2521 |
int32_t sum; \ |
2522 |
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
2523 |
RESULT(sum, n, 16); \
|
2524 |
if (sum >= 0) \ |
2525 |
ge |= 3 << (n * 2); \ |
2526 |
} while(0) |
2527 |
|
2528 |
#define SARITH8(a, b, n, op) do { \ |
2529 |
int32_t sum; \ |
2530 |
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
2531 |
RESULT(sum, n, 8); \
|
2532 |
if (sum >= 0) \ |
2533 |
ge |= 1 << n; \
|
2534 |
} while(0) |
2535 |
|
2536 |
|
2537 |
#define ADD16(a, b, n) SARITH16(a, b, n, +)
|
2538 |
#define SUB16(a, b, n) SARITH16(a, b, n, -)
|
2539 |
#define ADD8(a, b, n) SARITH8(a, b, n, +)
|
2540 |
#define SUB8(a, b, n) SARITH8(a, b, n, -)
|
2541 |
#define PFX s
|
2542 |
#define ARITH_GE
|
2543 |
|
2544 |
#include "op_addsub.h" |
2545 |
|
2546 |
/* Unsigned modulo arithmetic. */
|
2547 |
#define ADD16(a, b, n) do { \ |
2548 |
uint32_t sum; \ |
2549 |
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ |
2550 |
RESULT(sum, n, 16); \
|
2551 |
if ((sum >> 16) == 1) \ |
2552 |
ge |= 3 << (n * 2); \ |
2553 |
} while(0) |
2554 |
|
2555 |
#define ADD8(a, b, n) do { \ |
2556 |
uint32_t sum; \ |
2557 |
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ |
2558 |
RESULT(sum, n, 8); \
|
2559 |
if ((sum >> 8) == 1) \ |
2560 |
ge |= 1 << n; \
|
2561 |
} while(0) |
2562 |
|
2563 |
#define SUB16(a, b, n) do { \ |
2564 |
uint32_t sum; \ |
2565 |
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ |
2566 |
RESULT(sum, n, 16); \
|
2567 |
if ((sum >> 16) == 0) \ |
2568 |
ge |= 3 << (n * 2); \ |
2569 |
} while(0) |
2570 |
|
2571 |
#define SUB8(a, b, n) do { \ |
2572 |
uint32_t sum; \ |
2573 |
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ |
2574 |
RESULT(sum, n, 8); \
|
2575 |
if ((sum >> 8) == 0) \ |
2576 |
ge |= 1 << n; \
|
2577 |
} while(0) |
2578 |
|
2579 |
#define PFX u
|
2580 |
#define ARITH_GE
|
2581 |
|
2582 |
#include "op_addsub.h" |
2583 |
|
2584 |
/* Halved signed arithmetic. */
|
2585 |
#define ADD16(a, b, n) \
|
2586 |
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) |
2587 |
#define SUB16(a, b, n) \
|
2588 |
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) |
2589 |
#define ADD8(a, b, n) \
|
2590 |
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) |
2591 |
#define SUB8(a, b, n) \
|
2592 |
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) |
2593 |
#define PFX sh
|
2594 |
|
2595 |
#include "op_addsub.h" |
2596 |
|
2597 |
/* Halved unsigned arithmetic. */
|
2598 |
#define ADD16(a, b, n) \
|
2599 |
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2600 |
#define SUB16(a, b, n) \
|
2601 |
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2602 |
#define ADD8(a, b, n) \
|
2603 |
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2604 |
#define SUB8(a, b, n) \
|
2605 |
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2606 |
#define PFX uh
|
2607 |
|
2608 |
#include "op_addsub.h" |
2609 |
|
2610 |
static inline uint8_t do_usad(uint8_t a, uint8_t b) |
2611 |
{ |
2612 |
if (a > b)
|
2613 |
return a - b;
|
2614 |
else
|
2615 |
return b - a;
|
2616 |
} |
2617 |
|
2618 |
/* Unsigned sum of absolute byte differences. */
|
2619 |
uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
2620 |
{ |
2621 |
uint32_t sum; |
2622 |
sum = do_usad(a, b); |
2623 |
sum += do_usad(a >> 8, b >> 8); |
2624 |
sum += do_usad(a >> 16, b >>16); |
2625 |
sum += do_usad(a >> 24, b >> 24); |
2626 |
return sum;
|
2627 |
} |
2628 |
|
2629 |
/* For ARMv6 SEL instruction. */
|
2630 |
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) |
2631 |
{ |
2632 |
uint32_t mask; |
2633 |
|
2634 |
mask = 0;
|
2635 |
if (flags & 1) |
2636 |
mask |= 0xff;
|
2637 |
if (flags & 2) |
2638 |
mask |= 0xff00;
|
2639 |
if (flags & 4) |
2640 |
mask |= 0xff0000;
|
2641 |
if (flags & 8) |
2642 |
mask |= 0xff000000;
|
2643 |
return (a & mask) | (b & ~mask);
|
2644 |
} |
2645 |
|
2646 |
uint32_t HELPER(logicq_cc)(uint64_t val) |
2647 |
{ |
2648 |
return (val >> 32) | (val != 0); |
2649 |
} |
2650 |
|
2651 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
2652 |
Single precition routines have a "s" suffix, double precision a
|
2653 |
"d" suffix. */
|
2654 |
|
2655 |
/* Convert host exception flags to vfp form. */
|
2656 |
static inline int vfp_exceptbits_from_host(int host_bits) |
2657 |
{ |
2658 |
int target_bits = 0; |
2659 |
|
2660 |
if (host_bits & float_flag_invalid)
|
2661 |
target_bits |= 1;
|
2662 |
if (host_bits & float_flag_divbyzero)
|
2663 |
target_bits |= 2;
|
2664 |
if (host_bits & float_flag_overflow)
|
2665 |
target_bits |= 4;
|
2666 |
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
|
2667 |
target_bits |= 8;
|
2668 |
if (host_bits & float_flag_inexact)
|
2669 |
target_bits |= 0x10;
|
2670 |
if (host_bits & float_flag_input_denormal)
|
2671 |
target_bits |= 0x80;
|
2672 |
return target_bits;
|
2673 |
} |
2674 |
|
2675 |
uint32_t HELPER(vfp_get_fpscr)(CPUState *env) |
2676 |
{ |
2677 |
int i;
|
2678 |
uint32_t fpscr; |
2679 |
|
2680 |
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
|
2681 |
| (env->vfp.vec_len << 16)
|
2682 |
| (env->vfp.vec_stride << 20);
|
2683 |
i = get_float_exception_flags(&env->vfp.fp_status); |
2684 |
i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
2685 |
fpscr |= vfp_exceptbits_from_host(i); |
2686 |
return fpscr;
|
2687 |
} |
2688 |
|
2689 |
uint32_t vfp_get_fpscr(CPUState *env) |
2690 |
{ |
2691 |
return HELPER(vfp_get_fpscr)(env);
|
2692 |
} |
2693 |
|
2694 |
/* Convert vfp exception flags to target form. */
|
2695 |
static inline int vfp_exceptbits_to_host(int target_bits) |
2696 |
{ |
2697 |
int host_bits = 0; |
2698 |
|
2699 |
if (target_bits & 1) |
2700 |
host_bits |= float_flag_invalid; |
2701 |
if (target_bits & 2) |
2702 |
host_bits |= float_flag_divbyzero; |
2703 |
if (target_bits & 4) |
2704 |
host_bits |= float_flag_overflow; |
2705 |
if (target_bits & 8) |
2706 |
host_bits |= float_flag_underflow; |
2707 |
if (target_bits & 0x10) |
2708 |
host_bits |= float_flag_inexact; |
2709 |
if (target_bits & 0x80) |
2710 |
host_bits |= float_flag_input_denormal; |
2711 |
return host_bits;
|
2712 |
} |
2713 |
|
2714 |
void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
|
2715 |
{ |
2716 |
int i;
|
2717 |
uint32_t changed; |
2718 |
|
2719 |
changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
2720 |
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
|
2721 |
env->vfp.vec_len = (val >> 16) & 7; |
2722 |
env->vfp.vec_stride = (val >> 20) & 3; |
2723 |
|
2724 |
changed ^= val; |
2725 |
if (changed & (3 << 22)) { |
2726 |
i = (val >> 22) & 3; |
2727 |
switch (i) {
|
2728 |
case 0: |
2729 |
i = float_round_nearest_even; |
2730 |
break;
|
2731 |
case 1: |
2732 |
i = float_round_up; |
2733 |
break;
|
2734 |
case 2: |
2735 |
i = float_round_down; |
2736 |
break;
|
2737 |
case 3: |
2738 |
i = float_round_to_zero; |
2739 |
break;
|
2740 |
} |
2741 |
set_float_rounding_mode(i, &env->vfp.fp_status); |
2742 |
} |
2743 |
if (changed & (1 << 24)) { |
2744 |
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2745 |
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2746 |
} |
2747 |
if (changed & (1 << 25)) |
2748 |
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); |
2749 |
|
2750 |
i = vfp_exceptbits_to_host(val); |
2751 |
set_float_exception_flags(i, &env->vfp.fp_status); |
2752 |
set_float_exception_flags(0, &env->vfp.standard_fp_status);
|
2753 |
} |
2754 |
|
2755 |
void vfp_set_fpscr(CPUState *env, uint32_t val)
|
2756 |
{ |
2757 |
HELPER(vfp_set_fpscr)(env, val); |
2758 |
} |
2759 |
|
2760 |
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
|
2761 |
|
2762 |
#define VFP_BINOP(name) \
|
2763 |
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
|
2764 |
{ \ |
2765 |
float_status *fpst = fpstp; \ |
2766 |
return float32_ ## name(a, b, fpst); \ |
2767 |
} \ |
2768 |
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
|
2769 |
{ \ |
2770 |
float_status *fpst = fpstp; \ |
2771 |
return float64_ ## name(a, b, fpst); \ |
2772 |
} |
2773 |
VFP_BINOP(add) |
2774 |
VFP_BINOP(sub) |
2775 |
VFP_BINOP(mul) |
2776 |
VFP_BINOP(div) |
2777 |
#undef VFP_BINOP
|
2778 |
|
2779 |
float32 VFP_HELPER(neg, s)(float32 a) |
2780 |
{ |
2781 |
return float32_chs(a);
|
2782 |
} |
2783 |
|
2784 |
float64 VFP_HELPER(neg, d)(float64 a) |
2785 |
{ |
2786 |
return float64_chs(a);
|
2787 |
} |
2788 |
|
2789 |
float32 VFP_HELPER(abs, s)(float32 a) |
2790 |
{ |
2791 |
return float32_abs(a);
|
2792 |
} |
2793 |
|
2794 |
float64 VFP_HELPER(abs, d)(float64 a) |
2795 |
{ |
2796 |
return float64_abs(a);
|
2797 |
} |
2798 |
|
2799 |
float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env) |
2800 |
{ |
2801 |
return float32_sqrt(a, &env->vfp.fp_status);
|
2802 |
} |
2803 |
|
2804 |
float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env) |
2805 |
{ |
2806 |
return float64_sqrt(a, &env->vfp.fp_status);
|
2807 |
} |
2808 |
|
2809 |
/* XXX: check quiet/signaling case */
|
2810 |
#define DO_VFP_cmp(p, type) \
|
2811 |
void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
|
2812 |
{ \ |
2813 |
uint32_t flags; \ |
2814 |
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ |
2815 |
case 0: flags = 0x6; break; \ |
2816 |
case -1: flags = 0x8; break; \ |
2817 |
case 1: flags = 0x2; break; \ |
2818 |
default: case 2: flags = 0x3; break; \ |
2819 |
} \ |
2820 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2821 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2822 |
} \ |
2823 |
void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
|
2824 |
{ \ |
2825 |
uint32_t flags; \ |
2826 |
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ |
2827 |
case 0: flags = 0x6; break; \ |
2828 |
case -1: flags = 0x8; break; \ |
2829 |
case 1: flags = 0x2; break; \ |
2830 |
default: case 2: flags = 0x3; break; \ |
2831 |
} \ |
2832 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2833 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2834 |
} |
2835 |
DO_VFP_cmp(s, float32) |
2836 |
DO_VFP_cmp(d, float64) |
2837 |
#undef DO_VFP_cmp
|
2838 |
|
2839 |
/* Integer to float and float to integer conversions */
|
2840 |
|
2841 |
#define CONV_ITOF(name, fsz, sign) \
|
2842 |
float##fsz HELPER(name)(uint32_t x, void *fpstp) \ |
2843 |
{ \ |
2844 |
float_status *fpst = fpstp; \ |
2845 |
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
2846 |
} |
2847 |
|
2848 |
#define CONV_FTOI(name, fsz, sign, round) \
|
2849 |
uint32_t HELPER(name)(float##fsz x, void *fpstp) \ |
2850 |
{ \ |
2851 |
float_status *fpst = fpstp; \ |
2852 |
if (float##fsz##_is_any_nan(x)) { \ |
2853 |
float_raise(float_flag_invalid, fpst); \ |
2854 |
return 0; \ |
2855 |
} \ |
2856 |
return float##fsz##_to_##sign##int32##round(x, fpst); \ |
2857 |
} |
2858 |
|
2859 |
#define FLOAT_CONVS(name, p, fsz, sign) \
|
2860 |
CONV_ITOF(vfp_##name##to##p, fsz, sign) \ |
2861 |
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ |
2862 |
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) |
2863 |
|
2864 |
FLOAT_CONVS(si, s, 32, )
|
2865 |
FLOAT_CONVS(si, d, 64, )
|
2866 |
FLOAT_CONVS(ui, s, 32, u)
|
2867 |
FLOAT_CONVS(ui, d, 64, u)
|
2868 |
|
2869 |
#undef CONV_ITOF
|
2870 |
#undef CONV_FTOI
|
2871 |
#undef FLOAT_CONVS
|
2872 |
|
2873 |
/* floating point conversion */
|
2874 |
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) |
2875 |
{ |
2876 |
float64 r = float32_to_float64(x, &env->vfp.fp_status); |
2877 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
2878 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
2879 |
*/
|
2880 |
return float64_maybe_silence_nan(r);
|
2881 |
} |
2882 |
|
2883 |
float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) |
2884 |
{ |
2885 |
float32 r = float64_to_float32(x, &env->vfp.fp_status); |
2886 |
/* ARM requires that S<->D conversion of any kind of NaN generates
|
2887 |
* a quiet NaN by forcing the most significant frac bit to 1.
|
2888 |
*/
|
2889 |
return float32_maybe_silence_nan(r);
|
2890 |
} |
2891 |
|
2892 |
/* VFP3 fixed point conversion. */
|
2893 |
#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
|
2894 |
float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \ |
2895 |
void *fpstp) \
|
2896 |
{ \ |
2897 |
float_status *fpst = fpstp; \ |
2898 |
float##fsz tmp; \ |
2899 |
tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \ |
2900 |
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
2901 |
} \ |
2902 |
uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \ |
2903 |
void *fpstp) \
|
2904 |
{ \ |
2905 |
float_status *fpst = fpstp; \ |
2906 |
float##fsz tmp; \ |
2907 |
if (float##fsz##_is_any_nan(x)) { \ |
2908 |
float_raise(float_flag_invalid, fpst); \ |
2909 |
return 0; \ |
2910 |
} \ |
2911 |
tmp = float##fsz##_scalbn(x, shift, fpst); \ |
2912 |
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \ |
2913 |
} |
2914 |
|
2915 |
VFP_CONV_FIX(sh, d, 64, int16, )
|
2916 |
VFP_CONV_FIX(sl, d, 64, int32, )
|
2917 |
VFP_CONV_FIX(uh, d, 64, uint16, u)
|
2918 |
VFP_CONV_FIX(ul, d, 64, uint32, u)
|
2919 |
VFP_CONV_FIX(sh, s, 32, int16, )
|
2920 |
VFP_CONV_FIX(sl, s, 32, int32, )
|
2921 |
VFP_CONV_FIX(uh, s, 32, uint16, u)
|
2922 |
VFP_CONV_FIX(ul, s, 32, uint32, u)
|
2923 |
#undef VFP_CONV_FIX
|
2924 |
|
2925 |
/* Half precision conversions. */
|
2926 |
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
|
2927 |
{ |
2928 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2929 |
float32 r = float16_to_float32(make_float16(a), ieee, s); |
2930 |
if (ieee) {
|
2931 |
return float32_maybe_silence_nan(r);
|
2932 |
} |
2933 |
return r;
|
2934 |
} |
2935 |
|
2936 |
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
|
2937 |
{ |
2938 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2939 |
float16 r = float32_to_float16(a, ieee, s); |
2940 |
if (ieee) {
|
2941 |
r = float16_maybe_silence_nan(r); |
2942 |
} |
2943 |
return float16_val(r);
|
2944 |
} |
2945 |
|
2946 |
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env) |
2947 |
{ |
2948 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
|
2949 |
} |
2950 |
|
2951 |
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env) |
2952 |
{ |
2953 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
|
2954 |
} |
2955 |
|
2956 |
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env) |
2957 |
{ |
2958 |
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
|
2959 |
} |
2960 |
|
2961 |
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) |
2962 |
{ |
2963 |
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
|
2964 |
} |
2965 |
|
2966 |
#define float32_two make_float32(0x40000000) |
2967 |
#define float32_three make_float32(0x40400000) |
2968 |
#define float32_one_point_five make_float32(0x3fc00000) |
2969 |
|
2970 |
float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) |
2971 |
{ |
2972 |
float_status *s = &env->vfp.standard_fp_status; |
2973 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
2974 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { |
2975 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
2976 |
float_raise(float_flag_input_denormal, s); |
2977 |
} |
2978 |
return float32_two;
|
2979 |
} |
2980 |
return float32_sub(float32_two, float32_mul(a, b, s), s);
|
2981 |
} |
2982 |
|
2983 |
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env) |
2984 |
{ |
2985 |
float_status *s = &env->vfp.standard_fp_status; |
2986 |
float32 product; |
2987 |
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
2988 |
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { |
2989 |
if (!(float32_is_zero(a) || float32_is_zero(b))) {
|
2990 |
float_raise(float_flag_input_denormal, s); |
2991 |
} |
2992 |
return float32_one_point_five;
|
2993 |
} |
2994 |
product = float32_mul(a, b, s); |
2995 |
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
|
2996 |
} |
2997 |
|
2998 |
/* NEON helpers. */
|
2999 |
|
3000 |
/* Constants 256 and 512 are used in some helpers; we avoid relying on
|
3001 |
* int->float conversions at run-time. */
|
3002 |
#define float64_256 make_float64(0x4070000000000000LL) |
3003 |
#define float64_512 make_float64(0x4080000000000000LL) |
3004 |
|
3005 |
/* The algorithm that must be used to calculate the estimate
|
3006 |
* is specified by the ARM ARM.
|
3007 |
*/
|
3008 |
static float64 recip_estimate(float64 a, CPUState *env)
|
3009 |
{ |
3010 |
/* These calculations mustn't set any fp exception flags,
|
3011 |
* so we use a local copy of the fp_status.
|
3012 |
*/
|
3013 |
float_status dummy_status = env->vfp.standard_fp_status; |
3014 |
float_status *s = &dummy_status; |
3015 |
/* q = (int)(a * 512.0) */
|
3016 |
float64 q = float64_mul(float64_512, a, s); |
3017 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
3018 |
|
3019 |
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
|
3020 |
q = int64_to_float64(q_int, s); |
3021 |
q = float64_add(q, float64_half, s); |
3022 |
q = float64_div(q, float64_512, s); |
3023 |
q = float64_div(float64_one, q, s); |
3024 |
|
3025 |
/* s = (int)(256.0 * r + 0.5) */
|
3026 |
q = float64_mul(q, float64_256, s); |
3027 |
q = float64_add(q, float64_half, s); |
3028 |
q_int = float64_to_int64_round_to_zero(q, s); |
3029 |
|
3030 |
/* return (double)s / 256.0 */
|
3031 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
3032 |
} |
3033 |
|
3034 |
float32 HELPER(recpe_f32)(float32 a, CPUState *env) |
3035 |
{ |
3036 |
float_status *s = &env->vfp.standard_fp_status; |
3037 |
float64 f64; |
3038 |
uint32_t val32 = float32_val(a); |
3039 |
|
3040 |
int result_exp;
|
3041 |
int a_exp = (val32 & 0x7f800000) >> 23; |
3042 |
int sign = val32 & 0x80000000; |
3043 |
|
3044 |
if (float32_is_any_nan(a)) {
|
3045 |
if (float32_is_signaling_nan(a)) {
|
3046 |
float_raise(float_flag_invalid, s); |
3047 |
} |
3048 |
return float32_default_nan;
|
3049 |
} else if (float32_is_infinity(a)) { |
3050 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
3051 |
} else if (float32_is_zero_or_denormal(a)) { |
3052 |
if (!float32_is_zero(a)) {
|
3053 |
float_raise(float_flag_input_denormal, s); |
3054 |
} |
3055 |
float_raise(float_flag_divbyzero, s); |
3056 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
3057 |
} else if (a_exp >= 253) { |
3058 |
float_raise(float_flag_underflow, s); |
3059 |
return float32_set_sign(float32_zero, float32_is_neg(a));
|
3060 |
} |
3061 |
|
3062 |
f64 = make_float64((0x3feULL << 52) |
3063 |
| ((int64_t)(val32 & 0x7fffff) << 29)); |
3064 |
|
3065 |
result_exp = 253 - a_exp;
|
3066 |
|
3067 |
f64 = recip_estimate(f64, env); |
3068 |
|
3069 |
val32 = sign |
3070 |
| ((result_exp & 0xff) << 23) |
3071 |
| ((float64_val(f64) >> 29) & 0x7fffff); |
3072 |
return make_float32(val32);
|
3073 |
} |
3074 |
|
3075 |
/* The algorithm that must be used to calculate the estimate
|
3076 |
* is specified by the ARM ARM.
|
3077 |
*/
|
3078 |
static float64 recip_sqrt_estimate(float64 a, CPUState *env)
|
3079 |
{ |
3080 |
/* These calculations mustn't set any fp exception flags,
|
3081 |
* so we use a local copy of the fp_status.
|
3082 |
*/
|
3083 |
float_status dummy_status = env->vfp.standard_fp_status; |
3084 |
float_status *s = &dummy_status; |
3085 |
float64 q; |
3086 |
int64_t q_int; |
3087 |
|
3088 |
if (float64_lt(a, float64_half, s)) {
|
3089 |
/* range 0.25 <= a < 0.5 */
|
3090 |
|
3091 |
/* a in units of 1/512 rounded down */
|
3092 |
/* q0 = (int)(a * 512.0); */
|
3093 |
q = float64_mul(float64_512, a, s); |
3094 |
q_int = float64_to_int64_round_to_zero(q, s); |
3095 |
|
3096 |
/* reciprocal root r */
|
3097 |
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
|
3098 |
q = int64_to_float64(q_int, s); |
3099 |
q = float64_add(q, float64_half, s); |
3100 |
q = float64_div(q, float64_512, s); |
3101 |
q = float64_sqrt(q, s); |
3102 |
q = float64_div(float64_one, q, s); |
3103 |
} else {
|
3104 |
/* range 0.5 <= a < 1.0 */
|
3105 |
|
3106 |
/* a in units of 1/256 rounded down */
|
3107 |
/* q1 = (int)(a * 256.0); */
|
3108 |
q = float64_mul(float64_256, a, s); |
3109 |
int64_t q_int = float64_to_int64_round_to_zero(q, s); |
3110 |
|
3111 |
/* reciprocal root r */
|
3112 |
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
|
3113 |
q = int64_to_float64(q_int, s); |
3114 |
q = float64_add(q, float64_half, s); |
3115 |
q = float64_div(q, float64_256, s); |
3116 |
q = float64_sqrt(q, s); |
3117 |
q = float64_div(float64_one, q, s); |
3118 |
} |
3119 |
/* r in units of 1/256 rounded to nearest */
|
3120 |
/* s = (int)(256.0 * r + 0.5); */
|
3121 |
|
3122 |
q = float64_mul(q, float64_256,s ); |
3123 |
q = float64_add(q, float64_half, s); |
3124 |
q_int = float64_to_int64_round_to_zero(q, s); |
3125 |
|
3126 |
/* return (double)s / 256.0;*/
|
3127 |
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
3128 |
} |
3129 |
|
3130 |
float32 HELPER(rsqrte_f32)(float32 a, CPUState *env) |
3131 |
{ |
3132 |
float_status *s = &env->vfp.standard_fp_status; |
3133 |
int result_exp;
|
3134 |
float64 f64; |
3135 |
uint32_t val; |
3136 |
uint64_t val64; |
3137 |
|
3138 |
val = float32_val(a); |
3139 |
|
3140 |
if (float32_is_any_nan(a)) {
|
3141 |
if (float32_is_signaling_nan(a)) {
|
3142 |
float_raise(float_flag_invalid, s); |
3143 |
} |
3144 |
return float32_default_nan;
|
3145 |
} else if (float32_is_zero_or_denormal(a)) { |
3146 |
if (!float32_is_zero(a)) {
|
3147 |
float_raise(float_flag_input_denormal, s); |
3148 |
} |
3149 |
float_raise(float_flag_divbyzero, s); |
3150 |
return float32_set_sign(float32_infinity, float32_is_neg(a));
|
3151 |
} else if (float32_is_neg(a)) { |
3152 |
float_raise(float_flag_invalid, s); |
3153 |
return float32_default_nan;
|
3154 |
} else if (float32_is_infinity(a)) { |
3155 |
return float32_zero;
|
3156 |
} |
3157 |
|
3158 |
/* Normalize to a double-precision value between 0.25 and 1.0,
|
3159 |
* preserving the parity of the exponent. */
|
3160 |
if ((val & 0x800000) == 0) { |
3161 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
3162 |
| (0x3feULL << 52) |
3163 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
3164 |
} else {
|
3165 |
f64 = make_float64(((uint64_t)(val & 0x80000000) << 32) |
3166 |
| (0x3fdULL << 52) |
3167 |
| ((uint64_t)(val & 0x7fffff) << 29)); |
3168 |
} |
3169 |
|
3170 |
result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2; |
3171 |
|
3172 |
f64 = recip_sqrt_estimate(f64, env); |
3173 |
|
3174 |
val64 = float64_val(f64); |
3175 |
|
3176 |
val = ((result_exp & 0xff) << 23) |
3177 |
| ((val64 >> 29) & 0x7fffff); |
3178 |
return make_float32(val);
|
3179 |
} |
3180 |
|
3181 |
uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env) |
3182 |
{ |
3183 |
float64 f64; |
3184 |
|
3185 |
if ((a & 0x80000000) == 0) { |
3186 |
return 0xffffffff; |
3187 |
} |
3188 |
|
3189 |
f64 = make_float64((0x3feULL << 52) |
3190 |
| ((int64_t)(a & 0x7fffffff) << 21)); |
3191 |
|
3192 |
f64 = recip_estimate (f64, env); |
3193 |
|
3194 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
3195 |
} |
3196 |
|
3197 |
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) |
3198 |
{ |
3199 |
float64 f64; |
3200 |
|
3201 |
if ((a & 0xc0000000) == 0) { |
3202 |
return 0xffffffff; |
3203 |
} |
3204 |
|
3205 |
if (a & 0x80000000) { |
3206 |
f64 = make_float64((0x3feULL << 52) |
3207 |
| ((uint64_t)(a & 0x7fffffff) << 21)); |
3208 |
} else { /* bits 31-30 == '01' */ |
3209 |
f64 = make_float64((0x3fdULL << 52) |
3210 |
| ((uint64_t)(a & 0x3fffffff) << 22)); |
3211 |
} |
3212 |
|
3213 |
f64 = recip_sqrt_estimate(f64, env); |
3214 |
|
3215 |
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); |
3216 |
} |
3217 |
|
3218 |
/* VFPv4 fused multiply-accumulate */
|
3219 |
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
|
3220 |
{ |
3221 |
float_status *fpst = fpstp; |
3222 |
return float32_muladd(a, b, c, 0, fpst); |
3223 |
} |
3224 |
|
3225 |
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
|
3226 |
{ |
3227 |
float_status *fpst = fpstp; |
3228 |
return float64_muladd(a, b, c, 0, fpst); |
3229 |
} |
3230 |
|
3231 |
void HELPER(set_teecr)(CPUState *env, uint32_t val)
|
3232 |
{ |
3233 |
val &= 1;
|
3234 |
if (env->teecr != val) {
|
3235 |
env->teecr = val; |
3236 |
tb_flush(env); |
3237 |
} |
3238 |
} |