root / hw / exynos4210.c @ 0b7ade1d
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1 | 0caa7113 | Evgeny Voevodin | /*
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2 | 0caa7113 | Evgeny Voevodin | * Samsung exynos4210 SoC emulation
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3 | 0caa7113 | Evgeny Voevodin | *
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4 | 0caa7113 | Evgeny Voevodin | * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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5 | 0caa7113 | Evgeny Voevodin | * Maksim Kozlov <m.kozlov@samsung.com>
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6 | 0caa7113 | Evgeny Voevodin | * Evgeny Voevodin <e.voevodin@samsung.com>
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7 | 0caa7113 | Evgeny Voevodin | * Igor Mitsyanko <i.mitsyanko@samsung.com>
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8 | 0caa7113 | Evgeny Voevodin | *
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9 | 0caa7113 | Evgeny Voevodin | * This program is free software; you can redistribute it and/or modify it
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10 | 0caa7113 | Evgeny Voevodin | * under the terms of the GNU General Public License as published by the
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11 | 0caa7113 | Evgeny Voevodin | * Free Software Foundation; either version 2 of the License, or
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12 | 0caa7113 | Evgeny Voevodin | * (at your option) any later version.
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13 | 0caa7113 | Evgeny Voevodin | *
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14 | 0caa7113 | Evgeny Voevodin | * This program is distributed in the hope that it will be useful, but WITHOUT
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15 | 0caa7113 | Evgeny Voevodin | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 | 0caa7113 | Evgeny Voevodin | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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17 | 0caa7113 | Evgeny Voevodin | * for more details.
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18 | 0caa7113 | Evgeny Voevodin | *
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19 | 0caa7113 | Evgeny Voevodin | * You should have received a copy of the GNU General Public License along
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20 | 0caa7113 | Evgeny Voevodin | * with this program; if not, see <http://www.gnu.org/licenses/>.
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21 | 0caa7113 | Evgeny Voevodin | *
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22 | 0caa7113 | Evgeny Voevodin | */
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23 | 0caa7113 | Evgeny Voevodin | |
24 | 0caa7113 | Evgeny Voevodin | #include "boards.h" |
25 | 0caa7113 | Evgeny Voevodin | #include "sysemu.h" |
26 | 0caa7113 | Evgeny Voevodin | #include "sysbus.h" |
27 | 0caa7113 | Evgeny Voevodin | #include "arm-misc.h" |
28 | 0caa7113 | Evgeny Voevodin | #include "exynos4210.h" |
29 | 0caa7113 | Evgeny Voevodin | |
30 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_CHIPID_ADDR 0x10000000 |
31 | 0caa7113 | Evgeny Voevodin | |
32 | 62db8bf3 | Evgeny Voevodin | /* PWM */
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33 | 62db8bf3 | Evgeny Voevodin | #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 |
34 | 62db8bf3 | Evgeny Voevodin | |
35 | 12c775db | Evgeny Voevodin | /* MCT */
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36 | 12c775db | Evgeny Voevodin | #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 |
37 | 12c775db | Evgeny Voevodin | |
38 | e5a4914e | Maksim Kozlov | /* UART's definitions */
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39 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 |
40 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 |
41 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 |
42 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 |
43 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART0_FIFO_SIZE 256 |
44 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART1_FIFO_SIZE 64 |
45 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART2_FIFO_SIZE 16 |
46 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART3_FIFO_SIZE 16 |
47 | e5a4914e | Maksim Kozlov | /* Interrupt Group of External Interrupt Combiner for UART */
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48 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART_INT_GRP 26 |
49 | e5a4914e | Maksim Kozlov | |
50 | 0caa7113 | Evgeny Voevodin | /* External GIC */
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51 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 |
52 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 |
53 | 0caa7113 | Evgeny Voevodin | |
54 | 0caa7113 | Evgeny Voevodin | /* Combiner */
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55 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 |
56 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 |
57 | 0caa7113 | Evgeny Voevodin | |
58 | df91b48f | Maksim Kozlov | /* PMU SFR base address */
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59 | df91b48f | Maksim Kozlov | #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 |
60 | df91b48f | Maksim Kozlov | |
61 | 30628cb1 | Mitsyanko Igor | /* Display controllers (FIMD) */
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62 | 30628cb1 | Mitsyanko Igor | #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 |
63 | 30628cb1 | Mitsyanko Igor | |
64 | 0caa7113 | Evgeny Voevodin | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
65 | 0caa7113 | Evgeny Voevodin | 0x09, 0x00, 0x00, 0x00 }; |
66 | 0caa7113 | Evgeny Voevodin | |
67 | 0caa7113 | Evgeny Voevodin | Exynos4210State *exynos4210_init(MemoryRegion *system_mem, |
68 | 0caa7113 | Evgeny Voevodin | unsigned long ram_size) |
69 | 0caa7113 | Evgeny Voevodin | { |
70 | 0caa7113 | Evgeny Voevodin | qemu_irq cpu_irq[4];
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71 | 0caa7113 | Evgeny Voevodin | int n;
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72 | 0caa7113 | Evgeny Voevodin | Exynos4210State *s = g_new(Exynos4210State, 1);
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73 | 0caa7113 | Evgeny Voevodin | qemu_irq *irqp; |
74 | 0caa7113 | Evgeny Voevodin | qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS]; |
75 | 0caa7113 | Evgeny Voevodin | unsigned long mem_size; |
76 | 0caa7113 | Evgeny Voevodin | DeviceState *dev; |
77 | 0caa7113 | Evgeny Voevodin | SysBusDevice *busdev; |
78 | 0caa7113 | Evgeny Voevodin | |
79 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
80 | 0caa7113 | Evgeny Voevodin | s->env[n] = cpu_init("cortex-a9");
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81 | 0caa7113 | Evgeny Voevodin | if (!s->env[n]) {
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82 | 0caa7113 | Evgeny Voevodin | fprintf(stderr, "Unable to find CPU %d definition\n", n);
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83 | 0caa7113 | Evgeny Voevodin | exit(1);
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84 | 0caa7113 | Evgeny Voevodin | } |
85 | 0caa7113 | Evgeny Voevodin | /* Create PIC controller for each processor instance */
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86 | 0caa7113 | Evgeny Voevodin | irqp = arm_pic_init_cpu(s->env[n]); |
87 | 0caa7113 | Evgeny Voevodin | |
88 | 0caa7113 | Evgeny Voevodin | /*
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89 | 0caa7113 | Evgeny Voevodin | * Get GICs gpio_in cpu_irq to connect a combiner to them later.
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90 | 0caa7113 | Evgeny Voevodin | * Use only IRQ for a while.
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91 | 0caa7113 | Evgeny Voevodin | */
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92 | 0caa7113 | Evgeny Voevodin | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
93 | 0caa7113 | Evgeny Voevodin | } |
94 | 0caa7113 | Evgeny Voevodin | |
95 | 0caa7113 | Evgeny Voevodin | /*** IRQs ***/
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96 | 0caa7113 | Evgeny Voevodin | |
97 | 0caa7113 | Evgeny Voevodin | s->irq_table = exynos4210_init_irq(&s->irqs); |
98 | 0caa7113 | Evgeny Voevodin | |
99 | 0caa7113 | Evgeny Voevodin | /* IRQ Gate */
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100 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.irq_gate"); |
101 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
102 | 0caa7113 | Evgeny Voevodin | /* Get IRQ Gate input in gate_irq */
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103 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { |
104 | 0caa7113 | Evgeny Voevodin | gate_irq[n] = qdev_get_gpio_in(dev, n); |
105 | 0caa7113 | Evgeny Voevodin | } |
106 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
107 | 0caa7113 | Evgeny Voevodin | /* Connect IRQ Gate output to cpu_irq */
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108 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
109 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
110 | 0caa7113 | Evgeny Voevodin | } |
111 | 0caa7113 | Evgeny Voevodin | |
112 | 0caa7113 | Evgeny Voevodin | /* Private memory region and Internal GIC */
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113 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "a9mpcore_priv"); |
114 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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115 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
116 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
117 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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118 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
119 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, gate_irq[n * 2]);
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120 | 0caa7113 | Evgeny Voevodin | } |
121 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { |
122 | 0caa7113 | Evgeny Voevodin | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); |
123 | 0caa7113 | Evgeny Voevodin | } |
124 | 0caa7113 | Evgeny Voevodin | |
125 | 0caa7113 | Evgeny Voevodin | /* Cache controller */
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126 | 0caa7113 | Evgeny Voevodin | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); |
127 | 0caa7113 | Evgeny Voevodin | |
128 | 0caa7113 | Evgeny Voevodin | /* External GIC */
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129 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.gic"); |
130 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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131 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
132 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
133 | 0caa7113 | Evgeny Voevodin | /* Map CPU interface */
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134 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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135 | 0caa7113 | Evgeny Voevodin | /* Map Distributer interface */
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136 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
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137 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
138 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]); |
139 | 0caa7113 | Evgeny Voevodin | } |
140 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { |
141 | 0caa7113 | Evgeny Voevodin | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); |
142 | 0caa7113 | Evgeny Voevodin | } |
143 | 0caa7113 | Evgeny Voevodin | |
144 | 0caa7113 | Evgeny Voevodin | /* Internal Interrupt Combiner */
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145 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.combiner"); |
146 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
147 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
148 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
149 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); |
150 | 0caa7113 | Evgeny Voevodin | } |
151 | 0caa7113 | Evgeny Voevodin | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
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152 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
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153 | 0caa7113 | Evgeny Voevodin | |
154 | 0caa7113 | Evgeny Voevodin | /* External Interrupt Combiner */
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155 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.combiner"); |
156 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "external", 1); |
157 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
158 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
159 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
160 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); |
161 | 0caa7113 | Evgeny Voevodin | } |
162 | 0caa7113 | Evgeny Voevodin | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
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163 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
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164 | 0caa7113 | Evgeny Voevodin | |
165 | 0caa7113 | Evgeny Voevodin | /* Initialize board IRQs. */
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166 | 0caa7113 | Evgeny Voevodin | exynos4210_init_board_irqs(&s->irqs); |
167 | 0caa7113 | Evgeny Voevodin | |
168 | 0caa7113 | Evgeny Voevodin | /*** Memory ***/
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169 | 0caa7113 | Evgeny Voevodin | |
170 | 0caa7113 | Evgeny Voevodin | /* Chip-ID and OMR */
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171 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
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172 | 0caa7113 | Evgeny Voevodin | sizeof(chipid_and_omr), chipid_and_omr);
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173 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->chipid_mem, true);
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174 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, |
175 | 0caa7113 | Evgeny Voevodin | &s->chipid_mem); |
176 | 0caa7113 | Evgeny Voevodin | |
177 | 0caa7113 | Evgeny Voevodin | /* Internal ROM */
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178 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
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179 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IROM_SIZE); |
180 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->irom_mem, true);
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181 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, |
182 | 0caa7113 | Evgeny Voevodin | &s->irom_mem); |
183 | 0caa7113 | Evgeny Voevodin | /* mirror of iROM */
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184 | 0caa7113 | Evgeny Voevodin | memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
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185 | 0caa7113 | Evgeny Voevodin | &s->irom_mem, |
186 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IROM_BASE_ADDR, |
187 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IROM_SIZE); |
188 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->irom_alias_mem, true);
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189 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, |
190 | 0caa7113 | Evgeny Voevodin | &s->irom_alias_mem); |
191 | 0caa7113 | Evgeny Voevodin | |
192 | 0caa7113 | Evgeny Voevodin | /* Internal RAM */
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193 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
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194 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IRAM_SIZE); |
195 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->iram_mem); |
196 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, |
197 | 0caa7113 | Evgeny Voevodin | &s->iram_mem); |
198 | 0caa7113 | Evgeny Voevodin | |
199 | 0caa7113 | Evgeny Voevodin | /* DRAM */
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200 | 0caa7113 | Evgeny Voevodin | mem_size = ram_size; |
201 | 0caa7113 | Evgeny Voevodin | if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
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202 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
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203 | 0caa7113 | Evgeny Voevodin | mem_size - EXYNOS4210_DRAM_MAX_SIZE); |
204 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->dram1_mem); |
205 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, |
206 | 0caa7113 | Evgeny Voevodin | &s->dram1_mem); |
207 | 0caa7113 | Evgeny Voevodin | mem_size = EXYNOS4210_DRAM_MAX_SIZE; |
208 | 0caa7113 | Evgeny Voevodin | } |
209 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
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210 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->dram0_mem); |
211 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, |
212 | 0caa7113 | Evgeny Voevodin | &s->dram0_mem); |
213 | 0caa7113 | Evgeny Voevodin | |
214 | df91b48f | Maksim Kozlov | /* PMU.
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215 | df91b48f | Maksim Kozlov | * The only reason of existence at the moment is that secondary CPU boot
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216 | df91b48f | Maksim Kozlov | * loader uses PMU INFORM5 register as a holding pen.
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217 | df91b48f | Maksim Kozlov | */
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218 | df91b48f | Maksim Kozlov | sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); |
219 | df91b48f | Maksim Kozlov | |
220 | 62db8bf3 | Evgeny Voevodin | /* PWM */
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221 | 62db8bf3 | Evgeny Voevodin | sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
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222 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 0)], |
223 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 1)], |
224 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 2)], |
225 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 3)], |
226 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 4)], |
227 | 62db8bf3 | Evgeny Voevodin | NULL);
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228 | 62db8bf3 | Evgeny Voevodin | |
229 | 12c775db | Evgeny Voevodin | /* Multi Core Timer */
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230 | 12c775db | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.mct"); |
231 | 12c775db | Evgeny Voevodin | qdev_init_nofail(dev); |
232 | 12c775db | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
233 | 12c775db | Evgeny Voevodin | for (n = 0; n < 4; n++) { |
234 | 12c775db | Evgeny Voevodin | /* Connect global timer interrupts to Combiner gpio_in */
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235 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, n, |
236 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(1, 4 + n)]); |
237 | 12c775db | Evgeny Voevodin | } |
238 | 12c775db | Evgeny Voevodin | /* Connect local timer interrupts to Combiner gpio_in */
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239 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, 4,
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240 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(51, 0)]); |
241 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, 5,
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242 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(35, 3)]); |
243 | 12c775db | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
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244 | 12c775db | Evgeny Voevodin | |
245 | e5a4914e | Maksim Kozlov | /*** UARTs ***/
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246 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, |
247 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, |
248 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
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249 | e5a4914e | Maksim Kozlov | |
250 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, |
251 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, |
252 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
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253 | e5a4914e | Maksim Kozlov | |
254 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, |
255 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, |
256 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
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257 | e5a4914e | Maksim Kozlov | |
258 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, |
259 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, |
260 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
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261 | e5a4914e | Maksim Kozlov | |
262 | 30628cb1 | Mitsyanko Igor | /*** Display controller (FIMD) ***/
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263 | 30628cb1 | Mitsyanko Igor | sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
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264 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 0)], |
265 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 1)], |
266 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 2)], |
267 | 30628cb1 | Mitsyanko Igor | NULL);
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268 | 30628cb1 | Mitsyanko Igor | |
269 | 0caa7113 | Evgeny Voevodin | return s;
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270 | 0caa7113 | Evgeny Voevodin | } |