root / hw / lm32_timer.c @ 0b7ade1d
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1 | ea7924dc | Michael Walle | /*
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2 | ea7924dc | Michael Walle | * QEMU model of the LatticeMico32 timer block.
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3 | ea7924dc | Michael Walle | *
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4 | ea7924dc | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | ea7924dc | Michael Walle | *
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6 | ea7924dc | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | ea7924dc | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | ea7924dc | Michael Walle | * License as published by the Free Software Foundation; either
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9 | ea7924dc | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | ea7924dc | Michael Walle | *
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11 | ea7924dc | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | ea7924dc | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ea7924dc | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ea7924dc | Michael Walle | * Lesser General Public License for more details.
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15 | ea7924dc | Michael Walle | *
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16 | ea7924dc | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | ea7924dc | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | ea7924dc | Michael Walle | *
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19 | ea7924dc | Michael Walle | *
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20 | ea7924dc | Michael Walle | * Specification available at:
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21 | ea7924dc | Michael Walle | * http://www.latticesemi.com/documents/mico32timer.pdf
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22 | ea7924dc | Michael Walle | */
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23 | ea7924dc | Michael Walle | |
24 | ea7924dc | Michael Walle | #include "hw.h" |
25 | ea7924dc | Michael Walle | #include "sysbus.h" |
26 | ea7924dc | Michael Walle | #include "trace.h" |
27 | ea7924dc | Michael Walle | #include "qemu-timer.h" |
28 | 49d4d9b6 | Paolo Bonzini | #include "ptimer.h" |
29 | ea7924dc | Michael Walle | #include "qemu-error.h" |
30 | ea7924dc | Michael Walle | |
31 | ea7924dc | Michael Walle | #define DEFAULT_FREQUENCY (50*1000000) |
32 | ea7924dc | Michael Walle | |
33 | ea7924dc | Michael Walle | enum {
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34 | ea7924dc | Michael Walle | R_SR = 0,
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35 | ea7924dc | Michael Walle | R_CR, |
36 | ea7924dc | Michael Walle | R_PERIOD, |
37 | ea7924dc | Michael Walle | R_SNAPSHOT, |
38 | ea7924dc | Michael Walle | R_MAX |
39 | ea7924dc | Michael Walle | }; |
40 | ea7924dc | Michael Walle | |
41 | ea7924dc | Michael Walle | enum {
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42 | ea7924dc | Michael Walle | SR_TO = (1 << 0), |
43 | ea7924dc | Michael Walle | SR_RUN = (1 << 1), |
44 | ea7924dc | Michael Walle | }; |
45 | ea7924dc | Michael Walle | |
46 | ea7924dc | Michael Walle | enum {
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47 | ea7924dc | Michael Walle | CR_ITO = (1 << 0), |
48 | ea7924dc | Michael Walle | CR_CONT = (1 << 1), |
49 | ea7924dc | Michael Walle | CR_START = (1 << 2), |
50 | ea7924dc | Michael Walle | CR_STOP = (1 << 3), |
51 | ea7924dc | Michael Walle | }; |
52 | ea7924dc | Michael Walle | |
53 | ea7924dc | Michael Walle | struct LM32TimerState {
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54 | ea7924dc | Michael Walle | SysBusDevice busdev; |
55 | d09510b2 | Avi Kivity | MemoryRegion iomem; |
56 | ea7924dc | Michael Walle | |
57 | ea7924dc | Michael Walle | QEMUBH *bh; |
58 | ea7924dc | Michael Walle | ptimer_state *ptimer; |
59 | ea7924dc | Michael Walle | |
60 | ea7924dc | Michael Walle | qemu_irq irq; |
61 | ea7924dc | Michael Walle | uint32_t freq_hz; |
62 | ea7924dc | Michael Walle | |
63 | ea7924dc | Michael Walle | uint32_t regs[R_MAX]; |
64 | ea7924dc | Michael Walle | }; |
65 | ea7924dc | Michael Walle | typedef struct LM32TimerState LM32TimerState; |
66 | ea7924dc | Michael Walle | |
67 | ea7924dc | Michael Walle | static void timer_update_irq(LM32TimerState *s) |
68 | ea7924dc | Michael Walle | { |
69 | ea7924dc | Michael Walle | int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
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70 | ea7924dc | Michael Walle | |
71 | ea7924dc | Michael Walle | trace_lm32_timer_irq_state(state); |
72 | ea7924dc | Michael Walle | qemu_set_irq(s->irq, state); |
73 | ea7924dc | Michael Walle | } |
74 | ea7924dc | Michael Walle | |
75 | d09510b2 | Avi Kivity | static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size) |
76 | ea7924dc | Michael Walle | { |
77 | ea7924dc | Michael Walle | LM32TimerState *s = opaque; |
78 | ea7924dc | Michael Walle | uint32_t r = 0;
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79 | ea7924dc | Michael Walle | |
80 | ea7924dc | Michael Walle | addr >>= 2;
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81 | ea7924dc | Michael Walle | switch (addr) {
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82 | ea7924dc | Michael Walle | case R_SR:
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83 | ea7924dc | Michael Walle | case R_CR:
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84 | ea7924dc | Michael Walle | case R_PERIOD:
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85 | ea7924dc | Michael Walle | r = s->regs[addr]; |
86 | ea7924dc | Michael Walle | break;
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87 | ea7924dc | Michael Walle | case R_SNAPSHOT:
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88 | ea7924dc | Michael Walle | r = (uint32_t)ptimer_get_count(s->ptimer); |
89 | ea7924dc | Michael Walle | break;
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90 | ea7924dc | Michael Walle | default:
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91 | dd3d6775 | Markus Armbruster | error_report("lm32_timer: read access to unknown register 0x"
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92 | ea7924dc | Michael Walle | TARGET_FMT_plx, addr << 2);
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93 | ea7924dc | Michael Walle | break;
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94 | ea7924dc | Michael Walle | } |
95 | ea7924dc | Michael Walle | |
96 | ea7924dc | Michael Walle | trace_lm32_timer_memory_read(addr << 2, r);
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97 | ea7924dc | Michael Walle | return r;
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98 | ea7924dc | Michael Walle | } |
99 | ea7924dc | Michael Walle | |
100 | d09510b2 | Avi Kivity | static void timer_write(void *opaque, target_phys_addr_t addr, |
101 | d09510b2 | Avi Kivity | uint64_t value, unsigned size)
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102 | ea7924dc | Michael Walle | { |
103 | ea7924dc | Michael Walle | LM32TimerState *s = opaque; |
104 | ea7924dc | Michael Walle | |
105 | ea7924dc | Michael Walle | trace_lm32_timer_memory_write(addr, value); |
106 | ea7924dc | Michael Walle | |
107 | ea7924dc | Michael Walle | addr >>= 2;
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108 | ea7924dc | Michael Walle | switch (addr) {
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109 | ea7924dc | Michael Walle | case R_SR:
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110 | ea7924dc | Michael Walle | s->regs[R_SR] &= ~SR_TO; |
111 | ea7924dc | Michael Walle | break;
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112 | ea7924dc | Michael Walle | case R_CR:
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113 | ea7924dc | Michael Walle | s->regs[R_CR] = value; |
114 | ea7924dc | Michael Walle | if (s->regs[R_CR] & CR_START) {
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115 | ea7924dc | Michael Walle | ptimer_run(s->ptimer, 1);
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116 | ea7924dc | Michael Walle | } |
117 | ea7924dc | Michael Walle | if (s->regs[R_CR] & CR_STOP) {
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118 | ea7924dc | Michael Walle | ptimer_stop(s->ptimer); |
119 | ea7924dc | Michael Walle | } |
120 | ea7924dc | Michael Walle | break;
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121 | ea7924dc | Michael Walle | case R_PERIOD:
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122 | ea7924dc | Michael Walle | s->regs[R_PERIOD] = value; |
123 | ea7924dc | Michael Walle | ptimer_set_count(s->ptimer, value); |
124 | ea7924dc | Michael Walle | break;
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125 | ea7924dc | Michael Walle | case R_SNAPSHOT:
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126 | ea7924dc | Michael Walle | error_report("lm32_timer: write access to read only register 0x"
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127 | ea7924dc | Michael Walle | TARGET_FMT_plx, addr << 2);
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128 | ea7924dc | Michael Walle | break;
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129 | ea7924dc | Michael Walle | default:
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130 | dd3d6775 | Markus Armbruster | error_report("lm32_timer: write access to unknown register 0x"
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131 | ea7924dc | Michael Walle | TARGET_FMT_plx, addr << 2);
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132 | ea7924dc | Michael Walle | break;
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133 | ea7924dc | Michael Walle | } |
134 | ea7924dc | Michael Walle | timer_update_irq(s); |
135 | ea7924dc | Michael Walle | } |
136 | ea7924dc | Michael Walle | |
137 | d09510b2 | Avi Kivity | static const MemoryRegionOps timer_ops = { |
138 | d09510b2 | Avi Kivity | .read = timer_read, |
139 | d09510b2 | Avi Kivity | .write = timer_write, |
140 | d09510b2 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
141 | d09510b2 | Avi Kivity | .valid = { |
142 | d09510b2 | Avi Kivity | .min_access_size = 4,
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143 | d09510b2 | Avi Kivity | .max_access_size = 4,
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144 | d09510b2 | Avi Kivity | }, |
145 | ea7924dc | Michael Walle | }; |
146 | ea7924dc | Michael Walle | |
147 | ea7924dc | Michael Walle | static void timer_hit(void *opaque) |
148 | ea7924dc | Michael Walle | { |
149 | ea7924dc | Michael Walle | LM32TimerState *s = opaque; |
150 | ea7924dc | Michael Walle | |
151 | ea7924dc | Michael Walle | trace_lm32_timer_hit(); |
152 | ea7924dc | Michael Walle | |
153 | ea7924dc | Michael Walle | s->regs[R_SR] |= SR_TO; |
154 | ea7924dc | Michael Walle | |
155 | ea7924dc | Michael Walle | if (s->regs[R_CR] & CR_CONT) {
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156 | ea7924dc | Michael Walle | ptimer_set_count(s->ptimer, s->regs[R_PERIOD]); |
157 | ea7924dc | Michael Walle | ptimer_run(s->ptimer, 1);
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158 | ea7924dc | Michael Walle | } |
159 | ea7924dc | Michael Walle | timer_update_irq(s); |
160 | ea7924dc | Michael Walle | } |
161 | ea7924dc | Michael Walle | |
162 | ea7924dc | Michael Walle | static void timer_reset(DeviceState *d) |
163 | ea7924dc | Michael Walle | { |
164 | ea7924dc | Michael Walle | LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev); |
165 | ea7924dc | Michael Walle | int i;
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166 | ea7924dc | Michael Walle | |
167 | ea7924dc | Michael Walle | for (i = 0; i < R_MAX; i++) { |
168 | ea7924dc | Michael Walle | s->regs[i] = 0;
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169 | ea7924dc | Michael Walle | } |
170 | ea7924dc | Michael Walle | ptimer_stop(s->ptimer); |
171 | ea7924dc | Michael Walle | } |
172 | ea7924dc | Michael Walle | |
173 | ea7924dc | Michael Walle | static int lm32_timer_init(SysBusDevice *dev) |
174 | ea7924dc | Michael Walle | { |
175 | ea7924dc | Michael Walle | LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev); |
176 | ea7924dc | Michael Walle | |
177 | ea7924dc | Michael Walle | sysbus_init_irq(dev, &s->irq); |
178 | ea7924dc | Michael Walle | |
179 | ea7924dc | Michael Walle | s->bh = qemu_bh_new(timer_hit, s); |
180 | ea7924dc | Michael Walle | s->ptimer = ptimer_init(s->bh); |
181 | ea7924dc | Michael Walle | ptimer_set_freq(s->ptimer, s->freq_hz); |
182 | ea7924dc | Michael Walle | |
183 | d09510b2 | Avi Kivity | memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4); |
184 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
185 | ea7924dc | Michael Walle | |
186 | ea7924dc | Michael Walle | return 0; |
187 | ea7924dc | Michael Walle | } |
188 | ea7924dc | Michael Walle | |
189 | ea7924dc | Michael Walle | static const VMStateDescription vmstate_lm32_timer = { |
190 | ea7924dc | Michael Walle | .name = "lm32-timer",
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191 | ea7924dc | Michael Walle | .version_id = 1,
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192 | ea7924dc | Michael Walle | .minimum_version_id = 1,
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193 | ea7924dc | Michael Walle | .minimum_version_id_old = 1,
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194 | ea7924dc | Michael Walle | .fields = (VMStateField[]) { |
195 | ea7924dc | Michael Walle | VMSTATE_PTIMER(ptimer, LM32TimerState), |
196 | ea7924dc | Michael Walle | VMSTATE_UINT32(freq_hz, LM32TimerState), |
197 | ea7924dc | Michael Walle | VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX), |
198 | ea7924dc | Michael Walle | VMSTATE_END_OF_LIST() |
199 | ea7924dc | Michael Walle | } |
200 | ea7924dc | Michael Walle | }; |
201 | ea7924dc | Michael Walle | |
202 | 999e12bb | Anthony Liguori | static Property lm32_timer_properties[] = {
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203 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
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204 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
205 | 999e12bb | Anthony Liguori | }; |
206 | 999e12bb | Anthony Liguori | |
207 | 999e12bb | Anthony Liguori | static void lm32_timer_class_init(ObjectClass *klass, void *data) |
208 | 999e12bb | Anthony Liguori | { |
209 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
210 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
211 | 999e12bb | Anthony Liguori | |
212 | 999e12bb | Anthony Liguori | k->init = lm32_timer_init; |
213 | 39bffca2 | Anthony Liguori | dc->reset = timer_reset; |
214 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_lm32_timer; |
215 | 39bffca2 | Anthony Liguori | dc->props = lm32_timer_properties; |
216 | 999e12bb | Anthony Liguori | } |
217 | 999e12bb | Anthony Liguori | |
218 | 39bffca2 | Anthony Liguori | static TypeInfo lm32_timer_info = {
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219 | 39bffca2 | Anthony Liguori | .name = "lm32-timer",
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220 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
221 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(LM32TimerState),
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222 | 39bffca2 | Anthony Liguori | .class_init = lm32_timer_class_init, |
223 | ea7924dc | Michael Walle | }; |
224 | ea7924dc | Michael Walle | |
225 | 83f7d43a | Andreas Färber | static void lm32_timer_register_types(void) |
226 | ea7924dc | Michael Walle | { |
227 | 39bffca2 | Anthony Liguori | type_register_static(&lm32_timer_info); |
228 | ea7924dc | Michael Walle | } |
229 | ea7924dc | Michael Walle | |
230 | 83f7d43a | Andreas Färber | type_init(lm32_timer_register_types) |