Archipelago » qemu

/*

 * QEMU VGA Emulator.

 *

 * Copyright (c) 2003 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "vga.h"

#include "console.h"

#include "pc.h"

#include "pci.h"

#include "vga_int.h"

#include "pixel_ops.h"

#include "qemu-timer.h"

#include "xen.h"

#include "trace.h"

//#define DEBUG_VGA

//#define DEBUG_VGA_MEM

//#define DEBUG_VGA_REG

//#define DEBUG_BOCHS_VBE

/*

 * Video Graphics Array (VGA)

 *

 * Chipset docs for original IBM VGA:

 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf

 *

 * FreeVGA site:

 * http://www.osdever.net/FreeVGA/home.htm

 *

 * Standard VGA features and Bochs VBE extensions are implemented.

 */

/* force some bits to zero */

const uint8_t sr_mask[8] = {

    0x03,

    0x3d,

    0x0f,

    0x3f,

    0x0e,

    0x00,

    0x00,

    0xff,

};

const uint8_t gr_mask[16] = {

    0x0f, /* 0x00 */

    0x0f, /* 0x01 */

    0x0f, /* 0x02 */

    0x1f, /* 0x03 */

    0x03, /* 0x04 */

    0x7b, /* 0x05 */

    0x0f, /* 0x06 */

    0x0f, /* 0x07 */

    0xff, /* 0x08 */

    0x00, /* 0x09 */

    0x00, /* 0x0a */

    0x00, /* 0x0b */

    0x00, /* 0x0c */

    0x00, /* 0x0d */

    0x00, /* 0x0e */

    0x00, /* 0x0f */

};

#define cbswap_32(__x) \

((uint32_t)( \

                (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \

                (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \

                (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \

                (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))

#ifdef HOST_WORDS_BIGENDIAN

#define PAT(x) cbswap_32(x)

#else

#define PAT(x) (x)

#endif

#ifdef HOST_WORDS_BIGENDIAN

#define BIG 1

#else

#define BIG 0

#endif

#ifdef HOST_WORDS_BIGENDIAN

#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)

#else

#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)

#endif

static const uint32_t mask16[16] = {

    PAT(0x00000000),

    PAT(0x000000ff),

    PAT(0x0000ff00),

    PAT(0x0000ffff),

    PAT(0x00ff0000),

    PAT(0x00ff00ff),

    PAT(0x00ffff00),

    PAT(0x00ffffff),

    PAT(0xff000000),

    PAT(0xff0000ff),

    PAT(0xff00ff00),

    PAT(0xff00ffff),

    PAT(0xffff0000),

    PAT(0xffff00ff),

    PAT(0xffffff00),

    PAT(0xffffffff),

};

#undef PAT

#ifdef HOST_WORDS_BIGENDIAN

#define PAT(x) (x)

#else

#define PAT(x) cbswap_32(x)

#endif

static const uint32_t dmask16[16] = {

    PAT(0x00000000),

    PAT(0x000000ff),

    PAT(0x0000ff00),

    PAT(0x0000ffff),

    PAT(0x00ff0000),

    PAT(0x00ff00ff),

    PAT(0x00ffff00),

    PAT(0x00ffffff),

    PAT(0xff000000),

    PAT(0xff0000ff),

    PAT(0xff00ff00),

    PAT(0xff00ffff),

    PAT(0xffff0000),

    PAT(0xffff00ff),

    PAT(0xffffff00),

    PAT(0xffffffff),

};

static const uint32_t dmask4[4] = {

    PAT(0x00000000),

    PAT(0x0000ffff),

    PAT(0xffff0000),

    PAT(0xffffffff),

};

static uint32_t expand4[256];

static uint16_t expand2[256];

static uint8_t expand4to8[16];

static void vga_screen_dump(void *opaque, const char *filename, bool cswitch);

static void vga_update_memory_access(VGACommonState *s)

{

    MemoryRegion *region, *old_region = s->chain4_alias;

    target_phys_addr_t base, offset, size;

    s->chain4_alias = NULL;

    if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==

        VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        offset = 0;

        switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {

        case 0:

            base = 0xa0000;

            size = 0x20000;

            break;

        case 1:

            base = 0xa0000;

            size = 0x10000;

            offset = s->bank_offset;

            break;

        case 2:

            base = 0xb0000;

            size = 0x8000;

            break;

        case 3:

        default:

            base = 0xb8000;

            size = 0x8000;

            break;

        }

        base += isa_mem_base;

        region = g_malloc(sizeof(*region));

        memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);

        memory_region_add_subregion_overlap(s->legacy_address_space, base,

                                            region, 2);

        s->chain4_alias = region;

    }

    if (old_region) {

        memory_region_del_subregion(s->legacy_address_space, old_region);

        memory_region_destroy(old_region);

        g_free(old_region);

        s->plane_updated = 0xf;

    }

}

static void vga_dumb_update_retrace_info(VGACommonState *s)

{

    (void) s;

}

static void vga_precise_update_retrace_info(VGACommonState *s)

{

    int htotal_chars;

    int hretr_start_char;

    int hretr_skew_chars;

    int hretr_end_char;

    int vtotal_lines;

    int vretr_start_line;

    int vretr_end_line;

    int dots;

#if 0

    int div2, sldiv2;

#endif

    int clocking_mode;

    int clock_sel;

    const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};

    int64_t chars_per_sec;

    struct vga_precise_retrace *r = &s->retrace_info.precise;

    htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;

    hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];

    hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;

    hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;

    vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |

                    (((s->cr[VGA_CRTC_OVERFLOW] & 1) |

                      ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;

    vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |

        ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |

          ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);

    vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;

    clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;

    clock_sel = (s->msr >> 2) & 3;

    dots = (s->msr & 1) ? 8 : 9;

    chars_per_sec = clk_hz[clock_sel] / dots;

    htotal_chars <<= clocking_mode;

    r->total_chars = vtotal_lines * htotal_chars;

    if (r->freq) {

        r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);

    } else {

        r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;

    }

    r->vstart = vretr_start_line;

    r->vend = r->vstart + vretr_end_line + 1;

    r->hstart = hretr_start_char + hretr_skew_chars;

    r->hend = r->hstart + hretr_end_char + 1;

    r->htotal = htotal_chars;

#if 0

    div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;

    sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;

    printf (

        "hz=%f\n"

        "htotal = %d\n"

        "hretr_start = %d\n"

        "hretr_skew = %d\n"

        "hretr_end = %d\n"

        "vtotal = %d\n"

        "vretr_start = %d\n"

        "vretr_end = %d\n"

        "div2 = %d sldiv2 = %d\n"

        "clocking_mode = %d\n"

        "clock_sel = %d %d\n"

        "dots = %d\n"

        "ticks/char = %" PRId64 "\n"

        "\n",

        (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),

        htotal_chars,

        hretr_start_char,

        hretr_skew_chars,

        hretr_end_char,

        vtotal_lines,

        vretr_start_line,

        vretr_end_line,

        div2, sldiv2,

        clocking_mode,

        clock_sel,

        clk_hz[clock_sel],

        dots,

        r->ticks_per_char

        );

#endif

}

static uint8_t vga_precise_retrace(VGACommonState *s)

{

    struct vga_precise_retrace *r = &s->retrace_info.precise;

    uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);

    if (r->total_chars) {

        int cur_line, cur_line_char, cur_char;

        int64_t cur_tick;

        cur_tick = qemu_get_clock_ns(vm_clock);

        cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;

        cur_line = cur_char / r->htotal;

        if (cur_line >= r->vstart && cur_line <= r->vend) {

            val |= ST01_V_RETRACE | ST01_DISP_ENABLE;

        } else {

            cur_line_char = cur_char % r->htotal;

            if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {

                val |= ST01_DISP_ENABLE;

            }

        }

        return val;

    } else {

        return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);

    }

}

static uint8_t vga_dumb_retrace(VGACommonState *s)

{

    return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);

}

int vga_ioport_invalid(VGACommonState *s, uint32_t addr)

{

    if (s->msr & VGA_MIS_COLOR) {

        /* Color */

        return (addr >= 0x3b0 && addr <= 0x3bf);

    } else {

        /* Monochrome */

        return (addr >= 0x3d0 && addr <= 0x3df);

    }

}

uint32_t vga_ioport_read(void *opaque, uint32_t addr)

{

    VGACommonState *s = opaque;

    int val, index;

    if (vga_ioport_invalid(s, addr)) {

        val = 0xff;

    } else {

        switch(addr) {

        case VGA_ATT_W:

            if (s->ar_flip_flop == 0) {

                val = s->ar_index;

            } else {

                val = 0;

            }

            break;

        case VGA_ATT_R:

            index = s->ar_index & 0x1f;

            if (index < VGA_ATT_C) {

                val = s->ar[index];

            } else {

                val = 0;

            }

            break;

        case VGA_MIS_W:

            val = s->st00;

            break;

        case VGA_SEQ_I:

            val = s->sr_index;

            break;

        case VGA_SEQ_D:

            val = s->sr[s->sr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);

#endif

            break;

        case VGA_PEL_IR:

            val = s->dac_state;

            break;

        case VGA_PEL_IW:

            val = s->dac_write_index;

            break;

        case VGA_PEL_D:

            val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];

            if (++s->dac_sub_index == 3) {

                s->dac_sub_index = 0;

                s->dac_read_index++;

            }

            break;

        case VGA_FTC_R:

            val = s->fcr;

            break;

        case VGA_MIS_R:

            val = s->msr;

            break;

        case VGA_GFX_I:

            val = s->gr_index;

            break;

        case VGA_GFX_D:

            val = s->gr[s->gr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);

#endif

            break;

        case VGA_CRT_IM:

        case VGA_CRT_IC:

            val = s->cr_index;

            break;

        case VGA_CRT_DM:

        case VGA_CRT_DC:

            val = s->cr[s->cr_index];

#ifdef DEBUG_VGA_REG

            printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);

#endif

            break;

        case VGA_IS1_RM:

        case VGA_IS1_RC:

            /* just toggle to fool polling */

            val = s->st01 = s->retrace(s);

            s->ar_flip_flop = 0;

            break;

        default:

            val = 0x00;

            break;

        }

    }

#if defined(DEBUG_VGA)

    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);

#endif

    return val;

}

void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)

{

    VGACommonState *s = opaque;

    int index;

    /* check port range access depending on color/monochrome mode */

    if (vga_ioport_invalid(s, addr)) {

        return;

    }

#ifdef DEBUG_VGA

    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);

#endif

    switch(addr) {

    case VGA_ATT_W:

        if (s->ar_flip_flop == 0) {

            val &= 0x3f;

            s->ar_index = val;

        } else {

            index = s->ar_index & 0x1f;

            switch(index) {

            case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:

                s->ar[index] = val & 0x3f;

                break;

            case VGA_ATC_MODE:

                s->ar[index] = val & ~0x10;

                break;

            case VGA_ATC_OVERSCAN:

                s->ar[index] = val;

                break;

            case VGA_ATC_PLANE_ENABLE:

                s->ar[index] = val & ~0xc0;

                break;

            case VGA_ATC_PEL:

                s->ar[index] = val & ~0xf0;

                break;

            case VGA_ATC_COLOR_PAGE:

                s->ar[index] = val & ~0xf0;

                break;

            default:

                break;

            }

        }

        s->ar_flip_flop ^= 1;

        break;

    case VGA_MIS_W:

        s->msr = val & ~0x10;

        s->update_retrace_info(s);

        break;

    case VGA_SEQ_I:

        s->sr_index = val & 7;

        break;

    case VGA_SEQ_D:

#ifdef DEBUG_VGA_REG

        printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);

#endif

        s->sr[s->sr_index] = val & sr_mask[s->sr_index];

        if (s->sr_index == VGA_SEQ_CLOCK_MODE) {

            s->update_retrace_info(s);

        }

        vga_update_memory_access(s);

        break;

    case VGA_PEL_IR:

        s->dac_read_index = val;

        s->dac_sub_index = 0;

        s->dac_state = 3;

        break;

    case VGA_PEL_IW:

        s->dac_write_index = val;

        s->dac_sub_index = 0;

        s->dac_state = 0;

        break;

    case VGA_PEL_D:

        s->dac_cache[s->dac_sub_index] = val;

        if (++s->dac_sub_index == 3) {

            memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);

            s->dac_sub_index = 0;

            s->dac_write_index++;

        }

        break;

    case VGA_GFX_I:

        s->gr_index = val & 0x0f;

        break;

    case VGA_GFX_D:

#ifdef DEBUG_VGA_REG

        printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);

#endif

        s->gr[s->gr_index] = val & gr_mask[s->gr_index];

        vga_update_memory_access(s);

        break;

    case VGA_CRT_IM:

    case VGA_CRT_IC:

        s->cr_index = val;

        break;

    case VGA_CRT_DM:

    case VGA_CRT_DC:

#ifdef DEBUG_VGA_REG

        printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);

#endif

        /* handle CR0-7 protection */

        if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&

            s->cr_index <= VGA_CRTC_OVERFLOW) {

            /* can always write bit 4 of CR7 */

            if (s->cr_index == VGA_CRTC_OVERFLOW) {

                s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |

                    (val & 0x10);

            }

            return;

        }

        s->cr[s->cr_index] = val;

        switch(s->cr_index) {

        case VGA_CRTC_H_TOTAL:

        case VGA_CRTC_H_SYNC_START:

        case VGA_CRTC_H_SYNC_END:

        case VGA_CRTC_V_TOTAL:

        case VGA_CRTC_OVERFLOW:

        case VGA_CRTC_V_SYNC_END:

        case VGA_CRTC_MODE:

            s->update_retrace_info(s);

            break;

        }

        break;

    case VGA_IS1_RM:

    case VGA_IS1_RC:

        s->fcr = val & 0x10;

        break;

    }

}

#ifdef CONFIG_BOCHS_VBE

static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)

{

    VGACommonState *s = opaque;

    uint32_t val;

    val = s->vbe_index;

    return val;

}

static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)

{

    VGACommonState *s = opaque;

    uint32_t val;

    if (s->vbe_index < VBE_DISPI_INDEX_NB) {

        if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {

            switch(s->vbe_index) {

                /* XXX: do not hardcode ? */

            case VBE_DISPI_INDEX_XRES:

                val = VBE_DISPI_MAX_XRES;

                break;

            case VBE_DISPI_INDEX_YRES:

                val = VBE_DISPI_MAX_YRES;

                break;

            case VBE_DISPI_INDEX_BPP:

                val = VBE_DISPI_MAX_BPP;

                break;

            default:

                val = s->vbe_regs[s->vbe_index];

                break;

            }

        } else {

            val = s->vbe_regs[s->vbe_index];

        }

    } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {

        val = s->vram_size / (64 * 1024);

    } else {

        val = 0;

    }

#ifdef DEBUG_BOCHS_VBE

    printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);

#endif

    return val;

}

static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)

{

    VGACommonState *s = opaque;

    s->vbe_index = val;

}

static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)

{

    VGACommonState *s = opaque;

    if (s->vbe_index <= VBE_DISPI_INDEX_NB) {

#ifdef DEBUG_BOCHS_VBE

        printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);

#endif

        switch(s->vbe_index) {

        case VBE_DISPI_INDEX_ID:

            if (val == VBE_DISPI_ID0 ||

                val == VBE_DISPI_ID1 ||

                val == VBE_DISPI_ID2 ||

                val == VBE_DISPI_ID3 ||

                val == VBE_DISPI_ID4) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_XRES:

            if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_YRES:

            if (val <= VBE_DISPI_MAX_YRES) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_BPP:

            if (val == 0)

                val = 8;

            if (val == 4 || val == 8 || val == 15 ||

                val == 16 || val == 24 || val == 32) {

                s->vbe_regs[s->vbe_index] = val;

            }

            break;

        case VBE_DISPI_INDEX_BANK:

            if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {

              val &= (s->vbe_bank_mask >> 2);

            } else {

              val &= s->vbe_bank_mask;

            }

            s->vbe_regs[s->vbe_index] = val;

            s->bank_offset = (val << 16);

            vga_update_memory_access(s);

            break;

        case VBE_DISPI_INDEX_ENABLE:

            if ((val & VBE_DISPI_ENABLED) &&

                !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {

                int h, shift_control;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =

                    s->vbe_regs[VBE_DISPI_INDEX_XRES];

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =

                    s->vbe_regs[VBE_DISPI_INDEX_YRES];

                s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;

                s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;

                else

                    s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *

                        ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                s->vbe_start_addr = 0;

                /* clear the screen (should be done in BIOS) */

                if (!(val & VBE_DISPI_NOCLEARMEM)) {

                    memset(s->vram_ptr, 0,

                           s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);

                }

                /* we initialize the VGA graphic mode (should be done

                   in BIOS) */

                /* graphic mode + memory map 1 */

                s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |

                    VGA_GR06_GRAPHICS_MODE;

                s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */

                s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;

                /* width */

                s->cr[VGA_CRTC_H_DISP] =

                    (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;

                /* height (only meaningful if < 1024) */

                h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;

                s->cr[VGA_CRTC_V_DISP_END] = h;

                s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |

                    ((h >> 7) & 0x02) | ((h >> 3) & 0x40);

                /* line compare to 1023 */

                s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;

                s->cr[VGA_CRTC_OVERFLOW] |= 0x10;

                s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {

                    shift_control = 0;

                    s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */

                } else {

                    shift_control = 2;

                    /* set chain 4 mode */

                    s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;

                    /* activate all planes */

                    s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;

                }

                s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |

                    (shift_control << 5);

                s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */

            } else {

                /* XXX: the bios should do that */

                s->bank_offset = 0;

            }

            s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;

            s->vbe_regs[s->vbe_index] = val;

            vga_update_memory_access(s);

            break;

        case VBE_DISPI_INDEX_VIRT_WIDTH:

            {

                int w, h, line_offset;

                if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])

                    return;

                w = val;

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    line_offset = w >> 1;

                else

                    line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                h = s->vram_size / line_offset;

                /* XXX: support weird bochs semantics ? */

                if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])

                    return;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;

                s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;

                s->vbe_line_offset = line_offset;

            }

            break;

        case VBE_DISPI_INDEX_X_OFFSET:

        case VBE_DISPI_INDEX_Y_OFFSET:

            {

                int x;

                s->vbe_regs[s->vbe_index] = val;

                s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];

                x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];

                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)

                    s->vbe_start_addr += x >> 1;

                else

                    s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);

                s->vbe_start_addr >>= 2;

            }

            break;

        default:

            break;

        }

    }

}

#endif

/* called for accesses between 0xa0000 and 0xc0000 */

uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)

{

    int memory_map_mode, plane;

    uint32_t ret;

    /* convert to VGA memory offset */

    memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;

    addr &= 0x1ffff;

    switch(memory_map_mode) {

    case 0:

        break;

    case 1:

        if (addr >= 0x10000)

            return 0xff;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0x10000;

        if (addr >= 0x8000)

            return 0xff;

        break;

    default:

    case 3:

        addr -= 0x18000;

        if (addr >= 0x8000)

            return 0xff;

        break;

    }

    if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        /* chain 4 mode : simplest access */

        ret = s->vram_ptr[addr];

    } else if (s->gr[VGA_GFX_MODE] & 0x10) {

        /* odd/even mode (aka text mode mapping) */

        plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);

        ret = s->vram_ptr[((addr & ~1) << 1) | plane];

    } else {

        /* standard VGA latched access */

        s->latch = ((uint32_t *)s->vram_ptr)[addr];

        if (!(s->gr[VGA_GFX_MODE] & 0x08)) {

            /* read mode 0 */

            plane = s->gr[VGA_GFX_PLANE_READ];

            ret = GET_PLANE(s->latch, plane);

        } else {

            /* read mode 1 */

            ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &

                mask16[s->gr[VGA_GFX_COMPARE_MASK]];

            ret |= ret >> 16;

            ret |= ret >> 8;

            ret = (~ret) & 0xff;

        }

    }

    return ret;

}

/* called for accesses between 0xa0000 and 0xc0000 */

void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)

{

    int memory_map_mode, plane, write_mode, b, func_select, mask;

    uint32_t write_mask, bit_mask, set_mask;

#ifdef DEBUG_VGA_MEM

    printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);

#endif

    /* convert to VGA memory offset */

    memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;

    addr &= 0x1ffff;

    switch(memory_map_mode) {

    case 0:

        break;

    case 1:

        if (addr >= 0x10000)

            return;

        addr += s->bank_offset;

        break;

    case 2:

        addr -= 0x10000;

        if (addr >= 0x8000)

            return;

        break;

    default:

    case 3:

        addr -= 0x18000;

        if (addr >= 0x8000)

            return;

        break;

    }

    if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {

        /* chain 4 mode : simplest access */

        plane = addr & 3;

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {

            s->vram_ptr[addr] = val;

#ifdef DEBUG_VGA_MEM

            printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);

#endif

            s->plane_updated |= mask; /* only used to detect font change */

            memory_region_set_dirty(&s->vram, addr, 1);

        }

    } else if (s->gr[VGA_GFX_MODE] & 0x10) {

        /* odd/even mode (aka text mode mapping) */

        plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);

        mask = (1 << plane);

        if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {