root / hw / zynq_slcr.c @ 0b7ade1d
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1 | e3260506 | Peter A. G. Crosthwaite | /*
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2 | e3260506 | Peter A. G. Crosthwaite | * Status and system control registers for Xilinx Zynq Platform
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3 | e3260506 | Peter A. G. Crosthwaite | *
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4 | e3260506 | Peter A. G. Crosthwaite | * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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5 | e3260506 | Peter A. G. Crosthwaite | * Copyright (c) 2012 PetaLogix Pty Ltd.
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6 | e3260506 | Peter A. G. Crosthwaite | * Based on hw/arm_sysctl.c, written by Paul Brook
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7 | e3260506 | Peter A. G. Crosthwaite | *
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8 | e3260506 | Peter A. G. Crosthwaite | * This program is free software; you can redistribute it and/or
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9 | e3260506 | Peter A. G. Crosthwaite | * modify it under the terms of the GNU General Public License
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10 | e3260506 | Peter A. G. Crosthwaite | * as published by the Free Software Foundation; either version
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11 | e3260506 | Peter A. G. Crosthwaite | * 2 of the License, or (at your option) any later version.
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12 | e3260506 | Peter A. G. Crosthwaite | *
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13 | e3260506 | Peter A. G. Crosthwaite | * You should have received a copy of the GNU General Public License along
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14 | e3260506 | Peter A. G. Crosthwaite | * with this program; if not, see <http://www.gnu.org/licenses/>.
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15 | e3260506 | Peter A. G. Crosthwaite | */
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16 | e3260506 | Peter A. G. Crosthwaite | |
17 | e3260506 | Peter A. G. Crosthwaite | #include "hw.h" |
18 | e3260506 | Peter A. G. Crosthwaite | #include "qemu-timer.h" |
19 | e3260506 | Peter A. G. Crosthwaite | #include "sysbus.h" |
20 | e3260506 | Peter A. G. Crosthwaite | #include "sysemu.h" |
21 | e3260506 | Peter A. G. Crosthwaite | |
22 | e3260506 | Peter A. G. Crosthwaite | #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
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23 | e3260506 | Peter A. G. Crosthwaite | #define DB_PRINT(...) do { \ |
24 | e3260506 | Peter A. G. Crosthwaite | fprintf(stderr, ": %s: ", __func__); \
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25 | e3260506 | Peter A. G. Crosthwaite | fprintf(stderr, ## __VA_ARGS__); \ |
26 | e3260506 | Peter A. G. Crosthwaite | } while (0); |
27 | e3260506 | Peter A. G. Crosthwaite | #else
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28 | e3260506 | Peter A. G. Crosthwaite | #define DB_PRINT(...)
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29 | e3260506 | Peter A. G. Crosthwaite | #endif
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30 | e3260506 | Peter A. G. Crosthwaite | |
31 | e3260506 | Peter A. G. Crosthwaite | #define XILINX_LOCK_KEY 0x767b |
32 | e3260506 | Peter A. G. Crosthwaite | #define XILINX_UNLOCK_KEY 0xdf0d |
33 | e3260506 | Peter A. G. Crosthwaite | |
34 | e3260506 | Peter A. G. Crosthwaite | typedef enum { |
35 | e3260506 | Peter A. G. Crosthwaite | ARM_PLL_CTRL, |
36 | e3260506 | Peter A. G. Crosthwaite | DDR_PLL_CTRL, |
37 | e3260506 | Peter A. G. Crosthwaite | IO_PLL_CTRL, |
38 | e3260506 | Peter A. G. Crosthwaite | PLL_STATUS, |
39 | e3260506 | Peter A. G. Crosthwaite | ARM_PPL_CFG, |
40 | e3260506 | Peter A. G. Crosthwaite | DDR_PLL_CFG, |
41 | e3260506 | Peter A. G. Crosthwaite | IO_PLL_CFG, |
42 | e3260506 | Peter A. G. Crosthwaite | PLL_BG_CTRL, |
43 | e3260506 | Peter A. G. Crosthwaite | PLL_MAX |
44 | e3260506 | Peter A. G. Crosthwaite | } PLLValues; |
45 | e3260506 | Peter A. G. Crosthwaite | |
46 | e3260506 | Peter A. G. Crosthwaite | typedef enum { |
47 | e3260506 | Peter A. G. Crosthwaite | ARM_CLK_CTRL, |
48 | e3260506 | Peter A. G. Crosthwaite | DDR_CLK_CTRL, |
49 | e3260506 | Peter A. G. Crosthwaite | DCI_CLK_CTRL, |
50 | e3260506 | Peter A. G. Crosthwaite | APER_CLK_CTRL, |
51 | e3260506 | Peter A. G. Crosthwaite | USB0_CLK_CTRL, |
52 | e3260506 | Peter A. G. Crosthwaite | USB1_CLK_CTRL, |
53 | e3260506 | Peter A. G. Crosthwaite | GEM0_RCLK_CTRL, |
54 | e3260506 | Peter A. G. Crosthwaite | GEM1_RCLK_CTRL, |
55 | e3260506 | Peter A. G. Crosthwaite | GEM0_CLK_CTRL, |
56 | e3260506 | Peter A. G. Crosthwaite | GEM1_CLK_CTRL, |
57 | e3260506 | Peter A. G. Crosthwaite | SMC_CLK_CTRL, |
58 | e3260506 | Peter A. G. Crosthwaite | LQSPI_CLK_CTRL, |
59 | e3260506 | Peter A. G. Crosthwaite | SDIO_CLK_CTRL, |
60 | e3260506 | Peter A. G. Crosthwaite | UART_CLK_CTRL, |
61 | e3260506 | Peter A. G. Crosthwaite | SPI_CLK_CTRL, |
62 | e3260506 | Peter A. G. Crosthwaite | CAN_CLK_CTRL, |
63 | e3260506 | Peter A. G. Crosthwaite | CAN_MIOCLK_CTRL, |
64 | e3260506 | Peter A. G. Crosthwaite | DBG_CLK_CTRL, |
65 | e3260506 | Peter A. G. Crosthwaite | PCAP_CLK_CTRL, |
66 | e3260506 | Peter A. G. Crosthwaite | TOPSW_CLK_CTRL, |
67 | e3260506 | Peter A. G. Crosthwaite | CLK_MAX |
68 | e3260506 | Peter A. G. Crosthwaite | } ClkValues; |
69 | e3260506 | Peter A. G. Crosthwaite | |
70 | e3260506 | Peter A. G. Crosthwaite | typedef enum { |
71 | e3260506 | Peter A. G. Crosthwaite | CLK_CTRL, |
72 | e3260506 | Peter A. G. Crosthwaite | THR_CTRL, |
73 | e3260506 | Peter A. G. Crosthwaite | THR_CNT, |
74 | e3260506 | Peter A. G. Crosthwaite | THR_STA, |
75 | e3260506 | Peter A. G. Crosthwaite | FPGA_MAX |
76 | e3260506 | Peter A. G. Crosthwaite | } FPGAValues; |
77 | e3260506 | Peter A. G. Crosthwaite | |
78 | e3260506 | Peter A. G. Crosthwaite | typedef enum { |
79 | e3260506 | Peter A. G. Crosthwaite | SYNC_CTRL, |
80 | e3260506 | Peter A. G. Crosthwaite | SYNC_STATUS, |
81 | e3260506 | Peter A. G. Crosthwaite | BANDGAP_TRIP, |
82 | e3260506 | Peter A. G. Crosthwaite | CC_TEST, |
83 | e3260506 | Peter A. G. Crosthwaite | PLL_PREDIVISOR, |
84 | e3260506 | Peter A. G. Crosthwaite | CLK_621_TRUE, |
85 | e3260506 | Peter A. G. Crosthwaite | PICTURE_DBG, |
86 | e3260506 | Peter A. G. Crosthwaite | PICTURE_DBG_UCNT, |
87 | e3260506 | Peter A. G. Crosthwaite | PICTURE_DBG_LCNT, |
88 | e3260506 | Peter A. G. Crosthwaite | MISC_MAX |
89 | e3260506 | Peter A. G. Crosthwaite | } MiscValues; |
90 | e3260506 | Peter A. G. Crosthwaite | |
91 | e3260506 | Peter A. G. Crosthwaite | typedef enum { |
92 | e3260506 | Peter A. G. Crosthwaite | PSS, |
93 | e3260506 | Peter A. G. Crosthwaite | DDDR, |
94 | e3260506 | Peter A. G. Crosthwaite | DMAC, |
95 | e3260506 | Peter A. G. Crosthwaite | USB, |
96 | e3260506 | Peter A. G. Crosthwaite | GEM, |
97 | e3260506 | Peter A. G. Crosthwaite | SDIO, |
98 | e3260506 | Peter A. G. Crosthwaite | SPI, |
99 | e3260506 | Peter A. G. Crosthwaite | CAN, |
100 | e3260506 | Peter A. G. Crosthwaite | I2C, |
101 | e3260506 | Peter A. G. Crosthwaite | UART, |
102 | e3260506 | Peter A. G. Crosthwaite | GPIO, |
103 | e3260506 | Peter A. G. Crosthwaite | LQSPI, |
104 | e3260506 | Peter A. G. Crosthwaite | SMC, |
105 | e3260506 | Peter A. G. Crosthwaite | OCM, |
106 | e3260506 | Peter A. G. Crosthwaite | DEVCI, |
107 | e3260506 | Peter A. G. Crosthwaite | FPGA, |
108 | e3260506 | Peter A. G. Crosthwaite | A9_CPU, |
109 | e3260506 | Peter A. G. Crosthwaite | RS_AWDT, |
110 | e3260506 | Peter A. G. Crosthwaite | RST_REASON, |
111 | e3260506 | Peter A. G. Crosthwaite | RST_REASON_CLR, |
112 | e3260506 | Peter A. G. Crosthwaite | REBOOT_STATUS, |
113 | e3260506 | Peter A. G. Crosthwaite | BOOT_MODE, |
114 | e3260506 | Peter A. G. Crosthwaite | RESET_MAX |
115 | e3260506 | Peter A. G. Crosthwaite | } ResetValues; |
116 | e3260506 | Peter A. G. Crosthwaite | |
117 | e3260506 | Peter A. G. Crosthwaite | typedef struct { |
118 | e3260506 | Peter A. G. Crosthwaite | SysBusDevice busdev; |
119 | e3260506 | Peter A. G. Crosthwaite | MemoryRegion iomem; |
120 | e3260506 | Peter A. G. Crosthwaite | |
121 | e3260506 | Peter A. G. Crosthwaite | union {
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122 | e3260506 | Peter A. G. Crosthwaite | struct {
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123 | e3260506 | Peter A. G. Crosthwaite | uint16_t scl; |
124 | e3260506 | Peter A. G. Crosthwaite | uint16_t lockval; |
125 | e3260506 | Peter A. G. Crosthwaite | uint32_t pll[PLL_MAX]; /* 0x100 - 0x11C */
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126 | e3260506 | Peter A. G. Crosthwaite | uint32_t clk[CLK_MAX]; /* 0x120 - 0x16C */
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127 | e3260506 | Peter A. G. Crosthwaite | uint32_t fpga[4][FPGA_MAX]; /* 0x170 - 0x1AC */ |
128 | e3260506 | Peter A. G. Crosthwaite | uint32_t misc[MISC_MAX]; /* 0x1B0 - 0x1D8 */
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129 | e3260506 | Peter A. G. Crosthwaite | uint32_t reset[RESET_MAX]; /* 0x200 - 0x25C */
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130 | e3260506 | Peter A. G. Crosthwaite | uint32_t apu_ctrl; /* 0x300 */
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131 | e3260506 | Peter A. G. Crosthwaite | uint32_t wdt_clk_sel; /* 0x304 */
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132 | e3260506 | Peter A. G. Crosthwaite | uint32_t tz_ocm[3]; /* 0x400 - 0x408 */ |
133 | e3260506 | Peter A. G. Crosthwaite | uint32_t tz_ddr; /* 0x430 */
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134 | e3260506 | Peter A. G. Crosthwaite | uint32_t tz_dma[3]; /* 0x440 - 0x448 */ |
135 | e3260506 | Peter A. G. Crosthwaite | uint32_t tz_misc[3]; /* 0x450 - 0x458 */ |
136 | e3260506 | Peter A. G. Crosthwaite | uint32_t tz_fpga[2]; /* 0x484 - 0x488 */ |
137 | e3260506 | Peter A. G. Crosthwaite | uint32_t dbg_ctrl; /* 0x500 */
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138 | e3260506 | Peter A. G. Crosthwaite | uint32_t pss_idcode; /* 0x530 */
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139 | e3260506 | Peter A. G. Crosthwaite | uint32_t ddr[8]; /* 0x600 - 0x620 - 0x604-missing */ |
140 | e3260506 | Peter A. G. Crosthwaite | uint32_t mio[54]; /* 0x700 - 0x7D4 */ |
141 | e3260506 | Peter A. G. Crosthwaite | uint32_t mio_func[4]; /* 0x800 - 0x810 */ |
142 | e3260506 | Peter A. G. Crosthwaite | uint32_t sd[2]; /* 0x830 - 0x834 */ |
143 | e3260506 | Peter A. G. Crosthwaite | uint32_t lvl_shftr_en; /* 0x900 */
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144 | e3260506 | Peter A. G. Crosthwaite | uint32_t ocm_cfg; /* 0x910 */
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145 | e3260506 | Peter A. G. Crosthwaite | uint32_t cpu_ram[8]; /* 0xA00 - 0xA1C */ |
146 | e3260506 | Peter A. G. Crosthwaite | uint32_t iou[7]; /* 0xA30 - 0xA48 */ |
147 | e3260506 | Peter A. G. Crosthwaite | uint32_t dmac_ram; /* 0xA50 */
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148 | e3260506 | Peter A. G. Crosthwaite | uint32_t afi[4][3]; /* 0xA60 - 0xA8C */ |
149 | e3260506 | Peter A. G. Crosthwaite | uint32_t ocm[3]; /* 0xA90 - 0xA98 */ |
150 | e3260506 | Peter A. G. Crosthwaite | uint32_t devci_ram; /* 0xAA0 */
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151 | e3260506 | Peter A. G. Crosthwaite | uint32_t csg_ram; /* 0xAB0 */
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152 | e3260506 | Peter A. G. Crosthwaite | uint32_t gpiob[12]; /* 0xB00 - 0xB2C */ |
153 | e3260506 | Peter A. G. Crosthwaite | uint32_t ddriob[14]; /* 0xB40 - 0xB74 */ |
154 | e3260506 | Peter A. G. Crosthwaite | }; |
155 | e3260506 | Peter A. G. Crosthwaite | uint8_t data[0x1000];
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156 | e3260506 | Peter A. G. Crosthwaite | }; |
157 | e3260506 | Peter A. G. Crosthwaite | } ZynqSLCRState; |
158 | e3260506 | Peter A. G. Crosthwaite | |
159 | e3260506 | Peter A. G. Crosthwaite | static void zynq_slcr_reset(DeviceState *d) |
160 | e3260506 | Peter A. G. Crosthwaite | { |
161 | e3260506 | Peter A. G. Crosthwaite | int i;
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162 | e3260506 | Peter A. G. Crosthwaite | ZynqSLCRState *s = |
163 | e3260506 | Peter A. G. Crosthwaite | FROM_SYSBUS(ZynqSLCRState, sysbus_from_qdev(d)); |
164 | e3260506 | Peter A. G. Crosthwaite | |
165 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("RESET\n");
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166 | e3260506 | Peter A. G. Crosthwaite | |
167 | e3260506 | Peter A. G. Crosthwaite | s->lockval = 1;
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168 | e3260506 | Peter A. G. Crosthwaite | /* 0x100 - 0x11C */
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169 | e3260506 | Peter A. G. Crosthwaite | s->pll[ARM_PLL_CTRL] = 0x0001A008;
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170 | e3260506 | Peter A. G. Crosthwaite | s->pll[DDR_PLL_CTRL] = 0x0001A008;
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171 | e3260506 | Peter A. G. Crosthwaite | s->pll[IO_PLL_CTRL] = 0x0001A008;
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172 | e3260506 | Peter A. G. Crosthwaite | s->pll[PLL_STATUS] = 0x0000003F;
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173 | e3260506 | Peter A. G. Crosthwaite | s->pll[ARM_PPL_CFG] = 0x00014000;
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174 | e3260506 | Peter A. G. Crosthwaite | s->pll[DDR_PLL_CFG] = 0x00014000;
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175 | e3260506 | Peter A. G. Crosthwaite | s->pll[IO_PLL_CFG] = 0x00014000;
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176 | e3260506 | Peter A. G. Crosthwaite | |
177 | e3260506 | Peter A. G. Crosthwaite | /* 0x120 - 0x16C */
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178 | e3260506 | Peter A. G. Crosthwaite | s->clk[ARM_CLK_CTRL] = 0x1F000400;
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179 | e3260506 | Peter A. G. Crosthwaite | s->clk[DDR_CLK_CTRL] = 0x18400003;
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180 | e3260506 | Peter A. G. Crosthwaite | s->clk[DCI_CLK_CTRL] = 0x01E03201;
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181 | e3260506 | Peter A. G. Crosthwaite | s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
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182 | e3260506 | Peter A. G. Crosthwaite | s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
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183 | e3260506 | Peter A. G. Crosthwaite | s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
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184 | e3260506 | Peter A. G. Crosthwaite | s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
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185 | e3260506 | Peter A. G. Crosthwaite | s->clk[SMC_CLK_CTRL] = 0x00003C01;
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186 | e3260506 | Peter A. G. Crosthwaite | s->clk[LQSPI_CLK_CTRL] = 0x00002821;
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187 | e3260506 | Peter A. G. Crosthwaite | s->clk[SDIO_CLK_CTRL] = 0x00001E03;
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188 | e3260506 | Peter A. G. Crosthwaite | s->clk[UART_CLK_CTRL] = 0x00003F03;
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189 | e3260506 | Peter A. G. Crosthwaite | s->clk[SPI_CLK_CTRL] = 0x00003F03;
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190 | e3260506 | Peter A. G. Crosthwaite | s->clk[CAN_CLK_CTRL] = 0x00501903;
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191 | e3260506 | Peter A. G. Crosthwaite | s->clk[DBG_CLK_CTRL] = 0x00000F03;
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192 | e3260506 | Peter A. G. Crosthwaite | s->clk[PCAP_CLK_CTRL] = 0x00000F01;
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193 | e3260506 | Peter A. G. Crosthwaite | |
194 | e3260506 | Peter A. G. Crosthwaite | /* 0x170 - 0x1AC */
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195 | e3260506 | Peter A. G. Crosthwaite | s->fpga[0][CLK_CTRL] = s->fpga[1][CLK_CTRL] = s->fpga[2][CLK_CTRL] = |
196 | e3260506 | Peter A. G. Crosthwaite | s->fpga[3][CLK_CTRL] = 0x00101800; |
197 | e3260506 | Peter A. G. Crosthwaite | s->fpga[0][THR_STA] = s->fpga[1][THR_STA] = s->fpga[2][THR_STA] = |
198 | e3260506 | Peter A. G. Crosthwaite | s->fpga[3][THR_STA] = 0x00010000; |
199 | e3260506 | Peter A. G. Crosthwaite | |
200 | e3260506 | Peter A. G. Crosthwaite | /* 0x1B0 - 0x1D8 */
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201 | e3260506 | Peter A. G. Crosthwaite | s->misc[BANDGAP_TRIP] = 0x0000001F;
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202 | e3260506 | Peter A. G. Crosthwaite | s->misc[PLL_PREDIVISOR] = 0x00000001;
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203 | e3260506 | Peter A. G. Crosthwaite | s->misc[CLK_621_TRUE] = 0x00000001;
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204 | e3260506 | Peter A. G. Crosthwaite | |
205 | e3260506 | Peter A. G. Crosthwaite | /* 0x200 - 0x25C */
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206 | e3260506 | Peter A. G. Crosthwaite | s->reset[FPGA] = 0x01F33F0F;
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207 | e3260506 | Peter A. G. Crosthwaite | s->reset[RST_REASON] = 0x00000040;
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208 | e3260506 | Peter A. G. Crosthwaite | |
209 | e3260506 | Peter A. G. Crosthwaite | /* 0x700 - 0x7D4 */
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210 | e3260506 | Peter A. G. Crosthwaite | for (i = 0; i < 54; i++) { |
211 | e3260506 | Peter A. G. Crosthwaite | s->mio[i] = 0x00001601;
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212 | e3260506 | Peter A. G. Crosthwaite | } |
213 | e3260506 | Peter A. G. Crosthwaite | for (i = 2; i <= 8; i++) { |
214 | e3260506 | Peter A. G. Crosthwaite | s->mio[i] = 0x00000601;
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215 | e3260506 | Peter A. G. Crosthwaite | } |
216 | e3260506 | Peter A. G. Crosthwaite | |
217 | e3260506 | Peter A. G. Crosthwaite | /* MIO_MST_TRI0, MIO_MST_TRI1 */
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218 | e3260506 | Peter A. G. Crosthwaite | s->mio_func[2] = s->mio_func[3] = 0xFFFFFFFF; |
219 | e3260506 | Peter A. G. Crosthwaite | |
220 | e3260506 | Peter A. G. Crosthwaite | s->cpu_ram[0] = s->cpu_ram[1] = s->cpu_ram[3] = |
221 | e3260506 | Peter A. G. Crosthwaite | s->cpu_ram[4] = s->cpu_ram[7] = 0x00010101; |
222 | e3260506 | Peter A. G. Crosthwaite | s->cpu_ram[2] = s->cpu_ram[5] = 0x01010101; |
223 | e3260506 | Peter A. G. Crosthwaite | s->cpu_ram[6] = 0x00000001; |
224 | e3260506 | Peter A. G. Crosthwaite | |
225 | e3260506 | Peter A. G. Crosthwaite | s->iou[0] = s->iou[1] = s->iou[2] = s->iou[3] = 0x09090909; |
226 | e3260506 | Peter A. G. Crosthwaite | s->iou[4] = s->iou[5] = 0x00090909; |
227 | e3260506 | Peter A. G. Crosthwaite | s->iou[6] = 0x00000909; |
228 | e3260506 | Peter A. G. Crosthwaite | |
229 | e3260506 | Peter A. G. Crosthwaite | s->dmac_ram = 0x00000009;
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230 | e3260506 | Peter A. G. Crosthwaite | |
231 | e3260506 | Peter A. G. Crosthwaite | s->afi[0][0] = s->afi[0][1] = 0x09090909; |
232 | e3260506 | Peter A. G. Crosthwaite | s->afi[1][0] = s->afi[1][1] = 0x09090909; |
233 | e3260506 | Peter A. G. Crosthwaite | s->afi[2][0] = s->afi[2][1] = 0x09090909; |
234 | e3260506 | Peter A. G. Crosthwaite | s->afi[3][0] = s->afi[3][1] = 0x09090909; |
235 | e3260506 | Peter A. G. Crosthwaite | s->afi[0][2] = s->afi[1][2] = s->afi[2][2] = s->afi[3][2] = 0x00000909; |
236 | e3260506 | Peter A. G. Crosthwaite | |
237 | e3260506 | Peter A. G. Crosthwaite | s->ocm[0] = 0x01010101; |
238 | e3260506 | Peter A. G. Crosthwaite | s->ocm[1] = s->ocm[2] = 0x09090909; |
239 | e3260506 | Peter A. G. Crosthwaite | |
240 | e3260506 | Peter A. G. Crosthwaite | s->devci_ram = 0x00000909;
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241 | e3260506 | Peter A. G. Crosthwaite | s->csg_ram = 0x00000001;
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242 | e3260506 | Peter A. G. Crosthwaite | |
243 | e3260506 | Peter A. G. Crosthwaite | s->ddriob[0] = s->ddriob[1] = s->ddriob[2] = s->ddriob[3] = 0x00000e00; |
244 | e3260506 | Peter A. G. Crosthwaite | s->ddriob[4] = s->ddriob[5] = s->ddriob[6] = 0x00000e00; |
245 | e3260506 | Peter A. G. Crosthwaite | s->ddriob[12] = 0x00000021; |
246 | e3260506 | Peter A. G. Crosthwaite | } |
247 | e3260506 | Peter A. G. Crosthwaite | |
248 | e3260506 | Peter A. G. Crosthwaite | static inline uint32_t zynq_slcr_read_imp(void *opaque, |
249 | e3260506 | Peter A. G. Crosthwaite | target_phys_addr_t offset) |
250 | e3260506 | Peter A. G. Crosthwaite | { |
251 | e3260506 | Peter A. G. Crosthwaite | ZynqSLCRState *s = (ZynqSLCRState *)opaque; |
252 | e3260506 | Peter A. G. Crosthwaite | |
253 | e3260506 | Peter A. G. Crosthwaite | switch (offset) {
|
254 | e3260506 | Peter A. G. Crosthwaite | case 0x0: /* SCL */ |
255 | e3260506 | Peter A. G. Crosthwaite | return s->scl;
|
256 | e3260506 | Peter A. G. Crosthwaite | case 0x4: /* LOCK */ |
257 | e3260506 | Peter A. G. Crosthwaite | case 0x8: /* UNLOCK */ |
258 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("Reading SCLR_LOCK/UNLOCK is not enabled\n");
|
259 | e3260506 | Peter A. G. Crosthwaite | return 0; |
260 | e3260506 | Peter A. G. Crosthwaite | case 0x0C: /* LOCKSTA */ |
261 | e3260506 | Peter A. G. Crosthwaite | return s->lockval;
|
262 | e3260506 | Peter A. G. Crosthwaite | case 0x100 ... 0x11C: |
263 | e3260506 | Peter A. G. Crosthwaite | return s->pll[(offset - 0x100) / 4]; |
264 | e3260506 | Peter A. G. Crosthwaite | case 0x120 ... 0x16C: |
265 | e3260506 | Peter A. G. Crosthwaite | return s->clk[(offset - 0x120) / 4]; |
266 | e3260506 | Peter A. G. Crosthwaite | case 0x170 ... 0x1AC: |
267 | e3260506 | Peter A. G. Crosthwaite | return s->fpga[0][(offset - 0x170) / 4]; |
268 | e3260506 | Peter A. G. Crosthwaite | case 0x1B0 ... 0x1D8: |
269 | e3260506 | Peter A. G. Crosthwaite | return s->misc[(offset - 0x1B0) / 4]; |
270 | e3260506 | Peter A. G. Crosthwaite | case 0x200 ... 0x258: |
271 | e3260506 | Peter A. G. Crosthwaite | return s->reset[(offset - 0x200) / 4]; |
272 | e3260506 | Peter A. G. Crosthwaite | case 0x25c: |
273 | e3260506 | Peter A. G. Crosthwaite | return 1; |
274 | e3260506 | Peter A. G. Crosthwaite | case 0x300: |
275 | e3260506 | Peter A. G. Crosthwaite | return s->apu_ctrl;
|
276 | e3260506 | Peter A. G. Crosthwaite | case 0x304: |
277 | e3260506 | Peter A. G. Crosthwaite | return s->wdt_clk_sel;
|
278 | e3260506 | Peter A. G. Crosthwaite | case 0x400 ... 0x408: |
279 | e3260506 | Peter A. G. Crosthwaite | return s->tz_ocm[(offset - 0x400) / 4]; |
280 | e3260506 | Peter A. G. Crosthwaite | case 0x430: |
281 | e3260506 | Peter A. G. Crosthwaite | return s->tz_ddr;
|
282 | e3260506 | Peter A. G. Crosthwaite | case 0x440 ... 0x448: |
283 | e3260506 | Peter A. G. Crosthwaite | return s->tz_dma[(offset - 0x440) / 4]; |
284 | e3260506 | Peter A. G. Crosthwaite | case 0x450 ... 0x458: |
285 | e3260506 | Peter A. G. Crosthwaite | return s->tz_misc[(offset - 0x450) / 4]; |
286 | e3260506 | Peter A. G. Crosthwaite | case 0x484 ... 0x488: |
287 | e3260506 | Peter A. G. Crosthwaite | return s->tz_fpga[(offset - 0x484) / 4]; |
288 | e3260506 | Peter A. G. Crosthwaite | case 0x500: |
289 | e3260506 | Peter A. G. Crosthwaite | return s->dbg_ctrl;
|
290 | e3260506 | Peter A. G. Crosthwaite | case 0x530: |
291 | e3260506 | Peter A. G. Crosthwaite | return s->pss_idcode;
|
292 | e3260506 | Peter A. G. Crosthwaite | case 0x600 ... 0x620: |
293 | e3260506 | Peter A. G. Crosthwaite | if (offset == 0x604) { |
294 | e3260506 | Peter A. G. Crosthwaite | goto bad_reg;
|
295 | e3260506 | Peter A. G. Crosthwaite | } |
296 | e3260506 | Peter A. G. Crosthwaite | return s->ddr[(offset - 0x600) / 4]; |
297 | e3260506 | Peter A. G. Crosthwaite | case 0x700 ... 0x7D4: |
298 | e3260506 | Peter A. G. Crosthwaite | return s->mio[(offset - 0x700) / 4]; |
299 | e3260506 | Peter A. G. Crosthwaite | case 0x800 ... 0x810: |
300 | e3260506 | Peter A. G. Crosthwaite | return s->mio_func[(offset - 0x800) / 4]; |
301 | e3260506 | Peter A. G. Crosthwaite | case 0x830 ... 0x834: |
302 | e3260506 | Peter A. G. Crosthwaite | return s->sd[(offset - 0x830) / 4]; |
303 | e3260506 | Peter A. G. Crosthwaite | case 0x900: |
304 | e3260506 | Peter A. G. Crosthwaite | return s->lvl_shftr_en;
|
305 | e3260506 | Peter A. G. Crosthwaite | case 0x910: |
306 | e3260506 | Peter A. G. Crosthwaite | return s->ocm_cfg;
|
307 | e3260506 | Peter A. G. Crosthwaite | case 0xA00 ... 0xA1C: |
308 | e3260506 | Peter A. G. Crosthwaite | return s->cpu_ram[(offset - 0xA00) / 4]; |
309 | e3260506 | Peter A. G. Crosthwaite | case 0xA30 ... 0xA48: |
310 | e3260506 | Peter A. G. Crosthwaite | return s->iou[(offset - 0xA30) / 4]; |
311 | e3260506 | Peter A. G. Crosthwaite | case 0xA50: |
312 | e3260506 | Peter A. G. Crosthwaite | return s->dmac_ram;
|
313 | e3260506 | Peter A. G. Crosthwaite | case 0xA60 ... 0xA8C: |
314 | 0d10f627 | Anthony Liguori | return s->afi[0][(offset - 0xA60) / 4]; |
315 | e3260506 | Peter A. G. Crosthwaite | case 0xA90 ... 0xA98: |
316 | e3260506 | Peter A. G. Crosthwaite | return s->ocm[(offset - 0xA90) / 4]; |
317 | e3260506 | Peter A. G. Crosthwaite | case 0xAA0: |
318 | e3260506 | Peter A. G. Crosthwaite | return s->devci_ram;
|
319 | e3260506 | Peter A. G. Crosthwaite | case 0xAB0: |
320 | e3260506 | Peter A. G. Crosthwaite | return s->csg_ram;
|
321 | e3260506 | Peter A. G. Crosthwaite | case 0xB00 ... 0xB2C: |
322 | e3260506 | Peter A. G. Crosthwaite | return s->gpiob[(offset - 0xB00) / 4]; |
323 | e3260506 | Peter A. G. Crosthwaite | case 0xB40 ... 0xB74: |
324 | e3260506 | Peter A. G. Crosthwaite | return s->ddriob[(offset - 0xB40) / 4]; |
325 | e3260506 | Peter A. G. Crosthwaite | default:
|
326 | e3260506 | Peter A. G. Crosthwaite | bad_reg:
|
327 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("Bad register offset 0x%x\n", (int)offset); |
328 | e3260506 | Peter A. G. Crosthwaite | return 0; |
329 | e3260506 | Peter A. G. Crosthwaite | } |
330 | e3260506 | Peter A. G. Crosthwaite | } |
331 | e3260506 | Peter A. G. Crosthwaite | |
332 | e3260506 | Peter A. G. Crosthwaite | static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset, |
333 | e3260506 | Peter A. G. Crosthwaite | unsigned size)
|
334 | e3260506 | Peter A. G. Crosthwaite | { |
335 | e3260506 | Peter A. G. Crosthwaite | uint32_t ret = zynq_slcr_read_imp(opaque, offset); |
336 | e3260506 | Peter A. G. Crosthwaite | |
337 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("addr: %08x data: %08x\n", offset, ret);
|
338 | e3260506 | Peter A. G. Crosthwaite | return ret;
|
339 | e3260506 | Peter A. G. Crosthwaite | } |
340 | e3260506 | Peter A. G. Crosthwaite | |
341 | e3260506 | Peter A. G. Crosthwaite | static void zynq_slcr_write(void *opaque, target_phys_addr_t offset, |
342 | e3260506 | Peter A. G. Crosthwaite | uint64_t val, unsigned size)
|
343 | e3260506 | Peter A. G. Crosthwaite | { |
344 | e3260506 | Peter A. G. Crosthwaite | ZynqSLCRState *s = (ZynqSLCRState *)opaque; |
345 | e3260506 | Peter A. G. Crosthwaite | |
346 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val); |
347 | e3260506 | Peter A. G. Crosthwaite | |
348 | e3260506 | Peter A. G. Crosthwaite | switch (offset) {
|
349 | e3260506 | Peter A. G. Crosthwaite | case 0x00: /* SCL */ |
350 | e3260506 | Peter A. G. Crosthwaite | s->scl = val & 0x1;
|
351 | e3260506 | Peter A. G. Crosthwaite | return;
|
352 | e3260506 | Peter A. G. Crosthwaite | case 0x4: /* SLCR_LOCK */ |
353 | e3260506 | Peter A. G. Crosthwaite | if ((val & 0xFFFF) == XILINX_LOCK_KEY) { |
354 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
355 | e3260506 | Peter A. G. Crosthwaite | (unsigned)val & 0xFFFF); |
356 | e3260506 | Peter A. G. Crosthwaite | s->lockval = 1;
|
357 | e3260506 | Peter A. G. Crosthwaite | } else {
|
358 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
359 | e3260506 | Peter A. G. Crosthwaite | (int)offset, (unsigned)val & 0xFFFF); |
360 | e3260506 | Peter A. G. Crosthwaite | } |
361 | e3260506 | Peter A. G. Crosthwaite | return;
|
362 | e3260506 | Peter A. G. Crosthwaite | case 0x8: /* SLCR_UNLOCK */ |
363 | e3260506 | Peter A. G. Crosthwaite | if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { |
364 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, |
365 | e3260506 | Peter A. G. Crosthwaite | (unsigned)val & 0xFFFF); |
366 | e3260506 | Peter A. G. Crosthwaite | s->lockval = 0;
|
367 | e3260506 | Peter A. G. Crosthwaite | } else {
|
368 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
369 | e3260506 | Peter A. G. Crosthwaite | (int)offset, (unsigned)val & 0xFFFF); |
370 | e3260506 | Peter A. G. Crosthwaite | } |
371 | e3260506 | Peter A. G. Crosthwaite | return;
|
372 | e3260506 | Peter A. G. Crosthwaite | case 0xc: /* LOCKSTA */ |
373 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("Writing SCLR_LOCKSTA is not enabled\n");
|
374 | e3260506 | Peter A. G. Crosthwaite | return;
|
375 | e3260506 | Peter A. G. Crosthwaite | } |
376 | e3260506 | Peter A. G. Crosthwaite | |
377 | e3260506 | Peter A. G. Crosthwaite | if (!s->lockval) {
|
378 | e3260506 | Peter A. G. Crosthwaite | switch (offset) {
|
379 | e3260506 | Peter A. G. Crosthwaite | case 0x100 ... 0x11C: |
380 | e3260506 | Peter A. G. Crosthwaite | if (offset == 0x10C) { |
381 | e3260506 | Peter A. G. Crosthwaite | goto bad_reg;
|
382 | e3260506 | Peter A. G. Crosthwaite | } |
383 | e3260506 | Peter A. G. Crosthwaite | s->pll[(offset - 0x100) / 4] = val; |
384 | e3260506 | Peter A. G. Crosthwaite | break;
|
385 | e3260506 | Peter A. G. Crosthwaite | case 0x120 ... 0x16C: |
386 | e3260506 | Peter A. G. Crosthwaite | s->clk[(offset - 0x120) / 4] = val; |
387 | e3260506 | Peter A. G. Crosthwaite | break;
|
388 | e3260506 | Peter A. G. Crosthwaite | case 0x170 ... 0x1AC: |
389 | e3260506 | Peter A. G. Crosthwaite | s->fpga[0][(offset - 0x170) / 4] = val; |
390 | e3260506 | Peter A. G. Crosthwaite | break;
|
391 | e3260506 | Peter A. G. Crosthwaite | case 0x1B0 ... 0x1D8: |
392 | e3260506 | Peter A. G. Crosthwaite | s->misc[(offset - 0x1B0) / 4] = val; |
393 | e3260506 | Peter A. G. Crosthwaite | break;
|
394 | e3260506 | Peter A. G. Crosthwaite | case 0x200 ... 0x25C: |
395 | e3260506 | Peter A. G. Crosthwaite | if (offset == 0x250) { |
396 | e3260506 | Peter A. G. Crosthwaite | goto bad_reg;
|
397 | e3260506 | Peter A. G. Crosthwaite | } |
398 | e3260506 | Peter A. G. Crosthwaite | s->reset[(offset - 0x200) / 4] = val; |
399 | e3260506 | Peter A. G. Crosthwaite | break;
|
400 | e3260506 | Peter A. G. Crosthwaite | case 0x300: |
401 | e3260506 | Peter A. G. Crosthwaite | s->apu_ctrl = val; |
402 | e3260506 | Peter A. G. Crosthwaite | break;
|
403 | e3260506 | Peter A. G. Crosthwaite | case 0x304: |
404 | e3260506 | Peter A. G. Crosthwaite | s->wdt_clk_sel = val; |
405 | e3260506 | Peter A. G. Crosthwaite | break;
|
406 | e3260506 | Peter A. G. Crosthwaite | case 0x400 ... 0x408: |
407 | e3260506 | Peter A. G. Crosthwaite | s->tz_ocm[(offset - 0x400) / 4] = val; |
408 | e3260506 | Peter A. G. Crosthwaite | break;
|
409 | e3260506 | Peter A. G. Crosthwaite | case 0x430: |
410 | e3260506 | Peter A. G. Crosthwaite | s->tz_ddr = val; |
411 | e3260506 | Peter A. G. Crosthwaite | break;
|
412 | e3260506 | Peter A. G. Crosthwaite | case 0x440 ... 0x448: |
413 | e3260506 | Peter A. G. Crosthwaite | s->tz_dma[(offset - 0x440) / 4] = val; |
414 | e3260506 | Peter A. G. Crosthwaite | break;
|
415 | e3260506 | Peter A. G. Crosthwaite | case 0x450 ... 0x458: |
416 | e3260506 | Peter A. G. Crosthwaite | s->tz_misc[(offset - 0x450) / 4] = val; |
417 | e3260506 | Peter A. G. Crosthwaite | break;
|
418 | e3260506 | Peter A. G. Crosthwaite | case 0x484 ... 0x488: |
419 | e3260506 | Peter A. G. Crosthwaite | s->tz_fpga[(offset - 0x484) / 4] = val; |
420 | e3260506 | Peter A. G. Crosthwaite | break;
|
421 | e3260506 | Peter A. G. Crosthwaite | case 0x500: |
422 | e3260506 | Peter A. G. Crosthwaite | s->dbg_ctrl = val; |
423 | e3260506 | Peter A. G. Crosthwaite | break;
|
424 | e3260506 | Peter A. G. Crosthwaite | case 0x530: |
425 | e3260506 | Peter A. G. Crosthwaite | s->pss_idcode = val; |
426 | e3260506 | Peter A. G. Crosthwaite | break;
|
427 | e3260506 | Peter A. G. Crosthwaite | case 0x600 ... 0x620: |
428 | e3260506 | Peter A. G. Crosthwaite | if (offset == 0x604) { |
429 | e3260506 | Peter A. G. Crosthwaite | goto bad_reg;
|
430 | e3260506 | Peter A. G. Crosthwaite | } |
431 | e3260506 | Peter A. G. Crosthwaite | s->ddr[(offset - 0x600) / 4] = val; |
432 | e3260506 | Peter A. G. Crosthwaite | break;
|
433 | e3260506 | Peter A. G. Crosthwaite | case 0x700 ... 0x7D4: |
434 | e3260506 | Peter A. G. Crosthwaite | s->mio[(offset - 0x700) / 4] = val; |
435 | e3260506 | Peter A. G. Crosthwaite | break;
|
436 | e3260506 | Peter A. G. Crosthwaite | case 0x800 ... 0x810: |
437 | e3260506 | Peter A. G. Crosthwaite | s->mio_func[(offset - 0x800) / 4] = val; |
438 | e3260506 | Peter A. G. Crosthwaite | break;
|
439 | e3260506 | Peter A. G. Crosthwaite | case 0x830 ... 0x834: |
440 | e3260506 | Peter A. G. Crosthwaite | s->sd[(offset - 0x830) / 4] = val; |
441 | e3260506 | Peter A. G. Crosthwaite | break;
|
442 | e3260506 | Peter A. G. Crosthwaite | case 0x900: |
443 | e3260506 | Peter A. G. Crosthwaite | s->lvl_shftr_en = val; |
444 | e3260506 | Peter A. G. Crosthwaite | break;
|
445 | e3260506 | Peter A. G. Crosthwaite | case 0x910: |
446 | e3260506 | Peter A. G. Crosthwaite | break;
|
447 | e3260506 | Peter A. G. Crosthwaite | case 0xA00 ... 0xA1C: |
448 | e3260506 | Peter A. G. Crosthwaite | s->cpu_ram[(offset - 0xA00) / 4] = val; |
449 | e3260506 | Peter A. G. Crosthwaite | break;
|
450 | e3260506 | Peter A. G. Crosthwaite | case 0xA30 ... 0xA48: |
451 | e3260506 | Peter A. G. Crosthwaite | s->iou[(offset - 0xA30) / 4] = val; |
452 | e3260506 | Peter A. G. Crosthwaite | break;
|
453 | e3260506 | Peter A. G. Crosthwaite | case 0xA50: |
454 | e3260506 | Peter A. G. Crosthwaite | s->dmac_ram = val; |
455 | e3260506 | Peter A. G. Crosthwaite | break;
|
456 | e3260506 | Peter A. G. Crosthwaite | case 0xA60 ... 0xA8C: |
457 | 0d10f627 | Anthony Liguori | s->afi[0][(offset - 0xA60) / 4] = val; |
458 | e3260506 | Peter A. G. Crosthwaite | break;
|
459 | e3260506 | Peter A. G. Crosthwaite | case 0xA90: |
460 | e3260506 | Peter A. G. Crosthwaite | s->ocm[0] = val;
|
461 | e3260506 | Peter A. G. Crosthwaite | break;
|
462 | e3260506 | Peter A. G. Crosthwaite | case 0xAA0: |
463 | e3260506 | Peter A. G. Crosthwaite | s->devci_ram = val; |
464 | e3260506 | Peter A. G. Crosthwaite | break;
|
465 | e3260506 | Peter A. G. Crosthwaite | case 0xAB0: |
466 | e3260506 | Peter A. G. Crosthwaite | s->csg_ram = val; |
467 | e3260506 | Peter A. G. Crosthwaite | break;
|
468 | e3260506 | Peter A. G. Crosthwaite | case 0xB00 ... 0xB2C: |
469 | e3260506 | Peter A. G. Crosthwaite | if (offset == 0xB20 || offset == 0xB2C) { |
470 | e3260506 | Peter A. G. Crosthwaite | goto bad_reg;
|
471 | e3260506 | Peter A. G. Crosthwaite | } |
472 | e3260506 | Peter A. G. Crosthwaite | s->gpiob[(offset - 0xB00) / 4] = val; |
473 | e3260506 | Peter A. G. Crosthwaite | break;
|
474 | e3260506 | Peter A. G. Crosthwaite | case 0xB40 ... 0xB74: |
475 | e3260506 | Peter A. G. Crosthwaite | s->ddriob[(offset - 0xB40) / 4] = val; |
476 | e3260506 | Peter A. G. Crosthwaite | break;
|
477 | e3260506 | Peter A. G. Crosthwaite | default:
|
478 | e3260506 | Peter A. G. Crosthwaite | bad_reg:
|
479 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("Bad register write %x <= %08x\n", (int)offset, val); |
480 | e3260506 | Peter A. G. Crosthwaite | } |
481 | e3260506 | Peter A. G. Crosthwaite | } else {
|
482 | e3260506 | Peter A. G. Crosthwaite | DB_PRINT("SCLR registers are locked. Unlock them first\n");
|
483 | e3260506 | Peter A. G. Crosthwaite | } |
484 | e3260506 | Peter A. G. Crosthwaite | } |
485 | e3260506 | Peter A. G. Crosthwaite | |
486 | e3260506 | Peter A. G. Crosthwaite | static const MemoryRegionOps slcr_ops = { |
487 | e3260506 | Peter A. G. Crosthwaite | .read = zynq_slcr_read, |
488 | e3260506 | Peter A. G. Crosthwaite | .write = zynq_slcr_write, |
489 | e3260506 | Peter A. G. Crosthwaite | .endianness = DEVICE_NATIVE_ENDIAN, |
490 | e3260506 | Peter A. G. Crosthwaite | }; |
491 | e3260506 | Peter A. G. Crosthwaite | |
492 | e3260506 | Peter A. G. Crosthwaite | static int zynq_slcr_init(SysBusDevice *dev) |
493 | e3260506 | Peter A. G. Crosthwaite | { |
494 | e3260506 | Peter A. G. Crosthwaite | ZynqSLCRState *s = FROM_SYSBUS(ZynqSLCRState, dev); |
495 | e3260506 | Peter A. G. Crosthwaite | |
496 | e3260506 | Peter A. G. Crosthwaite | memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000); |
497 | e3260506 | Peter A. G. Crosthwaite | sysbus_init_mmio(dev, &s->iomem); |
498 | e3260506 | Peter A. G. Crosthwaite | |
499 | e3260506 | Peter A. G. Crosthwaite | return 0; |
500 | e3260506 | Peter A. G. Crosthwaite | } |
501 | e3260506 | Peter A. G. Crosthwaite | |
502 | e3260506 | Peter A. G. Crosthwaite | static const VMStateDescription vmstate_zynq_slcr = { |
503 | e3260506 | Peter A. G. Crosthwaite | .name = "zynq_slcr",
|
504 | e3260506 | Peter A. G. Crosthwaite | .version_id = 1,
|
505 | e3260506 | Peter A. G. Crosthwaite | .minimum_version_id = 1,
|
506 | e3260506 | Peter A. G. Crosthwaite | .minimum_version_id_old = 1,
|
507 | e3260506 | Peter A. G. Crosthwaite | .fields = (VMStateField[]) { |
508 | e3260506 | Peter A. G. Crosthwaite | VMSTATE_UINT8_ARRAY(data, ZynqSLCRState, 0x1000),
|
509 | e3260506 | Peter A. G. Crosthwaite | VMSTATE_END_OF_LIST() |
510 | e3260506 | Peter A. G. Crosthwaite | } |
511 | e3260506 | Peter A. G. Crosthwaite | }; |
512 | e3260506 | Peter A. G. Crosthwaite | |
513 | e3260506 | Peter A. G. Crosthwaite | static void zynq_slcr_class_init(ObjectClass *klass, void *data) |
514 | e3260506 | Peter A. G. Crosthwaite | { |
515 | e3260506 | Peter A. G. Crosthwaite | DeviceClass *dc = DEVICE_CLASS(klass); |
516 | e3260506 | Peter A. G. Crosthwaite | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
517 | e3260506 | Peter A. G. Crosthwaite | |
518 | e3260506 | Peter A. G. Crosthwaite | sdc->init = zynq_slcr_init; |
519 | e3260506 | Peter A. G. Crosthwaite | dc->vmsd = &vmstate_zynq_slcr; |
520 | e3260506 | Peter A. G. Crosthwaite | dc->reset = zynq_slcr_reset; |
521 | e3260506 | Peter A. G. Crosthwaite | } |
522 | e3260506 | Peter A. G. Crosthwaite | |
523 | e3260506 | Peter A. G. Crosthwaite | static TypeInfo zynq_slcr_info = {
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524 | e3260506 | Peter A. G. Crosthwaite | .class_init = zynq_slcr_class_init, |
525 | e3260506 | Peter A. G. Crosthwaite | .name = "xilinx,zynq_slcr",
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526 | e3260506 | Peter A. G. Crosthwaite | .parent = TYPE_SYS_BUS_DEVICE, |
527 | e3260506 | Peter A. G. Crosthwaite | .instance_size = sizeof(ZynqSLCRState),
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528 | e3260506 | Peter A. G. Crosthwaite | }; |
529 | e3260506 | Peter A. G. Crosthwaite | |
530 | e3260506 | Peter A. G. Crosthwaite | static void zynq_slcr_register_types(void) |
531 | e3260506 | Peter A. G. Crosthwaite | { |
532 | e3260506 | Peter A. G. Crosthwaite | type_register_static(&zynq_slcr_info); |
533 | e3260506 | Peter A. G. Crosthwaite | } |
534 | e3260506 | Peter A. G. Crosthwaite | |
535 | e3260506 | Peter A. G. Crosthwaite | type_init(zynq_slcr_register_types) |