Revision 0ba365f4
| b/target-mips/dsp_helper.c | ||
|---|---|---|
| 19 | 19 |
|
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#include "cpu.h" |
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#include "helper.h" |
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#include "qemu/bitops.h" |
|
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|
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/* As the byte ordering doesn't matter, i.e. all columns are treated |
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identically, these unions can be used directly. */ |
| ... | ... | |
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dspc = env->active_tc.DSPControl; |
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#ifndef TARGET_MIPS64 |
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dspc = dspc & 0xFFFFFFC0; |
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dspc |= pos;
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|
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dspc |= (pos & 0x3F);
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|
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#else |
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dspc = dspc & 0xFFFFFF80; |
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dspc |= pos;
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|
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dspc |= (pos & 0x7F);
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|
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#endif |
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env->active_tc.DSPControl = dspc; |
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} |
| ... | ... | |
| 3439 | 3440 |
if (sub >= -1) {
|
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acc = ((uint64_t)env->active_tc.HI[ac] << 32) | |
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((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); |
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temp = (acc >> (start_pos - size)) & |
|
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(((uint32_t)0x01 << (size + 1)) - 1); |
|
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temp = extract64(acc, start_pos - size, size + 1); |
|
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|
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set_DSPControl_pos(start_pos - (size + 1), env);
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|
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set_DSPControl_pos(sub, env);
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|
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set_DSPControl_efi(0, env); |
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} else {
|
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set_DSPControl_efi(1, env); |
| b/tests/tcg/mips/mips32-dsp/extpdp.c | ||
|---|---|---|
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efi = (dsp >> 14) & 0x01; |
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assert(efi == 1); |
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|
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|
|
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ach = 0; |
|
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acl = 0; |
|
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dsp = 0; |
|
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result = 0; |
|
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|
|
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__asm |
|
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("wrdsp %1\n\t"
|
|
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"mthi %2, $ac1\n\t" |
|
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"mtlo %3, $ac1\n\t" |
|
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"extpdp %0, $ac1, 0x00\n\t" |
|
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"rddsp %1\n\t" |
|
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: "=r"(rt), "+r"(dsp) |
|
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: "r"(ach), "r"(acl) |
|
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); |
|
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assert(dsp == 0x3F); |
|
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assert(result == rt); |
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|
|
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return 0; |
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} |
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