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1 | 02645926 | balrog | /*
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2 | 02645926 | balrog | * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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3 | 02645926 | balrog | *
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4 | 02645926 | balrog | * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | 02645926 | balrog | *
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6 | 02645926 | balrog | * This program is free software; you can redistribute it and/or
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7 | 02645926 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 02645926 | balrog | * published by the Free Software Foundation; either version 2 of
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9 | 02645926 | balrog | * the License, or (at your option) any later version.
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10 | 02645926 | balrog | *
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11 | 02645926 | balrog | * This program is distributed in the hope that it will be useful,
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12 | 02645926 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 02645926 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 02645926 | balrog | * GNU General Public License for more details.
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15 | 02645926 | balrog | *
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16 | 02645926 | balrog | * You should have received a copy of the GNU General Public License
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17 | 02645926 | balrog | * along with this program; if not, write to the Free Software
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18 | 02645926 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | 02645926 | balrog | * MA 02111-1307 USA
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20 | 02645926 | balrog | */
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21 | 87ecb68b | pbrook | #include "hw.h" |
22 | 87ecb68b | pbrook | #include "i2c.h" |
23 | 87ecb68b | pbrook | #include "omap.h" |
24 | 02645926 | balrog | |
25 | 02645926 | balrog | struct omap_i2c_s {
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26 | 02645926 | balrog | qemu_irq irq; |
27 | 02645926 | balrog | qemu_irq drq[2];
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28 | 02645926 | balrog | i2c_slave slave; |
29 | 02645926 | balrog | i2c_bus *bus; |
30 | 02645926 | balrog | |
31 | 29885477 | balrog | uint8_t revision; |
32 | 02645926 | balrog | uint8_t mask; |
33 | 02645926 | balrog | uint16_t stat; |
34 | 02645926 | balrog | uint16_t dma; |
35 | 02645926 | balrog | uint16_t count; |
36 | 02645926 | balrog | int count_cur;
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37 | 02645926 | balrog | uint32_t fifo; |
38 | 02645926 | balrog | int rxlen;
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39 | 02645926 | balrog | int txlen;
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40 | 02645926 | balrog | uint16_t control; |
41 | 02645926 | balrog | uint16_t addr[2];
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42 | 02645926 | balrog | uint8_t divider; |
43 | 02645926 | balrog | uint8_t times[2];
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44 | 02645926 | balrog | uint16_t test; |
45 | 02645926 | balrog | }; |
46 | 02645926 | balrog | |
47 | 29885477 | balrog | #define OMAP2_INTR_REV 0x34 |
48 | 29885477 | balrog | #define OMAP2_GC_REV 0x34 |
49 | 29885477 | balrog | |
50 | 02645926 | balrog | static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
51 | 02645926 | balrog | { |
52 | 02645926 | balrog | qemu_set_irq(s->irq, s->stat & s->mask); |
53 | 02645926 | balrog | if ((s->dma >> 15) & 1) /* RDMA_EN */ |
54 | 02645926 | balrog | qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
55 | 02645926 | balrog | if ((s->dma >> 7) & 1) /* XDMA_EN */ |
56 | 02645926 | balrog | qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
57 | 02645926 | balrog | } |
58 | 02645926 | balrog | |
59 | 02645926 | balrog | /* These are only stubs now. */
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60 | 02645926 | balrog | static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event) |
61 | 02645926 | balrog | { |
62 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
63 | 02645926 | balrog | |
64 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
65 | 02645926 | balrog | return;
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66 | 02645926 | balrog | |
67 | 02645926 | balrog | switch (event) {
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68 | 02645926 | balrog | case I2C_START_SEND:
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69 | 02645926 | balrog | case I2C_START_RECV:
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70 | 02645926 | balrog | s->stat |= 1 << 9; /* AAS */ |
71 | 02645926 | balrog | break;
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72 | 02645926 | balrog | case I2C_FINISH:
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73 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
74 | 02645926 | balrog | break;
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75 | 02645926 | balrog | case I2C_NACK:
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76 | 02645926 | balrog | s->stat |= 1 << 1; /* NACK */ |
77 | 02645926 | balrog | break;
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78 | 02645926 | balrog | } |
79 | 02645926 | balrog | |
80 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
81 | 02645926 | balrog | } |
82 | 02645926 | balrog | |
83 | 02645926 | balrog | static int omap_i2c_rx(i2c_slave *i2c) |
84 | 02645926 | balrog | { |
85 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
86 | 02645926 | balrog | uint8_t ret = 0;
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87 | 02645926 | balrog | |
88 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
89 | 02645926 | balrog | return -1; |
90 | 02645926 | balrog | |
91 | 02645926 | balrog | if (s->txlen)
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92 | 02645926 | balrog | ret = s->fifo >> ((-- s->txlen) << 3) & 0xff; |
93 | 02645926 | balrog | else
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94 | 02645926 | balrog | s->stat |= 1 << 10; /* XUDF */ |
95 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
96 | 02645926 | balrog | |
97 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
98 | 02645926 | balrog | return ret;
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99 | 02645926 | balrog | } |
100 | 02645926 | balrog | |
101 | 02645926 | balrog | static int omap_i2c_tx(i2c_slave *i2c, uint8_t data) |
102 | 02645926 | balrog | { |
103 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
104 | 02645926 | balrog | |
105 | 02645926 | balrog | if ((~s->control >> 15) & 1) /* I2C_EN */ |
106 | 02645926 | balrog | return 1; |
107 | 02645926 | balrog | |
108 | 02645926 | balrog | if (s->rxlen < 4) |
109 | 02645926 | balrog | s->fifo |= data << ((s->rxlen ++) << 3);
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110 | 02645926 | balrog | else
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111 | 02645926 | balrog | s->stat |= 1 << 11; /* ROVR */ |
112 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
113 | 02645926 | balrog | |
114 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
115 | 02645926 | balrog | return 1; |
116 | 02645926 | balrog | } |
117 | 02645926 | balrog | |
118 | 02645926 | balrog | static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
119 | 02645926 | balrog | { |
120 | 02645926 | balrog | int ack = 1; |
121 | 02645926 | balrog | |
122 | 02645926 | balrog | if (!i2c_bus_busy(s->bus))
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123 | 02645926 | balrog | return;
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124 | 02645926 | balrog | |
125 | 02645926 | balrog | if ((s->control >> 2) & 1) { /* RM */ |
126 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
127 | 02645926 | balrog | i2c_end_transfer(s->bus); |
128 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
129 | 02645926 | balrog | s->count_cur = s->count; |
130 | 29885477 | balrog | s->txlen = 0;
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131 | 02645926 | balrog | } else if ((s->control >> 9) & 1) { /* TRX */ |
132 | 02645926 | balrog | while (ack && s->txlen)
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133 | 02645926 | balrog | ack = (i2c_send(s->bus, |
134 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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135 | 02645926 | balrog | 0xff) >= 0); |
136 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
137 | 02645926 | balrog | } else {
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138 | 02645926 | balrog | while (s->rxlen < 4) |
139 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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140 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
141 | 02645926 | balrog | } |
142 | 02645926 | balrog | } else {
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143 | 02645926 | balrog | if ((s->control >> 9) & 1) { /* TRX */ |
144 | 02645926 | balrog | while (ack && s->count_cur && s->txlen) {
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145 | 02645926 | balrog | ack = (i2c_send(s->bus, |
146 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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147 | 02645926 | balrog | 0xff) >= 0); |
148 | 02645926 | balrog | s->count_cur --; |
149 | 02645926 | balrog | } |
150 | 02645926 | balrog | if (ack && s->count_cur)
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151 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
152 | 827df9f3 | balrog | else
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153 | 827df9f3 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
154 | 02645926 | balrog | if (!s->count_cur) {
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155 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
156 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
157 | 02645926 | balrog | } |
158 | 02645926 | balrog | } else {
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159 | 02645926 | balrog | while (s->count_cur && s->rxlen < 4) { |
160 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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161 | 02645926 | balrog | s->count_cur --; |
162 | 02645926 | balrog | } |
163 | 02645926 | balrog | if (s->rxlen)
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164 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
165 | 827df9f3 | balrog | else
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166 | 827df9f3 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
167 | 02645926 | balrog | } |
168 | 02645926 | balrog | if (!s->count_cur) {
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169 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
170 | 02645926 | balrog | i2c_end_transfer(s->bus); |
171 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
172 | 02645926 | balrog | s->count_cur = s->count; |
173 | 29885477 | balrog | s->txlen = 0;
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174 | 02645926 | balrog | } else {
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175 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
176 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
177 | 02645926 | balrog | } |
178 | 02645926 | balrog | } |
179 | 02645926 | balrog | } |
180 | 02645926 | balrog | |
181 | 02645926 | balrog | s->stat |= (!ack) << 1; /* NACK */ |
182 | 02645926 | balrog | if (!ack)
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183 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
184 | 02645926 | balrog | } |
185 | 02645926 | balrog | |
186 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s) |
187 | 02645926 | balrog | { |
188 | 02645926 | balrog | s->mask = 0;
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189 | 02645926 | balrog | s->stat = 0;
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190 | 02645926 | balrog | s->dma = 0;
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191 | 02645926 | balrog | s->count = 0;
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192 | 02645926 | balrog | s->count_cur = 0;
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193 | 02645926 | balrog | s->fifo = 0;
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194 | 02645926 | balrog | s->rxlen = 0;
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195 | 02645926 | balrog | s->txlen = 0;
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196 | 02645926 | balrog | s->control = 0;
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197 | 02645926 | balrog | s->addr[0] = 0; |
198 | 02645926 | balrog | s->addr[1] = 0; |
199 | 02645926 | balrog | s->divider = 0;
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200 | 02645926 | balrog | s->times[0] = 0; |
201 | 02645926 | balrog | s->times[1] = 0; |
202 | 02645926 | balrog | s->test = 0;
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203 | 02645926 | balrog | } |
204 | 02645926 | balrog | |
205 | 02645926 | balrog | static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) |
206 | 02645926 | balrog | { |
207 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
208 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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209 | 02645926 | balrog | uint16_t ret; |
210 | 02645926 | balrog | |
211 | 02645926 | balrog | switch (offset) {
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212 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
213 | 29885477 | balrog | return s->revision; /* REV */ |
214 | 02645926 | balrog | |
215 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
216 | 02645926 | balrog | return s->mask;
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217 | 02645926 | balrog | |
218 | 02645926 | balrog | case 0x08: /* I2C_STAT */ |
219 | 02645926 | balrog | return s->stat | (i2c_bus_busy(s->bus) << 12); |
220 | 02645926 | balrog | |
221 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
222 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV)
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223 | 29885477 | balrog | break;
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224 | 02645926 | balrog | ret = ffs(s->stat & s->mask); |
225 | 02645926 | balrog | if (ret)
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226 | 02645926 | balrog | s->stat ^= 1 << (ret - 1); |
227 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
228 | 02645926 | balrog | return ret;
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229 | 02645926 | balrog | |
230 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
231 | 29885477 | balrog | return (s->control >> 15) & 1; /* I2C_EN */ |
232 | 29885477 | balrog | |
233 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
234 | 02645926 | balrog | return s->dma;
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235 | 02645926 | balrog | |
236 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
237 | 02645926 | balrog | return s->count_cur; /* DCOUNT */ |
238 | 02645926 | balrog | |
239 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
240 | 02645926 | balrog | ret = 0;
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241 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
242 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 8; |
243 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 0; |
244 | 02645926 | balrog | } else {
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245 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 8; |
246 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 0; |
247 | 02645926 | balrog | } |
248 | 02645926 | balrog | if (s->rxlen == 1) { |
249 | 02645926 | balrog | s->stat |= 1 << 15; /* SBD */ |
250 | 02645926 | balrog | s->rxlen = 0;
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251 | 02645926 | balrog | } else if (s->rxlen > 1) { |
252 | 02645926 | balrog | if (s->rxlen > 2) |
253 | 02645926 | balrog | s->fifo >>= 16;
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254 | 02645926 | balrog | s->rxlen -= 2;
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255 | 02645926 | balrog | } else
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256 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */;
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257 | 02645926 | balrog | if (!s->rxlen) {
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258 | 29885477 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
259 | 02645926 | balrog | if (((s->control >> 10) & 1) && /* MST */ |
260 | 02645926 | balrog | ((~s->control >> 9) & 1)) { /* TRX */ |
261 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
262 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
263 | 02645926 | balrog | } |
264 | 02645926 | balrog | } |
265 | 02645926 | balrog | s->stat &= ~(1 << 11); /* ROVR */ |
266 | 02645926 | balrog | omap_i2c_fifo_run(s); |
267 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
268 | 02645926 | balrog | return ret;
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269 | 02645926 | balrog | |
270 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
271 | 29885477 | balrog | return 0; |
272 | 29885477 | balrog | |
273 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
274 | 02645926 | balrog | return s->control;
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275 | 02645926 | balrog | |
276 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
277 | 02645926 | balrog | return s->addr[0]; |
278 | 02645926 | balrog | |
279 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
280 | 02645926 | balrog | return s->addr[1]; |
281 | 02645926 | balrog | |
282 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
283 | 02645926 | balrog | return s->divider;
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284 | 02645926 | balrog | |
285 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
286 | 02645926 | balrog | return s->times[0]; |
287 | 02645926 | balrog | |
288 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
289 | 02645926 | balrog | return s->times[1]; |
290 | 02645926 | balrog | |
291 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
292 | 02645926 | balrog | if (s->test & (1 << 15)) { /* ST_EN */ |
293 | 02645926 | balrog | s->test ^= 0xa;
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294 | 02645926 | balrog | return s->test;
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295 | 02645926 | balrog | } else
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296 | 02645926 | balrog | return s->test & ~0x300f; |
297 | 02645926 | balrog | } |
298 | 02645926 | balrog | |
299 | 02645926 | balrog | OMAP_BAD_REG(addr); |
300 | 02645926 | balrog | return 0; |
301 | 02645926 | balrog | } |
302 | 02645926 | balrog | |
303 | 02645926 | balrog | static void omap_i2c_write(void *opaque, target_phys_addr_t addr, |
304 | 02645926 | balrog | uint32_t value) |
305 | 02645926 | balrog | { |
306 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
307 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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308 | 02645926 | balrog | int nack;
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309 | 02645926 | balrog | |
310 | 02645926 | balrog | switch (offset) {
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311 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
312 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
313 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
314 | 29885477 | balrog | OMAP_RO_REG(addr); |
315 | 02645926 | balrog | return;
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316 | 02645926 | balrog | |
317 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
318 | 29885477 | balrog | s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); |
319 | 29885477 | balrog | break;
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320 | 29885477 | balrog | |
321 | 29885477 | balrog | case 0x08: /* I2C_STAT */ |
322 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
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323 | 29885477 | balrog | OMAP_RO_REG(addr); |
324 | 29885477 | balrog | return;
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325 | 29885477 | balrog | } |
326 | 29885477 | balrog | |
327 | 827df9f3 | balrog | /* RRDY and XRDY are reset by hardware. (in all versions???) */
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328 | 827df9f3 | balrog | s->stat &= ~(value & 0x27);
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329 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
330 | 02645926 | balrog | break;
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331 | 02645926 | balrog | |
332 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
333 | 02645926 | balrog | s->dma = value & 0x8080;
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334 | 02645926 | balrog | if (value & (1 << 15)) /* RDMA_EN */ |
335 | 02645926 | balrog | s->mask &= ~(1 << 3); /* RRDY_IE */ |
336 | 02645926 | balrog | if (value & (1 << 7)) /* XDMA_EN */ |
337 | 02645926 | balrog | s->mask &= ~(1 << 4); /* XRDY_IE */ |
338 | 02645926 | balrog | break;
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339 | 02645926 | balrog | |
340 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
341 | 02645926 | balrog | s->count = value; /* DCOUNT */
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342 | 02645926 | balrog | break;
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343 | 02645926 | balrog | |
344 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
345 | 02645926 | balrog | if (s->txlen > 2) { |
346 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */
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347 | 02645926 | balrog | break;
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348 | 02645926 | balrog | } |
349 | 02645926 | balrog | s->fifo <<= 16;
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350 | 02645926 | balrog | s->txlen += 2;
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351 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
352 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 8; |
353 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 0; |
354 | 02645926 | balrog | } else {
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355 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 8; |
356 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 0; |
357 | 02645926 | balrog | } |
358 | 02645926 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
359 | 02645926 | balrog | if (s->txlen > 2) |
360 | 02645926 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
361 | 02645926 | balrog | omap_i2c_fifo_run(s); |
362 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
363 | 02645926 | balrog | break;
|
364 | 02645926 | balrog | |
365 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
366 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
|
367 | 29885477 | balrog | OMAP_BAD_REG(addr); |
368 | 29885477 | balrog | return;
|
369 | 29885477 | balrog | } |
370 | 29885477 | balrog | |
371 | 29885477 | balrog | if (value & 2) |
372 | 29885477 | balrog | omap_i2c_reset(s); |
373 | 29885477 | balrog | break;
|
374 | 29885477 | balrog | |
375 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
376 | 29885477 | balrog | s->control = value & 0xcf87;
|
377 | 02645926 | balrog | if (~value & (1 << 15)) { /* I2C_EN */ |
378 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV)
|
379 | 29885477 | balrog | omap_i2c_reset(s); |
380 | 02645926 | balrog | break;
|
381 | 02645926 | balrog | } |
382 | 29885477 | balrog | if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ |
383 | 827df9f3 | balrog | fprintf(stderr, "%s: I^2C slave mode not supported\n",
|
384 | 827df9f3 | balrog | __FUNCTION__); |
385 | 02645926 | balrog | break;
|
386 | 02645926 | balrog | } |
387 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ |
388 | 827df9f3 | balrog | fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
|
389 | 827df9f3 | balrog | __FUNCTION__); |
390 | 02645926 | balrog | break;
|
391 | 02645926 | balrog | } |
392 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ |
393 | 02645926 | balrog | nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
394 | 02645926 | balrog | (~value >> 9) & 1); /* TRX */ |
395 | 02645926 | balrog | s->stat |= nack << 1; /* NACK */ |
396 | 02645926 | balrog | s->control &= ~(1 << 0); /* STT */ |
397 | 51fec3cc | balrog | s->fifo = 0;
|
398 | 02645926 | balrog | if (nack)
|
399 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
400 | 29885477 | balrog | else {
|
401 | 29885477 | balrog | s->count_cur = s->count; |
402 | 02645926 | balrog | omap_i2c_fifo_run(s); |
403 | 29885477 | balrog | } |
404 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
405 | 02645926 | balrog | } |
406 | 02645926 | balrog | break;
|
407 | 02645926 | balrog | |
408 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
409 | 02645926 | balrog | s->addr[0] = value & 0x3ff; |
410 | 02645926 | balrog | i2c_set_slave_address(&s->slave, value & 0x7f);
|
411 | 02645926 | balrog | break;
|
412 | 02645926 | balrog | |
413 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
414 | 02645926 | balrog | s->addr[1] = value & 0x3ff; |
415 | 02645926 | balrog | break;
|
416 | 02645926 | balrog | |
417 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
418 | 02645926 | balrog | s->divider = value; |
419 | 02645926 | balrog | break;
|
420 | 02645926 | balrog | |
421 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
422 | 02645926 | balrog | s->times[0] = value;
|
423 | 02645926 | balrog | break;
|
424 | 02645926 | balrog | |
425 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
426 | 02645926 | balrog | s->times[1] = value;
|
427 | 02645926 | balrog | break;
|
428 | 02645926 | balrog | |
429 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
430 | 29885477 | balrog | s->test = value & 0xf80f;
|
431 | 29885477 | balrog | if (value & (1 << 11)) /* SBB */ |
432 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV) {
|
433 | 29885477 | balrog | s->stat |= 0x3f;
|
434 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
435 | 29885477 | balrog | } |
436 | 02645926 | balrog | if (value & (1 << 15)) /* ST_EN */ |
437 | 827df9f3 | balrog | fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
|
438 | 02645926 | balrog | break;
|
439 | 02645926 | balrog | |
440 | 02645926 | balrog | default:
|
441 | 02645926 | balrog | OMAP_BAD_REG(addr); |
442 | 02645926 | balrog | return;
|
443 | 02645926 | balrog | } |
444 | 02645926 | balrog | } |
445 | 02645926 | balrog | |
446 | 29885477 | balrog | static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, |
447 | 29885477 | balrog | uint32_t value) |
448 | 29885477 | balrog | { |
449 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
450 | 29885477 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
451 | 29885477 | balrog | |
452 | 29885477 | balrog | switch (offset) {
|
453 | 29885477 | balrog | case 0x1c: /* I2C_DATA */ |
454 | 29885477 | balrog | if (s->txlen > 2) { |
455 | 29885477 | balrog | /* XXX: remote access (qualifier) error - what's that? */
|
456 | 29885477 | balrog | break;
|
457 | 29885477 | balrog | } |
458 | 29885477 | balrog | s->fifo <<= 8;
|
459 | 29885477 | balrog | s->txlen += 1;
|
460 | 29885477 | balrog | s->fifo |= value & 0xff;
|
461 | 29885477 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
462 | 29885477 | balrog | if (s->txlen > 2) |
463 | 29885477 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
464 | 29885477 | balrog | omap_i2c_fifo_run(s); |
465 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
466 | 29885477 | balrog | break;
|
467 | 29885477 | balrog | |
468 | 29885477 | balrog | default:
|
469 | 29885477 | balrog | OMAP_BAD_REG(addr); |
470 | 29885477 | balrog | return;
|
471 | 29885477 | balrog | } |
472 | 29885477 | balrog | } |
473 | 29885477 | balrog | |
474 | 02645926 | balrog | static CPUReadMemoryFunc *omap_i2c_readfn[] = {
|
475 | 02645926 | balrog | omap_badwidth_read16, |
476 | 02645926 | balrog | omap_i2c_read, |
477 | 02645926 | balrog | omap_badwidth_read16, |
478 | 02645926 | balrog | }; |
479 | 02645926 | balrog | |
480 | 02645926 | balrog | static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
|
481 | 29885477 | balrog | omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
|
482 | 02645926 | balrog | omap_i2c_write, |
483 | 29885477 | balrog | omap_badwidth_write16, |
484 | 02645926 | balrog | }; |
485 | 02645926 | balrog | |
486 | 02645926 | balrog | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
487 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk) |
488 | 02645926 | balrog | { |
489 | 02645926 | balrog | int iomemtype;
|
490 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
491 | 02645926 | balrog | qemu_mallocz(sizeof(struct omap_i2c_s)); |
492 | 02645926 | balrog | |
493 | 29885477 | balrog | /* TODO: set a value greater or equal to real hardware */
|
494 | 29885477 | balrog | s->revision = 0x11;
|
495 | 02645926 | balrog | s->irq = irq; |
496 | 02645926 | balrog | s->drq[0] = dma[0]; |
497 | 02645926 | balrog | s->drq[1] = dma[1]; |
498 | 02645926 | balrog | s->slave.event = omap_i2c_event; |
499 | 02645926 | balrog | s->slave.recv = omap_i2c_rx; |
500 | 02645926 | balrog | s->slave.send = omap_i2c_tx; |
501 | 02645926 | balrog | s->bus = i2c_init_bus(); |
502 | 02645926 | balrog | omap_i2c_reset(s); |
503 | 02645926 | balrog | |
504 | 02645926 | balrog | iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
|
505 | 02645926 | balrog | omap_i2c_writefn, s); |
506 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
507 | 02645926 | balrog | |
508 | 02645926 | balrog | return s;
|
509 | 02645926 | balrog | } |
510 | 02645926 | balrog | |
511 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
512 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) |
513 | 29885477 | balrog | { |
514 | 29885477 | balrog | int iomemtype;
|
515 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
516 | 29885477 | balrog | qemu_mallocz(sizeof(struct omap_i2c_s)); |
517 | 29885477 | balrog | |
518 | 29885477 | balrog | s->revision = 0x34;
|
519 | 29885477 | balrog | s->irq = irq; |
520 | 29885477 | balrog | s->drq[0] = dma[0]; |
521 | 29885477 | balrog | s->drq[1] = dma[1]; |
522 | 29885477 | balrog | s->slave.event = omap_i2c_event; |
523 | 29885477 | balrog | s->slave.recv = omap_i2c_rx; |
524 | 29885477 | balrog | s->slave.send = omap_i2c_tx; |
525 | 29885477 | balrog | s->bus = i2c_init_bus(); |
526 | 29885477 | balrog | omap_i2c_reset(s); |
527 | 29885477 | balrog | |
528 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_i2c_readfn,
|
529 | 29885477 | balrog | omap_i2c_writefn, s); |
530 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
531 | 29885477 | balrog | |
532 | 29885477 | balrog | return s;
|
533 | 29885477 | balrog | } |
534 | 29885477 | balrog | |
535 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
536 | 02645926 | balrog | { |
537 | 02645926 | balrog | return s->bus;
|
538 | 02645926 | balrog | } |