root / hw / vmware_vga.c @ 0bf43016
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1 | d34cab9f | ths | /*
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2 | d34cab9f | ths | * QEMU VMware-SVGA "chipset".
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3 | d34cab9f | ths | *
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4 | d34cab9f | ths | * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | d34cab9f | ths | *
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6 | d34cab9f | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | d34cab9f | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | d34cab9f | ths | * in the Software without restriction, including without limitation the rights
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9 | d34cab9f | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | d34cab9f | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | d34cab9f | ths | * furnished to do so, subject to the following conditions:
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12 | d34cab9f | ths | *
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13 | d34cab9f | ths | * The above copyright notice and this permission notice shall be included in
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14 | d34cab9f | ths | * all copies or substantial portions of the Software.
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15 | d34cab9f | ths | *
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16 | d34cab9f | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | d34cab9f | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | d34cab9f | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | d34cab9f | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | d34cab9f | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | d34cab9f | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | d34cab9f | ths | * THE SOFTWARE.
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23 | d34cab9f | ths | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | b3c3f123 | Dave Airlie | #include "loader.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 18e08a55 | Michael S. Tsirkin | #include "vmware_vga.h" |
29 | d34cab9f | ths | |
30 | d34cab9f | ths | #define VERBOSE
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31 | d34cab9f | ths | #undef DIRECT_VRAM
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32 | d34cab9f | ths | #define HW_RECT_ACCEL
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33 | d34cab9f | ths | #define HW_FILL_ACCEL
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34 | d34cab9f | ths | #define HW_MOUSE_ACCEL
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35 | d34cab9f | ths | |
36 | d34cab9f | ths | # include "vga_int.h" |
37 | d34cab9f | ths | |
38 | d34cab9f | ths | struct vmsvga_state_s {
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39 | 4e12cd94 | Avi Kivity | VGACommonState vga; |
40 | d34cab9f | ths | |
41 | d34cab9f | ths | int width;
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42 | d34cab9f | ths | int height;
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43 | d34cab9f | ths | int invalidated;
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44 | d34cab9f | ths | int depth;
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45 | d34cab9f | ths | int bypp;
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46 | d34cab9f | ths | int enable;
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47 | d34cab9f | ths | int config;
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48 | d34cab9f | ths | struct {
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49 | d34cab9f | ths | int id;
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50 | d34cab9f | ths | int x;
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51 | d34cab9f | ths | int y;
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52 | d34cab9f | ths | int on;
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53 | d34cab9f | ths | } cursor; |
54 | d34cab9f | ths | |
55 | c227f099 | Anthony Liguori | target_phys_addr_t vram_base; |
56 | d34cab9f | ths | |
57 | d34cab9f | ths | int index;
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58 | d34cab9f | ths | int scratch_size;
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59 | d34cab9f | ths | uint32_t *scratch; |
60 | d34cab9f | ths | int new_width;
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61 | d34cab9f | ths | int new_height;
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62 | d34cab9f | ths | uint32_t guest; |
63 | d34cab9f | ths | uint32_t svgaid; |
64 | d34cab9f | ths | uint32_t wred; |
65 | d34cab9f | ths | uint32_t wgreen; |
66 | d34cab9f | ths | uint32_t wblue; |
67 | d34cab9f | ths | int syncing;
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68 | d34cab9f | ths | int fb_size;
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69 | d34cab9f | ths | |
70 | f351d050 | Dave Airlie | ram_addr_t fifo_offset; |
71 | f351d050 | Dave Airlie | uint8_t *fifo_ptr; |
72 | f351d050 | Dave Airlie | unsigned int fifo_size; |
73 | f351d050 | Dave Airlie | target_phys_addr_t fifo_base; |
74 | f351d050 | Dave Airlie | |
75 | d34cab9f | ths | union {
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76 | d34cab9f | ths | uint32_t *fifo; |
77 | d34cab9f | ths | struct __attribute__((__packed__)) {
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78 | d34cab9f | ths | uint32_t min; |
79 | d34cab9f | ths | uint32_t max; |
80 | d34cab9f | ths | uint32_t next_cmd; |
81 | d34cab9f | ths | uint32_t stop; |
82 | d34cab9f | ths | /* Add registers here when adding capabilities. */
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83 | d34cab9f | ths | uint32_t fifo[0];
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84 | d34cab9f | ths | } *cmd; |
85 | d34cab9f | ths | }; |
86 | d34cab9f | ths | |
87 | d34cab9f | ths | #define REDRAW_FIFO_LEN 512 |
88 | d34cab9f | ths | struct vmsvga_rect_s {
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89 | d34cab9f | ths | int x, y, w, h;
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90 | d34cab9f | ths | } redraw_fifo[REDRAW_FIFO_LEN]; |
91 | d34cab9f | ths | int redraw_fifo_first, redraw_fifo_last;
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92 | d34cab9f | ths | }; |
93 | d34cab9f | ths | |
94 | d34cab9f | ths | struct pci_vmsvga_state_s {
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95 | d34cab9f | ths | PCIDevice card; |
96 | d34cab9f | ths | struct vmsvga_state_s chip;
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97 | d34cab9f | ths | }; |
98 | d34cab9f | ths | |
99 | d34cab9f | ths | #define SVGA_MAGIC 0x900000UL |
100 | d34cab9f | ths | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
101 | d34cab9f | ths | #define SVGA_ID_0 SVGA_MAKE_ID(0) |
102 | d34cab9f | ths | #define SVGA_ID_1 SVGA_MAKE_ID(1) |
103 | d34cab9f | ths | #define SVGA_ID_2 SVGA_MAKE_ID(2) |
104 | d34cab9f | ths | |
105 | d34cab9f | ths | #define SVGA_LEGACY_BASE_PORT 0x4560 |
106 | d34cab9f | ths | #define SVGA_INDEX_PORT 0x0 |
107 | d34cab9f | ths | #define SVGA_VALUE_PORT 0x1 |
108 | d34cab9f | ths | #define SVGA_BIOS_PORT 0x2 |
109 | d34cab9f | ths | |
110 | d34cab9f | ths | #define SVGA_VERSION_2
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111 | d34cab9f | ths | |
112 | d34cab9f | ths | #ifdef SVGA_VERSION_2
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113 | d34cab9f | ths | # define SVGA_ID SVGA_ID_2
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114 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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115 | d34cab9f | ths | # define SVGA_IO_MUL 1 |
116 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
117 | 1f72aae5 | balrog | # define SVGA_MEM_BASE 0xe0000000 |
118 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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119 | d34cab9f | ths | #else
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120 | d34cab9f | ths | # define SVGA_ID SVGA_ID_1
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121 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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122 | d34cab9f | ths | # define SVGA_IO_MUL 4 |
123 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
124 | 1f72aae5 | balrog | # define SVGA_MEM_BASE 0xe0000000 |
125 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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126 | d34cab9f | ths | #endif
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127 | d34cab9f | ths | |
128 | d34cab9f | ths | enum {
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129 | d34cab9f | ths | /* ID 0, 1 and 2 registers */
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130 | d34cab9f | ths | SVGA_REG_ID = 0,
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131 | d34cab9f | ths | SVGA_REG_ENABLE = 1,
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132 | d34cab9f | ths | SVGA_REG_WIDTH = 2,
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133 | d34cab9f | ths | SVGA_REG_HEIGHT = 3,
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134 | d34cab9f | ths | SVGA_REG_MAX_WIDTH = 4,
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135 | d34cab9f | ths | SVGA_REG_MAX_HEIGHT = 5,
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136 | d34cab9f | ths | SVGA_REG_DEPTH = 6,
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137 | d34cab9f | ths | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
138 | d34cab9f | ths | SVGA_REG_PSEUDOCOLOR = 8,
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139 | d34cab9f | ths | SVGA_REG_RED_MASK = 9,
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140 | d34cab9f | ths | SVGA_REG_GREEN_MASK = 10,
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141 | d34cab9f | ths | SVGA_REG_BLUE_MASK = 11,
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142 | d34cab9f | ths | SVGA_REG_BYTES_PER_LINE = 12,
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143 | d34cab9f | ths | SVGA_REG_FB_START = 13,
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144 | d34cab9f | ths | SVGA_REG_FB_OFFSET = 14,
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145 | d34cab9f | ths | SVGA_REG_VRAM_SIZE = 15,
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146 | d34cab9f | ths | SVGA_REG_FB_SIZE = 16,
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147 | d34cab9f | ths | |
148 | d34cab9f | ths | /* ID 1 and 2 registers */
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149 | d34cab9f | ths | SVGA_REG_CAPABILITIES = 17,
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150 | d34cab9f | ths | SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
151 | d34cab9f | ths | SVGA_REG_MEM_SIZE = 19,
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152 | d34cab9f | ths | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
153 | d34cab9f | ths | SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
154 | d34cab9f | ths | SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
155 | d34cab9f | ths | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
156 | d34cab9f | ths | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
157 | d34cab9f | ths | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
158 | d34cab9f | ths | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
159 | d34cab9f | ths | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
160 | d34cab9f | ths | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
161 | d34cab9f | ths | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
162 | d34cab9f | ths | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
163 | d34cab9f | ths | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
164 | d34cab9f | ths | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
165 | d34cab9f | ths | |
166 | d34cab9f | ths | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
167 | d34cab9f | ths | SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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168 | d34cab9f | ths | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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169 | d34cab9f | ths | }; |
170 | d34cab9f | ths | |
171 | d34cab9f | ths | #define SVGA_CAP_NONE 0 |
172 | d34cab9f | ths | #define SVGA_CAP_RECT_FILL (1 << 0) |
173 | d34cab9f | ths | #define SVGA_CAP_RECT_COPY (1 << 1) |
174 | d34cab9f | ths | #define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
175 | d34cab9f | ths | #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
176 | d34cab9f | ths | #define SVGA_CAP_RASTER_OP (1 << 4) |
177 | d34cab9f | ths | #define SVGA_CAP_CURSOR (1 << 5) |
178 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
179 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
180 | d34cab9f | ths | #define SVGA_CAP_8BIT_EMULATION (1 << 8) |
181 | d34cab9f | ths | #define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
182 | d34cab9f | ths | #define SVGA_CAP_GLYPH (1 << 10) |
183 | d34cab9f | ths | #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
184 | d34cab9f | ths | #define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
185 | d34cab9f | ths | #define SVGA_CAP_ALPHA_BLEND (1 << 13) |
186 | d34cab9f | ths | #define SVGA_CAP_3D (1 << 14) |
187 | d34cab9f | ths | #define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
188 | d34cab9f | ths | #define SVGA_CAP_MULTIMON (1 << 16) |
189 | d34cab9f | ths | #define SVGA_CAP_PITCHLOCK (1 << 17) |
190 | d34cab9f | ths | |
191 | d34cab9f | ths | /*
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192 | d34cab9f | ths | * FIFO offsets (seen as an array of 32-bit words)
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193 | d34cab9f | ths | */
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194 | d34cab9f | ths | enum {
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195 | d34cab9f | ths | /*
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196 | d34cab9f | ths | * The original defined FIFO offsets
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197 | d34cab9f | ths | */
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198 | d34cab9f | ths | SVGA_FIFO_MIN = 0,
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199 | d34cab9f | ths | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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200 | d34cab9f | ths | SVGA_FIFO_NEXT_CMD, |
201 | d34cab9f | ths | SVGA_FIFO_STOP, |
202 | d34cab9f | ths | |
203 | d34cab9f | ths | /*
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204 | d34cab9f | ths | * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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205 | d34cab9f | ths | */
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206 | d34cab9f | ths | SVGA_FIFO_CAPABILITIES = 4,
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207 | d34cab9f | ths | SVGA_FIFO_FLAGS, |
208 | d34cab9f | ths | SVGA_FIFO_FENCE, |
209 | d34cab9f | ths | SVGA_FIFO_3D_HWVERSION, |
210 | d34cab9f | ths | SVGA_FIFO_PITCHLOCK, |
211 | d34cab9f | ths | }; |
212 | d34cab9f | ths | |
213 | d34cab9f | ths | #define SVGA_FIFO_CAP_NONE 0 |
214 | d34cab9f | ths | #define SVGA_FIFO_CAP_FENCE (1 << 0) |
215 | d34cab9f | ths | #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
216 | d34cab9f | ths | #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
217 | d34cab9f | ths | |
218 | d34cab9f | ths | #define SVGA_FIFO_FLAG_NONE 0 |
219 | d34cab9f | ths | #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
220 | d34cab9f | ths | |
221 | d34cab9f | ths | /* These values can probably be changed arbitrarily. */
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222 | d34cab9f | ths | #define SVGA_SCRATCH_SIZE 0x8000 |
223 | d34cab9f | ths | #define SVGA_MAX_WIDTH 2360 |
224 | d34cab9f | ths | #define SVGA_MAX_HEIGHT 1770 |
225 | d34cab9f | ths | |
226 | d34cab9f | ths | #ifdef VERBOSE
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227 | d34cab9f | ths | # define GUEST_OS_BASE 0x5001 |
228 | d34cab9f | ths | static const char *vmsvga_guest_id[] = { |
229 | f707cfba | balrog | [0x00] = "Dos", |
230 | f707cfba | balrog | [0x01] = "Windows 3.1", |
231 | f707cfba | balrog | [0x02] = "Windows 95", |
232 | f707cfba | balrog | [0x03] = "Windows 98", |
233 | f707cfba | balrog | [0x04] = "Windows ME", |
234 | f707cfba | balrog | [0x05] = "Windows NT", |
235 | f707cfba | balrog | [0x06] = "Windows 2000", |
236 | f707cfba | balrog | [0x07] = "Linux", |
237 | f707cfba | balrog | [0x08] = "OS/2", |
238 | 511d2b14 | blueswir1 | [0x09] = "an unknown OS", |
239 | f707cfba | balrog | [0x0a] = "BSD", |
240 | f707cfba | balrog | [0x0b] = "Whistler", |
241 | 511d2b14 | blueswir1 | [0x0c] = "an unknown OS", |
242 | 511d2b14 | blueswir1 | [0x0d] = "an unknown OS", |
243 | 511d2b14 | blueswir1 | [0x0e] = "an unknown OS", |
244 | 511d2b14 | blueswir1 | [0x0f] = "an unknown OS", |
245 | 511d2b14 | blueswir1 | [0x10] = "an unknown OS", |
246 | 511d2b14 | blueswir1 | [0x11] = "an unknown OS", |
247 | 511d2b14 | blueswir1 | [0x12] = "an unknown OS", |
248 | 511d2b14 | blueswir1 | [0x13] = "an unknown OS", |
249 | 511d2b14 | blueswir1 | [0x14] = "an unknown OS", |
250 | f707cfba | balrog | [0x15] = "Windows 2003", |
251 | d34cab9f | ths | }; |
252 | d34cab9f | ths | #endif
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253 | d34cab9f | ths | |
254 | d34cab9f | ths | enum {
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255 | d34cab9f | ths | SVGA_CMD_INVALID_CMD = 0,
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256 | d34cab9f | ths | SVGA_CMD_UPDATE = 1,
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257 | d34cab9f | ths | SVGA_CMD_RECT_FILL = 2,
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258 | d34cab9f | ths | SVGA_CMD_RECT_COPY = 3,
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259 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP = 4,
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260 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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261 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP = 6,
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262 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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263 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_FILL = 8,
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264 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_FILL = 9,
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265 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_COPY = 10,
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266 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_COPY = 11,
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267 | d34cab9f | ths | SVGA_CMD_FREE_OBJECT = 12,
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268 | d34cab9f | ths | SVGA_CMD_RECT_ROP_FILL = 13,
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269 | d34cab9f | ths | SVGA_CMD_RECT_ROP_COPY = 14,
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270 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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271 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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272 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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273 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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274 | d34cab9f | ths | SVGA_CMD_DEFINE_CURSOR = 19,
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275 | d34cab9f | ths | SVGA_CMD_DISPLAY_CURSOR = 20,
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276 | d34cab9f | ths | SVGA_CMD_MOVE_CURSOR = 21,
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277 | d34cab9f | ths | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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278 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH = 23,
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279 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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280 | d34cab9f | ths | SVGA_CMD_UPDATE_VERBOSE = 25,
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281 | d34cab9f | ths | SVGA_CMD_SURFACE_FILL = 26,
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282 | d34cab9f | ths | SVGA_CMD_SURFACE_COPY = 27,
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283 | d34cab9f | ths | SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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284 | d34cab9f | ths | SVGA_CMD_FRONT_ROP_FILL = 29,
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285 | d34cab9f | ths | SVGA_CMD_FENCE = 30,
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286 | d34cab9f | ths | }; |
287 | d34cab9f | ths | |
288 | d34cab9f | ths | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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289 | d34cab9f | ths | enum {
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290 | d34cab9f | ths | SVGA_CURSOR_ON_HIDE = 0,
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291 | d34cab9f | ths | SVGA_CURSOR_ON_SHOW = 1,
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292 | d34cab9f | ths | SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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293 | d34cab9f | ths | SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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294 | d34cab9f | ths | }; |
295 | d34cab9f | ths | |
296 | d34cab9f | ths | static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
297 | d34cab9f | ths | int x, int y, int w, int h) |
298 | d34cab9f | ths | { |
299 | d34cab9f | ths | #ifndef DIRECT_VRAM
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300 | a8fbaf96 | balrog | int line;
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301 | a8fbaf96 | balrog | int bypl;
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302 | a8fbaf96 | balrog | int width;
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303 | a8fbaf96 | balrog | int start;
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304 | a8fbaf96 | balrog | uint8_t *src; |
305 | a8fbaf96 | balrog | uint8_t *dst; |
306 | a8fbaf96 | balrog | |
307 | a8fbaf96 | balrog | if (x + w > s->width) {
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308 | a8fbaf96 | balrog | fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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309 | a8fbaf96 | balrog | __FUNCTION__, x, w); |
310 | a8fbaf96 | balrog | x = MIN(x, s->width); |
311 | a8fbaf96 | balrog | w = s->width - x; |
312 | a8fbaf96 | balrog | } |
313 | a8fbaf96 | balrog | |
314 | a8fbaf96 | balrog | if (y + h > s->height) {
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315 | a8fbaf96 | balrog | fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
|
316 | a8fbaf96 | balrog | __FUNCTION__, y, h); |
317 | a8fbaf96 | balrog | y = MIN(y, s->height); |
318 | a8fbaf96 | balrog | h = s->height - y; |
319 | a8fbaf96 | balrog | } |
320 | a8fbaf96 | balrog | |
321 | a8fbaf96 | balrog | line = h; |
322 | a8fbaf96 | balrog | bypl = s->bypp * s->width; |
323 | a8fbaf96 | balrog | width = s->bypp * w; |
324 | a8fbaf96 | balrog | start = s->bypp * x + bypl * y; |
325 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + start; |
326 | 4e12cd94 | Avi Kivity | dst = ds_get_data(s->vga.ds) + start; |
327 | d34cab9f | ths | |
328 | d34cab9f | ths | for (; line > 0; line --, src += bypl, dst += bypl) |
329 | d34cab9f | ths | memcpy(dst, src, width); |
330 | d34cab9f | ths | #endif
|
331 | d34cab9f | ths | |
332 | 4e12cd94 | Avi Kivity | dpy_update(s->vga.ds, x, y, w, h); |
333 | d34cab9f | ths | } |
334 | d34cab9f | ths | |
335 | d34cab9f | ths | static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
336 | d34cab9f | ths | { |
337 | d34cab9f | ths | #ifndef DIRECT_VRAM
|
338 | 4e12cd94 | Avi Kivity | memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); |
339 | d34cab9f | ths | #endif
|
340 | d34cab9f | ths | |
341 | 4e12cd94 | Avi Kivity | dpy_update(s->vga.ds, 0, 0, s->width, s->height); |
342 | d34cab9f | ths | } |
343 | d34cab9f | ths | |
344 | d34cab9f | ths | #ifdef DIRECT_VRAM
|
345 | d34cab9f | ths | # define vmsvga_update_rect_delayed vmsvga_update_rect
|
346 | d34cab9f | ths | #else
|
347 | d34cab9f | ths | static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
348 | d34cab9f | ths | int x, int y, int w, int h) |
349 | d34cab9f | ths | { |
350 | d34cab9f | ths | struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
|
351 | d34cab9f | ths | s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
|
352 | d34cab9f | ths | rect->x = x; |
353 | d34cab9f | ths | rect->y = y; |
354 | d34cab9f | ths | rect->w = w; |
355 | d34cab9f | ths | rect->h = h; |
356 | d34cab9f | ths | } |
357 | d34cab9f | ths | #endif
|
358 | d34cab9f | ths | |
359 | d34cab9f | ths | static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
360 | d34cab9f | ths | { |
361 | d34cab9f | ths | struct vmsvga_rect_s *rect;
|
362 | d34cab9f | ths | if (s->invalidated) {
|
363 | d34cab9f | ths | s->redraw_fifo_first = s->redraw_fifo_last; |
364 | d34cab9f | ths | return;
|
365 | d34cab9f | ths | } |
366 | d34cab9f | ths | /* Overlapping region updates can be optimised out here - if someone
|
367 | d34cab9f | ths | * knows a smart algorithm to do that, please share. */
|
368 | d34cab9f | ths | while (s->redraw_fifo_first != s->redraw_fifo_last) {
|
369 | d34cab9f | ths | rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
370 | d34cab9f | ths | s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
|
371 | d34cab9f | ths | vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
372 | d34cab9f | ths | } |
373 | d34cab9f | ths | } |
374 | d34cab9f | ths | |
375 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
376 | d34cab9f | ths | static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
377 | d34cab9f | ths | int x0, int y0, int x1, int y1, int w, int h) |
378 | d34cab9f | ths | { |
379 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
380 | 0e1f5a0c | aliguori | uint8_t *vram = ds_get_data(s->ds); |
381 | d34cab9f | ths | # else
|
382 | 4e12cd94 | Avi Kivity | uint8_t *vram = s->vga.vram_ptr; |
383 | d34cab9f | ths | # endif
|
384 | d34cab9f | ths | int bypl = s->bypp * s->width;
|
385 | d34cab9f | ths | int width = s->bypp * w;
|
386 | d34cab9f | ths | int line = h;
|
387 | d34cab9f | ths | uint8_t *ptr[2];
|
388 | d34cab9f | ths | |
389 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
390 | d34cab9f | ths | if (s->ds->dpy_copy)
|
391 | 3023f332 | aliguori | qemu_console_copy(s->ds, x0, y0, x1, y1, w, h); |
392 | d34cab9f | ths | else
|
393 | d34cab9f | ths | # endif
|
394 | d34cab9f | ths | { |
395 | d34cab9f | ths | if (y1 > y0) {
|
396 | d34cab9f | ths | ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
397 | d34cab9f | ths | ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
398 | d34cab9f | ths | for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) |
399 | d34cab9f | ths | memmove(ptr[1], ptr[0], width); |
400 | d34cab9f | ths | } else {
|
401 | d34cab9f | ths | ptr[0] = vram + s->bypp * x0 + bypl * y0;
|
402 | d34cab9f | ths | ptr[1] = vram + s->bypp * x1 + bypl * y1;
|
403 | d34cab9f | ths | for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) |
404 | d34cab9f | ths | memmove(ptr[1], ptr[0], width); |
405 | d34cab9f | ths | } |
406 | d34cab9f | ths | } |
407 | d34cab9f | ths | |
408 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x1, y1, w, h); |
409 | d34cab9f | ths | } |
410 | d34cab9f | ths | #endif
|
411 | d34cab9f | ths | |
412 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
413 | d34cab9f | ths | static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
414 | d34cab9f | ths | uint32_t c, int x, int y, int w, int h) |
415 | d34cab9f | ths | { |
416 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
417 | 0e1f5a0c | aliguori | uint8_t *vram = ds_get_data(s->ds); |
418 | d34cab9f | ths | # else
|
419 | 4e12cd94 | Avi Kivity | uint8_t *vram = s->vga.vram_ptr; |
420 | d34cab9f | ths | # endif
|
421 | d34cab9f | ths | int bypp = s->bypp;
|
422 | d34cab9f | ths | int bypl = bypp * s->width;
|
423 | d34cab9f | ths | int width = bypp * w;
|
424 | d34cab9f | ths | int line = h;
|
425 | d34cab9f | ths | int column;
|
426 | d34cab9f | ths | uint8_t *fst = vram + bypp * x + bypl * y; |
427 | d34cab9f | ths | uint8_t *dst; |
428 | d34cab9f | ths | uint8_t *src; |
429 | d34cab9f | ths | uint8_t col[4];
|
430 | d34cab9f | ths | |
431 | d34cab9f | ths | # ifdef DIRECT_VRAM
|
432 | d34cab9f | ths | if (s->ds->dpy_fill)
|
433 | d34cab9f | ths | s->ds->dpy_fill(s->ds, x, y, w, h, c); |
434 | d34cab9f | ths | else
|
435 | d34cab9f | ths | # endif
|
436 | d34cab9f | ths | { |
437 | d34cab9f | ths | col[0] = c;
|
438 | d34cab9f | ths | col[1] = c >> 8; |
439 | d34cab9f | ths | col[2] = c >> 16; |
440 | d34cab9f | ths | col[3] = c >> 24; |
441 | d34cab9f | ths | |
442 | d34cab9f | ths | if (line --) {
|
443 | d34cab9f | ths | dst = fst; |
444 | d34cab9f | ths | src = col; |
445 | d34cab9f | ths | for (column = width; column > 0; column --) { |
446 | d34cab9f | ths | *(dst ++) = *(src ++); |
447 | d34cab9f | ths | if (src - col == bypp)
|
448 | d34cab9f | ths | src = col; |
449 | d34cab9f | ths | } |
450 | d34cab9f | ths | dst = fst; |
451 | d34cab9f | ths | for (; line > 0; line --) { |
452 | d34cab9f | ths | dst += bypl; |
453 | d34cab9f | ths | memcpy(dst, fst, width); |
454 | d34cab9f | ths | } |
455 | d34cab9f | ths | } |
456 | d34cab9f | ths | } |
457 | d34cab9f | ths | |
458 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, w, h); |
459 | d34cab9f | ths | } |
460 | d34cab9f | ths | #endif
|
461 | d34cab9f | ths | |
462 | d34cab9f | ths | struct vmsvga_cursor_definition_s {
|
463 | d34cab9f | ths | int width;
|
464 | d34cab9f | ths | int height;
|
465 | d34cab9f | ths | int id;
|
466 | d34cab9f | ths | int bpp;
|
467 | d34cab9f | ths | int hot_x;
|
468 | d34cab9f | ths | int hot_y;
|
469 | d34cab9f | ths | uint32_t mask[1024];
|
470 | 8095cb3e | Dave Airlie | uint32_t image[4096];
|
471 | d34cab9f | ths | }; |
472 | d34cab9f | ths | |
473 | d34cab9f | ths | #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
474 | d34cab9f | ths | #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
475 | d34cab9f | ths | |
476 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
477 | d34cab9f | ths | static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
478 | d34cab9f | ths | struct vmsvga_cursor_definition_s *c)
|
479 | d34cab9f | ths | { |
480 | fbe6d7a4 | Gerd Hoffmann | QEMUCursor *qc; |
481 | fbe6d7a4 | Gerd Hoffmann | int i, pixels;
|
482 | fbe6d7a4 | Gerd Hoffmann | |
483 | fbe6d7a4 | Gerd Hoffmann | qc = cursor_alloc(c->width, c->height); |
484 | fbe6d7a4 | Gerd Hoffmann | qc->hot_x = c->hot_x; |
485 | fbe6d7a4 | Gerd Hoffmann | qc->hot_y = c->hot_y; |
486 | fbe6d7a4 | Gerd Hoffmann | switch (c->bpp) {
|
487 | fbe6d7a4 | Gerd Hoffmann | case 1: |
488 | fbe6d7a4 | Gerd Hoffmann | cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image, |
489 | fbe6d7a4 | Gerd Hoffmann | 1, (void*)c->mask); |
490 | fbe6d7a4 | Gerd Hoffmann | #ifdef DEBUG
|
491 | fbe6d7a4 | Gerd Hoffmann | cursor_print_ascii_art(qc, "vmware/mono");
|
492 | fbe6d7a4 | Gerd Hoffmann | #endif
|
493 | fbe6d7a4 | Gerd Hoffmann | break;
|
494 | fbe6d7a4 | Gerd Hoffmann | case 32: |
495 | fbe6d7a4 | Gerd Hoffmann | /* fill alpha channel from mask, set color to zero */
|
496 | fbe6d7a4 | Gerd Hoffmann | cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask, |
497 | fbe6d7a4 | Gerd Hoffmann | 1, (void*)c->mask); |
498 | fbe6d7a4 | Gerd Hoffmann | /* add in rgb values */
|
499 | fbe6d7a4 | Gerd Hoffmann | pixels = c->width * c->height; |
500 | fbe6d7a4 | Gerd Hoffmann | for (i = 0; i < pixels; i++) { |
501 | fbe6d7a4 | Gerd Hoffmann | qc->data[i] |= c->image[i] & 0xffffff;
|
502 | fbe6d7a4 | Gerd Hoffmann | } |
503 | fbe6d7a4 | Gerd Hoffmann | #ifdef DEBUG
|
504 | fbe6d7a4 | Gerd Hoffmann | cursor_print_ascii_art(qc, "vmware/32bit");
|
505 | fbe6d7a4 | Gerd Hoffmann | #endif
|
506 | fbe6d7a4 | Gerd Hoffmann | break;
|
507 | fbe6d7a4 | Gerd Hoffmann | default:
|
508 | fbe6d7a4 | Gerd Hoffmann | fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
509 | fbe6d7a4 | Gerd Hoffmann | __FUNCTION__, c->bpp); |
510 | fbe6d7a4 | Gerd Hoffmann | cursor_put(qc); |
511 | fbe6d7a4 | Gerd Hoffmann | qc = cursor_builtin_left_ptr(); |
512 | fbe6d7a4 | Gerd Hoffmann | } |
513 | d34cab9f | ths | |
514 | 4e12cd94 | Avi Kivity | if (s->vga.ds->cursor_define)
|
515 | fbe6d7a4 | Gerd Hoffmann | s->vga.ds->cursor_define(qc); |
516 | fbe6d7a4 | Gerd Hoffmann | cursor_put(qc); |
517 | d34cab9f | ths | } |
518 | d34cab9f | ths | #endif
|
519 | d34cab9f | ths | |
520 | ff9cf2cb | balrog | #define CMD(f) le32_to_cpu(s->cmd->f)
|
521 | ff9cf2cb | balrog | |
522 | d34cab9f | ths | static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s) |
523 | d34cab9f | ths | { |
524 | d34cab9f | ths | if (!s->config || !s->enable)
|
525 | f707cfba | balrog | return 1; |
526 | d34cab9f | ths | return (s->cmd->next_cmd == s->cmd->stop);
|
527 | d34cab9f | ths | } |
528 | d34cab9f | ths | |
529 | ff9cf2cb | balrog | static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
530 | d34cab9f | ths | { |
531 | ff9cf2cb | balrog | uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
532 | ff9cf2cb | balrog | s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
533 | ff9cf2cb | balrog | if (CMD(stop) >= CMD(max))
|
534 | d34cab9f | ths | s->cmd->stop = s->cmd->min; |
535 | d34cab9f | ths | return cmd;
|
536 | d34cab9f | ths | } |
537 | d34cab9f | ths | |
538 | ff9cf2cb | balrog | static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
539 | ff9cf2cb | balrog | { |
540 | ff9cf2cb | balrog | return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
541 | ff9cf2cb | balrog | } |
542 | ff9cf2cb | balrog | |
543 | d34cab9f | ths | static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
544 | d34cab9f | ths | { |
545 | d34cab9f | ths | uint32_t cmd, colour; |
546 | d34cab9f | ths | int args = 0; |
547 | d34cab9f | ths | int x, y, dx, dy, width, height;
|
548 | d34cab9f | ths | struct vmsvga_cursor_definition_s cursor;
|
549 | d34cab9f | ths | while (!vmsvga_fifo_empty(s))
|
550 | d34cab9f | ths | switch (cmd = vmsvga_fifo_read(s)) {
|
551 | d34cab9f | ths | case SVGA_CMD_UPDATE:
|
552 | d34cab9f | ths | case SVGA_CMD_UPDATE_VERBOSE:
|
553 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
554 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
555 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
556 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
557 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, width, height); |
558 | d34cab9f | ths | break;
|
559 | d34cab9f | ths | |
560 | d34cab9f | ths | case SVGA_CMD_RECT_FILL:
|
561 | d34cab9f | ths | colour = vmsvga_fifo_read(s); |
562 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
563 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
564 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
565 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
566 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
567 | d34cab9f | ths | vmsvga_fill_rect(s, colour, x, y, width, height); |
568 | d34cab9f | ths | break;
|
569 | d34cab9f | ths | #else
|
570 | d34cab9f | ths | goto badcmd;
|
571 | d34cab9f | ths | #endif
|
572 | d34cab9f | ths | |
573 | d34cab9f | ths | case SVGA_CMD_RECT_COPY:
|
574 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
575 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
576 | d34cab9f | ths | dx = vmsvga_fifo_read(s); |
577 | d34cab9f | ths | dy = vmsvga_fifo_read(s); |
578 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
579 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
580 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
581 | d34cab9f | ths | vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
582 | d34cab9f | ths | break;
|
583 | d34cab9f | ths | #else
|
584 | d34cab9f | ths | goto badcmd;
|
585 | d34cab9f | ths | #endif
|
586 | d34cab9f | ths | |
587 | d34cab9f | ths | case SVGA_CMD_DEFINE_CURSOR:
|
588 | d34cab9f | ths | cursor.id = vmsvga_fifo_read(s); |
589 | d34cab9f | ths | cursor.hot_x = vmsvga_fifo_read(s); |
590 | d34cab9f | ths | cursor.hot_y = vmsvga_fifo_read(s); |
591 | d34cab9f | ths | cursor.width = x = vmsvga_fifo_read(s); |
592 | d34cab9f | ths | cursor.height = y = vmsvga_fifo_read(s); |
593 | d34cab9f | ths | vmsvga_fifo_read(s); |
594 | d34cab9f | ths | cursor.bpp = vmsvga_fifo_read(s); |
595 | f2d928d4 | Roland Dreier | |
596 | f2d928d4 | Roland Dreier | if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || |
597 | f2d928d4 | Roland Dreier | SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
|
598 | f2d928d4 | Roland Dreier | args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
599 | f2d928d4 | Roland Dreier | goto badcmd;
|
600 | f2d928d4 | Roland Dreier | } |
601 | f2d928d4 | Roland Dreier | |
602 | d34cab9f | ths | for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
603 | ff9cf2cb | balrog | cursor.mask[args] = vmsvga_fifo_read_raw(s); |
604 | d34cab9f | ths | for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
605 | ff9cf2cb | balrog | cursor.image[args] = vmsvga_fifo_read_raw(s); |
606 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
607 | d34cab9f | ths | vmsvga_cursor_define(s, &cursor); |
608 | d34cab9f | ths | break;
|
609 | d34cab9f | ths | #else
|
610 | d34cab9f | ths | args = 0;
|
611 | d34cab9f | ths | goto badcmd;
|
612 | d34cab9f | ths | #endif
|
613 | d34cab9f | ths | |
614 | d34cab9f | ths | /*
|
615 | d34cab9f | ths | * Other commands that we at least know the number of arguments
|
616 | d34cab9f | ths | * for so we can avoid FIFO desync if driver uses them illegally.
|
617 | d34cab9f | ths | */
|
618 | d34cab9f | ths | case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
619 | d34cab9f | ths | vmsvga_fifo_read(s); |
620 | d34cab9f | ths | vmsvga_fifo_read(s); |
621 | d34cab9f | ths | vmsvga_fifo_read(s); |
622 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
623 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
624 | d34cab9f | ths | args = x * y; |
625 | d34cab9f | ths | goto badcmd;
|
626 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_FILL:
|
627 | d34cab9f | ths | args = 6;
|
628 | d34cab9f | ths | goto badcmd;
|
629 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_COPY:
|
630 | d34cab9f | ths | args = 7;
|
631 | d34cab9f | ths | goto badcmd;
|
632 | d34cab9f | ths | case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
633 | d34cab9f | ths | vmsvga_fifo_read(s); |
634 | d34cab9f | ths | vmsvga_fifo_read(s); |
635 | d34cab9f | ths | args = 7 + (vmsvga_fifo_read(s) >> 2); |
636 | d34cab9f | ths | goto badcmd;
|
637 | d34cab9f | ths | case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
638 | d34cab9f | ths | args = 12;
|
639 | d34cab9f | ths | goto badcmd;
|
640 | d34cab9f | ths | |
641 | d34cab9f | ths | /*
|
642 | d34cab9f | ths | * Other commands that are not listed as depending on any
|
643 | d34cab9f | ths | * CAPABILITIES bits, but are not described in the README either.
|
644 | d34cab9f | ths | */
|
645 | d34cab9f | ths | case SVGA_CMD_SURFACE_FILL:
|
646 | d34cab9f | ths | case SVGA_CMD_SURFACE_COPY:
|
647 | d34cab9f | ths | case SVGA_CMD_FRONT_ROP_FILL:
|
648 | d34cab9f | ths | case SVGA_CMD_FENCE:
|
649 | d34cab9f | ths | case SVGA_CMD_INVALID_CMD:
|
650 | d34cab9f | ths | break; /* Nop */ |
651 | d34cab9f | ths | |
652 | d34cab9f | ths | default:
|
653 | d34cab9f | ths | badcmd:
|
654 | d34cab9f | ths | while (args --)
|
655 | d34cab9f | ths | vmsvga_fifo_read(s); |
656 | d34cab9f | ths | printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
657 | d34cab9f | ths | __FUNCTION__, cmd); |
658 | d34cab9f | ths | break;
|
659 | d34cab9f | ths | } |
660 | d34cab9f | ths | |
661 | d34cab9f | ths | s->syncing = 0;
|
662 | d34cab9f | ths | } |
663 | d34cab9f | ths | |
664 | d34cab9f | ths | static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
665 | d34cab9f | ths | { |
666 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
667 | d34cab9f | ths | return s->index;
|
668 | d34cab9f | ths | } |
669 | d34cab9f | ths | |
670 | d34cab9f | ths | static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
671 | d34cab9f | ths | { |
672 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
673 | d34cab9f | ths | s->index = index; |
674 | d34cab9f | ths | } |
675 | d34cab9f | ths | |
676 | d34cab9f | ths | static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
677 | d34cab9f | ths | { |
678 | d34cab9f | ths | uint32_t caps; |
679 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
680 | d34cab9f | ths | switch (s->index) {
|
681 | d34cab9f | ths | case SVGA_REG_ID:
|
682 | d34cab9f | ths | return s->svgaid;
|
683 | d34cab9f | ths | |
684 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
685 | d34cab9f | ths | return s->enable;
|
686 | d34cab9f | ths | |
687 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
688 | d34cab9f | ths | return s->width;
|
689 | d34cab9f | ths | |
690 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
691 | d34cab9f | ths | return s->height;
|
692 | d34cab9f | ths | |
693 | d34cab9f | ths | case SVGA_REG_MAX_WIDTH:
|
694 | d34cab9f | ths | return SVGA_MAX_WIDTH;
|
695 | d34cab9f | ths | |
696 | d34cab9f | ths | case SVGA_REG_MAX_HEIGHT:
|
697 | f707cfba | balrog | return SVGA_MAX_HEIGHT;
|
698 | d34cab9f | ths | |
699 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
700 | d34cab9f | ths | return s->depth;
|
701 | d34cab9f | ths | |
702 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
703 | d34cab9f | ths | return (s->depth + 7) & ~7; |
704 | d34cab9f | ths | |
705 | d34cab9f | ths | case SVGA_REG_PSEUDOCOLOR:
|
706 | d34cab9f | ths | return 0x0; |
707 | d34cab9f | ths | |
708 | d34cab9f | ths | case SVGA_REG_RED_MASK:
|
709 | d34cab9f | ths | return s->wred;
|
710 | d34cab9f | ths | case SVGA_REG_GREEN_MASK:
|
711 | d34cab9f | ths | return s->wgreen;
|
712 | d34cab9f | ths | case SVGA_REG_BLUE_MASK:
|
713 | d34cab9f | ths | return s->wblue;
|
714 | d34cab9f | ths | |
715 | d34cab9f | ths | case SVGA_REG_BYTES_PER_LINE:
|
716 | d34cab9f | ths | return ((s->depth + 7) >> 3) * s->new_width; |
717 | d34cab9f | ths | |
718 | d34cab9f | ths | case SVGA_REG_FB_START:
|
719 | 3016d80b | balrog | return s->vram_base;
|
720 | d34cab9f | ths | |
721 | d34cab9f | ths | case SVGA_REG_FB_OFFSET:
|
722 | d34cab9f | ths | return 0x0; |
723 | d34cab9f | ths | |
724 | d34cab9f | ths | case SVGA_REG_VRAM_SIZE:
|
725 | f351d050 | Dave Airlie | return s->vga.vram_size;
|
726 | d34cab9f | ths | |
727 | d34cab9f | ths | case SVGA_REG_FB_SIZE:
|
728 | d34cab9f | ths | return s->fb_size;
|
729 | d34cab9f | ths | |
730 | d34cab9f | ths | case SVGA_REG_CAPABILITIES:
|
731 | d34cab9f | ths | caps = SVGA_CAP_NONE; |
732 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
733 | d34cab9f | ths | caps |= SVGA_CAP_RECT_COPY; |
734 | d34cab9f | ths | #endif
|
735 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
736 | d34cab9f | ths | caps |= SVGA_CAP_RECT_FILL; |
737 | d34cab9f | ths | #endif
|
738 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
739 | 4e12cd94 | Avi Kivity | if (s->vga.ds->mouse_set)
|
740 | d34cab9f | ths | caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
741 | d34cab9f | ths | SVGA_CAP_CURSOR_BYPASS; |
742 | d34cab9f | ths | #endif
|
743 | d34cab9f | ths | return caps;
|
744 | d34cab9f | ths | |
745 | d34cab9f | ths | case SVGA_REG_MEM_START:
|
746 | f351d050 | Dave Airlie | return s->fifo_base;
|
747 | d34cab9f | ths | |
748 | d34cab9f | ths | case SVGA_REG_MEM_SIZE:
|
749 | f351d050 | Dave Airlie | return s->fifo_size;
|
750 | d34cab9f | ths | |
751 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
752 | d34cab9f | ths | return s->config;
|
753 | d34cab9f | ths | |
754 | d34cab9f | ths | case SVGA_REG_SYNC:
|
755 | d34cab9f | ths | case SVGA_REG_BUSY:
|
756 | d34cab9f | ths | return s->syncing;
|
757 | d34cab9f | ths | |
758 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
759 | d34cab9f | ths | return s->guest;
|
760 | d34cab9f | ths | |
761 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
762 | d34cab9f | ths | return s->cursor.id;
|
763 | d34cab9f | ths | |
764 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
765 | d34cab9f | ths | return s->cursor.x;
|
766 | d34cab9f | ths | |
767 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
768 | d34cab9f | ths | return s->cursor.x;
|
769 | d34cab9f | ths | |
770 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
771 | d34cab9f | ths | return s->cursor.on;
|
772 | d34cab9f | ths | |
773 | d34cab9f | ths | case SVGA_REG_HOST_BITS_PER_PIXEL:
|
774 | d34cab9f | ths | return (s->depth + 7) & ~7; |
775 | d34cab9f | ths | |
776 | d34cab9f | ths | case SVGA_REG_SCRATCH_SIZE:
|
777 | d34cab9f | ths | return s->scratch_size;
|
778 | d34cab9f | ths | |
779 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
780 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
781 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
782 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
783 | d34cab9f | ths | return 0; |
784 | d34cab9f | ths | |
785 | d34cab9f | ths | default:
|
786 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
787 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
788 | d34cab9f | ths | return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
789 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
790 | d34cab9f | ths | } |
791 | d34cab9f | ths | |
792 | d34cab9f | ths | return 0; |
793 | d34cab9f | ths | } |
794 | d34cab9f | ths | |
795 | d34cab9f | ths | static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
796 | d34cab9f | ths | { |
797 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
798 | d34cab9f | ths | switch (s->index) {
|
799 | d34cab9f | ths | case SVGA_REG_ID:
|
800 | d34cab9f | ths | if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
801 | d34cab9f | ths | s->svgaid = value; |
802 | d34cab9f | ths | break;
|
803 | d34cab9f | ths | |
804 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
805 | f707cfba | balrog | s->enable = value; |
806 | f707cfba | balrog | s->config &= !!value; |
807 | d34cab9f | ths | s->width = -1;
|
808 | d34cab9f | ths | s->height = -1;
|
809 | d34cab9f | ths | s->invalidated = 1;
|
810 | 4e12cd94 | Avi Kivity | s->vga.invalidate(&s->vga); |
811 | b5cc6e32 | Anthony Liguori | if (s->enable) {
|
812 | b5cc6e32 | Anthony Liguori | s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
813 | b5cc6e32 | Anthony Liguori | vga_dirty_log_stop(&s->vga); |
814 | b5cc6e32 | Anthony Liguori | } else {
|
815 | b5cc6e32 | Anthony Liguori | vga_dirty_log_start(&s->vga); |
816 | b5cc6e32 | Anthony Liguori | } |
817 | d34cab9f | ths | break;
|
818 | d34cab9f | ths | |
819 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
820 | d34cab9f | ths | s->new_width = value; |
821 | d34cab9f | ths | s->invalidated = 1;
|
822 | d34cab9f | ths | break;
|
823 | d34cab9f | ths | |
824 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
825 | d34cab9f | ths | s->new_height = value; |
826 | d34cab9f | ths | s->invalidated = 1;
|
827 | d34cab9f | ths | break;
|
828 | d34cab9f | ths | |
829 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
830 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
831 | d34cab9f | ths | if (value != s->depth) {
|
832 | d34cab9f | ths | printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
833 | d34cab9f | ths | s->config = 0;
|
834 | d34cab9f | ths | } |
835 | d34cab9f | ths | break;
|
836 | d34cab9f | ths | |
837 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
838 | d34cab9f | ths | if (value) {
|
839 | f351d050 | Dave Airlie | s->fifo = (uint32_t *) s->fifo_ptr; |
840 | d34cab9f | ths | /* Check range and alignment. */
|
841 | ff9cf2cb | balrog | if ((CMD(min) | CMD(max) |
|
842 | ff9cf2cb | balrog | CMD(next_cmd) | CMD(stop)) & 3)
|
843 | d34cab9f | ths | break;
|
844 | ff9cf2cb | balrog | if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
845 | d34cab9f | ths | break;
|
846 | ff9cf2cb | balrog | if (CMD(max) > SVGA_FIFO_SIZE)
|
847 | d34cab9f | ths | break;
|
848 | ff9cf2cb | balrog | if (CMD(max) < CMD(min) + 10 * 1024) |
849 | d34cab9f | ths | break;
|
850 | d34cab9f | ths | } |
851 | f707cfba | balrog | s->config = !!value; |
852 | d34cab9f | ths | break;
|
853 | d34cab9f | ths | |
854 | d34cab9f | ths | case SVGA_REG_SYNC:
|
855 | d34cab9f | ths | s->syncing = 1;
|
856 | d34cab9f | ths | vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
857 | d34cab9f | ths | break;
|
858 | d34cab9f | ths | |
859 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
860 | d34cab9f | ths | s->guest = value; |
861 | d34cab9f | ths | #ifdef VERBOSE
|
862 | d34cab9f | ths | if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
863 | b1503cda | malc | ARRAY_SIZE(vmsvga_guest_id)) |
864 | d34cab9f | ths | printf("%s: guest runs %s.\n", __FUNCTION__,
|
865 | d34cab9f | ths | vmsvga_guest_id[value - GUEST_OS_BASE]); |
866 | d34cab9f | ths | #endif
|
867 | d34cab9f | ths | break;
|
868 | d34cab9f | ths | |
869 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
870 | d34cab9f | ths | s->cursor.id = value; |
871 | d34cab9f | ths | break;
|
872 | d34cab9f | ths | |
873 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
874 | d34cab9f | ths | s->cursor.x = value; |
875 | d34cab9f | ths | break;
|
876 | d34cab9f | ths | |
877 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
878 | d34cab9f | ths | s->cursor.y = value; |
879 | d34cab9f | ths | break;
|
880 | d34cab9f | ths | |
881 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
882 | d34cab9f | ths | s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
883 | d34cab9f | ths | s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
884 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
885 | 4e12cd94 | Avi Kivity | if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
886 | 4e12cd94 | Avi Kivity | s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
887 | d34cab9f | ths | #endif
|
888 | d34cab9f | ths | break;
|
889 | d34cab9f | ths | |
890 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
891 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
892 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
893 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
894 | d34cab9f | ths | break;
|
895 | d34cab9f | ths | |
896 | d34cab9f | ths | default:
|
897 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
898 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
899 | d34cab9f | ths | s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
900 | d34cab9f | ths | break;
|
901 | d34cab9f | ths | } |
902 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
903 | d34cab9f | ths | } |
904 | d34cab9f | ths | } |
905 | d34cab9f | ths | |
906 | d34cab9f | ths | static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
907 | d34cab9f | ths | { |
908 | d34cab9f | ths | printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
909 | d34cab9f | ths | return 0xcafe; |
910 | d34cab9f | ths | } |
911 | d34cab9f | ths | |
912 | d34cab9f | ths | static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
913 | d34cab9f | ths | { |
914 | d34cab9f | ths | printf("%s: what are we supposed to do with (%08x)?\n",
|
915 | d34cab9f | ths | __FUNCTION__, data); |
916 | d34cab9f | ths | } |
917 | d34cab9f | ths | |
918 | d34cab9f | ths | static inline void vmsvga_size(struct vmsvga_state_s *s) |
919 | d34cab9f | ths | { |
920 | d34cab9f | ths | if (s->new_width != s->width || s->new_height != s->height) {
|
921 | d34cab9f | ths | s->width = s->new_width; |
922 | d34cab9f | ths | s->height = s->new_height; |
923 | 4e12cd94 | Avi Kivity | qemu_console_resize(s->vga.ds, s->width, s->height); |
924 | d34cab9f | ths | s->invalidated = 1;
|
925 | d34cab9f | ths | } |
926 | d34cab9f | ths | } |
927 | d34cab9f | ths | |
928 | d34cab9f | ths | static void vmsvga_update_display(void *opaque) |
929 | d34cab9f | ths | { |
930 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
931 | d34cab9f | ths | if (!s->enable) {
|
932 | 4e12cd94 | Avi Kivity | s->vga.update(&s->vga); |
933 | d34cab9f | ths | return;
|
934 | d34cab9f | ths | } |
935 | d34cab9f | ths | |
936 | d34cab9f | ths | vmsvga_size(s); |
937 | d34cab9f | ths | |
938 | d34cab9f | ths | vmsvga_fifo_run(s); |
939 | d34cab9f | ths | vmsvga_update_rect_flush(s); |
940 | d34cab9f | ths | |
941 | d34cab9f | ths | /*
|
942 | d34cab9f | ths | * Is it more efficient to look at vram VGA-dirty bits or wait
|
943 | d34cab9f | ths | * for the driver to issue SVGA_CMD_UPDATE?
|
944 | d34cab9f | ths | */
|
945 | d34cab9f | ths | if (s->invalidated) {
|
946 | d34cab9f | ths | s->invalidated = 0;
|
947 | d34cab9f | ths | vmsvga_update_screen(s); |
948 | d34cab9f | ths | } |
949 | d34cab9f | ths | } |
950 | d34cab9f | ths | |
951 | d34cab9f | ths | static void vmsvga_reset(struct vmsvga_state_s *s) |
952 | d34cab9f | ths | { |
953 | d34cab9f | ths | s->index = 0;
|
954 | d34cab9f | ths | s->enable = 0;
|
955 | d34cab9f | ths | s->config = 0;
|
956 | d34cab9f | ths | s->width = -1;
|
957 | d34cab9f | ths | s->height = -1;
|
958 | d34cab9f | ths | s->svgaid = SVGA_ID; |
959 | a6109ff1 | Anthony Liguori | s->depth = ds_get_bits_per_pixel(s->vga.ds); |
960 | a6109ff1 | Anthony Liguori | s->bypp = ds_get_bytes_per_pixel(s->vga.ds); |
961 | d34cab9f | ths | s->cursor.on = 0;
|
962 | d34cab9f | ths | s->redraw_fifo_first = 0;
|
963 | d34cab9f | ths | s->redraw_fifo_last = 0;
|
964 | d34cab9f | ths | switch (s->depth) {
|
965 | d34cab9f | ths | case 8: |
966 | d34cab9f | ths | s->wred = 0x00000007;
|
967 | d34cab9f | ths | s->wgreen = 0x00000038;
|
968 | d34cab9f | ths | s->wblue = 0x000000c0;
|
969 | d34cab9f | ths | break;
|
970 | d34cab9f | ths | case 15: |
971 | d34cab9f | ths | s->wred = 0x0000001f;
|
972 | d34cab9f | ths | s->wgreen = 0x000003e0;
|
973 | d34cab9f | ths | s->wblue = 0x00007c00;
|
974 | d34cab9f | ths | break;
|
975 | d34cab9f | ths | case 16: |
976 | d34cab9f | ths | s->wred = 0x0000001f;
|
977 | d34cab9f | ths | s->wgreen = 0x000007e0;
|
978 | d34cab9f | ths | s->wblue = 0x0000f800;
|
979 | d34cab9f | ths | break;
|
980 | d34cab9f | ths | case 24: |
981 | f707cfba | balrog | s->wred = 0x00ff0000;
|
982 | d34cab9f | ths | s->wgreen = 0x0000ff00;
|
983 | f707cfba | balrog | s->wblue = 0x000000ff;
|
984 | d34cab9f | ths | break;
|
985 | d34cab9f | ths | case 32: |
986 | f707cfba | balrog | s->wred = 0x00ff0000;
|
987 | d34cab9f | ths | s->wgreen = 0x0000ff00;
|
988 | f707cfba | balrog | s->wblue = 0x000000ff;
|
989 | d34cab9f | ths | break;
|
990 | d34cab9f | ths | } |
991 | d34cab9f | ths | s->syncing = 0;
|
992 | b5cc6e32 | Anthony Liguori | |
993 | b5cc6e32 | Anthony Liguori | vga_dirty_log_start(&s->vga); |
994 | d34cab9f | ths | } |
995 | d34cab9f | ths | |
996 | d34cab9f | ths | static void vmsvga_invalidate_display(void *opaque) |
997 | d34cab9f | ths | { |
998 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
999 | d34cab9f | ths | if (!s->enable) {
|
1000 | 4e12cd94 | Avi Kivity | s->vga.invalidate(&s->vga); |
1001 | d34cab9f | ths | return;
|
1002 | d34cab9f | ths | } |
1003 | d34cab9f | ths | |
1004 | d34cab9f | ths | s->invalidated = 1;
|
1005 | d34cab9f | ths | } |
1006 | d34cab9f | ths | |
1007 | f707cfba | balrog | /* save the vga display in a PPM image even if no display is
|
1008 | f707cfba | balrog | available */
|
1009 | d34cab9f | ths | static void vmsvga_screen_dump(void *opaque, const char *filename) |
1010 | d34cab9f | ths | { |
1011 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1012 | d34cab9f | ths | if (!s->enable) {
|
1013 | 4e12cd94 | Avi Kivity | s->vga.screen_dump(&s->vga, filename); |
1014 | d34cab9f | ths | return;
|
1015 | d34cab9f | ths | } |
1016 | d34cab9f | ths | |
1017 | f707cfba | balrog | if (s->depth == 32) { |
1018 | e07d630a | aliguori | DisplaySurface *ds = qemu_create_displaysurface_from(s->width, |
1019 | 4e12cd94 | Avi Kivity | s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
|
1020 | e07d630a | aliguori | ppm_save(filename, ds); |
1021 | e07d630a | aliguori | qemu_free(ds); |
1022 | f707cfba | balrog | } |
1023 | d34cab9f | ths | } |
1024 | d34cab9f | ths | |
1025 | c227f099 | Anthony Liguori | static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
1026 | 4d3b6f6e | balrog | { |
1027 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1028 | 4d3b6f6e | balrog | |
1029 | 4e12cd94 | Avi Kivity | if (s->vga.text_update)
|
1030 | 4e12cd94 | Avi Kivity | s->vga.text_update(&s->vga, chardata); |
1031 | 4d3b6f6e | balrog | } |
1032 | 4d3b6f6e | balrog | |
1033 | d34cab9f | ths | #ifdef DIRECT_VRAM
|
1034 | c227f099 | Anthony Liguori | static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) |
1035 | d34cab9f | ths | { |
1036 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1037 | d34cab9f | ths | if (addr < s->fb_size)
|
1038 | 0e1f5a0c | aliguori | return *(uint8_t *) (ds_get_data(s->ds) + addr);
|
1039 | d34cab9f | ths | else
|
1040 | b584726d | pbrook | return *(uint8_t *) (s->vram_ptr + addr);
|
1041 | d34cab9f | ths | } |
1042 | d34cab9f | ths | |
1043 | c227f099 | Anthony Liguori | static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) |
1044 | d34cab9f | ths | { |
1045 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1046 | d34cab9f | ths | if (addr < s->fb_size)
|
1047 | 0e1f5a0c | aliguori | return *(uint16_t *) (ds_get_data(s->ds) + addr);
|
1048 | d34cab9f | ths | else
|
1049 | b584726d | pbrook | return *(uint16_t *) (s->vram_ptr + addr);
|
1050 | d34cab9f | ths | } |
1051 | d34cab9f | ths | |
1052 | c227f099 | Anthony Liguori | static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) |
1053 | d34cab9f | ths | { |
1054 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1055 | d34cab9f | ths | if (addr < s->fb_size)
|
1056 | 0e1f5a0c | aliguori | return *(uint32_t *) (ds_get_data(s->ds) + addr);
|
1057 | d34cab9f | ths | else
|
1058 | b584726d | pbrook | return *(uint32_t *) (s->vram_ptr + addr);
|
1059 | d34cab9f | ths | } |
1060 | d34cab9f | ths | |
1061 | c227f099 | Anthony Liguori | static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, |
1062 | d34cab9f | ths | uint32_t value) |
1063 | d34cab9f | ths | { |
1064 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1065 | d34cab9f | ths | if (addr < s->fb_size)
|
1066 | 0e1f5a0c | aliguori | *(uint8_t *) (ds_get_data(s->ds) + addr) = value; |
1067 | d34cab9f | ths | else
|
1068 | b584726d | pbrook | *(uint8_t *) (s->vram_ptr + addr) = value; |
1069 | d34cab9f | ths | } |
1070 | d34cab9f | ths | |
1071 | c227f099 | Anthony Liguori | static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, |
1072 | d34cab9f | ths | uint32_t value) |
1073 | d34cab9f | ths | { |
1074 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1075 | d34cab9f | ths | if (addr < s->fb_size)
|
1076 | 0e1f5a0c | aliguori | *(uint16_t *) (ds_get_data(s->ds) + addr) = value; |
1077 | d34cab9f | ths | else
|
1078 | b584726d | pbrook | *(uint16_t *) (s->vram_ptr + addr) = value; |
1079 | d34cab9f | ths | } |
1080 | d34cab9f | ths | |
1081 | c227f099 | Anthony Liguori | static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, |
1082 | d34cab9f | ths | uint32_t value) |
1083 | d34cab9f | ths | { |
1084 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1085 | d34cab9f | ths | if (addr < s->fb_size)
|
1086 | 0e1f5a0c | aliguori | *(uint32_t *) (ds_get_data(s->ds) + addr) = value; |
1087 | d34cab9f | ths | else
|
1088 | b584726d | pbrook | *(uint32_t *) (s->vram_ptr + addr) = value; |
1089 | d34cab9f | ths | } |
1090 | d34cab9f | ths | |
1091 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const vmsvga_vram_read[] = { |
1092 | d34cab9f | ths | vmsvga_vram_readb, |
1093 | d34cab9f | ths | vmsvga_vram_readw, |
1094 | d34cab9f | ths | vmsvga_vram_readl, |
1095 | d34cab9f | ths | }; |
1096 | d34cab9f | ths | |
1097 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const vmsvga_vram_write[] = { |
1098 | d34cab9f | ths | vmsvga_vram_writeb, |
1099 | d34cab9f | ths | vmsvga_vram_writew, |
1100 | d34cab9f | ths | vmsvga_vram_writel, |
1101 | d34cab9f | ths | }; |
1102 | d34cab9f | ths | #endif
|
1103 | d34cab9f | ths | |
1104 | bacbe284 | Juan Quintela | static int vmsvga_post_load(void *opaque, int version_id) |
1105 | d34cab9f | ths | { |
1106 | bacbe284 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1107 | d34cab9f | ths | |
1108 | d34cab9f | ths | s->invalidated = 1;
|
1109 | d34cab9f | ths | if (s->config)
|
1110 | f351d050 | Dave Airlie | s->fifo = (uint32_t *) s->fifo_ptr; |
1111 | d34cab9f | ths | |
1112 | d34cab9f | ths | return 0; |
1113 | d34cab9f | ths | } |
1114 | d34cab9f | ths | |
1115 | d05ac8fa | Blue Swirl | static const VMStateDescription vmstate_vmware_vga_internal = { |
1116 | bacbe284 | Juan Quintela | .name = "vmware_vga_internal",
|
1117 | bacbe284 | Juan Quintela | .version_id = 0,
|
1118 | bacbe284 | Juan Quintela | .minimum_version_id = 0,
|
1119 | bacbe284 | Juan Quintela | .minimum_version_id_old = 0,
|
1120 | bacbe284 | Juan Quintela | .post_load = vmsvga_post_load, |
1121 | bacbe284 | Juan Quintela | .fields = (VMStateField []) { |
1122 | bacbe284 | Juan Quintela | VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
|
1123 | bacbe284 | Juan Quintela | VMSTATE_INT32(enable, struct vmsvga_state_s),
|
1124 | bacbe284 | Juan Quintela | VMSTATE_INT32(config, struct vmsvga_state_s),
|
1125 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
1126 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
1127 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
1128 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
1129 | bacbe284 | Juan Quintela | VMSTATE_INT32(index, struct vmsvga_state_s),
|
1130 | bacbe284 | Juan Quintela | VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
1131 | bacbe284 | Juan Quintela | scratch_size, 0, vmstate_info_uint32, uint32_t),
|
1132 | bacbe284 | Juan Quintela | VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
1133 | bacbe284 | Juan Quintela | VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
1134 | bacbe284 | Juan Quintela | VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
1135 | bacbe284 | Juan Quintela | VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
1136 | bacbe284 | Juan Quintela | VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
1137 | bacbe284 | Juan Quintela | VMSTATE_INT32(fb_size, struct vmsvga_state_s),
|
1138 | bacbe284 | Juan Quintela | VMSTATE_END_OF_LIST() |
1139 | bacbe284 | Juan Quintela | } |
1140 | bacbe284 | Juan Quintela | }; |
1141 | bacbe284 | Juan Quintela | |
1142 | d05ac8fa | Blue Swirl | static const VMStateDescription vmstate_vmware_vga = { |
1143 | bacbe284 | Juan Quintela | .name = "vmware_vga",
|
1144 | bacbe284 | Juan Quintela | .version_id = 0,
|
1145 | bacbe284 | Juan Quintela | .minimum_version_id = 0,
|
1146 | bacbe284 | Juan Quintela | .minimum_version_id_old = 0,
|
1147 | bacbe284 | Juan Quintela | .fields = (VMStateField []) { |
1148 | bacbe284 | Juan Quintela | VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
|
1149 | bacbe284 | Juan Quintela | VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1150 | bacbe284 | Juan Quintela | vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
1151 | bacbe284 | Juan Quintela | VMSTATE_END_OF_LIST() |
1152 | bacbe284 | Juan Quintela | } |
1153 | bacbe284 | Juan Quintela | }; |
1154 | bacbe284 | Juan Quintela | |
1155 | b584726d | pbrook | static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size) |
1156 | d34cab9f | ths | { |
1157 | d34cab9f | ths | s->scratch_size = SVGA_SCRATCH_SIZE; |
1158 | fe740c43 | Juan Quintela | s->scratch = qemu_malloc(s->scratch_size * 4);
|
1159 | d34cab9f | ths | |
1160 | a6109ff1 | Anthony Liguori | s->vga.ds = graphic_console_init(vmsvga_update_display, |
1161 | a6109ff1 | Anthony Liguori | vmsvga_invalidate_display, |
1162 | a6109ff1 | Anthony Liguori | vmsvga_screen_dump, |
1163 | a6109ff1 | Anthony Liguori | vmsvga_text_update, s); |
1164 | a6109ff1 | Anthony Liguori | |
1165 | 4445b0a6 | Andrzej Zaborowski | |
1166 | f351d050 | Dave Airlie | s->fifo_size = SVGA_FIFO_SIZE; |
1167 | f351d050 | Dave Airlie | s->fifo_offset = qemu_ram_alloc(s->fifo_size); |
1168 | f351d050 | Dave Airlie | s->fifo_ptr = qemu_get_ram_ptr(s->fifo_offset); |
1169 | f351d050 | Dave Airlie | |
1170 | a4a2f59c | Juan Quintela | vga_common_init(&s->vga, vga_ram_size); |
1171 | a4a2f59c | Juan Quintela | vga_init(&s->vga); |
1172 | f74599c4 | Juan Quintela | vmstate_register(0, &vmstate_vga_common, &s->vga);
|
1173 | e93a5f4f | balrog | |
1174 | f0138a63 | Anthony Liguori | vga_init_vbe(&s->vga); |
1175 | b5cc6e32 | Anthony Liguori | |
1176 | f0138a63 | Anthony Liguori | rom_add_vga(VGABIOS_FILENAME); |
1177 | b5cc6e32 | Anthony Liguori | |
1178 | b5cc6e32 | Anthony Liguori | vmsvga_reset(s); |
1179 | d34cab9f | ths | } |
1180 | d34cab9f | ths | |
1181 | 1492a3c4 | balrog | static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num, |
1182 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
1183 | 1492a3c4 | balrog | { |
1184 | 1492a3c4 | balrog | struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1185 | 1492a3c4 | balrog | struct vmsvga_state_s *s = &d->chip;
|
1186 | 1492a3c4 | balrog | |
1187 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1188 | 1492a3c4 | balrog | 1, 4, vmsvga_index_read, s); |
1189 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT, |
1190 | 1492a3c4 | balrog | 1, 4, vmsvga_index_write, s); |
1191 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1192 | 1492a3c4 | balrog | 1, 4, vmsvga_value_read, s); |
1193 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT, |
1194 | 1492a3c4 | balrog | 1, 4, vmsvga_value_write, s); |
1195 | 1492a3c4 | balrog | register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1196 | 1492a3c4 | balrog | 1, 4, vmsvga_bios_read, s); |
1197 | 1492a3c4 | balrog | register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT, |
1198 | 1492a3c4 | balrog | 1, 4, vmsvga_bios_write, s); |
1199 | 1492a3c4 | balrog | } |
1200 | 1492a3c4 | balrog | |
1201 | 3016d80b | balrog | static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, |
1202 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
1203 | 3016d80b | balrog | { |
1204 | 3016d80b | balrog | struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1205 | 3016d80b | balrog | struct vmsvga_state_s *s = &d->chip;
|
1206 | c227f099 | Anthony Liguori | ram_addr_t iomemtype; |
1207 | 3016d80b | balrog | |
1208 | 3016d80b | balrog | s->vram_base = addr; |
1209 | 3016d80b | balrog | #ifdef DIRECT_VRAM
|
1210 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(vmsvga_vram_read, |
1211 | 3016d80b | balrog | vmsvga_vram_write, s); |
1212 | 3016d80b | balrog | #else
|
1213 | 4e12cd94 | Avi Kivity | iomemtype = s->vga.vram_offset | IO_MEM_RAM; |
1214 | 3016d80b | balrog | #endif
|
1215 | 4e12cd94 | Avi Kivity | cpu_register_physical_memory(s->vram_base, s->vga.vram_size, |
1216 | 3016d80b | balrog | iomemtype); |
1217 | ee3e41a9 | Anthony Liguori | |
1218 | ee3e41a9 | Anthony Liguori | s->vga.map_addr = addr; |
1219 | ee3e41a9 | Anthony Liguori | s->vga.map_end = addr + s->vga.vram_size; |
1220 | b5cc6e32 | Anthony Liguori | vga_dirty_log_restart(&s->vga); |
1221 | 3016d80b | balrog | } |
1222 | 3016d80b | balrog | |
1223 | f351d050 | Dave Airlie | static void pci_vmsvga_map_fifo(PCIDevice *pci_dev, int region_num, |
1224 | f351d050 | Dave Airlie | pcibus_t addr, pcibus_t size, int type)
|
1225 | f351d050 | Dave Airlie | { |
1226 | f351d050 | Dave Airlie | struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev; |
1227 | f351d050 | Dave Airlie | struct vmsvga_state_s *s = &d->chip;
|
1228 | f351d050 | Dave Airlie | ram_addr_t iomemtype; |
1229 | f351d050 | Dave Airlie | |
1230 | f351d050 | Dave Airlie | s->fifo_base = addr; |
1231 | f351d050 | Dave Airlie | iomemtype = s->fifo_offset | IO_MEM_RAM; |
1232 | f351d050 | Dave Airlie | cpu_register_physical_memory(s->fifo_base, s->fifo_size, |
1233 | f351d050 | Dave Airlie | iomemtype); |
1234 | f351d050 | Dave Airlie | } |
1235 | f351d050 | Dave Airlie | |
1236 | 81a322d4 | Gerd Hoffmann | static int pci_vmsvga_initfn(PCIDevice *dev) |
1237 | d34cab9f | ths | { |
1238 | a414c306 | Gerd Hoffmann | struct pci_vmsvga_state_s *s =
|
1239 | a414c306 | Gerd Hoffmann | DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1240 | d34cab9f | ths | |
1241 | deb54399 | aliguori | pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE); |
1242 | deb54399 | aliguori | pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID); |
1243 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_COMMAND] = PCI_COMMAND_IO | |
1244 | 3fa0f955 | Michael S. Tsirkin | PCI_COMMAND_MEMORY | |
1245 | 3fa0f955 | Michael S. Tsirkin | PCI_COMMAND_MASTER; /* I/O + Memory */
|
1246 | 173a543b | blueswir1 | pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA); |
1247 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
1248 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ |
1249 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; |
1250 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_SUBSYSTEM_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
|
1251 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_SUBSYSTEM_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8; |
1252 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_SUBSYSTEM_ID] = SVGA_PCI_DEVICE_ID & 0xff;
|
1253 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_SUBSYSTEM_ID + 1] = SVGA_PCI_DEVICE_ID >> 8; |
1254 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ |
1255 | d34cab9f | ths | |
1256 | 28c2c264 | Avi Kivity | pci_register_bar(&s->card, 0, 0x10, |
1257 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport); |
1258 | 28c2c264 | Avi Kivity | pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
|
1259 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem); |
1260 | 1492a3c4 | balrog | |
1261 | f351d050 | Dave Airlie | pci_register_bar(&s->card, 2, SVGA_FIFO_SIZE,
|
1262 | f351d050 | Dave Airlie | PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_fifo); |
1263 | f351d050 | Dave Airlie | |
1264 | fbe1b595 | Paul Brook | vmsvga_init(&s->chip, VGA_RAM_SIZE); |
1265 | d34cab9f | ths | |
1266 | 81a322d4 | Gerd Hoffmann | return 0; |
1267 | d34cab9f | ths | } |
1268 | a414c306 | Gerd Hoffmann | |
1269 | a414c306 | Gerd Hoffmann | void pci_vmsvga_init(PCIBus *bus)
|
1270 | a414c306 | Gerd Hoffmann | { |
1271 | 556cd098 | Markus Armbruster | pci_create_simple(bus, -1, "vmware-svga"); |
1272 | a414c306 | Gerd Hoffmann | } |
1273 | a414c306 | Gerd Hoffmann | |
1274 | a414c306 | Gerd Hoffmann | static PCIDeviceInfo vmsvga_info = {
|
1275 | 556cd098 | Markus Armbruster | .qdev.name = "vmware-svga",
|
1276 | a414c306 | Gerd Hoffmann | .qdev.size = sizeof(struct pci_vmsvga_state_s), |
1277 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_vmware_vga, |
1278 | a414c306 | Gerd Hoffmann | .init = pci_vmsvga_initfn, |
1279 | a414c306 | Gerd Hoffmann | }; |
1280 | a414c306 | Gerd Hoffmann | |
1281 | a414c306 | Gerd Hoffmann | static void vmsvga_register(void) |
1282 | a414c306 | Gerd Hoffmann | { |
1283 | a414c306 | Gerd Hoffmann | pci_qdev_register(&vmsvga_info); |
1284 | a414c306 | Gerd Hoffmann | } |
1285 | a414c306 | Gerd Hoffmann | device_init(vmsvga_register); |