root / hw / slavio_timer.c @ 0bf9e31a
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | c70c59ee | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | c70c59ee | Blue Swirl | #include "sysbus.h" |
28 | e80cfcfc | bellard | |
29 | e80cfcfc | bellard | //#define DEBUG_TIMER
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30 | e80cfcfc | bellard | |
31 | 66321a11 | bellard | #ifdef DEBUG_TIMER
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32 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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33 | 001faf32 | Blue Swirl | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
34 | 66321a11 | bellard | #else
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35 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
36 | 66321a11 | bellard | #endif
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37 | 66321a11 | bellard | |
38 | e80cfcfc | bellard | /*
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39 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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40 | e80cfcfc | bellard | *
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41 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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42 | e80cfcfc | bellard | * produced as NCR89C105. See
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43 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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44 | 5fafdf24 | ths | *
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45 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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46 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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47 | e80cfcfc | bellard | *
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48 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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49 | ba3c64fb | bellard | * interrupt routing.
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50 | ba3c64fb | bellard | *
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51 | e80cfcfc | bellard | */
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52 | e80cfcfc | bellard | |
53 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
54 | 81732d19 | blueswir1 | |
55 | e80cfcfc | bellard | typedef struct SLAVIO_TIMERState { |
56 | c70c59ee | Blue Swirl | SysBusDevice busdev; |
57 | d7edfd27 | blueswir1 | qemu_irq irq; |
58 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
59 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
60 | 8d05ea8a | blueswir1 | uint64_t limit; |
61 | 115646b6 | blueswir1 | // processor only
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62 | 22548760 | blueswir1 | uint32_t running; |
63 | 115646b6 | blueswir1 | struct SLAVIO_TIMERState *master;
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64 | 22548760 | blueswir1 | uint32_t slave_index; |
65 | 115646b6 | blueswir1 | // system only
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66 | 22548760 | blueswir1 | uint32_t num_slaves; |
67 | 81732d19 | blueswir1 | struct SLAVIO_TIMERState *slave[MAX_CPUS];
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68 | 81732d19 | blueswir1 | uint32_t slave_mode; |
69 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
70 | e80cfcfc | bellard | |
71 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
72 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
73 | e80cfcfc | bellard | |
74 | d2c38b24 | blueswir1 | #define SYS_TIMER_OFFSET 0x10000ULL |
75 | d2c38b24 | blueswir1 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
76 | d2c38b24 | blueswir1 | |
77 | d2c38b24 | blueswir1 | #define TIMER_LIMIT 0 |
78 | d2c38b24 | blueswir1 | #define TIMER_COUNTER 1 |
79 | d2c38b24 | blueswir1 | #define TIMER_COUNTER_NORST 2 |
80 | d2c38b24 | blueswir1 | #define TIMER_STATUS 3 |
81 | d2c38b24 | blueswir1 | #define TIMER_MODE 4 |
82 | d2c38b24 | blueswir1 | |
83 | d2c38b24 | blueswir1 | #define TIMER_COUNT_MASK32 0xfffffe00 |
84 | d2c38b24 | blueswir1 | #define TIMER_LIMIT_MASK32 0x7fffffff |
85 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
86 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
87 | d2c38b24 | blueswir1 | #define TIMER_REACHED 0x80000000 |
88 | d2c38b24 | blueswir1 | #define TIMER_PERIOD 500ULL // 500ns |
89 | d2c38b24 | blueswir1 | #define LIMIT_TO_PERIODS(l) ((l) >> 9) |
90 | d2c38b24 | blueswir1 | #define PERIODS_TO_LIMIT(l) ((l) << 9) |
91 | d2c38b24 | blueswir1 | |
92 | 115646b6 | blueswir1 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) |
93 | 115646b6 | blueswir1 | { |
94 | 115646b6 | blueswir1 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); |
95 | 115646b6 | blueswir1 | } |
96 | 115646b6 | blueswir1 | |
97 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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98 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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99 | e80cfcfc | bellard | static void slavio_timer_get_out(SLAVIO_TIMERState *s) |
100 | e80cfcfc | bellard | { |
101 | bd7e2875 | blueswir1 | uint64_t count, limit; |
102 | e80cfcfc | bellard | |
103 | bd7e2875 | blueswir1 | if (s->limit == 0) /* free-run processor or system counter */ |
104 | bd7e2875 | blueswir1 | limit = TIMER_MAX_COUNT32; |
105 | bd7e2875 | blueswir1 | else
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106 | bd7e2875 | blueswir1 | limit = s->limit; |
107 | bd7e2875 | blueswir1 | |
108 | 85e3023e | blueswir1 | if (s->timer)
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109 | 85e3023e | blueswir1 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer)); |
110 | 85e3023e | blueswir1 | else
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111 | 85e3023e | blueswir1 | count = 0;
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112 | 85e3023e | blueswir1 | |
113 | d2c38b24 | blueswir1 | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, |
114 | d2c38b24 | blueswir1 | s->counthigh, s->count); |
115 | d2c38b24 | blueswir1 | s->count = count & TIMER_COUNT_MASK32; |
116 | 8d05ea8a | blueswir1 | s->counthigh = count >> 32;
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117 | e80cfcfc | bellard | } |
118 | e80cfcfc | bellard | |
119 | e80cfcfc | bellard | // timer callback
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120 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
121 | e80cfcfc | bellard | { |
122 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
123 | e80cfcfc | bellard | |
124 | e80cfcfc | bellard | slavio_timer_get_out(s); |
125 | 8d05ea8a | blueswir1 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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126 | e1cb9502 | blueswir1 | s->reached = TIMER_REACHED; |
127 | e1cb9502 | blueswir1 | if (!slavio_timer_is_user(s))
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128 | f930d07e | blueswir1 | qemu_irq_raise(s->irq); |
129 | e80cfcfc | bellard | } |
130 | e80cfcfc | bellard | |
131 | e80cfcfc | bellard | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
132 | e80cfcfc | bellard | { |
133 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
134 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
135 | e80cfcfc | bellard | |
136 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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137 | e80cfcfc | bellard | switch (saddr) {
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138 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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139 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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140 | f930d07e | blueswir1 | // part of counter (user mode)
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141 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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142 | 115646b6 | blueswir1 | // read user timer MSW
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143 | 115646b6 | blueswir1 | slavio_timer_get_out(s); |
144 | e1cb9502 | blueswir1 | ret = s->counthigh | s->reached; |
145 | 115646b6 | blueswir1 | } else {
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146 | 115646b6 | blueswir1 | // read limit
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147 | f930d07e | blueswir1 | // clear irq
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148 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
149 | f930d07e | blueswir1 | s->reached = 0;
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150 | d2c38b24 | blueswir1 | ret = s->limit & TIMER_LIMIT_MASK32; |
151 | f930d07e | blueswir1 | } |
152 | 8d05ea8a | blueswir1 | break;
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153 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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154 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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155 | f930d07e | blueswir1 | // of counter (user mode)
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156 | f930d07e | blueswir1 | slavio_timer_get_out(s); |
157 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) // read user timer LSW |
158 | e1cb9502 | blueswir1 | ret = s->count & TIMER_MAX_COUNT64; |
159 | 115646b6 | blueswir1 | else // read limit |
160 | d2c38b24 | blueswir1 | ret = (s->count & TIMER_MAX_COUNT32) | s->reached; |
161 | 8d05ea8a | blueswir1 | break;
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162 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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163 | 115646b6 | blueswir1 | // only available in processor counter/timer
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164 | f930d07e | blueswir1 | // read start/stop status
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165 | 115646b6 | blueswir1 | ret = s->running; |
166 | 8d05ea8a | blueswir1 | break;
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167 | d2c38b24 | blueswir1 | case TIMER_MODE:
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168 | 115646b6 | blueswir1 | // only available in system counter
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169 | f930d07e | blueswir1 | // read user/system mode
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170 | 81732d19 | blueswir1 | ret = s->slave_mode; |
171 | 8d05ea8a | blueswir1 | break;
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172 | e80cfcfc | bellard | default:
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173 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
174 | 8d05ea8a | blueswir1 | ret = 0;
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175 | 8d05ea8a | blueswir1 | break;
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176 | e80cfcfc | bellard | } |
177 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
178 | 8d05ea8a | blueswir1 | |
179 | 8d05ea8a | blueswir1 | return ret;
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180 | e80cfcfc | bellard | } |
181 | e80cfcfc | bellard | |
182 | d2c38b24 | blueswir1 | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
183 | d2c38b24 | blueswir1 | uint32_t val) |
184 | e80cfcfc | bellard | { |
185 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
186 | e80cfcfc | bellard | uint32_t saddr; |
187 | e80cfcfc | bellard | |
188 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
189 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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190 | e80cfcfc | bellard | switch (saddr) {
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191 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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192 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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193 | e1cb9502 | blueswir1 | uint64_t count; |
194 | e1cb9502 | blueswir1 | |
195 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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196 | d2c38b24 | blueswir1 | s->limit = TIMER_MAX_COUNT64; |
197 | e1cb9502 | blueswir1 | s->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
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198 | e1cb9502 | blueswir1 | s->reached = 0;
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199 | e1cb9502 | blueswir1 | count = ((uint64_t)s->counthigh << 32) | s->count;
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200 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
201 | 0bf9e31a | Blue Swirl | s->slave_index, count); |
202 | 67e42751 | blueswir1 | if (s->timer)
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203 | e1cb9502 | blueswir1 | ptimer_set_count(s->timer, LIMIT_TO_PERIODS(s->limit - count)); |
204 | 115646b6 | blueswir1 | } else {
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205 | 115646b6 | blueswir1 | // set limit, reset counter
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206 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
207 | d2c38b24 | blueswir1 | s->limit = val & TIMER_MAX_COUNT32; |
208 | 85e3023e | blueswir1 | if (s->timer) {
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209 | 85e3023e | blueswir1 | if (s->limit == 0) /* free-run */ |
210 | 77f193da | blueswir1 | ptimer_set_limit(s->timer, |
211 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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212 | 85e3023e | blueswir1 | else
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213 | 85e3023e | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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214 | 85e3023e | blueswir1 | } |
215 | 81732d19 | blueswir1 | } |
216 | 115646b6 | blueswir1 | break;
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217 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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218 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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219 | e1cb9502 | blueswir1 | uint64_t count; |
220 | e1cb9502 | blueswir1 | |
221 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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222 | d2c38b24 | blueswir1 | s->limit = TIMER_MAX_COUNT64; |
223 | e1cb9502 | blueswir1 | s->count = val & TIMER_MAX_COUNT64; |
224 | e1cb9502 | blueswir1 | s->reached = 0;
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225 | e1cb9502 | blueswir1 | count = ((uint64_t)s->counthigh) << 32 | s->count;
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226 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
227 | 0bf9e31a | Blue Swirl | s->slave_index, count); |
228 | 67e42751 | blueswir1 | if (s->timer)
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229 | e1cb9502 | blueswir1 | ptimer_set_count(s->timer, LIMIT_TO_PERIODS(s->limit - count)); |
230 | 115646b6 | blueswir1 | } else
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231 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
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232 | 115646b6 | blueswir1 | break;
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233 | d2c38b24 | blueswir1 | case TIMER_COUNTER_NORST:
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234 | f930d07e | blueswir1 | // set limit without resetting counter
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235 | d2c38b24 | blueswir1 | s->limit = val & TIMER_MAX_COUNT32; |
236 | 85e3023e | blueswir1 | if (s->timer) {
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237 | 85e3023e | blueswir1 | if (s->limit == 0) /* free-run */ |
238 | 77f193da | blueswir1 | ptimer_set_limit(s->timer, |
239 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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240 | 85e3023e | blueswir1 | else
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241 | 85e3023e | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
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242 | 85e3023e | blueswir1 | } |
243 | f930d07e | blueswir1 | break;
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244 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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245 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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246 | 115646b6 | blueswir1 | // start/stop user counter
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247 | 115646b6 | blueswir1 | if ((val & 1) && !s->running) { |
248 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer started\n", s->slave_index);
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249 | 85e3023e | blueswir1 | if (s->timer)
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250 | 85e3023e | blueswir1 | ptimer_run(s->timer, 0);
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251 | 115646b6 | blueswir1 | s->running = 1;
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252 | 115646b6 | blueswir1 | } else if (!(val & 1) && s->running) { |
253 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer stopped\n", s->slave_index);
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254 | 85e3023e | blueswir1 | if (s->timer)
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255 | 85e3023e | blueswir1 | ptimer_stop(s->timer); |
256 | 115646b6 | blueswir1 | s->running = 0;
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257 | f930d07e | blueswir1 | } |
258 | f930d07e | blueswir1 | } |
259 | f930d07e | blueswir1 | break;
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260 | d2c38b24 | blueswir1 | case TIMER_MODE:
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261 | 115646b6 | blueswir1 | if (s->master == NULL) { |
262 | 81732d19 | blueswir1 | unsigned int i; |
263 | 81732d19 | blueswir1 | |
264 | 19f8e5dd | blueswir1 | for (i = 0; i < s->num_slaves; i++) { |
265 | 67e42751 | blueswir1 | unsigned int processor = 1 << i; |
266 | 67e42751 | blueswir1 | |
267 | 67e42751 | blueswir1 | // check for a change in timer mode for this processor
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268 | 67e42751 | blueswir1 | if ((val & processor) != (s->slave_mode & processor)) {
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269 | 67e42751 | blueswir1 | if (val & processor) { // counter -> user timer |
270 | 67e42751 | blueswir1 | qemu_irq_lower(s->slave[i]->irq); |
271 | 67e42751 | blueswir1 | // counters are always running
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272 | 67e42751 | blueswir1 | ptimer_stop(s->slave[i]->timer); |
273 | 67e42751 | blueswir1 | s->slave[i]->running = 0;
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274 | 67e42751 | blueswir1 | // user timer limit is always the same
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275 | 67e42751 | blueswir1 | s->slave[i]->limit = TIMER_MAX_COUNT64; |
276 | 67e42751 | blueswir1 | ptimer_set_limit(s->slave[i]->timer, |
277 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(s->slave[i]->limit), |
278 | 77f193da | blueswir1 | 1);
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279 | 67e42751 | blueswir1 | // set this processors user timer bit in config
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280 | 67e42751 | blueswir1 | // register
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281 | 67e42751 | blueswir1 | s->slave_mode |= processor; |
282 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from counter to user "
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283 | 67e42751 | blueswir1 | "timer\n", s->slave[i]->slave_index);
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284 | 67e42751 | blueswir1 | } else { // user timer -> counter |
285 | 67e42751 | blueswir1 | // stop the user timer if it is running
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286 | 67e42751 | blueswir1 | if (s->slave[i]->running)
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287 | 67e42751 | blueswir1 | ptimer_stop(s->slave[i]->timer); |
288 | 67e42751 | blueswir1 | // start the counter
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289 | 67e42751 | blueswir1 | ptimer_run(s->slave[i]->timer, 0);
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290 | 67e42751 | blueswir1 | s->slave[i]->running = 1;
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291 | 67e42751 | blueswir1 | // clear this processors user timer bit in config
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292 | 67e42751 | blueswir1 | // register
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293 | 67e42751 | blueswir1 | s->slave_mode &= ~processor; |
294 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from user timer to "
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295 | 67e42751 | blueswir1 | "counter\n", s->slave[i]->slave_index);
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296 | 67e42751 | blueswir1 | } |
297 | 115646b6 | blueswir1 | } |
298 | 81732d19 | blueswir1 | } |
299 | 115646b6 | blueswir1 | } else
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300 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
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301 | f930d07e | blueswir1 | break;
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302 | e80cfcfc | bellard | default:
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303 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
304 | f930d07e | blueswir1 | break;
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305 | e80cfcfc | bellard | } |
306 | e80cfcfc | bellard | } |
307 | e80cfcfc | bellard | |
308 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_timer_mem_read[3] = { |
309 | 7c560456 | blueswir1 | NULL,
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310 | 7c560456 | blueswir1 | NULL,
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311 | e80cfcfc | bellard | slavio_timer_mem_readl, |
312 | e80cfcfc | bellard | }; |
313 | e80cfcfc | bellard | |
314 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = { |
315 | 7c560456 | blueswir1 | NULL,
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316 | 7c560456 | blueswir1 | NULL,
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317 | e80cfcfc | bellard | slavio_timer_mem_writel, |
318 | e80cfcfc | bellard | }; |
319 | e80cfcfc | bellard | |
320 | e80cfcfc | bellard | static void slavio_timer_save(QEMUFile *f, void *opaque) |
321 | e80cfcfc | bellard | { |
322 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
323 | e80cfcfc | bellard | |
324 | 8d05ea8a | blueswir1 | qemu_put_be64s(f, &s->limit); |
325 | e80cfcfc | bellard | qemu_put_be32s(f, &s->count); |
326 | e80cfcfc | bellard | qemu_put_be32s(f, &s->counthigh); |
327 | e80cfcfc | bellard | qemu_put_be32s(f, &s->reached); |
328 | 115646b6 | blueswir1 | qemu_put_be32s(f, &s->running); |
329 | 85e3023e | blueswir1 | if (s->timer)
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330 | 85e3023e | blueswir1 | qemu_put_ptimer(f, s->timer); |
331 | e80cfcfc | bellard | } |
332 | e80cfcfc | bellard | |
333 | e80cfcfc | bellard | static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id) |
334 | e80cfcfc | bellard | { |
335 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
336 | 3b46e624 | ths | |
337 | 85e3023e | blueswir1 | if (version_id != 3) |
338 | e80cfcfc | bellard | return -EINVAL;
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339 | e80cfcfc | bellard | |
340 | 8d05ea8a | blueswir1 | qemu_get_be64s(f, &s->limit); |
341 | e80cfcfc | bellard | qemu_get_be32s(f, &s->count); |
342 | e80cfcfc | bellard | qemu_get_be32s(f, &s->counthigh); |
343 | e80cfcfc | bellard | qemu_get_be32s(f, &s->reached); |
344 | 115646b6 | blueswir1 | qemu_get_be32s(f, &s->running); |
345 | 85e3023e | blueswir1 | if (s->timer)
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346 | 85e3023e | blueswir1 | qemu_get_ptimer(f, s->timer); |
347 | 8d05ea8a | blueswir1 | |
348 | e80cfcfc | bellard | return 0; |
349 | e80cfcfc | bellard | } |
350 | e80cfcfc | bellard | |
351 | e80cfcfc | bellard | static void slavio_timer_reset(void *opaque) |
352 | e80cfcfc | bellard | { |
353 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
354 | e80cfcfc | bellard | |
355 | 3b4aa426 | blueswir1 | s->limit = 0;
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356 | e80cfcfc | bellard | s->count = 0;
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357 | e80cfcfc | bellard | s->reached = 0;
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358 | 3b4aa426 | blueswir1 | s->slave_mode = 0;
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359 | 85e3023e | blueswir1 | if (!s->master || s->slave_index < s->master->num_slaves) {
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360 | 85e3023e | blueswir1 | ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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361 | 85e3023e | blueswir1 | ptimer_run(s->timer, 0);
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362 | 85e3023e | blueswir1 | } |
363 | 115646b6 | blueswir1 | s->running = 1;
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364 | e80cfcfc | bellard | } |
365 | e80cfcfc | bellard | |
366 | 81732d19 | blueswir1 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
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367 | 115646b6 | blueswir1 | qemu_irq irq, |
368 | 115646b6 | blueswir1 | SLAVIO_TIMERState *master, |
369 | c70c59ee | Blue Swirl | uint32_t slave_index, |
370 | c70c59ee | Blue Swirl | uint32_t num_slaves) |
371 | e80cfcfc | bellard | { |
372 | c70c59ee | Blue Swirl | DeviceState *dev; |
373 | c70c59ee | Blue Swirl | SysBusDevice *s; |
374 | c70c59ee | Blue Swirl | SLAVIO_TIMERState *d; |
375 | c70c59ee | Blue Swirl | |
376 | c70c59ee | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
377 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "slave_index", slave_index);
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378 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "num_slaves", num_slaves);
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379 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_ptr(dev, "master", master);
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380 | c70c59ee | Blue Swirl | qdev_init(dev); |
381 | c70c59ee | Blue Swirl | s = sysbus_from_qdev(dev); |
382 | c70c59ee | Blue Swirl | sysbus_connect_irq(s, 0, irq);
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383 | c70c59ee | Blue Swirl | sysbus_mmio_map(s, 0, addr);
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384 | c70c59ee | Blue Swirl | |
385 | c70c59ee | Blue Swirl | d = FROM_SYSBUS(SLAVIO_TIMERState, s); |
386 | c70c59ee | Blue Swirl | |
387 | c70c59ee | Blue Swirl | return d;
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388 | c70c59ee | Blue Swirl | } |
389 | c70c59ee | Blue Swirl | |
390 | c70c59ee | Blue Swirl | static void slavio_timer_init1(SysBusDevice *dev) |
391 | c70c59ee | Blue Swirl | { |
392 | c70c59ee | Blue Swirl | int io;
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393 | c70c59ee | Blue Swirl | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); |
394 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
395 | e80cfcfc | bellard | |
396 | c70c59ee | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
397 | c70c59ee | Blue Swirl | |
398 | c70c59ee | Blue Swirl | if (!s->master || s->slave_index < s->master->num_slaves) {
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399 | 85e3023e | blueswir1 | bh = qemu_bh_new(slavio_timer_irq, s); |
400 | 85e3023e | blueswir1 | s->timer = ptimer_init(bh); |
401 | 85e3023e | blueswir1 | ptimer_set_period(s->timer, TIMER_PERIOD); |
402 | 85e3023e | blueswir1 | } |
403 | e80cfcfc | bellard | |
404 | c70c59ee | Blue Swirl | io = cpu_register_io_memory(slavio_timer_mem_read, slavio_timer_mem_write, |
405 | c70c59ee | Blue Swirl | s); |
406 | c70c59ee | Blue Swirl | if (s->master) {
|
407 | c70c59ee | Blue Swirl | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); |
408 | c70c59ee | Blue Swirl | } else {
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409 | c70c59ee | Blue Swirl | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); |
410 | c70c59ee | Blue Swirl | } |
411 | c70c59ee | Blue Swirl | |
412 | c70c59ee | Blue Swirl | register_savevm("slavio_timer", -1, 3, slavio_timer_save, |
413 | d2c38b24 | blueswir1 | slavio_timer_load, s); |
414 | a08d4367 | Jan Kiszka | qemu_register_reset(slavio_timer_reset, s); |
415 | e80cfcfc | bellard | slavio_timer_reset(s); |
416 | 81732d19 | blueswir1 | } |
417 | 81732d19 | blueswir1 | |
418 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
419 | 19f8e5dd | blueswir1 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
420 | 81732d19 | blueswir1 | { |
421 | 81732d19 | blueswir1 | SLAVIO_TIMERState *master; |
422 | 81732d19 | blueswir1 | unsigned int i; |
423 | 81732d19 | blueswir1 | |
424 | c70c59ee | Blue Swirl | master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0, |
425 | c70c59ee | Blue Swirl | num_cpus); |
426 | 19f8e5dd | blueswir1 | |
427 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
428 | 81732d19 | blueswir1 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) |
429 | d2c38b24 | blueswir1 | CPU_TIMER_OFFSET(i), |
430 | c70c59ee | Blue Swirl | cpu_irqs[i], master, i, 0);
|
431 | 81732d19 | blueswir1 | } |
432 | e80cfcfc | bellard | } |
433 | c70c59ee | Blue Swirl | |
434 | c70c59ee | Blue Swirl | static SysBusDeviceInfo slavio_timer_info = {
|
435 | c70c59ee | Blue Swirl | .init = slavio_timer_init1, |
436 | c70c59ee | Blue Swirl | .qdev.name = "slavio_timer",
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437 | c70c59ee | Blue Swirl | .qdev.size = sizeof(SLAVIO_TIMERState),
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438 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
439 | ee6847d1 | Gerd Hoffmann | { |
440 | ee6847d1 | Gerd Hoffmann | .name = "num_slaves",
|
441 | ee6847d1 | Gerd Hoffmann | .info = &qdev_prop_uint32, |
442 | ee6847d1 | Gerd Hoffmann | .offset = offsetof(SLAVIO_TIMERState, num_slaves), |
443 | ee6847d1 | Gerd Hoffmann | }, |
444 | ee6847d1 | Gerd Hoffmann | { |
445 | ee6847d1 | Gerd Hoffmann | .name = "slave_index",
|
446 | ee6847d1 | Gerd Hoffmann | .info = &qdev_prop_uint32, |
447 | ee6847d1 | Gerd Hoffmann | .offset = offsetof(SLAVIO_TIMERState, slave_index), |
448 | ee6847d1 | Gerd Hoffmann | }, |
449 | ee6847d1 | Gerd Hoffmann | { |
450 | ee6847d1 | Gerd Hoffmann | .name = "master",
|
451 | ee6847d1 | Gerd Hoffmann | .info = &qdev_prop_ptr, |
452 | ee6847d1 | Gerd Hoffmann | .offset = offsetof(SLAVIO_TIMERState, master), |
453 | ee6847d1 | Gerd Hoffmann | }, |
454 | ee6847d1 | Gerd Hoffmann | {/* end of property list */}
|
455 | c70c59ee | Blue Swirl | } |
456 | c70c59ee | Blue Swirl | }; |
457 | c70c59ee | Blue Swirl | |
458 | c70c59ee | Blue Swirl | static void slavio_timer_register_devices(void) |
459 | c70c59ee | Blue Swirl | { |
460 | c70c59ee | Blue Swirl | sysbus_register_withprop(&slavio_timer_info); |
461 | c70c59ee | Blue Swirl | } |
462 | c70c59ee | Blue Swirl | |
463 | c70c59ee | Blue Swirl | device_init(slavio_timer_register_devices) |