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1 | 8977f3c1 | bellard | /*
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2 | 890fa6be | bellard | * QEMU Floppy disk emulator (Intel 82078)
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3 | 5fafdf24 | ths | *
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4 | 3ccacc4a | blueswir1 | * Copyright (c) 2003, 2007 Jocelyn Mayer
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5 | 65cef780 | blueswir1 | * Copyright (c) 2008 Herv? Poussineau
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6 | 5fafdf24 | ths | *
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7 | 8977f3c1 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 8977f3c1 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 8977f3c1 | bellard | * in the Software without restriction, including without limitation the rights
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10 | 8977f3c1 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 8977f3c1 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 8977f3c1 | bellard | * furnished to do so, subject to the following conditions:
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13 | 8977f3c1 | bellard | *
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14 | 8977f3c1 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 8977f3c1 | bellard | * all copies or substantial portions of the Software.
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16 | 8977f3c1 | bellard | *
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17 | 8977f3c1 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 8977f3c1 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 8977f3c1 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 8977f3c1 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 8977f3c1 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 8977f3c1 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 8977f3c1 | bellard | * THE SOFTWARE.
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24 | 8977f3c1 | bellard | */
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25 | e80cfcfc | bellard | /*
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26 | e80cfcfc | bellard | * The controller is used in Sun4m systems in a slightly different
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27 | e80cfcfc | bellard | * way. There are changes in DOR register and DMA is not available.
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28 | e80cfcfc | bellard | */
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29 | f64ab228 | Blue Swirl | |
30 | 87ecb68b | pbrook | #include "hw.h" |
31 | 87ecb68b | pbrook | #include "fdc.h" |
32 | b47b3525 | Markus Armbruster | #include "qemu-error.h" |
33 | 87ecb68b | pbrook | #include "qemu-timer.h" |
34 | 87ecb68b | pbrook | #include "isa.h" |
35 | f64ab228 | Blue Swirl | #include "sysbus.h" |
36 | e8133762 | Blue Swirl | #include "qdev-addr.h" |
37 | 2446333c | Blue Swirl | #include "blockdev.h" |
38 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
39 | 8977f3c1 | bellard | |
40 | 8977f3c1 | bellard | /********************************************************/
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41 | 8977f3c1 | bellard | /* debug Floppy devices */
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42 | 8977f3c1 | bellard | //#define DEBUG_FLOPPY
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43 | 8977f3c1 | bellard | |
44 | 8977f3c1 | bellard | #ifdef DEBUG_FLOPPY
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45 | 001faf32 | Blue Swirl | #define FLOPPY_DPRINTF(fmt, ...) \
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46 | 001faf32 | Blue Swirl | do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) |
47 | 8977f3c1 | bellard | #else
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48 | 001faf32 | Blue Swirl | #define FLOPPY_DPRINTF(fmt, ...)
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49 | 8977f3c1 | bellard | #endif
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50 | 8977f3c1 | bellard | |
51 | 001faf32 | Blue Swirl | #define FLOPPY_ERROR(fmt, ...) \
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52 | 001faf32 | Blue Swirl | do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
53 | 8977f3c1 | bellard | |
54 | 8977f3c1 | bellard | /********************************************************/
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55 | 8977f3c1 | bellard | /* Floppy drive emulation */
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56 | 8977f3c1 | bellard | |
57 | cefec4f5 | blueswir1 | #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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58 | cefec4f5 | blueswir1 | #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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59 | cefec4f5 | blueswir1 | |
60 | 8977f3c1 | bellard | /* Will always be a fixed parameter for us */
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61 | f2d81b33 | blueswir1 | #define FD_SECTOR_LEN 512 |
62 | f2d81b33 | blueswir1 | #define FD_SECTOR_SC 2 /* Sector size code */ |
63 | f2d81b33 | blueswir1 | #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ |
64 | 8977f3c1 | bellard | |
65 | 8977f3c1 | bellard | /* Floppy disk drive emulation */
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66 | 5c02c033 | Blue Swirl | typedef enum FDiskFlags { |
67 | baca51fa | bellard | FDISK_DBL_SIDES = 0x01,
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68 | 5c02c033 | Blue Swirl | } FDiskFlags; |
69 | baca51fa | bellard | |
70 | 5c02c033 | Blue Swirl | typedef struct FDrive { |
71 | 8977f3c1 | bellard | BlockDriverState *bs; |
72 | 8977f3c1 | bellard | /* Drive status */
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73 | 5c02c033 | Blue Swirl | FDriveType drive; |
74 | 8977f3c1 | bellard | uint8_t perpendicular; /* 2.88 MB access mode */
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75 | 8977f3c1 | bellard | /* Position */
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76 | 8977f3c1 | bellard | uint8_t head; |
77 | 8977f3c1 | bellard | uint8_t track; |
78 | 8977f3c1 | bellard | uint8_t sect; |
79 | 8977f3c1 | bellard | /* Media */
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80 | 5c02c033 | Blue Swirl | FDiskFlags flags; |
81 | 8977f3c1 | bellard | uint8_t last_sect; /* Nb sector per track */
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82 | 8977f3c1 | bellard | uint8_t max_track; /* Nb of tracks */
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83 | baca51fa | bellard | uint16_t bps; /* Bytes per sector */
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84 | 8977f3c1 | bellard | uint8_t ro; /* Is read-only */
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85 | 5c02c033 | Blue Swirl | } FDrive; |
86 | 8977f3c1 | bellard | |
87 | 5c02c033 | Blue Swirl | static void fd_init(FDrive *drv) |
88 | 8977f3c1 | bellard | { |
89 | 8977f3c1 | bellard | /* Drive */
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90 | b939777c | bellard | drv->drive = FDRIVE_DRV_NONE; |
91 | 8977f3c1 | bellard | drv->perpendicular = 0;
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92 | 8977f3c1 | bellard | /* Disk */
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93 | baca51fa | bellard | drv->last_sect = 0;
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94 | 8977f3c1 | bellard | drv->max_track = 0;
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95 | 8977f3c1 | bellard | } |
96 | 8977f3c1 | bellard | |
97 | 7859cb98 | Blue Swirl | static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, |
98 | 7859cb98 | Blue Swirl | uint8_t last_sect) |
99 | 8977f3c1 | bellard | { |
100 | 8977f3c1 | bellard | return (((track * 2) + head) * last_sect) + sect - 1; |
101 | 8977f3c1 | bellard | } |
102 | 8977f3c1 | bellard | |
103 | 8977f3c1 | bellard | /* Returns current position, in sectors, for given drive */
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104 | 5c02c033 | Blue Swirl | static int fd_sector(FDrive *drv) |
105 | 8977f3c1 | bellard | { |
106 | 7859cb98 | Blue Swirl | return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
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107 | 8977f3c1 | bellard | } |
108 | 8977f3c1 | bellard | |
109 | 77370520 | blueswir1 | /* Seek to a new position:
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110 | 77370520 | blueswir1 | * returns 0 if already on right track
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111 | 77370520 | blueswir1 | * returns 1 if track changed
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112 | 77370520 | blueswir1 | * returns 2 if track is invalid
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113 | 77370520 | blueswir1 | * returns 3 if sector is invalid
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114 | 77370520 | blueswir1 | * returns 4 if seek is disabled
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115 | 77370520 | blueswir1 | */
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116 | 5c02c033 | Blue Swirl | static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, |
117 | 5c02c033 | Blue Swirl | int enable_seek)
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118 | 8977f3c1 | bellard | { |
119 | 8977f3c1 | bellard | uint32_t sector; |
120 | baca51fa | bellard | int ret;
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121 | baca51fa | bellard | |
122 | baca51fa | bellard | if (track > drv->max_track ||
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123 | 4f431960 | j_mayer | (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
124 | ed5fd2cc | bellard | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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125 | ed5fd2cc | bellard | head, track, sect, 1,
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126 | ed5fd2cc | bellard | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
127 | ed5fd2cc | bellard | drv->max_track, drv->last_sect); |
128 | 8977f3c1 | bellard | return 2; |
129 | 8977f3c1 | bellard | } |
130 | 8977f3c1 | bellard | if (sect > drv->last_sect) {
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131 | ed5fd2cc | bellard | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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132 | ed5fd2cc | bellard | head, track, sect, 1,
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133 | ed5fd2cc | bellard | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
134 | ed5fd2cc | bellard | drv->max_track, drv->last_sect); |
135 | 8977f3c1 | bellard | return 3; |
136 | 8977f3c1 | bellard | } |
137 | 7859cb98 | Blue Swirl | sector = fd_sector_calc(head, track, sect, drv->last_sect); |
138 | baca51fa | bellard | ret = 0;
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139 | 8977f3c1 | bellard | if (sector != fd_sector(drv)) {
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140 | 8977f3c1 | bellard | #if 0
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141 | 8977f3c1 | bellard | if (!enable_seek) {
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142 | 8977f3c1 | bellard | FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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143 | 8977f3c1 | bellard | head, track, sect, 1, drv->max_track, drv->last_sect);
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144 | 8977f3c1 | bellard | return 4;
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145 | 8977f3c1 | bellard | }
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146 | 8977f3c1 | bellard | #endif
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147 | 8977f3c1 | bellard | drv->head = head; |
148 | 4f431960 | j_mayer | if (drv->track != track)
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149 | 4f431960 | j_mayer | ret = 1;
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150 | 8977f3c1 | bellard | drv->track = track; |
151 | 8977f3c1 | bellard | drv->sect = sect; |
152 | 8977f3c1 | bellard | } |
153 | 8977f3c1 | bellard | |
154 | baca51fa | bellard | return ret;
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155 | 8977f3c1 | bellard | } |
156 | 8977f3c1 | bellard | |
157 | 8977f3c1 | bellard | /* Set drive back to track 0 */
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158 | 5c02c033 | Blue Swirl | static void fd_recalibrate(FDrive *drv) |
159 | 8977f3c1 | bellard | { |
160 | 8977f3c1 | bellard | FLOPPY_DPRINTF("recalibrate\n");
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161 | 8977f3c1 | bellard | drv->head = 0;
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162 | 8977f3c1 | bellard | drv->track = 0;
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163 | 8977f3c1 | bellard | drv->sect = 1;
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164 | 8977f3c1 | bellard | } |
165 | 8977f3c1 | bellard | |
166 | 8977f3c1 | bellard | /* Revalidate a disk drive after a disk change */
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167 | 5c02c033 | Blue Swirl | static void fd_revalidate(FDrive *drv) |
168 | 8977f3c1 | bellard | { |
169 | baca51fa | bellard | int nb_heads, max_track, last_sect, ro;
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170 | 5bbdbb46 | Blue Swirl | FDriveType drive; |
171 | 8977f3c1 | bellard | |
172 | 8977f3c1 | bellard | FLOPPY_DPRINTF("revalidate\n");
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173 | a541f297 | bellard | if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { |
174 | 4f431960 | j_mayer | ro = bdrv_is_read_only(drv->bs); |
175 | 5bbdbb46 | Blue Swirl | bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track, |
176 | 5bbdbb46 | Blue Swirl | &last_sect, drv->drive, &drive); |
177 | 4f431960 | j_mayer | if (nb_heads != 0 && max_track != 0 && last_sect != 0) { |
178 | 4f431960 | j_mayer | FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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179 | ed5fd2cc | bellard | nb_heads - 1, max_track, last_sect);
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180 | 4f431960 | j_mayer | } else {
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181 | 5bbdbb46 | Blue Swirl | FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
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182 | 5bbdbb46 | Blue Swirl | max_track, last_sect, ro ? "ro" : "rw"); |
183 | 4f431960 | j_mayer | } |
184 | 4f431960 | j_mayer | if (nb_heads == 1) { |
185 | 4f431960 | j_mayer | drv->flags &= ~FDISK_DBL_SIDES; |
186 | 4f431960 | j_mayer | } else {
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187 | 4f431960 | j_mayer | drv->flags |= FDISK_DBL_SIDES; |
188 | 4f431960 | j_mayer | } |
189 | 4f431960 | j_mayer | drv->max_track = max_track; |
190 | 4f431960 | j_mayer | drv->last_sect = last_sect; |
191 | 4f431960 | j_mayer | drv->ro = ro; |
192 | 5bbdbb46 | Blue Swirl | drv->drive = drive; |
193 | 8977f3c1 | bellard | } else {
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194 | 4f431960 | j_mayer | FLOPPY_DPRINTF("No disk in drive\n");
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195 | baca51fa | bellard | drv->last_sect = 0;
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196 | 4f431960 | j_mayer | drv->max_track = 0;
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197 | 4f431960 | j_mayer | drv->flags &= ~FDISK_DBL_SIDES; |
198 | 8977f3c1 | bellard | } |
199 | caed8802 | bellard | } |
200 | caed8802 | bellard | |
201 | 8977f3c1 | bellard | /********************************************************/
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202 | 4b19ec0c | bellard | /* Intel 82078 floppy disk controller emulation */
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203 | 8977f3c1 | bellard | |
204 | 63ffb564 | Blue Swirl | typedef struct FDCtrl FDCtrl; |
205 | 63ffb564 | Blue Swirl | |
206 | 5c02c033 | Blue Swirl | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); |
207 | 5c02c033 | Blue Swirl | static void fdctrl_reset_fifo(FDCtrl *fdctrl); |
208 | 85571bc7 | bellard | static int fdctrl_transfer_handler (void *opaque, int nchan, |
209 | c227f099 | Anthony Liguori | int dma_pos, int dma_len); |
210 | 5c02c033 | Blue Swirl | static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0); |
211 | 5c02c033 | Blue Swirl | |
212 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
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213 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
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214 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
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215 | 5c02c033 | Blue Swirl | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); |
216 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
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217 | 5c02c033 | Blue Swirl | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); |
218 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
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219 | 5c02c033 | Blue Swirl | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); |
220 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
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221 | 5c02c033 | Blue Swirl | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); |
222 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
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223 | 8977f3c1 | bellard | |
224 | 8977f3c1 | bellard | enum {
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225 | 8977f3c1 | bellard | FD_DIR_WRITE = 0,
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226 | 8977f3c1 | bellard | FD_DIR_READ = 1,
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227 | 8977f3c1 | bellard | FD_DIR_SCANE = 2,
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228 | 8977f3c1 | bellard | FD_DIR_SCANL = 3,
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229 | 8977f3c1 | bellard | FD_DIR_SCANH = 4,
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230 | 8977f3c1 | bellard | }; |
231 | 8977f3c1 | bellard | |
232 | 8977f3c1 | bellard | enum {
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233 | b9b3d225 | blueswir1 | FD_STATE_MULTI = 0x01, /* multi track flag */ |
234 | b9b3d225 | blueswir1 | FD_STATE_FORMAT = 0x02, /* format flag */ |
235 | b9b3d225 | blueswir1 | FD_STATE_SEEK = 0x04, /* seek flag */ |
236 | 8977f3c1 | bellard | }; |
237 | 8977f3c1 | bellard | |
238 | 9fea808a | blueswir1 | enum {
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239 | 8c6a4d77 | blueswir1 | FD_REG_SRA = 0x00,
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240 | 8c6a4d77 | blueswir1 | FD_REG_SRB = 0x01,
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241 | 9fea808a | blueswir1 | FD_REG_DOR = 0x02,
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242 | 9fea808a | blueswir1 | FD_REG_TDR = 0x03,
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243 | 9fea808a | blueswir1 | FD_REG_MSR = 0x04,
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244 | 9fea808a | blueswir1 | FD_REG_DSR = 0x04,
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245 | 9fea808a | blueswir1 | FD_REG_FIFO = 0x05,
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246 | 9fea808a | blueswir1 | FD_REG_DIR = 0x07,
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247 | 9fea808a | blueswir1 | }; |
248 | 9fea808a | blueswir1 | |
249 | 9fea808a | blueswir1 | enum {
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250 | 65cef780 | blueswir1 | FD_CMD_READ_TRACK = 0x02,
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251 | 9fea808a | blueswir1 | FD_CMD_SPECIFY = 0x03,
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252 | 9fea808a | blueswir1 | FD_CMD_SENSE_DRIVE_STATUS = 0x04,
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253 | 65cef780 | blueswir1 | FD_CMD_WRITE = 0x05,
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254 | 65cef780 | blueswir1 | FD_CMD_READ = 0x06,
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255 | 9fea808a | blueswir1 | FD_CMD_RECALIBRATE = 0x07,
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256 | 9fea808a | blueswir1 | FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
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257 | 65cef780 | blueswir1 | FD_CMD_WRITE_DELETED = 0x09,
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258 | 65cef780 | blueswir1 | FD_CMD_READ_ID = 0x0a,
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259 | 65cef780 | blueswir1 | FD_CMD_READ_DELETED = 0x0c,
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260 | 65cef780 | blueswir1 | FD_CMD_FORMAT_TRACK = 0x0d,
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261 | 9fea808a | blueswir1 | FD_CMD_DUMPREG = 0x0e,
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262 | 9fea808a | blueswir1 | FD_CMD_SEEK = 0x0f,
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263 | 9fea808a | blueswir1 | FD_CMD_VERSION = 0x10,
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264 | 65cef780 | blueswir1 | FD_CMD_SCAN_EQUAL = 0x11,
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265 | 9fea808a | blueswir1 | FD_CMD_PERPENDICULAR_MODE = 0x12,
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266 | 9fea808a | blueswir1 | FD_CMD_CONFIGURE = 0x13,
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267 | 65cef780 | blueswir1 | FD_CMD_LOCK = 0x14,
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268 | 65cef780 | blueswir1 | FD_CMD_VERIFY = 0x16,
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269 | 9fea808a | blueswir1 | FD_CMD_POWERDOWN_MODE = 0x17,
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270 | 9fea808a | blueswir1 | FD_CMD_PART_ID = 0x18,
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271 | 65cef780 | blueswir1 | FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
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272 | 65cef780 | blueswir1 | FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
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273 | bb350a5e | Jes Sorensen | FD_CMD_SAVE = 0x2e,
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274 | 9fea808a | blueswir1 | FD_CMD_OPTION = 0x33,
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275 | bb350a5e | Jes Sorensen | FD_CMD_RESTORE = 0x4e,
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276 | 9fea808a | blueswir1 | FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
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277 | 9fea808a | blueswir1 | FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
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278 | 9fea808a | blueswir1 | FD_CMD_FORMAT_AND_WRITE = 0xcd,
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279 | 9fea808a | blueswir1 | FD_CMD_RELATIVE_SEEK_IN = 0xcf,
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280 | 9fea808a | blueswir1 | }; |
281 | 9fea808a | blueswir1 | |
282 | 9fea808a | blueswir1 | enum {
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283 | 9fea808a | blueswir1 | FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ |
284 | 9fea808a | blueswir1 | FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ |
285 | 9fea808a | blueswir1 | FD_CONFIG_POLL = 0x10, /* Poll enabled */ |
286 | 9fea808a | blueswir1 | FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ |
287 | 9fea808a | blueswir1 | FD_CONFIG_EIS = 0x40, /* No implied seeks */ |
288 | 9fea808a | blueswir1 | }; |
289 | 9fea808a | blueswir1 | |
290 | 9fea808a | blueswir1 | enum {
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291 | 9fea808a | blueswir1 | FD_SR0_EQPMT = 0x10,
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292 | 9fea808a | blueswir1 | FD_SR0_SEEK = 0x20,
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293 | 9fea808a | blueswir1 | FD_SR0_ABNTERM = 0x40,
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294 | 9fea808a | blueswir1 | FD_SR0_INVCMD = 0x80,
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295 | 9fea808a | blueswir1 | FD_SR0_RDYCHG = 0xc0,
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296 | 9fea808a | blueswir1 | }; |
297 | 9fea808a | blueswir1 | |
298 | 9fea808a | blueswir1 | enum {
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299 | 77370520 | blueswir1 | FD_SR1_EC = 0x80, /* End of cylinder */ |
300 | 77370520 | blueswir1 | }; |
301 | 77370520 | blueswir1 | |
302 | 77370520 | blueswir1 | enum {
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303 | 77370520 | blueswir1 | FD_SR2_SNS = 0x04, /* Scan not satisfied */ |
304 | 77370520 | blueswir1 | FD_SR2_SEH = 0x08, /* Scan equal hit */ |
305 | 77370520 | blueswir1 | }; |
306 | 77370520 | blueswir1 | |
307 | 77370520 | blueswir1 | enum {
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308 | 8c6a4d77 | blueswir1 | FD_SRA_DIR = 0x01,
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309 | 8c6a4d77 | blueswir1 | FD_SRA_nWP = 0x02,
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310 | 8c6a4d77 | blueswir1 | FD_SRA_nINDX = 0x04,
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311 | 8c6a4d77 | blueswir1 | FD_SRA_HDSEL = 0x08,
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312 | 8c6a4d77 | blueswir1 | FD_SRA_nTRK0 = 0x10,
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313 | 8c6a4d77 | blueswir1 | FD_SRA_STEP = 0x20,
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314 | 8c6a4d77 | blueswir1 | FD_SRA_nDRV2 = 0x40,
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315 | 8c6a4d77 | blueswir1 | FD_SRA_INTPEND = 0x80,
|
316 | 8c6a4d77 | blueswir1 | }; |
317 | 8c6a4d77 | blueswir1 | |
318 | 8c6a4d77 | blueswir1 | enum {
|
319 | 8c6a4d77 | blueswir1 | FD_SRB_MTR0 = 0x01,
|
320 | 8c6a4d77 | blueswir1 | FD_SRB_MTR1 = 0x02,
|
321 | 8c6a4d77 | blueswir1 | FD_SRB_WGATE = 0x04,
|
322 | 8c6a4d77 | blueswir1 | FD_SRB_RDATA = 0x08,
|
323 | 8c6a4d77 | blueswir1 | FD_SRB_WDATA = 0x10,
|
324 | 8c6a4d77 | blueswir1 | FD_SRB_DR0 = 0x20,
|
325 | 8c6a4d77 | blueswir1 | }; |
326 | 8c6a4d77 | blueswir1 | |
327 | 8c6a4d77 | blueswir1 | enum {
|
328 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
329 | 78ae820c | blueswir1 | FD_DOR_SELMASK = 0x03,
|
330 | 78ae820c | blueswir1 | #else
|
331 | 9fea808a | blueswir1 | FD_DOR_SELMASK = 0x01,
|
332 | 78ae820c | blueswir1 | #endif
|
333 | 9fea808a | blueswir1 | FD_DOR_nRESET = 0x04,
|
334 | 9fea808a | blueswir1 | FD_DOR_DMAEN = 0x08,
|
335 | 9fea808a | blueswir1 | FD_DOR_MOTEN0 = 0x10,
|
336 | 9fea808a | blueswir1 | FD_DOR_MOTEN1 = 0x20,
|
337 | 9fea808a | blueswir1 | FD_DOR_MOTEN2 = 0x40,
|
338 | 9fea808a | blueswir1 | FD_DOR_MOTEN3 = 0x80,
|
339 | 9fea808a | blueswir1 | }; |
340 | 9fea808a | blueswir1 | |
341 | 9fea808a | blueswir1 | enum {
|
342 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
343 | 9fea808a | blueswir1 | FD_TDR_BOOTSEL = 0x0c,
|
344 | 78ae820c | blueswir1 | #else
|
345 | 78ae820c | blueswir1 | FD_TDR_BOOTSEL = 0x04,
|
346 | 78ae820c | blueswir1 | #endif
|
347 | 9fea808a | blueswir1 | }; |
348 | 9fea808a | blueswir1 | |
349 | 9fea808a | blueswir1 | enum {
|
350 | 9fea808a | blueswir1 | FD_DSR_DRATEMASK= 0x03,
|
351 | 9fea808a | blueswir1 | FD_DSR_PWRDOWN = 0x40,
|
352 | 9fea808a | blueswir1 | FD_DSR_SWRESET = 0x80,
|
353 | 9fea808a | blueswir1 | }; |
354 | 9fea808a | blueswir1 | |
355 | 9fea808a | blueswir1 | enum {
|
356 | 9fea808a | blueswir1 | FD_MSR_DRV0BUSY = 0x01,
|
357 | 9fea808a | blueswir1 | FD_MSR_DRV1BUSY = 0x02,
|
358 | 9fea808a | blueswir1 | FD_MSR_DRV2BUSY = 0x04,
|
359 | 9fea808a | blueswir1 | FD_MSR_DRV3BUSY = 0x08,
|
360 | 9fea808a | blueswir1 | FD_MSR_CMDBUSY = 0x10,
|
361 | 9fea808a | blueswir1 | FD_MSR_NONDMA = 0x20,
|
362 | 9fea808a | blueswir1 | FD_MSR_DIO = 0x40,
|
363 | 9fea808a | blueswir1 | FD_MSR_RQM = 0x80,
|
364 | 9fea808a | blueswir1 | }; |
365 | 9fea808a | blueswir1 | |
366 | 9fea808a | blueswir1 | enum {
|
367 | 9fea808a | blueswir1 | FD_DIR_DSKCHG = 0x80,
|
368 | 9fea808a | blueswir1 | }; |
369 | 9fea808a | blueswir1 | |
370 | 8977f3c1 | bellard | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
|
371 | 8977f3c1 | bellard | #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
|
372 | baca51fa | bellard | #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
|
373 | 8977f3c1 | bellard | |
374 | 5c02c033 | Blue Swirl | struct FDCtrl {
|
375 | 4b19ec0c | bellard | /* Controller's identification */
|
376 | 8977f3c1 | bellard | uint8_t version; |
377 | 8977f3c1 | bellard | /* HW */
|
378 | d537cf6c | pbrook | qemu_irq irq; |
379 | 8977f3c1 | bellard | int dma_chann;
|
380 | 4b19ec0c | bellard | /* Controller state */
|
381 | ed5fd2cc | bellard | QEMUTimer *result_timer; |
382 | 8c6a4d77 | blueswir1 | uint8_t sra; |
383 | 8c6a4d77 | blueswir1 | uint8_t srb; |
384 | 368df94d | blueswir1 | uint8_t dor; |
385 | d7a6c270 | Juan Quintela | uint8_t dor_vmstate; /* only used as temp during vmstate */
|
386 | 46d3233b | blueswir1 | uint8_t tdr; |
387 | b9b3d225 | blueswir1 | uint8_t dsr; |
388 | 368df94d | blueswir1 | uint8_t msr; |
389 | 8977f3c1 | bellard | uint8_t cur_drv; |
390 | 77370520 | blueswir1 | uint8_t status0; |
391 | 77370520 | blueswir1 | uint8_t status1; |
392 | 77370520 | blueswir1 | uint8_t status2; |
393 | 8977f3c1 | bellard | /* Command FIFO */
|
394 | 33f00271 | balrog | uint8_t *fifo; |
395 | d7a6c270 | Juan Quintela | int32_t fifo_size; |
396 | 8977f3c1 | bellard | uint32_t data_pos; |
397 | 8977f3c1 | bellard | uint32_t data_len; |
398 | 8977f3c1 | bellard | uint8_t data_state; |
399 | 8977f3c1 | bellard | uint8_t data_dir; |
400 | 890fa6be | bellard | uint8_t eot; /* last wanted sector */
|
401 | 8977f3c1 | bellard | /* States kept only to be returned back */
|
402 | 8977f3c1 | bellard | /* Timers state */
|
403 | 8977f3c1 | bellard | uint8_t timer0; |
404 | 8977f3c1 | bellard | uint8_t timer1; |
405 | 8977f3c1 | bellard | /* precompensation */
|
406 | 8977f3c1 | bellard | uint8_t precomp_trk; |
407 | 8977f3c1 | bellard | uint8_t config; |
408 | 8977f3c1 | bellard | uint8_t lock; |
409 | 8977f3c1 | bellard | /* Power down config (also with status regB access mode */
|
410 | 8977f3c1 | bellard | uint8_t pwrd; |
411 | 741402f9 | blueswir1 | /* Sun4m quirks? */
|
412 | a06e5a3c | blueswir1 | int sun4m;
|
413 | 8977f3c1 | bellard | /* Floppy drives */
|
414 | d7a6c270 | Juan Quintela | uint8_t num_floppies; |
415 | 5c02c033 | Blue Swirl | FDrive drives[MAX_FD]; |
416 | f2d81b33 | blueswir1 | int reset_sensei;
|
417 | baca51fa | bellard | }; |
418 | baca51fa | bellard | |
419 | 5c02c033 | Blue Swirl | typedef struct FDCtrlSysBus { |
420 | 8baf73ad | Gerd Hoffmann | SysBusDevice busdev; |
421 | 5c02c033 | Blue Swirl | struct FDCtrl state;
|
422 | 5c02c033 | Blue Swirl | } FDCtrlSysBus; |
423 | 8baf73ad | Gerd Hoffmann | |
424 | 5c02c033 | Blue Swirl | typedef struct FDCtrlISABus { |
425 | 8baf73ad | Gerd Hoffmann | ISADevice busdev; |
426 | 5c02c033 | Blue Swirl | struct FDCtrl state;
|
427 | 1ca4d09a | Gleb Natapov | int32_t bootindexA; |
428 | 1ca4d09a | Gleb Natapov | int32_t bootindexB; |
429 | 5c02c033 | Blue Swirl | } FDCtrlISABus; |
430 | 8baf73ad | Gerd Hoffmann | |
431 | baca51fa | bellard | static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
432 | baca51fa | bellard | { |
433 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = opaque; |
434 | baca51fa | bellard | uint32_t retval; |
435 | baca51fa | bellard | |
436 | e64d7d59 | blueswir1 | switch (reg) {
|
437 | 8c6a4d77 | blueswir1 | case FD_REG_SRA:
|
438 | 8c6a4d77 | blueswir1 | retval = fdctrl_read_statusA(fdctrl); |
439 | 4f431960 | j_mayer | break;
|
440 | 8c6a4d77 | blueswir1 | case FD_REG_SRB:
|
441 | 4f431960 | j_mayer | retval = fdctrl_read_statusB(fdctrl); |
442 | 4f431960 | j_mayer | break;
|
443 | 9fea808a | blueswir1 | case FD_REG_DOR:
|
444 | 4f431960 | j_mayer | retval = fdctrl_read_dor(fdctrl); |
445 | 4f431960 | j_mayer | break;
|
446 | 9fea808a | blueswir1 | case FD_REG_TDR:
|
447 | baca51fa | bellard | retval = fdctrl_read_tape(fdctrl); |
448 | 4f431960 | j_mayer | break;
|
449 | 9fea808a | blueswir1 | case FD_REG_MSR:
|
450 | baca51fa | bellard | retval = fdctrl_read_main_status(fdctrl); |
451 | 4f431960 | j_mayer | break;
|
452 | 9fea808a | blueswir1 | case FD_REG_FIFO:
|
453 | baca51fa | bellard | retval = fdctrl_read_data(fdctrl); |
454 | 4f431960 | j_mayer | break;
|
455 | 9fea808a | blueswir1 | case FD_REG_DIR:
|
456 | baca51fa | bellard | retval = fdctrl_read_dir(fdctrl); |
457 | 4f431960 | j_mayer | break;
|
458 | a541f297 | bellard | default:
|
459 | 4f431960 | j_mayer | retval = (uint32_t)(-1);
|
460 | 4f431960 | j_mayer | break;
|
461 | a541f297 | bellard | } |
462 | ed5fd2cc | bellard | FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
463 | baca51fa | bellard | |
464 | baca51fa | bellard | return retval;
|
465 | baca51fa | bellard | } |
466 | baca51fa | bellard | |
467 | baca51fa | bellard | static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) |
468 | baca51fa | bellard | { |
469 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = opaque; |
470 | baca51fa | bellard | |
471 | ed5fd2cc | bellard | FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
472 | ed5fd2cc | bellard | |
473 | e64d7d59 | blueswir1 | switch (reg) {
|
474 | 9fea808a | blueswir1 | case FD_REG_DOR:
|
475 | 4f431960 | j_mayer | fdctrl_write_dor(fdctrl, value); |
476 | 4f431960 | j_mayer | break;
|
477 | 9fea808a | blueswir1 | case FD_REG_TDR:
|
478 | baca51fa | bellard | fdctrl_write_tape(fdctrl, value); |
479 | 4f431960 | j_mayer | break;
|
480 | 9fea808a | blueswir1 | case FD_REG_DSR:
|
481 | baca51fa | bellard | fdctrl_write_rate(fdctrl, value); |
482 | 4f431960 | j_mayer | break;
|
483 | 9fea808a | blueswir1 | case FD_REG_FIFO:
|
484 | baca51fa | bellard | fdctrl_write_data(fdctrl, value); |
485 | 4f431960 | j_mayer | break;
|
486 | a541f297 | bellard | default:
|
487 | 4f431960 | j_mayer | break;
|
488 | a541f297 | bellard | } |
489 | baca51fa | bellard | } |
490 | baca51fa | bellard | |
491 | e64d7d59 | blueswir1 | static uint32_t fdctrl_read_port (void *opaque, uint32_t reg) |
492 | e64d7d59 | blueswir1 | { |
493 | e64d7d59 | blueswir1 | return fdctrl_read(opaque, reg & 7); |
494 | e64d7d59 | blueswir1 | } |
495 | e64d7d59 | blueswir1 | |
496 | e64d7d59 | blueswir1 | static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) |
497 | e64d7d59 | blueswir1 | { |
498 | e64d7d59 | blueswir1 | fdctrl_write(opaque, reg & 7, value);
|
499 | e64d7d59 | blueswir1 | } |
500 | e64d7d59 | blueswir1 | |
501 | c227f099 | Anthony Liguori | static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
502 | 62a46c61 | bellard | { |
503 | 5dcb6b91 | blueswir1 | return fdctrl_read(opaque, (uint32_t)reg);
|
504 | 62a46c61 | bellard | } |
505 | 62a46c61 | bellard | |
506 | 5fafdf24 | ths | static void fdctrl_write_mem (void *opaque, |
507 | c227f099 | Anthony Liguori | target_phys_addr_t reg, uint32_t value) |
508 | 62a46c61 | bellard | { |
509 | 5dcb6b91 | blueswir1 | fdctrl_write(opaque, (uint32_t)reg, value); |
510 | 62a46c61 | bellard | } |
511 | 62a46c61 | bellard | |
512 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const fdctrl_mem_read[3] = { |
513 | 62a46c61 | bellard | fdctrl_read_mem, |
514 | 62a46c61 | bellard | fdctrl_read_mem, |
515 | 62a46c61 | bellard | fdctrl_read_mem, |
516 | e80cfcfc | bellard | }; |
517 | e80cfcfc | bellard | |
518 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = { |
519 | 62a46c61 | bellard | fdctrl_write_mem, |
520 | 62a46c61 | bellard | fdctrl_write_mem, |
521 | 62a46c61 | bellard | fdctrl_write_mem, |
522 | e80cfcfc | bellard | }; |
523 | e80cfcfc | bellard | |
524 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = { |
525 | 7c560456 | blueswir1 | fdctrl_read_mem, |
526 | 7c560456 | blueswir1 | NULL,
|
527 | 7c560456 | blueswir1 | NULL,
|
528 | 7c560456 | blueswir1 | }; |
529 | 7c560456 | blueswir1 | |
530 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = { |
531 | 7c560456 | blueswir1 | fdctrl_write_mem, |
532 | 7c560456 | blueswir1 | NULL,
|
533 | 7c560456 | blueswir1 | NULL,
|
534 | 7c560456 | blueswir1 | }; |
535 | 7c560456 | blueswir1 | |
536 | d7a6c270 | Juan Quintela | static const VMStateDescription vmstate_fdrive = { |
537 | d7a6c270 | Juan Quintela | .name = "fdrive",
|
538 | d7a6c270 | Juan Quintela | .version_id = 1,
|
539 | d7a6c270 | Juan Quintela | .minimum_version_id = 1,
|
540 | d7a6c270 | Juan Quintela | .minimum_version_id_old = 1,
|
541 | d7a6c270 | Juan Quintela | .fields = (VMStateField []) { |
542 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(head, FDrive), |
543 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(track, FDrive), |
544 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(sect, FDrive), |
545 | d7a6c270 | Juan Quintela | VMSTATE_END_OF_LIST() |
546 | d7a6c270 | Juan Quintela | } |
547 | d7a6c270 | Juan Quintela | }; |
548 | 3ccacc4a | blueswir1 | |
549 | d4bfa4d7 | Juan Quintela | static void fdc_pre_save(void *opaque) |
550 | 3ccacc4a | blueswir1 | { |
551 | 5c02c033 | Blue Swirl | FDCtrl *s = opaque; |
552 | 3ccacc4a | blueswir1 | |
553 | d7a6c270 | Juan Quintela | s->dor_vmstate = s->dor | GET_CUR_DRV(s); |
554 | 3ccacc4a | blueswir1 | } |
555 | 3ccacc4a | blueswir1 | |
556 | e59fb374 | Juan Quintela | static int fdc_post_load(void *opaque, int version_id) |
557 | 3ccacc4a | blueswir1 | { |
558 | 5c02c033 | Blue Swirl | FDCtrl *s = opaque; |
559 | 3ccacc4a | blueswir1 | |
560 | d7a6c270 | Juan Quintela | SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); |
561 | d7a6c270 | Juan Quintela | s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; |
562 | 3ccacc4a | blueswir1 | return 0; |
563 | 3ccacc4a | blueswir1 | } |
564 | 3ccacc4a | blueswir1 | |
565 | d7a6c270 | Juan Quintela | static const VMStateDescription vmstate_fdc = { |
566 | aef30c3c | Juan Quintela | .name = "fdc",
|
567 | d7a6c270 | Juan Quintela | .version_id = 2,
|
568 | d7a6c270 | Juan Quintela | .minimum_version_id = 2,
|
569 | d7a6c270 | Juan Quintela | .minimum_version_id_old = 2,
|
570 | d7a6c270 | Juan Quintela | .pre_save = fdc_pre_save, |
571 | d7a6c270 | Juan Quintela | .post_load = fdc_post_load, |
572 | d7a6c270 | Juan Quintela | .fields = (VMStateField []) { |
573 | d7a6c270 | Juan Quintela | /* Controller State */
|
574 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(sra, FDCtrl), |
575 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(srb, FDCtrl), |
576 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(dor_vmstate, FDCtrl), |
577 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(tdr, FDCtrl), |
578 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(dsr, FDCtrl), |
579 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(msr, FDCtrl), |
580 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(status0, FDCtrl), |
581 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(status1, FDCtrl), |
582 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(status2, FDCtrl), |
583 | d7a6c270 | Juan Quintela | /* Command FIFO */
|
584 | 8ec68b06 | Blue Swirl | VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
|
585 | 8ec68b06 | Blue Swirl | uint8_t), |
586 | 5c02c033 | Blue Swirl | VMSTATE_UINT32(data_pos, FDCtrl), |
587 | 5c02c033 | Blue Swirl | VMSTATE_UINT32(data_len, FDCtrl), |
588 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(data_state, FDCtrl), |
589 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(data_dir, FDCtrl), |
590 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(eot, FDCtrl), |
591 | d7a6c270 | Juan Quintela | /* States kept only to be returned back */
|
592 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(timer0, FDCtrl), |
593 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(timer1, FDCtrl), |
594 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(precomp_trk, FDCtrl), |
595 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(config, FDCtrl), |
596 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(lock, FDCtrl), |
597 | 5c02c033 | Blue Swirl | VMSTATE_UINT8(pwrd, FDCtrl), |
598 | 5c02c033 | Blue Swirl | VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), |
599 | 5c02c033 | Blue Swirl | VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
|
600 | 5c02c033 | Blue Swirl | vmstate_fdrive, FDrive), |
601 | d7a6c270 | Juan Quintela | VMSTATE_END_OF_LIST() |
602 | 78ae820c | blueswir1 | } |
603 | d7a6c270 | Juan Quintela | }; |
604 | 3ccacc4a | blueswir1 | |
605 | 2be37833 | Blue Swirl | static void fdctrl_external_reset_sysbus(DeviceState *d) |
606 | 3ccacc4a | blueswir1 | { |
607 | 5c02c033 | Blue Swirl | FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev); |
608 | 5c02c033 | Blue Swirl | FDCtrl *s = &sys->state; |
609 | 2be37833 | Blue Swirl | |
610 | 2be37833 | Blue Swirl | fdctrl_reset(s, 0);
|
611 | 2be37833 | Blue Swirl | } |
612 | 2be37833 | Blue Swirl | |
613 | 2be37833 | Blue Swirl | static void fdctrl_external_reset_isa(DeviceState *d) |
614 | 2be37833 | Blue Swirl | { |
615 | 5c02c033 | Blue Swirl | FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev); |
616 | 5c02c033 | Blue Swirl | FDCtrl *s = &isa->state; |
617 | 3ccacc4a | blueswir1 | |
618 | 3ccacc4a | blueswir1 | fdctrl_reset(s, 0);
|
619 | 3ccacc4a | blueswir1 | } |
620 | 3ccacc4a | blueswir1 | |
621 | 2be17ebd | blueswir1 | static void fdctrl_handle_tc(void *opaque, int irq, int level) |
622 | 2be17ebd | blueswir1 | { |
623 | 5c02c033 | Blue Swirl | //FDCtrl *s = opaque;
|
624 | 2be17ebd | blueswir1 | |
625 | 2be17ebd | blueswir1 | if (level) {
|
626 | 2be17ebd | blueswir1 | // XXX
|
627 | 2be17ebd | blueswir1 | FLOPPY_DPRINTF("TC pulsed\n");
|
628 | 2be17ebd | blueswir1 | } |
629 | 2be17ebd | blueswir1 | } |
630 | 2be17ebd | blueswir1 | |
631 | 8977f3c1 | bellard | /* Change IRQ state */
|
632 | 5c02c033 | Blue Swirl | static void fdctrl_reset_irq(FDCtrl *fdctrl) |
633 | 8977f3c1 | bellard | { |
634 | 8c6a4d77 | blueswir1 | if (!(fdctrl->sra & FD_SRA_INTPEND))
|
635 | 8c6a4d77 | blueswir1 | return;
|
636 | ed5fd2cc | bellard | FLOPPY_DPRINTF("Reset interrupt\n");
|
637 | d537cf6c | pbrook | qemu_set_irq(fdctrl->irq, 0);
|
638 | 8c6a4d77 | blueswir1 | fdctrl->sra &= ~FD_SRA_INTPEND; |
639 | 8977f3c1 | bellard | } |
640 | 8977f3c1 | bellard | |
641 | 5c02c033 | Blue Swirl | static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0) |
642 | 8977f3c1 | bellard | { |
643 | b9b3d225 | blueswir1 | /* Sparc mutation */
|
644 | b9b3d225 | blueswir1 | if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
|
645 | b9b3d225 | blueswir1 | /* XXX: not sure */
|
646 | b9b3d225 | blueswir1 | fdctrl->msr &= ~FD_MSR_CMDBUSY; |
647 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
648 | 77370520 | blueswir1 | fdctrl->status0 = status0; |
649 | 4f431960 | j_mayer | return;
|
650 | 6f7e9aec | bellard | } |
651 | 8c6a4d77 | blueswir1 | if (!(fdctrl->sra & FD_SRA_INTPEND)) {
|
652 | d537cf6c | pbrook | qemu_set_irq(fdctrl->irq, 1);
|
653 | 8c6a4d77 | blueswir1 | fdctrl->sra |= FD_SRA_INTPEND; |
654 | 8977f3c1 | bellard | } |
655 | f2d81b33 | blueswir1 | fdctrl->reset_sensei = 0;
|
656 | 77370520 | blueswir1 | fdctrl->status0 = status0; |
657 | 77370520 | blueswir1 | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
|
658 | 8977f3c1 | bellard | } |
659 | 8977f3c1 | bellard | |
660 | 4b19ec0c | bellard | /* Reset controller */
|
661 | 5c02c033 | Blue Swirl | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) |
662 | 8977f3c1 | bellard | { |
663 | 8977f3c1 | bellard | int i;
|
664 | 8977f3c1 | bellard | |
665 | 4b19ec0c | bellard | FLOPPY_DPRINTF("reset controller\n");
|
666 | baca51fa | bellard | fdctrl_reset_irq(fdctrl); |
667 | 4b19ec0c | bellard | /* Initialise controller */
|
668 | 8c6a4d77 | blueswir1 | fdctrl->sra = 0;
|
669 | 8c6a4d77 | blueswir1 | fdctrl->srb = 0xc0;
|
670 | 8c6a4d77 | blueswir1 | if (!fdctrl->drives[1].bs) |
671 | 8c6a4d77 | blueswir1 | fdctrl->sra |= FD_SRA_nDRV2; |
672 | baca51fa | bellard | fdctrl->cur_drv = 0;
|
673 | 1c346df2 | blueswir1 | fdctrl->dor = FD_DOR_nRESET; |
674 | 368df94d | blueswir1 | fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
675 | b9b3d225 | blueswir1 | fdctrl->msr = FD_MSR_RQM; |
676 | 8977f3c1 | bellard | /* FIFO state */
|
677 | baca51fa | bellard | fdctrl->data_pos = 0;
|
678 | baca51fa | bellard | fdctrl->data_len = 0;
|
679 | b9b3d225 | blueswir1 | fdctrl->data_state = 0;
|
680 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_WRITE; |
681 | 8977f3c1 | bellard | for (i = 0; i < MAX_FD; i++) |
682 | 1c346df2 | blueswir1 | fd_recalibrate(&fdctrl->drives[i]); |
683 | baca51fa | bellard | fdctrl_reset_fifo(fdctrl); |
684 | 77370520 | blueswir1 | if (do_irq) {
|
685 | 9fea808a | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG); |
686 | f2d81b33 | blueswir1 | fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
687 | 77370520 | blueswir1 | } |
688 | baca51fa | bellard | } |
689 | baca51fa | bellard | |
690 | 5c02c033 | Blue Swirl | static inline FDrive *drv0(FDCtrl *fdctrl) |
691 | baca51fa | bellard | { |
692 | 46d3233b | blueswir1 | return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
693 | baca51fa | bellard | } |
694 | baca51fa | bellard | |
695 | 5c02c033 | Blue Swirl | static inline FDrive *drv1(FDCtrl *fdctrl) |
696 | baca51fa | bellard | { |
697 | 46d3233b | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
698 | 46d3233b | blueswir1 | return &fdctrl->drives[1]; |
699 | 46d3233b | blueswir1 | else
|
700 | 46d3233b | blueswir1 | return &fdctrl->drives[0]; |
701 | baca51fa | bellard | } |
702 | baca51fa | bellard | |
703 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
704 | 5c02c033 | Blue Swirl | static inline FDrive *drv2(FDCtrl *fdctrl) |
705 | 78ae820c | blueswir1 | { |
706 | 78ae820c | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) |
707 | 78ae820c | blueswir1 | return &fdctrl->drives[2]; |
708 | 78ae820c | blueswir1 | else
|
709 | 78ae820c | blueswir1 | return &fdctrl->drives[1]; |
710 | 78ae820c | blueswir1 | } |
711 | 78ae820c | blueswir1 | |
712 | 5c02c033 | Blue Swirl | static inline FDrive *drv3(FDCtrl *fdctrl) |
713 | 78ae820c | blueswir1 | { |
714 | 78ae820c | blueswir1 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) |
715 | 78ae820c | blueswir1 | return &fdctrl->drives[3]; |
716 | 78ae820c | blueswir1 | else
|
717 | 78ae820c | blueswir1 | return &fdctrl->drives[2]; |
718 | 78ae820c | blueswir1 | } |
719 | 78ae820c | blueswir1 | #endif
|
720 | 78ae820c | blueswir1 | |
721 | 5c02c033 | Blue Swirl | static FDrive *get_cur_drv(FDCtrl *fdctrl)
|
722 | baca51fa | bellard | { |
723 | 78ae820c | blueswir1 | switch (fdctrl->cur_drv) {
|
724 | 78ae820c | blueswir1 | case 0: return drv0(fdctrl); |
725 | 78ae820c | blueswir1 | case 1: return drv1(fdctrl); |
726 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
727 | 78ae820c | blueswir1 | case 2: return drv2(fdctrl); |
728 | 78ae820c | blueswir1 | case 3: return drv3(fdctrl); |
729 | 78ae820c | blueswir1 | #endif
|
730 | 78ae820c | blueswir1 | default: return NULL; |
731 | 78ae820c | blueswir1 | } |
732 | 8977f3c1 | bellard | } |
733 | 8977f3c1 | bellard | |
734 | 8c6a4d77 | blueswir1 | /* Status A register : 0x00 (read-only) */
|
735 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
|
736 | 8c6a4d77 | blueswir1 | { |
737 | 8c6a4d77 | blueswir1 | uint32_t retval = fdctrl->sra; |
738 | 8c6a4d77 | blueswir1 | |
739 | 8c6a4d77 | blueswir1 | FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
|
740 | 8c6a4d77 | blueswir1 | |
741 | 8c6a4d77 | blueswir1 | return retval;
|
742 | 8c6a4d77 | blueswir1 | } |
743 | 8c6a4d77 | blueswir1 | |
744 | 8977f3c1 | bellard | /* Status B register : 0x01 (read-only) */
|
745 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
|
746 | 8977f3c1 | bellard | { |
747 | 8c6a4d77 | blueswir1 | uint32_t retval = fdctrl->srb; |
748 | 8c6a4d77 | blueswir1 | |
749 | 8c6a4d77 | blueswir1 | FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
|
750 | 8c6a4d77 | blueswir1 | |
751 | 8c6a4d77 | blueswir1 | return retval;
|
752 | 8977f3c1 | bellard | } |
753 | 8977f3c1 | bellard | |
754 | 8977f3c1 | bellard | /* Digital output register : 0x02 */
|
755 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
|
756 | 8977f3c1 | bellard | { |
757 | 1c346df2 | blueswir1 | uint32_t retval = fdctrl->dor; |
758 | 8977f3c1 | bellard | |
759 | 8977f3c1 | bellard | /* Selected drive */
|
760 | baca51fa | bellard | retval |= fdctrl->cur_drv; |
761 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
|
762 | 8977f3c1 | bellard | |
763 | 8977f3c1 | bellard | return retval;
|
764 | 8977f3c1 | bellard | } |
765 | 8977f3c1 | bellard | |
766 | 5c02c033 | Blue Swirl | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) |
767 | 8977f3c1 | bellard | { |
768 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
|
769 | 8c6a4d77 | blueswir1 | |
770 | 8c6a4d77 | blueswir1 | /* Motors */
|
771 | 8c6a4d77 | blueswir1 | if (value & FD_DOR_MOTEN0)
|
772 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_MTR0; |
773 | 8c6a4d77 | blueswir1 | else
|
774 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_MTR0; |
775 | 8c6a4d77 | blueswir1 | if (value & FD_DOR_MOTEN1)
|
776 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_MTR1; |
777 | 8c6a4d77 | blueswir1 | else
|
778 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_MTR1; |
779 | 8c6a4d77 | blueswir1 | |
780 | 8c6a4d77 | blueswir1 | /* Drive */
|
781 | 8c6a4d77 | blueswir1 | if (value & 1) |
782 | 8c6a4d77 | blueswir1 | fdctrl->srb |= FD_SRB_DR0; |
783 | 8c6a4d77 | blueswir1 | else
|
784 | 8c6a4d77 | blueswir1 | fdctrl->srb &= ~FD_SRB_DR0; |
785 | 8c6a4d77 | blueswir1 | |
786 | 8977f3c1 | bellard | /* Reset */
|
787 | 9fea808a | blueswir1 | if (!(value & FD_DOR_nRESET)) {
|
788 | 1c346df2 | blueswir1 | if (fdctrl->dor & FD_DOR_nRESET) {
|
789 | 4b19ec0c | bellard | FLOPPY_DPRINTF("controller enter RESET state\n");
|
790 | 8977f3c1 | bellard | } |
791 | 8977f3c1 | bellard | } else {
|
792 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
793 | 4b19ec0c | bellard | FLOPPY_DPRINTF("controller out of RESET state\n");
|
794 | fb6cf1d0 | bellard | fdctrl_reset(fdctrl, 1);
|
795 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
796 | 8977f3c1 | bellard | } |
797 | 8977f3c1 | bellard | } |
798 | 8977f3c1 | bellard | /* Selected drive */
|
799 | 9fea808a | blueswir1 | fdctrl->cur_drv = value & FD_DOR_SELMASK; |
800 | 368df94d | blueswir1 | |
801 | 368df94d | blueswir1 | fdctrl->dor = value; |
802 | 8977f3c1 | bellard | } |
803 | 8977f3c1 | bellard | |
804 | 8977f3c1 | bellard | /* Tape drive register : 0x03 */
|
805 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
|
806 | 8977f3c1 | bellard | { |
807 | 46d3233b | blueswir1 | uint32_t retval = fdctrl->tdr; |
808 | 8977f3c1 | bellard | |
809 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
|
810 | 8977f3c1 | bellard | |
811 | 8977f3c1 | bellard | return retval;
|
812 | 8977f3c1 | bellard | } |
813 | 8977f3c1 | bellard | |
814 | 5c02c033 | Blue Swirl | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) |
815 | 8977f3c1 | bellard | { |
816 | 8977f3c1 | bellard | /* Reset mode */
|
817 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
818 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
819 | 8977f3c1 | bellard | return;
|
820 | 8977f3c1 | bellard | } |
821 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
|
822 | 8977f3c1 | bellard | /* Disk boot selection indicator */
|
823 | 46d3233b | blueswir1 | fdctrl->tdr = value & FD_TDR_BOOTSEL; |
824 | 8977f3c1 | bellard | /* Tape indicators: never allow */
|
825 | 8977f3c1 | bellard | } |
826 | 8977f3c1 | bellard | |
827 | 8977f3c1 | bellard | /* Main status register : 0x04 (read) */
|
828 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
|
829 | 8977f3c1 | bellard | { |
830 | b9b3d225 | blueswir1 | uint32_t retval = fdctrl->msr; |
831 | 8977f3c1 | bellard | |
832 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
833 | 1c346df2 | blueswir1 | fdctrl->dor |= FD_DOR_nRESET; |
834 | b9b3d225 | blueswir1 | |
835 | 82407d1a | Artyom Tarasenko | /* Sparc mutation */
|
836 | 82407d1a | Artyom Tarasenko | if (fdctrl->sun4m) {
|
837 | 82407d1a | Artyom Tarasenko | retval |= FD_MSR_DIO; |
838 | 82407d1a | Artyom Tarasenko | fdctrl_reset_irq(fdctrl); |
839 | 82407d1a | Artyom Tarasenko | }; |
840 | 82407d1a | Artyom Tarasenko | |
841 | 8977f3c1 | bellard | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
|
842 | 8977f3c1 | bellard | |
843 | 8977f3c1 | bellard | return retval;
|
844 | 8977f3c1 | bellard | } |
845 | 8977f3c1 | bellard | |
846 | 8977f3c1 | bellard | /* Data select rate register : 0x04 (write) */
|
847 | 5c02c033 | Blue Swirl | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) |
848 | 8977f3c1 | bellard | { |
849 | 8977f3c1 | bellard | /* Reset mode */
|
850 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
851 | 4f431960 | j_mayer | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
852 | 4f431960 | j_mayer | return;
|
853 | 4f431960 | j_mayer | } |
854 | 8977f3c1 | bellard | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
|
855 | 8977f3c1 | bellard | /* Reset: autoclear */
|
856 | 9fea808a | blueswir1 | if (value & FD_DSR_SWRESET) {
|
857 | 1c346df2 | blueswir1 | fdctrl->dor &= ~FD_DOR_nRESET; |
858 | baca51fa | bellard | fdctrl_reset(fdctrl, 1);
|
859 | 1c346df2 | blueswir1 | fdctrl->dor |= FD_DOR_nRESET; |
860 | 8977f3c1 | bellard | } |
861 | 9fea808a | blueswir1 | if (value & FD_DSR_PWRDOWN) {
|
862 | baca51fa | bellard | fdctrl_reset(fdctrl, 1);
|
863 | 8977f3c1 | bellard | } |
864 | b9b3d225 | blueswir1 | fdctrl->dsr = value; |
865 | 8977f3c1 | bellard | } |
866 | 8977f3c1 | bellard | |
867 | 5c02c033 | Blue Swirl | static int fdctrl_media_changed(FDrive *drv) |
868 | ea185bbd | bellard | { |
869 | ea185bbd | bellard | int ret;
|
870 | 4f431960 | j_mayer | |
871 | 5fafdf24 | ths | if (!drv->bs)
|
872 | ea185bbd | bellard | return 0; |
873 | ea185bbd | bellard | ret = bdrv_media_changed(drv->bs); |
874 | ea185bbd | bellard | if (ret) {
|
875 | ea185bbd | bellard | fd_revalidate(drv); |
876 | ea185bbd | bellard | } |
877 | ea185bbd | bellard | return ret;
|
878 | ea185bbd | bellard | } |
879 | ea185bbd | bellard | |
880 | 8977f3c1 | bellard | /* Digital input register : 0x07 (read-only) */
|
881 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
|
882 | 8977f3c1 | bellard | { |
883 | 8977f3c1 | bellard | uint32_t retval = 0;
|
884 | 8977f3c1 | bellard | |
885 | 78ae820c | blueswir1 | if (fdctrl_media_changed(drv0(fdctrl))
|
886 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv1(fdctrl)) |
887 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
888 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv2(fdctrl)) |
889 | 78ae820c | blueswir1 | || fdctrl_media_changed(drv3(fdctrl)) |
890 | 78ae820c | blueswir1 | #endif
|
891 | 78ae820c | blueswir1 | ) |
892 | 9fea808a | blueswir1 | retval |= FD_DIR_DSKCHG; |
893 | 3c83eb4f | Blue Swirl | if (retval != 0) { |
894 | baca51fa | bellard | FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
|
895 | 3c83eb4f | Blue Swirl | } |
896 | 8977f3c1 | bellard | |
897 | 8977f3c1 | bellard | return retval;
|
898 | 8977f3c1 | bellard | } |
899 | 8977f3c1 | bellard | |
900 | 8977f3c1 | bellard | /* FIFO state control */
|
901 | 5c02c033 | Blue Swirl | static void fdctrl_reset_fifo(FDCtrl *fdctrl) |
902 | 8977f3c1 | bellard | { |
903 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_WRITE; |
904 | baca51fa | bellard | fdctrl->data_pos = 0;
|
905 | b9b3d225 | blueswir1 | fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
906 | 8977f3c1 | bellard | } |
907 | 8977f3c1 | bellard | |
908 | 8977f3c1 | bellard | /* Set FIFO status for the host to read */
|
909 | 5c02c033 | Blue Swirl | static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq) |
910 | 8977f3c1 | bellard | { |
911 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_READ; |
912 | baca51fa | bellard | fdctrl->data_len = fifo_len; |
913 | baca51fa | bellard | fdctrl->data_pos = 0;
|
914 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
915 | 8977f3c1 | bellard | if (do_irq)
|
916 | baca51fa | bellard | fdctrl_raise_irq(fdctrl, 0x00);
|
917 | 8977f3c1 | bellard | } |
918 | 8977f3c1 | bellard | |
919 | 8977f3c1 | bellard | /* Set an error: unimplemented/unknown command */
|
920 | 5c02c033 | Blue Swirl | static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) |
921 | 8977f3c1 | bellard | { |
922 | 77370520 | blueswir1 | FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); |
923 | 9fea808a | blueswir1 | fdctrl->fifo[0] = FD_SR0_INVCMD;
|
924 | baca51fa | bellard | fdctrl_set_fifo(fdctrl, 1, 0); |
925 | 8977f3c1 | bellard | } |
926 | 8977f3c1 | bellard | |
927 | 746d6de7 | blueswir1 | /* Seek to next sector */
|
928 | 5c02c033 | Blue Swirl | static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) |
929 | 746d6de7 | blueswir1 | { |
930 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
931 | 746d6de7 | blueswir1 | cur_drv->head, cur_drv->track, cur_drv->sect, |
932 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
933 | 746d6de7 | blueswir1 | /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
|
934 | 746d6de7 | blueswir1 | error in fact */
|
935 | 746d6de7 | blueswir1 | if (cur_drv->sect >= cur_drv->last_sect ||
|
936 | 746d6de7 | blueswir1 | cur_drv->sect == fdctrl->eot) { |
937 | 746d6de7 | blueswir1 | cur_drv->sect = 1;
|
938 | 746d6de7 | blueswir1 | if (FD_MULTI_TRACK(fdctrl->data_state)) {
|
939 | 746d6de7 | blueswir1 | if (cur_drv->head == 0 && |
940 | 746d6de7 | blueswir1 | (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
|
941 | 746d6de7 | blueswir1 | cur_drv->head = 1;
|
942 | 746d6de7 | blueswir1 | } else {
|
943 | 746d6de7 | blueswir1 | cur_drv->head = 0;
|
944 | 746d6de7 | blueswir1 | cur_drv->track++; |
945 | 746d6de7 | blueswir1 | if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) |
946 | 746d6de7 | blueswir1 | return 0; |
947 | 746d6de7 | blueswir1 | } |
948 | 746d6de7 | blueswir1 | } else {
|
949 | 746d6de7 | blueswir1 | cur_drv->track++; |
950 | 746d6de7 | blueswir1 | return 0; |
951 | 746d6de7 | blueswir1 | } |
952 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
|
953 | 746d6de7 | blueswir1 | cur_drv->head, cur_drv->track, |
954 | 746d6de7 | blueswir1 | cur_drv->sect, fd_sector(cur_drv)); |
955 | 746d6de7 | blueswir1 | } else {
|
956 | 746d6de7 | blueswir1 | cur_drv->sect++; |
957 | 746d6de7 | blueswir1 | } |
958 | 746d6de7 | blueswir1 | return 1; |
959 | 746d6de7 | blueswir1 | } |
960 | 746d6de7 | blueswir1 | |
961 | 8977f3c1 | bellard | /* Callback for transfer end (stop or abort) */
|
962 | 5c02c033 | Blue Swirl | static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, |
963 | 5c02c033 | Blue Swirl | uint8_t status1, uint8_t status2) |
964 | 8977f3c1 | bellard | { |
965 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
966 | 8977f3c1 | bellard | |
967 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
968 | 8977f3c1 | bellard | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
|
969 | 8977f3c1 | bellard | status0, status1, status2, |
970 | cefec4f5 | blueswir1 | status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
|
971 | cefec4f5 | blueswir1 | fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
972 | baca51fa | bellard | fdctrl->fifo[1] = status1;
|
973 | baca51fa | bellard | fdctrl->fifo[2] = status2;
|
974 | baca51fa | bellard | fdctrl->fifo[3] = cur_drv->track;
|
975 | baca51fa | bellard | fdctrl->fifo[4] = cur_drv->head;
|
976 | baca51fa | bellard | fdctrl->fifo[5] = cur_drv->sect;
|
977 | baca51fa | bellard | fdctrl->fifo[6] = FD_SECTOR_SC;
|
978 | baca51fa | bellard | fdctrl->data_dir = FD_DIR_READ; |
979 | 368df94d | blueswir1 | if (!(fdctrl->msr & FD_MSR_NONDMA)) {
|
980 | baca51fa | bellard | DMA_release_DREQ(fdctrl->dma_chann); |
981 | ed5fd2cc | bellard | } |
982 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
983 | 368df94d | blueswir1 | fdctrl->msr &= ~FD_MSR_NONDMA; |
984 | baca51fa | bellard | fdctrl_set_fifo(fdctrl, 7, 1); |
985 | 8977f3c1 | bellard | } |
986 | 8977f3c1 | bellard | |
987 | 8977f3c1 | bellard | /* Prepare a data transfer (either DMA or FIFO) */
|
988 | 5c02c033 | Blue Swirl | static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) |
989 | 8977f3c1 | bellard | { |
990 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
991 | 8977f3c1 | bellard | uint8_t kh, kt, ks; |
992 | 77370520 | blueswir1 | int did_seek = 0; |
993 | 8977f3c1 | bellard | |
994 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
995 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
996 | baca51fa | bellard | kt = fdctrl->fifo[2];
|
997 | baca51fa | bellard | kh = fdctrl->fifo[3];
|
998 | baca51fa | bellard | ks = fdctrl->fifo[4];
|
999 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
|
1000 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
1001 | 7859cb98 | Blue Swirl | fd_sector_calc(kh, kt, ks, cur_drv->last_sect)); |
1002 | 77370520 | blueswir1 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1003 | 8977f3c1 | bellard | case 2: |
1004 | 8977f3c1 | bellard | /* sect too big */
|
1005 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1006 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1007 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1008 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1009 | 8977f3c1 | bellard | return;
|
1010 | 8977f3c1 | bellard | case 3: |
1011 | 8977f3c1 | bellard | /* track too big */
|
1012 | 77370520 | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1013 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1014 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1015 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1016 | 8977f3c1 | bellard | return;
|
1017 | 8977f3c1 | bellard | case 4: |
1018 | 8977f3c1 | bellard | /* No seek enabled */
|
1019 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1020 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1021 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1022 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1023 | 8977f3c1 | bellard | return;
|
1024 | 8977f3c1 | bellard | case 1: |
1025 | 8977f3c1 | bellard | did_seek = 1;
|
1026 | 8977f3c1 | bellard | break;
|
1027 | 8977f3c1 | bellard | default:
|
1028 | 8977f3c1 | bellard | break;
|
1029 | 8977f3c1 | bellard | } |
1030 | b9b3d225 | blueswir1 | |
1031 | 8977f3c1 | bellard | /* Set the FIFO state */
|
1032 | baca51fa | bellard | fdctrl->data_dir = direction; |
1033 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1034 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_CMDBUSY; |
1035 | baca51fa | bellard | if (fdctrl->fifo[0] & 0x80) |
1036 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_MULTI; |
1037 | baca51fa | bellard | else
|
1038 | baca51fa | bellard | fdctrl->data_state &= ~FD_STATE_MULTI; |
1039 | 8977f3c1 | bellard | if (did_seek)
|
1040 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_SEEK; |
1041 | baca51fa | bellard | else
|
1042 | baca51fa | bellard | fdctrl->data_state &= ~FD_STATE_SEEK; |
1043 | baca51fa | bellard | if (fdctrl->fifo[5] == 00) { |
1044 | baca51fa | bellard | fdctrl->data_len = fdctrl->fifo[8];
|
1045 | baca51fa | bellard | } else {
|
1046 | 4f431960 | j_mayer | int tmp;
|
1047 | 3bcb80f1 | ths | fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
1048 | 771effeb | blueswir1 | tmp = (fdctrl->fifo[6] - ks + 1); |
1049 | baca51fa | bellard | if (fdctrl->fifo[0] & 0x80) |
1050 | 771effeb | blueswir1 | tmp += fdctrl->fifo[6];
|
1051 | 4f431960 | j_mayer | fdctrl->data_len *= tmp; |
1052 | baca51fa | bellard | } |
1053 | 890fa6be | bellard | fdctrl->eot = fdctrl->fifo[6];
|
1054 | 368df94d | blueswir1 | if (fdctrl->dor & FD_DOR_DMAEN) {
|
1055 | 8977f3c1 | bellard | int dma_mode;
|
1056 | 8977f3c1 | bellard | /* DMA transfer are enabled. Check if DMA channel is well programmed */
|
1057 | baca51fa | bellard | dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
1058 | 8977f3c1 | bellard | dma_mode = (dma_mode >> 2) & 3; |
1059 | baca51fa | bellard | FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
|
1060 | 4f431960 | j_mayer | dma_mode, direction, |
1061 | baca51fa | bellard | (128 << fdctrl->fifo[5]) * |
1062 | 4f431960 | j_mayer | (cur_drv->last_sect - ks + 1), fdctrl->data_len);
|
1063 | 8977f3c1 | bellard | if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
|
1064 | 8977f3c1 | bellard | direction == FD_DIR_SCANH) && dma_mode == 0) ||
|
1065 | 8977f3c1 | bellard | (direction == FD_DIR_WRITE && dma_mode == 2) ||
|
1066 | 8977f3c1 | bellard | (direction == FD_DIR_READ && dma_mode == 1)) {
|
1067 | 8977f3c1 | bellard | /* No access is allowed until DMA transfer has completed */
|
1068 | b9b3d225 | blueswir1 | fdctrl->msr &= ~FD_MSR_RQM; |
1069 | 4b19ec0c | bellard | /* Now, we just have to wait for the DMA controller to
|
1070 | 8977f3c1 | bellard | * recall us...
|
1071 | 8977f3c1 | bellard | */
|
1072 | baca51fa | bellard | DMA_hold_DREQ(fdctrl->dma_chann); |
1073 | baca51fa | bellard | DMA_schedule(fdctrl->dma_chann); |
1074 | 8977f3c1 | bellard | return;
|
1075 | baca51fa | bellard | } else {
|
1076 | 4f431960 | j_mayer | FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
|
1077 | 8977f3c1 | bellard | } |
1078 | 8977f3c1 | bellard | } |
1079 | 8977f3c1 | bellard | FLOPPY_DPRINTF("start non-DMA transfer\n");
|
1080 | 368df94d | blueswir1 | fdctrl->msr |= FD_MSR_NONDMA; |
1081 | b9b3d225 | blueswir1 | if (direction != FD_DIR_WRITE)
|
1082 | b9b3d225 | blueswir1 | fdctrl->msr |= FD_MSR_DIO; |
1083 | 8977f3c1 | bellard | /* IO based transfer: calculate len */
|
1084 | baca51fa | bellard | fdctrl_raise_irq(fdctrl, 0x00);
|
1085 | 8977f3c1 | bellard | |
1086 | 8977f3c1 | bellard | return;
|
1087 | 8977f3c1 | bellard | } |
1088 | 8977f3c1 | bellard | |
1089 | 8977f3c1 | bellard | /* Prepare a transfer of deleted data */
|
1090 | 5c02c033 | Blue Swirl | static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) |
1091 | 8977f3c1 | bellard | { |
1092 | 77370520 | blueswir1 | FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
|
1093 | 77370520 | blueswir1 | |
1094 | 8977f3c1 | bellard | /* We don't handle deleted data,
|
1095 | 8977f3c1 | bellard | * so we don't return *ANYTHING*
|
1096 | 8977f3c1 | bellard | */
|
1097 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1098 | 8977f3c1 | bellard | } |
1099 | 8977f3c1 | bellard | |
1100 | 8977f3c1 | bellard | /* handlers for DMA transfers */
|
1101 | 85571bc7 | bellard | static int fdctrl_transfer_handler (void *opaque, int nchan, |
1102 | 85571bc7 | bellard | int dma_pos, int dma_len) |
1103 | 8977f3c1 | bellard | { |
1104 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl; |
1105 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1106 | baca51fa | bellard | int len, start_pos, rel_pos;
|
1107 | 8977f3c1 | bellard | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
1108 | 8977f3c1 | bellard | |
1109 | baca51fa | bellard | fdctrl = opaque; |
1110 | b9b3d225 | blueswir1 | if (fdctrl->msr & FD_MSR_RQM) {
|
1111 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
|
1112 | 8977f3c1 | bellard | return 0; |
1113 | 8977f3c1 | bellard | } |
1114 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1115 | baca51fa | bellard | if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
|
1116 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANH) |
1117 | 77370520 | blueswir1 | status2 = FD_SR2_SNS; |
1118 | 85571bc7 | bellard | if (dma_len > fdctrl->data_len)
|
1119 | 85571bc7 | bellard | dma_len = fdctrl->data_len; |
1120 | 890fa6be | bellard | if (cur_drv->bs == NULL) { |
1121 | 4f431960 | j_mayer | if (fdctrl->data_dir == FD_DIR_WRITE)
|
1122 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1123 | 4f431960 | j_mayer | else
|
1124 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1125 | 4f431960 | j_mayer | len = 0;
|
1126 | 890fa6be | bellard | goto transfer_error;
|
1127 | 890fa6be | bellard | } |
1128 | baca51fa | bellard | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1129 | 85571bc7 | bellard | for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
|
1130 | 85571bc7 | bellard | len = dma_len - fdctrl->data_pos; |
1131 | baca51fa | bellard | if (len + rel_pos > FD_SECTOR_LEN)
|
1132 | baca51fa | bellard | len = FD_SECTOR_LEN - rel_pos; |
1133 | 6f7e9aec | bellard | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
|
1134 | 6f7e9aec | bellard | "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
|
1135 | cefec4f5 | blueswir1 | fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
1136 | baca51fa | bellard | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
1137 | 9fea808a | blueswir1 | fd_sector(cur_drv) * FD_SECTOR_LEN); |
1138 | baca51fa | bellard | if (fdctrl->data_dir != FD_DIR_WRITE ||
|
1139 | 4f431960 | j_mayer | len < FD_SECTOR_LEN || rel_pos != 0) {
|
1140 | baca51fa | bellard | /* READ & SCAN commands and realign to a sector for WRITE */
|
1141 | baca51fa | bellard | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
|
1142 | 4f431960 | j_mayer | fdctrl->fifo, 1) < 0) { |
1143 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
|
1144 | 8977f3c1 | bellard | fd_sector(cur_drv)); |
1145 | 8977f3c1 | bellard | /* Sure, image size is too small... */
|
1146 | baca51fa | bellard | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1147 | 8977f3c1 | bellard | } |
1148 | 890fa6be | bellard | } |
1149 | 4f431960 | j_mayer | switch (fdctrl->data_dir) {
|
1150 | 4f431960 | j_mayer | case FD_DIR_READ:
|
1151 | 4f431960 | j_mayer | /* READ commands */
|
1152 | 85571bc7 | bellard | DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
1153 | 85571bc7 | bellard | fdctrl->data_pos, len); |
1154 | 4f431960 | j_mayer | break;
|
1155 | 4f431960 | j_mayer | case FD_DIR_WRITE:
|
1156 | baca51fa | bellard | /* WRITE commands */
|
1157 | 85571bc7 | bellard | DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
1158 | 85571bc7 | bellard | fdctrl->data_pos, len); |
1159 | baca51fa | bellard | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
|
1160 | 4f431960 | j_mayer | fdctrl->fifo, 1) < 0) { |
1161 | 77370520 | blueswir1 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1162 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1163 | baca51fa | bellard | goto transfer_error;
|
1164 | 890fa6be | bellard | } |
1165 | 4f431960 | j_mayer | break;
|
1166 | 4f431960 | j_mayer | default:
|
1167 | 4f431960 | j_mayer | /* SCAN commands */
|
1168 | baca51fa | bellard | { |
1169 | 4f431960 | j_mayer | uint8_t tmpbuf[FD_SECTOR_LEN]; |
1170 | baca51fa | bellard | int ret;
|
1171 | 85571bc7 | bellard | DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
1172 | baca51fa | bellard | ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
1173 | 8977f3c1 | bellard | if (ret == 0) { |
1174 | 77370520 | blueswir1 | status2 = FD_SR2_SEH; |
1175 | 8977f3c1 | bellard | goto end_transfer;
|
1176 | 8977f3c1 | bellard | } |
1177 | baca51fa | bellard | if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1178 | baca51fa | bellard | (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
|
1179 | 8977f3c1 | bellard | status2 = 0x00;
|
1180 | 8977f3c1 | bellard | goto end_transfer;
|
1181 | 8977f3c1 | bellard | } |
1182 | 8977f3c1 | bellard | } |
1183 | 4f431960 | j_mayer | break;
|
1184 | 8977f3c1 | bellard | } |
1185 | 4f431960 | j_mayer | fdctrl->data_pos += len; |
1186 | 4f431960 | j_mayer | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1187 | baca51fa | bellard | if (rel_pos == 0) { |
1188 | 8977f3c1 | bellard | /* Seek to next sector */
|
1189 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
|
1190 | 746d6de7 | blueswir1 | break;
|
1191 | 8977f3c1 | bellard | } |
1192 | 8977f3c1 | bellard | } |
1193 | 4f431960 | j_mayer | end_transfer:
|
1194 | baca51fa | bellard | len = fdctrl->data_pos - start_pos; |
1195 | baca51fa | bellard | FLOPPY_DPRINTF("end transfer %d %d %d\n",
|
1196 | 4f431960 | j_mayer | fdctrl->data_pos, len, fdctrl->data_len); |
1197 | baca51fa | bellard | if (fdctrl->data_dir == FD_DIR_SCANE ||
|
1198 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANL || |
1199 | baca51fa | bellard | fdctrl->data_dir == FD_DIR_SCANH) |
1200 | 77370520 | blueswir1 | status2 = FD_SR2_SEH; |
1201 | baca51fa | bellard | if (FD_DID_SEEK(fdctrl->data_state))
|
1202 | 9fea808a | blueswir1 | status0 |= FD_SR0_SEEK; |
1203 | baca51fa | bellard | fdctrl->data_len -= len; |
1204 | 890fa6be | bellard | fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
1205 | 4f431960 | j_mayer | transfer_error:
|
1206 | 8977f3c1 | bellard | |
1207 | baca51fa | bellard | return len;
|
1208 | 8977f3c1 | bellard | } |
1209 | 8977f3c1 | bellard | |
1210 | 8977f3c1 | bellard | /* Data register : 0x05 */
|
1211 | 5c02c033 | Blue Swirl | static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
|
1212 | 8977f3c1 | bellard | { |
1213 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1214 | 8977f3c1 | bellard | uint32_t retval = 0;
|
1215 | 746d6de7 | blueswir1 | int pos;
|
1216 | 8977f3c1 | bellard | |
1217 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1218 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1219 | b9b3d225 | blueswir1 | if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
|
1220 | b9b3d225 | blueswir1 | FLOPPY_ERROR("controller not ready for reading\n");
|
1221 | 8977f3c1 | bellard | return 0; |
1222 | 8977f3c1 | bellard | } |
1223 | baca51fa | bellard | pos = fdctrl->data_pos; |
1224 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1225 | 8977f3c1 | bellard | pos %= FD_SECTOR_LEN; |
1226 | 8977f3c1 | bellard | if (pos == 0) { |
1227 | 746d6de7 | blueswir1 | if (fdctrl->data_pos != 0) |
1228 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1229 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1230 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
1231 | 746d6de7 | blueswir1 | return 0; |
1232 | 746d6de7 | blueswir1 | } |
1233 | 77370520 | blueswir1 | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1234 | 77370520 | blueswir1 | FLOPPY_DPRINTF("error getting sector %d\n",
|
1235 | 77370520 | blueswir1 | fd_sector(cur_drv)); |
1236 | 77370520 | blueswir1 | /* Sure, image size is too small... */
|
1237 | 77370520 | blueswir1 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1238 | 77370520 | blueswir1 | } |
1239 | 8977f3c1 | bellard | } |
1240 | 8977f3c1 | bellard | } |
1241 | baca51fa | bellard | retval = fdctrl->fifo[pos]; |
1242 | baca51fa | bellard | if (++fdctrl->data_pos == fdctrl->data_len) {
|
1243 | baca51fa | bellard | fdctrl->data_pos = 0;
|
1244 | 890fa6be | bellard | /* Switch from transfer mode to status mode
|
1245 | 8977f3c1 | bellard | * then from status mode to command mode
|
1246 | 8977f3c1 | bellard | */
|
1247 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1248 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1249 | ed5fd2cc | bellard | } else {
|
1250 | baca51fa | bellard | fdctrl_reset_fifo(fdctrl); |
1251 | ed5fd2cc | bellard | fdctrl_reset_irq(fdctrl); |
1252 | ed5fd2cc | bellard | } |
1253 | 8977f3c1 | bellard | } |
1254 | 8977f3c1 | bellard | FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
|
1255 | 8977f3c1 | bellard | |
1256 | 8977f3c1 | bellard | return retval;
|
1257 | 8977f3c1 | bellard | } |
1258 | 8977f3c1 | bellard | |
1259 | 5c02c033 | Blue Swirl | static void fdctrl_format_sector(FDCtrl *fdctrl) |
1260 | 8977f3c1 | bellard | { |
1261 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1262 | baca51fa | bellard | uint8_t kh, kt, ks; |
1263 | 8977f3c1 | bellard | |
1264 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1265 | baca51fa | bellard | cur_drv = get_cur_drv(fdctrl); |
1266 | baca51fa | bellard | kt = fdctrl->fifo[6];
|
1267 | baca51fa | bellard | kh = fdctrl->fifo[7];
|
1268 | baca51fa | bellard | ks = fdctrl->fifo[8];
|
1269 | baca51fa | bellard | FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
|
1270 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
1271 | 7859cb98 | Blue Swirl | fd_sector_calc(kh, kt, ks, cur_drv->last_sect)); |
1272 | 9fea808a | blueswir1 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1273 | baca51fa | bellard | case 2: |
1274 | baca51fa | bellard | /* sect too big */
|
1275 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1276 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1277 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1278 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1279 | baca51fa | bellard | return;
|
1280 | baca51fa | bellard | case 3: |
1281 | baca51fa | bellard | /* track too big */
|
1282 | 77370520 | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1283 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1284 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1285 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1286 | baca51fa | bellard | return;
|
1287 | baca51fa | bellard | case 4: |
1288 | baca51fa | bellard | /* No seek enabled */
|
1289 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1290 | baca51fa | bellard | fdctrl->fifo[3] = kt;
|
1291 | baca51fa | bellard | fdctrl->fifo[4] = kh;
|
1292 | baca51fa | bellard | fdctrl->fifo[5] = ks;
|
1293 | baca51fa | bellard | return;
|
1294 | baca51fa | bellard | case 1: |
1295 | baca51fa | bellard | fdctrl->data_state |= FD_STATE_SEEK; |
1296 | baca51fa | bellard | break;
|
1297 | baca51fa | bellard | default:
|
1298 | baca51fa | bellard | break;
|
1299 | baca51fa | bellard | } |
1300 | baca51fa | bellard | memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1301 | baca51fa | bellard | if (cur_drv->bs == NULL || |
1302 | baca51fa | bellard | bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1303 | 37a4c539 | ths | FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
|
1304 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1305 | baca51fa | bellard | } else {
|
1306 | 4f431960 | j_mayer | if (cur_drv->sect == cur_drv->last_sect) {
|
1307 | 4f431960 | j_mayer | fdctrl->data_state &= ~FD_STATE_FORMAT; |
1308 | 4f431960 | j_mayer | /* Last sector done */
|
1309 | 4f431960 | j_mayer | if (FD_DID_SEEK(fdctrl->data_state))
|
1310 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1311 | 4f431960 | j_mayer | else
|
1312 | 4f431960 | j_mayer | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1313 | 4f431960 | j_mayer | } else {
|
1314 | 4f431960 | j_mayer | /* More to do */
|
1315 | 4f431960 | j_mayer | fdctrl->data_pos = 0;
|
1316 | 4f431960 | j_mayer | fdctrl->data_len = 4;
|
1317 | 4f431960 | j_mayer | } |
1318 | baca51fa | bellard | } |
1319 | baca51fa | bellard | } |
1320 | baca51fa | bellard | |
1321 | 5c02c033 | Blue Swirl | static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) |
1322 | 65cef780 | blueswir1 | { |
1323 | 65cef780 | blueswir1 | fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; |
1324 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->lock << 4; |
1325 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
|
1326 | 65cef780 | blueswir1 | } |
1327 | 65cef780 | blueswir1 | |
1328 | 5c02c033 | Blue Swirl | static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) |
1329 | 65cef780 | blueswir1 | { |
1330 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1331 | 65cef780 | blueswir1 | |
1332 | 65cef780 | blueswir1 | /* Drives position */
|
1333 | 65cef780 | blueswir1 | fdctrl->fifo[0] = drv0(fdctrl)->track;
|
1334 | 65cef780 | blueswir1 | fdctrl->fifo[1] = drv1(fdctrl)->track;
|
1335 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1336 | 78ae820c | blueswir1 | fdctrl->fifo[2] = drv2(fdctrl)->track;
|
1337 | 78ae820c | blueswir1 | fdctrl->fifo[3] = drv3(fdctrl)->track;
|
1338 | 78ae820c | blueswir1 | #else
|
1339 | 65cef780 | blueswir1 | fdctrl->fifo[2] = 0; |
1340 | 65cef780 | blueswir1 | fdctrl->fifo[3] = 0; |
1341 | 78ae820c | blueswir1 | #endif
|
1342 | 65cef780 | blueswir1 | /* timers */
|
1343 | 65cef780 | blueswir1 | fdctrl->fifo[4] = fdctrl->timer0;
|
1344 | 368df94d | blueswir1 | fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
1345 | 65cef780 | blueswir1 | fdctrl->fifo[6] = cur_drv->last_sect;
|
1346 | 65cef780 | blueswir1 | fdctrl->fifo[7] = (fdctrl->lock << 7) | |
1347 | 65cef780 | blueswir1 | (cur_drv->perpendicular << 2);
|
1348 | 65cef780 | blueswir1 | fdctrl->fifo[8] = fdctrl->config;
|
1349 | 65cef780 | blueswir1 | fdctrl->fifo[9] = fdctrl->precomp_trk;
|
1350 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 10, 0); |
1351 | 65cef780 | blueswir1 | } |
1352 | 65cef780 | blueswir1 | |
1353 | 5c02c033 | Blue Swirl | static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) |
1354 | 65cef780 | blueswir1 | { |
1355 | 65cef780 | blueswir1 | /* Controller's version */
|
1356 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->version;
|
1357 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1358 | 65cef780 | blueswir1 | } |
1359 | 65cef780 | blueswir1 | |
1360 | 5c02c033 | Blue Swirl | static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) |
1361 | 65cef780 | blueswir1 | { |
1362 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0x41; /* Stepping 1 */ |
1363 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 0); |
1364 | 65cef780 | blueswir1 | } |
1365 | 65cef780 | blueswir1 | |
1366 | 5c02c033 | Blue Swirl | static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) |
1367 | 65cef780 | blueswir1 | { |
1368 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1369 | 65cef780 | blueswir1 | |
1370 | 65cef780 | blueswir1 | /* Drives position */
|
1371 | 65cef780 | blueswir1 | drv0(fdctrl)->track = fdctrl->fifo[3];
|
1372 | 65cef780 | blueswir1 | drv1(fdctrl)->track = fdctrl->fifo[4];
|
1373 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1374 | 78ae820c | blueswir1 | drv2(fdctrl)->track = fdctrl->fifo[5];
|
1375 | 78ae820c | blueswir1 | drv3(fdctrl)->track = fdctrl->fifo[6];
|
1376 | 78ae820c | blueswir1 | #endif
|
1377 | 65cef780 | blueswir1 | /* timers */
|
1378 | 65cef780 | blueswir1 | fdctrl->timer0 = fdctrl->fifo[7];
|
1379 | 65cef780 | blueswir1 | fdctrl->timer1 = fdctrl->fifo[8];
|
1380 | 65cef780 | blueswir1 | cur_drv->last_sect = fdctrl->fifo[9];
|
1381 | 65cef780 | blueswir1 | fdctrl->lock = fdctrl->fifo[10] >> 7; |
1382 | 65cef780 | blueswir1 | cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; |
1383 | 65cef780 | blueswir1 | fdctrl->config = fdctrl->fifo[11];
|
1384 | 65cef780 | blueswir1 | fdctrl->precomp_trk = fdctrl->fifo[12];
|
1385 | 65cef780 | blueswir1 | fdctrl->pwrd = fdctrl->fifo[13];
|
1386 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1387 | 65cef780 | blueswir1 | } |
1388 | 65cef780 | blueswir1 | |
1389 | 5c02c033 | Blue Swirl | static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) |
1390 | 65cef780 | blueswir1 | { |
1391 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1392 | 65cef780 | blueswir1 | |
1393 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0; |
1394 | 65cef780 | blueswir1 | fdctrl->fifo[1] = 0; |
1395 | 65cef780 | blueswir1 | /* Drives position */
|
1396 | 65cef780 | blueswir1 | fdctrl->fifo[2] = drv0(fdctrl)->track;
|
1397 | 65cef780 | blueswir1 | fdctrl->fifo[3] = drv1(fdctrl)->track;
|
1398 | 78ae820c | blueswir1 | #if MAX_FD == 4 |
1399 | 78ae820c | blueswir1 | fdctrl->fifo[4] = drv2(fdctrl)->track;
|
1400 | 78ae820c | blueswir1 | fdctrl->fifo[5] = drv3(fdctrl)->track;
|
1401 | 78ae820c | blueswir1 | #else
|
1402 | 65cef780 | blueswir1 | fdctrl->fifo[4] = 0; |
1403 | 65cef780 | blueswir1 | fdctrl->fifo[5] = 0; |
1404 | 78ae820c | blueswir1 | #endif
|
1405 | 65cef780 | blueswir1 | /* timers */
|
1406 | 65cef780 | blueswir1 | fdctrl->fifo[6] = fdctrl->timer0;
|
1407 | 65cef780 | blueswir1 | fdctrl->fifo[7] = fdctrl->timer1;
|
1408 | 65cef780 | blueswir1 | fdctrl->fifo[8] = cur_drv->last_sect;
|
1409 | 65cef780 | blueswir1 | fdctrl->fifo[9] = (fdctrl->lock << 7) | |
1410 | 65cef780 | blueswir1 | (cur_drv->perpendicular << 2);
|
1411 | 65cef780 | blueswir1 | fdctrl->fifo[10] = fdctrl->config;
|
1412 | 65cef780 | blueswir1 | fdctrl->fifo[11] = fdctrl->precomp_trk;
|
1413 | 65cef780 | blueswir1 | fdctrl->fifo[12] = fdctrl->pwrd;
|
1414 | 65cef780 | blueswir1 | fdctrl->fifo[13] = 0; |
1415 | 65cef780 | blueswir1 | fdctrl->fifo[14] = 0; |
1416 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 15, 1); |
1417 | 65cef780 | blueswir1 | } |
1418 | 65cef780 | blueswir1 | |
1419 | 5c02c033 | Blue Swirl | static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) |
1420 | 65cef780 | blueswir1 | { |
1421 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1422 | 65cef780 | blueswir1 | |
1423 | 65cef780 | blueswir1 | /* XXX: should set main status register to busy */
|
1424 | 65cef780 | blueswir1 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1425 | 65cef780 | blueswir1 | qemu_mod_timer(fdctrl->result_timer, |
1426 | 6ee093c9 | Juan Quintela | qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
|
1427 | 65cef780 | blueswir1 | } |
1428 | 65cef780 | blueswir1 | |
1429 | 5c02c033 | Blue Swirl | static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) |
1430 | 65cef780 | blueswir1 | { |
1431 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1432 | 65cef780 | blueswir1 | |
1433 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1434 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1435 | 65cef780 | blueswir1 | fdctrl->data_state |= FD_STATE_FORMAT; |
1436 | 65cef780 | blueswir1 | if (fdctrl->fifo[0] & 0x80) |
1437 | 65cef780 | blueswir1 | fdctrl->data_state |= FD_STATE_MULTI; |
1438 | 65cef780 | blueswir1 | else
|
1439 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_MULTI; |
1440 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_SEEK; |
1441 | 65cef780 | blueswir1 | cur_drv->bps = |
1442 | 65cef780 | blueswir1 | fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; |
1443 | 65cef780 | blueswir1 | #if 0
|
1444 | 65cef780 | blueswir1 | cur_drv->last_sect =
|
1445 | 65cef780 | blueswir1 | cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
|
1446 | 65cef780 | blueswir1 | fdctrl->fifo[3] / 2;
|
1447 | 65cef780 | blueswir1 | #else
|
1448 | 65cef780 | blueswir1 | cur_drv->last_sect = fdctrl->fifo[3];
|
1449 | 65cef780 | blueswir1 | #endif
|
1450 | 65cef780 | blueswir1 | /* TODO: implement format using DMA expected by the Bochs BIOS
|
1451 | 65cef780 | blueswir1 | * and Linux fdformat (read 3 bytes per sector via DMA and fill
|
1452 | 65cef780 | blueswir1 | * the sector with the specified fill byte
|
1453 | 65cef780 | blueswir1 | */
|
1454 | 65cef780 | blueswir1 | fdctrl->data_state &= ~FD_STATE_FORMAT; |
1455 | 65cef780 | blueswir1 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1456 | 65cef780 | blueswir1 | } |
1457 | 65cef780 | blueswir1 | |
1458 | 5c02c033 | Blue Swirl | static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) |
1459 | 65cef780 | blueswir1 | { |
1460 | 65cef780 | blueswir1 | fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; |
1461 | 65cef780 | blueswir1 | fdctrl->timer1 = fdctrl->fifo[2] >> 1; |
1462 | 368df94d | blueswir1 | if (fdctrl->fifo[2] & 1) |
1463 | 368df94d | blueswir1 | fdctrl->dor &= ~FD_DOR_DMAEN; |
1464 | 368df94d | blueswir1 | else
|
1465 | 368df94d | blueswir1 | fdctrl->dor |= FD_DOR_DMAEN; |
1466 | 65cef780 | blueswir1 | /* No result back */
|
1467 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1468 | 65cef780 | blueswir1 | } |
1469 | 65cef780 | blueswir1 | |
1470 | 5c02c033 | Blue Swirl | static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) |
1471 | 65cef780 | blueswir1 | { |
1472 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1473 | 65cef780 | blueswir1 | |
1474 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1475 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1476 | 65cef780 | blueswir1 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1477 | 65cef780 | blueswir1 | /* 1 Byte status back */
|
1478 | 65cef780 | blueswir1 | fdctrl->fifo[0] = (cur_drv->ro << 6) | |
1479 | 65cef780 | blueswir1 | (cur_drv->track == 0 ? 0x10 : 0x00) | |
1480 | 65cef780 | blueswir1 | (cur_drv->head << 2) |
|
1481 | cefec4f5 | blueswir1 | GET_CUR_DRV(fdctrl) | |
1482 | 65cef780 | blueswir1 | 0x28;
|
1483 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 0); |
1484 | 65cef780 | blueswir1 | } |
1485 | 65cef780 | blueswir1 | |
1486 | 5c02c033 | Blue Swirl | static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) |
1487 | 65cef780 | blueswir1 | { |
1488 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1489 | 65cef780 | blueswir1 | |
1490 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1491 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1492 | 65cef780 | blueswir1 | fd_recalibrate(cur_drv); |
1493 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1494 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1495 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1496 | 65cef780 | blueswir1 | } |
1497 | 65cef780 | blueswir1 | |
1498 | 5c02c033 | Blue Swirl | static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) |
1499 | 65cef780 | blueswir1 | { |
1500 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1501 | 65cef780 | blueswir1 | |
1502 | f2d81b33 | blueswir1 | if(fdctrl->reset_sensei > 0) { |
1503 | f2d81b33 | blueswir1 | fdctrl->fifo[0] =
|
1504 | f2d81b33 | blueswir1 | FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; |
1505 | f2d81b33 | blueswir1 | fdctrl->reset_sensei--; |
1506 | f2d81b33 | blueswir1 | } else {
|
1507 | f2d81b33 | blueswir1 | /* XXX: status0 handling is broken for read/write
|
1508 | f2d81b33 | blueswir1 | commands, so we do this hack. It should be suppressed
|
1509 | f2d81b33 | blueswir1 | ASAP */
|
1510 | f2d81b33 | blueswir1 | fdctrl->fifo[0] =
|
1511 | f2d81b33 | blueswir1 | FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1512 | f2d81b33 | blueswir1 | } |
1513 | f2d81b33 | blueswir1 | |
1514 | 65cef780 | blueswir1 | fdctrl->fifo[1] = cur_drv->track;
|
1515 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 2, 0); |
1516 | 65cef780 | blueswir1 | fdctrl_reset_irq(fdctrl); |
1517 | 77370520 | blueswir1 | fdctrl->status0 = FD_SR0_RDYCHG; |
1518 | 65cef780 | blueswir1 | } |
1519 | 65cef780 | blueswir1 | |
1520 | 5c02c033 | Blue Swirl | static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) |
1521 | 65cef780 | blueswir1 | { |
1522 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1523 | 65cef780 | blueswir1 | |
1524 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1525 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1526 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1527 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] > cur_drv->max_track) { |
1528 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK); |
1529 | 65cef780 | blueswir1 | } else {
|
1530 | 65cef780 | blueswir1 | cur_drv->track = fdctrl->fifo[2];
|
1531 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1532 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1533 | 65cef780 | blueswir1 | } |
1534 | 65cef780 | blueswir1 | } |
1535 | 65cef780 | blueswir1 | |
1536 | 5c02c033 | Blue Swirl | static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) |
1537 | 65cef780 | blueswir1 | { |
1538 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1539 | 65cef780 | blueswir1 | |
1540 | 65cef780 | blueswir1 | if (fdctrl->fifo[1] & 0x80) |
1541 | 65cef780 | blueswir1 | cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; |
1542 | 65cef780 | blueswir1 | /* No result back */
|
1543 | 1c346df2 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1544 | 65cef780 | blueswir1 | } |
1545 | 65cef780 | blueswir1 | |
1546 | 5c02c033 | Blue Swirl | static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) |
1547 | 65cef780 | blueswir1 | { |
1548 | 65cef780 | blueswir1 | fdctrl->config = fdctrl->fifo[2];
|
1549 | 65cef780 | blueswir1 | fdctrl->precomp_trk = fdctrl->fifo[3];
|
1550 | 65cef780 | blueswir1 | /* No result back */
|
1551 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1552 | 65cef780 | blueswir1 | } |
1553 | 65cef780 | blueswir1 | |
1554 | 5c02c033 | Blue Swirl | static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) |
1555 | 65cef780 | blueswir1 | { |
1556 | 65cef780 | blueswir1 | fdctrl->pwrd = fdctrl->fifo[1];
|
1557 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
1558 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1559 | 65cef780 | blueswir1 | } |
1560 | 65cef780 | blueswir1 | |
1561 | 5c02c033 | Blue Swirl | static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) |
1562 | 65cef780 | blueswir1 | { |
1563 | 65cef780 | blueswir1 | /* No result back */
|
1564 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1565 | 65cef780 | blueswir1 | } |
1566 | 65cef780 | blueswir1 | |
1567 | 5c02c033 | Blue Swirl | static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) |
1568 | 65cef780 | blueswir1 | { |
1569 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1570 | 65cef780 | blueswir1 | |
1571 | 65cef780 | blueswir1 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { |
1572 | 65cef780 | blueswir1 | /* Command parameters done */
|
1573 | 65cef780 | blueswir1 | if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { |
1574 | 65cef780 | blueswir1 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
1575 | 65cef780 | blueswir1 | fdctrl->fifo[2] = 0; |
1576 | 65cef780 | blueswir1 | fdctrl->fifo[3] = 0; |
1577 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 4, 1); |
1578 | 65cef780 | blueswir1 | } else {
|
1579 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1580 | 65cef780 | blueswir1 | } |
1581 | 65cef780 | blueswir1 | } else if (fdctrl->data_len > 7) { |
1582 | 65cef780 | blueswir1 | /* ERROR */
|
1583 | 65cef780 | blueswir1 | fdctrl->fifo[0] = 0x80 | |
1584 | cefec4f5 | blueswir1 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1585 | 65cef780 | blueswir1 | fdctrl_set_fifo(fdctrl, 1, 1); |
1586 | 65cef780 | blueswir1 | } |
1587 | 65cef780 | blueswir1 | } |
1588 | 65cef780 | blueswir1 | |
1589 | 5c02c033 | Blue Swirl | static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) |
1590 | 65cef780 | blueswir1 | { |
1591 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1592 | 65cef780 | blueswir1 | |
1593 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1594 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1595 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
1596 | 65cef780 | blueswir1 | cur_drv->track = cur_drv->max_track - 1;
|
1597 | 65cef780 | blueswir1 | } else {
|
1598 | 65cef780 | blueswir1 | cur_drv->track += fdctrl->fifo[2];
|
1599 | 65cef780 | blueswir1 | } |
1600 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1601 | 77370520 | blueswir1 | /* Raise Interrupt */
|
1602 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1603 | 65cef780 | blueswir1 | } |
1604 | 65cef780 | blueswir1 | |
1605 | 5c02c033 | Blue Swirl | static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) |
1606 | 65cef780 | blueswir1 | { |
1607 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1608 | 65cef780 | blueswir1 | |
1609 | cefec4f5 | blueswir1 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1610 | 65cef780 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1611 | 65cef780 | blueswir1 | if (fdctrl->fifo[2] > cur_drv->track) { |
1612 | 65cef780 | blueswir1 | cur_drv->track = 0;
|
1613 | 65cef780 | blueswir1 | } else {
|
1614 | 65cef780 | blueswir1 | cur_drv->track -= fdctrl->fifo[2];
|
1615 | 65cef780 | blueswir1 | } |
1616 | 65cef780 | blueswir1 | fdctrl_reset_fifo(fdctrl); |
1617 | 65cef780 | blueswir1 | /* Raise Interrupt */
|
1618 | 65cef780 | blueswir1 | fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1619 | 65cef780 | blueswir1 | } |
1620 | 65cef780 | blueswir1 | |
1621 | 678803ab | blueswir1 | static const struct { |
1622 | 678803ab | blueswir1 | uint8_t value; |
1623 | 678803ab | blueswir1 | uint8_t mask; |
1624 | 678803ab | blueswir1 | const char* name; |
1625 | 678803ab | blueswir1 | int parameters;
|
1626 | 5c02c033 | Blue Swirl | void (*handler)(FDCtrl *fdctrl, int direction); |
1627 | 678803ab | blueswir1 | int direction;
|
1628 | 678803ab | blueswir1 | } handlers[] = { |
1629 | 678803ab | blueswir1 | { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1630 | 678803ab | blueswir1 | { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, |
1631 | 678803ab | blueswir1 | { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, |
1632 | 678803ab | blueswir1 | { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, |
1633 | 678803ab | blueswir1 | { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, |
1634 | 678803ab | blueswir1 | { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, |
1635 | 678803ab | blueswir1 | { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1636 | 678803ab | blueswir1 | { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ |
1637 | 678803ab | blueswir1 | { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ |
1638 | 678803ab | blueswir1 | { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, |
1639 | 678803ab | blueswir1 | { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, |
1640 | 678803ab | blueswir1 | { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented }, |
1641 | 678803ab | blueswir1 | { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, |
1642 | 678803ab | blueswir1 | { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, |
1643 | 678803ab | blueswir1 | { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, |
1644 | 678803ab | blueswir1 | { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, |
1645 | 678803ab | blueswir1 | { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, |
1646 | 678803ab | blueswir1 | { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, |
1647 | 678803ab | blueswir1 | { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, |
1648 | 678803ab | blueswir1 | { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, |
1649 | 678803ab | blueswir1 | { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, |
1650 | 678803ab | blueswir1 | { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, |
1651 | 678803ab | blueswir1 | { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, |
1652 | 678803ab | blueswir1 | { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, |
1653 | 678803ab | blueswir1 | { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, |
1654 | 678803ab | blueswir1 | { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, |
1655 | 678803ab | blueswir1 | { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, |
1656 | 678803ab | blueswir1 | { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, |
1657 | 678803ab | blueswir1 | { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, |
1658 | 678803ab | blueswir1 | { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, |
1659 | 678803ab | blueswir1 | { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ |
1660 | 678803ab | blueswir1 | { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ |
1661 | 678803ab | blueswir1 | }; |
1662 | 678803ab | blueswir1 | /* Associate command to an index in the 'handlers' array */
|
1663 | 678803ab | blueswir1 | static uint8_t command_to_handler[256]; |
1664 | 678803ab | blueswir1 | |
1665 | 5c02c033 | Blue Swirl | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) |
1666 | baca51fa | bellard | { |
1667 | 5c02c033 | Blue Swirl | FDrive *cur_drv; |
1668 | 65cef780 | blueswir1 | int pos;
|
1669 | baca51fa | bellard | |
1670 | 8977f3c1 | bellard | /* Reset mode */
|
1671 | 1c346df2 | blueswir1 | if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
1672 | 4b19ec0c | bellard | FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
1673 | 8977f3c1 | bellard | return;
|
1674 | 8977f3c1 | bellard | } |
1675 | b9b3d225 | blueswir1 | if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
|
1676 | b9b3d225 | blueswir1 | FLOPPY_ERROR("controller not ready for writing\n");
|
1677 | 8977f3c1 | bellard | return;
|
1678 | 8977f3c1 | bellard | } |
1679 | b9b3d225 | blueswir1 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1680 | 8977f3c1 | bellard | /* Is it write command time ? */
|
1681 | 368df94d | blueswir1 | if (fdctrl->msr & FD_MSR_NONDMA) {
|
1682 | 8977f3c1 | bellard | /* FIFO data write */
|
1683 | b3bc1540 | blueswir1 | pos = fdctrl->data_pos++; |
1684 | b3bc1540 | blueswir1 | pos %= FD_SECTOR_LEN; |
1685 | b3bc1540 | blueswir1 | fdctrl->fifo[pos] = value; |
1686 | b3bc1540 | blueswir1 | if (pos == FD_SECTOR_LEN - 1 || |
1687 | baca51fa | bellard | fdctrl->data_pos == fdctrl->data_len) { |
1688 | 77370520 | blueswir1 | cur_drv = get_cur_drv(fdctrl); |
1689 | 77370520 | blueswir1 | if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1690 | 77370520 | blueswir1 | FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1691 | 77370520 | blueswir1 | return;
|
1692 | 77370520 | blueswir1 | } |
1693 | 746d6de7 | blueswir1 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1694 | 746d6de7 | blueswir1 | FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1695 | 746d6de7 | blueswir1 | fd_sector(cur_drv)); |
1696 | 746d6de7 | blueswir1 | return;
|
1697 | 746d6de7 | blueswir1 | } |
1698 | 8977f3c1 | bellard | } |
1699 | 890fa6be | bellard | /* Switch from transfer mode to status mode
|
1700 | 8977f3c1 | bellard | * then from status mode to command mode
|
1701 | 8977f3c1 | bellard | */
|
1702 | b9b3d225 | blueswir1 | if (fdctrl->data_pos == fdctrl->data_len)
|
1703 | 9fea808a | blueswir1 | fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1704 | 8977f3c1 | bellard | return;
|
1705 | 8977f3c1 | bellard | } |
1706 | baca51fa | bellard | if (fdctrl->data_pos == 0) { |
1707 | 8977f3c1 | bellard | /* Command */
|
1708 | 678803ab | blueswir1 | pos = command_to_handler[value & 0xff];
|
1709 | 678803ab | blueswir1 | FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
|
1710 | 678803ab | blueswir1 | fdctrl->data_len = handlers[pos].parameters + 1;
|
1711 | 8977f3c1 | bellard | } |
1712 | 678803ab | blueswir1 | |
1713 | baca51fa | bellard | FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
|
1714 | 77370520 | blueswir1 | fdctrl->fifo[fdctrl->data_pos++] = value; |
1715 | 77370520 | blueswir1 | if (fdctrl->data_pos == fdctrl->data_len) {
|
1716 | 8977f3c1 | bellard | /* We now have all parameters
|
1717 | 8977f3c1 | bellard | * and will be able to treat the command
|
1718 | 8977f3c1 | bellard | */
|
1719 | 4f431960 | j_mayer | if (fdctrl->data_state & FD_STATE_FORMAT) {
|
1720 | 4f431960 | j_mayer | fdctrl_format_sector(fdctrl); |
1721 | 8977f3c1 | bellard | return;
|
1722 | 8977f3c1 | bellard | } |
1723 | 65cef780 | blueswir1 | |
1724 | 678803ab | blueswir1 | pos = command_to_handler[fdctrl->fifo[0] & 0xff]; |
1725 | 678803ab | blueswir1 | FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
|
1726 | 678803ab | blueswir1 | (*handlers[pos].handler)(fdctrl, handlers[pos].direction); |
1727 | 8977f3c1 | bellard | } |
1728 | 8977f3c1 | bellard | } |
1729 | ed5fd2cc | bellard | |
1730 | ed5fd2cc | bellard | static void fdctrl_result_timer(void *opaque) |
1731 | ed5fd2cc | bellard | { |
1732 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = opaque; |
1733 | 5c02c033 | Blue Swirl | FDrive *cur_drv = get_cur_drv(fdctrl); |
1734 | 4f431960 | j_mayer | |
1735 | b7ffa3b1 | ths | /* Pretend we are spinning.
|
1736 | b7ffa3b1 | ths | * This is needed for Coherent, which uses READ ID to check for
|
1737 | b7ffa3b1 | ths | * sector interleaving.
|
1738 | b7ffa3b1 | ths | */
|
1739 | b7ffa3b1 | ths | if (cur_drv->last_sect != 0) { |
1740 | b7ffa3b1 | ths | cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
|
1741 | b7ffa3b1 | ths | } |
1742 | ed5fd2cc | bellard | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1743 | ed5fd2cc | bellard | } |
1744 | 678803ab | blueswir1 | |
1745 | 678803ab | blueswir1 | /* Init functions */
|
1746 | b47b3525 | Markus Armbruster | static int fdctrl_connect_drives(FDCtrl *fdctrl) |
1747 | 678803ab | blueswir1 | { |
1748 | 12a71a02 | Blue Swirl | unsigned int i; |
1749 | 7d0d6950 | Markus Armbruster | FDrive *drive; |
1750 | 678803ab | blueswir1 | |
1751 | 678803ab | blueswir1 | for (i = 0; i < MAX_FD; i++) { |
1752 | 7d0d6950 | Markus Armbruster | drive = &fdctrl->drives[i]; |
1753 | 7d0d6950 | Markus Armbruster | |
1754 | b47b3525 | Markus Armbruster | if (drive->bs) {
|
1755 | b47b3525 | Markus Armbruster | if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) { |
1756 | b47b3525 | Markus Armbruster | error_report("fdc doesn't support drive option werror");
|
1757 | b47b3525 | Markus Armbruster | return -1; |
1758 | b47b3525 | Markus Armbruster | } |
1759 | b47b3525 | Markus Armbruster | if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) { |
1760 | b47b3525 | Markus Armbruster | error_report("fdc doesn't support drive option rerror");
|
1761 | b47b3525 | Markus Armbruster | return -1; |
1762 | b47b3525 | Markus Armbruster | } |
1763 | b47b3525 | Markus Armbruster | } |
1764 | b47b3525 | Markus Armbruster | |
1765 | 7d0d6950 | Markus Armbruster | fd_init(drive); |
1766 | 7d0d6950 | Markus Armbruster | fd_revalidate(drive); |
1767 | 7d0d6950 | Markus Armbruster | if (drive->bs) {
|
1768 | 7d0d6950 | Markus Armbruster | bdrv_set_removable(drive->bs, 1);
|
1769 | 7d0d6950 | Markus Armbruster | } |
1770 | 678803ab | blueswir1 | } |
1771 | b47b3525 | Markus Armbruster | return 0; |
1772 | 678803ab | blueswir1 | } |
1773 | 678803ab | blueswir1 | |
1774 | 63ffb564 | Blue Swirl | void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, |
1775 | 63ffb564 | Blue Swirl | target_phys_addr_t mmio_base, DriveInfo **fds) |
1776 | 2091ba23 | Gerd Hoffmann | { |
1777 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl; |
1778 | 2091ba23 | Gerd Hoffmann | DeviceState *dev; |
1779 | 5c02c033 | Blue Swirl | FDCtrlSysBus *sys; |
1780 | 2091ba23 | Gerd Hoffmann | |
1781 | 2091ba23 | Gerd Hoffmann | dev = qdev_create(NULL, "sysbus-fdc"); |
1782 | 5c02c033 | Blue Swirl | sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
1783 | 99244fa1 | Gerd Hoffmann | fdctrl = &sys->state; |
1784 | 99244fa1 | Gerd Hoffmann | fdctrl->dma_chann = dma_chann; /* FIXME */
|
1785 | 995bf0ca | Gerd Hoffmann | if (fds[0]) { |
1786 | 18846dee | Markus Armbruster | qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); |
1787 | 995bf0ca | Gerd Hoffmann | } |
1788 | 995bf0ca | Gerd Hoffmann | if (fds[1]) { |
1789 | 18846dee | Markus Armbruster | qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); |
1790 | 995bf0ca | Gerd Hoffmann | } |
1791 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1792 | 2091ba23 | Gerd Hoffmann | sysbus_connect_irq(&sys->busdev, 0, irq);
|
1793 | 2091ba23 | Gerd Hoffmann | sysbus_mmio_map(&sys->busdev, 0, mmio_base);
|
1794 | 678803ab | blueswir1 | } |
1795 | 678803ab | blueswir1 | |
1796 | 63ffb564 | Blue Swirl | void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
|
1797 | 63ffb564 | Blue Swirl | DriveInfo **fds, qemu_irq *fdc_tc) |
1798 | 678803ab | blueswir1 | { |
1799 | f64ab228 | Blue Swirl | DeviceState *dev; |
1800 | 5c02c033 | Blue Swirl | FDCtrlSysBus *sys; |
1801 | 678803ab | blueswir1 | |
1802 | 12a71a02 | Blue Swirl | dev = qdev_create(NULL, "SUNW,fdtwo"); |
1803 | 995bf0ca | Gerd Hoffmann | if (fds[0]) { |
1804 | 18846dee | Markus Armbruster | qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); |
1805 | 995bf0ca | Gerd Hoffmann | } |
1806 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1807 | 5c02c033 | Blue Swirl | sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
1808 | 8baf73ad | Gerd Hoffmann | sysbus_connect_irq(&sys->busdev, 0, irq);
|
1809 | 8baf73ad | Gerd Hoffmann | sysbus_mmio_map(&sys->busdev, 0, io_base);
|
1810 | f64ab228 | Blue Swirl | *fdc_tc = qdev_get_gpio_in(dev, 0);
|
1811 | 678803ab | blueswir1 | } |
1812 | f64ab228 | Blue Swirl | |
1813 | a64405d1 | Jan Kiszka | static int fdctrl_init_common(FDCtrl *fdctrl) |
1814 | f64ab228 | Blue Swirl | { |
1815 | 12a71a02 | Blue Swirl | int i, j;
|
1816 | 12a71a02 | Blue Swirl | static int command_tables_inited = 0; |
1817 | f64ab228 | Blue Swirl | |
1818 | 12a71a02 | Blue Swirl | /* Fill 'command_to_handler' lookup table */
|
1819 | 12a71a02 | Blue Swirl | if (!command_tables_inited) {
|
1820 | 12a71a02 | Blue Swirl | command_tables_inited = 1;
|
1821 | 12a71a02 | Blue Swirl | for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { |
1822 | 12a71a02 | Blue Swirl | for (j = 0; j < sizeof(command_to_handler); j++) { |
1823 | 12a71a02 | Blue Swirl | if ((j & handlers[i].mask) == handlers[i].value) {
|
1824 | 12a71a02 | Blue Swirl | command_to_handler[j] = i; |
1825 | 12a71a02 | Blue Swirl | } |
1826 | 12a71a02 | Blue Swirl | } |
1827 | 12a71a02 | Blue Swirl | } |
1828 | 12a71a02 | Blue Swirl | } |
1829 | 12a71a02 | Blue Swirl | |
1830 | 12a71a02 | Blue Swirl | FLOPPY_DPRINTF("init controller\n");
|
1831 | 12a71a02 | Blue Swirl | fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
|
1832 | d7a6c270 | Juan Quintela | fdctrl->fifo_size = 512;
|
1833 | 12a71a02 | Blue Swirl | fdctrl->result_timer = qemu_new_timer(vm_clock, |
1834 | 12a71a02 | Blue Swirl | fdctrl_result_timer, fdctrl); |
1835 | 12a71a02 | Blue Swirl | |
1836 | 12a71a02 | Blue Swirl | fdctrl->version = 0x90; /* Intel 82078 controller */ |
1837 | 12a71a02 | Blue Swirl | fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
|
1838 | d7a6c270 | Juan Quintela | fdctrl->num_floppies = MAX_FD; |
1839 | 12a71a02 | Blue Swirl | |
1840 | 99244fa1 | Gerd Hoffmann | if (fdctrl->dma_chann != -1) |
1841 | 99244fa1 | Gerd Hoffmann | DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); |
1842 | b47b3525 | Markus Armbruster | return fdctrl_connect_drives(fdctrl);
|
1843 | f64ab228 | Blue Swirl | } |
1844 | f64ab228 | Blue Swirl | |
1845 | 81a322d4 | Gerd Hoffmann | static int isabus_fdc_init1(ISADevice *dev) |
1846 | 8baf73ad | Gerd Hoffmann | { |
1847 | 5c02c033 | Blue Swirl | FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); |
1848 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = &isa->state; |
1849 | 86c86157 | Gerd Hoffmann | int iobase = 0x3f0; |
1850 | 2e15e23b | Gerd Hoffmann | int isairq = 6; |
1851 | 99244fa1 | Gerd Hoffmann | int dma_chann = 2; |
1852 | 2be37833 | Blue Swirl | int ret;
|
1853 | 8baf73ad | Gerd Hoffmann | |
1854 | 86c86157 | Gerd Hoffmann | register_ioport_read(iobase + 0x01, 5, 1, |
1855 | 8baf73ad | Gerd Hoffmann | &fdctrl_read_port, fdctrl); |
1856 | 86c86157 | Gerd Hoffmann | register_ioport_read(iobase + 0x07, 1, 1, |
1857 | 8baf73ad | Gerd Hoffmann | &fdctrl_read_port, fdctrl); |
1858 | 86c86157 | Gerd Hoffmann | register_ioport_write(iobase + 0x01, 5, 1, |
1859 | 8baf73ad | Gerd Hoffmann | &fdctrl_write_port, fdctrl); |
1860 | 86c86157 | Gerd Hoffmann | register_ioport_write(iobase + 0x07, 1, 1, |
1861 | 8baf73ad | Gerd Hoffmann | &fdctrl_write_port, fdctrl); |
1862 | dee41d58 | Gleb Natapov | isa_init_ioport_range(dev, iobase, 6);
|
1863 | dee41d58 | Gleb Natapov | isa_init_ioport(dev, iobase + 7);
|
1864 | dee41d58 | Gleb Natapov | |
1865 | 2e15e23b | Gerd Hoffmann | isa_init_irq(&isa->busdev, &fdctrl->irq, isairq); |
1866 | 99244fa1 | Gerd Hoffmann | fdctrl->dma_chann = dma_chann; |
1867 | 8baf73ad | Gerd Hoffmann | |
1868 | a64405d1 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
|
1869 | a64405d1 | Jan Kiszka | ret = fdctrl_init_common(fdctrl); |
1870 | 2be37833 | Blue Swirl | |
1871 | 1ca4d09a | Gleb Natapov | add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
|
1872 | 1ca4d09a | Gleb Natapov | add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
|
1873 | 1ca4d09a | Gleb Natapov | |
1874 | 2be37833 | Blue Swirl | return ret;
|
1875 | 8baf73ad | Gerd Hoffmann | } |
1876 | 8baf73ad | Gerd Hoffmann | |
1877 | 81a322d4 | Gerd Hoffmann | static int sysbus_fdc_init1(SysBusDevice *dev) |
1878 | 12a71a02 | Blue Swirl | { |
1879 | 5c02c033 | Blue Swirl | FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev); |
1880 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = &sys->state; |
1881 | 12a71a02 | Blue Swirl | int io;
|
1882 | 2be37833 | Blue Swirl | int ret;
|
1883 | 12a71a02 | Blue Swirl | |
1884 | 2507c12a | Alexander Graf | io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl, |
1885 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1886 | 8baf73ad | Gerd Hoffmann | sysbus_init_mmio(dev, 0x08, io);
|
1887 | 8baf73ad | Gerd Hoffmann | sysbus_init_irq(dev, &fdctrl->irq); |
1888 | 8baf73ad | Gerd Hoffmann | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
1889 | 99244fa1 | Gerd Hoffmann | fdctrl->dma_chann = -1;
|
1890 | 8baf73ad | Gerd Hoffmann | |
1891 | a64405d1 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, io, 2);
|
1892 | a64405d1 | Jan Kiszka | ret = fdctrl_init_common(fdctrl); |
1893 | 2be37833 | Blue Swirl | |
1894 | 2be37833 | Blue Swirl | return ret;
|
1895 | 12a71a02 | Blue Swirl | } |
1896 | 12a71a02 | Blue Swirl | |
1897 | 81a322d4 | Gerd Hoffmann | static int sun4m_fdc_init1(SysBusDevice *dev) |
1898 | 12a71a02 | Blue Swirl | { |
1899 | 5c02c033 | Blue Swirl | FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state); |
1900 | 12a71a02 | Blue Swirl | int io;
|
1901 | 12a71a02 | Blue Swirl | |
1902 | 12a71a02 | Blue Swirl | io = cpu_register_io_memory(fdctrl_mem_read_strict, |
1903 | 2507c12a | Alexander Graf | fdctrl_mem_write_strict, fdctrl, |
1904 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1905 | 8baf73ad | Gerd Hoffmann | sysbus_init_mmio(dev, 0x08, io);
|
1906 | 8baf73ad | Gerd Hoffmann | sysbus_init_irq(dev, &fdctrl->irq); |
1907 | 8baf73ad | Gerd Hoffmann | qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
1908 | 8baf73ad | Gerd Hoffmann | |
1909 | 8baf73ad | Gerd Hoffmann | fdctrl->sun4m = 1;
|
1910 | a64405d1 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, io, 2);
|
1911 | a64405d1 | Jan Kiszka | return fdctrl_init_common(fdctrl);
|
1912 | 12a71a02 | Blue Swirl | } |
1913 | f64ab228 | Blue Swirl | |
1914 | a64405d1 | Jan Kiszka | static const VMStateDescription vmstate_isa_fdc ={ |
1915 | a64405d1 | Jan Kiszka | .name = "fdc",
|
1916 | a64405d1 | Jan Kiszka | .version_id = 2,
|
1917 | a64405d1 | Jan Kiszka | .minimum_version_id = 2,
|
1918 | a64405d1 | Jan Kiszka | .fields = (VMStateField []) { |
1919 | a64405d1 | Jan Kiszka | VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
|
1920 | a64405d1 | Jan Kiszka | VMSTATE_END_OF_LIST() |
1921 | a64405d1 | Jan Kiszka | } |
1922 | a64405d1 | Jan Kiszka | }; |
1923 | a64405d1 | Jan Kiszka | |
1924 | 8baf73ad | Gerd Hoffmann | static ISADeviceInfo isa_fdc_info = {
|
1925 | 8baf73ad | Gerd Hoffmann | .init = isabus_fdc_init1, |
1926 | 8baf73ad | Gerd Hoffmann | .qdev.name = "isa-fdc",
|
1927 | 779206de | Gleb Natapov | .qdev.fw_name = "fdc",
|
1928 | 5c02c033 | Blue Swirl | .qdev.size = sizeof(FDCtrlISABus),
|
1929 | 39a51dfd | Markus Armbruster | .qdev.no_user = 1,
|
1930 | a64405d1 | Jan Kiszka | .qdev.vmsd = &vmstate_isa_fdc, |
1931 | 2be37833 | Blue Swirl | .qdev.reset = fdctrl_external_reset_isa, |
1932 | fd8014e1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
1933 | f8b6cc00 | Markus Armbruster | DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), |
1934 | f8b6cc00 | Markus Armbruster | DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), |
1935 | 1ca4d09a | Gleb Natapov | DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), |
1936 | 1ca4d09a | Gleb Natapov | DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), |
1937 | fd8014e1 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
1938 | fd8014e1 | Gerd Hoffmann | }, |
1939 | 8baf73ad | Gerd Hoffmann | }; |
1940 | 8baf73ad | Gerd Hoffmann | |
1941 | a64405d1 | Jan Kiszka | static const VMStateDescription vmstate_sysbus_fdc ={ |
1942 | a64405d1 | Jan Kiszka | .name = "fdc",
|
1943 | a64405d1 | Jan Kiszka | .version_id = 2,
|
1944 | a64405d1 | Jan Kiszka | .minimum_version_id = 2,
|
1945 | a64405d1 | Jan Kiszka | .fields = (VMStateField []) { |
1946 | a64405d1 | Jan Kiszka | VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
|
1947 | a64405d1 | Jan Kiszka | VMSTATE_END_OF_LIST() |
1948 | a64405d1 | Jan Kiszka | } |
1949 | a64405d1 | Jan Kiszka | }; |
1950 | a64405d1 | Jan Kiszka | |
1951 | 8baf73ad | Gerd Hoffmann | static SysBusDeviceInfo sysbus_fdc_info = {
|
1952 | 8baf73ad | Gerd Hoffmann | .init = sysbus_fdc_init1, |
1953 | 8baf73ad | Gerd Hoffmann | .qdev.name = "sysbus-fdc",
|
1954 | 5c02c033 | Blue Swirl | .qdev.size = sizeof(FDCtrlSysBus),
|
1955 | a64405d1 | Jan Kiszka | .qdev.vmsd = &vmstate_sysbus_fdc, |
1956 | 2be37833 | Blue Swirl | .qdev.reset = fdctrl_external_reset_sysbus, |
1957 | fd8014e1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
1958 | f8b6cc00 | Markus Armbruster | DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), |
1959 | f8b6cc00 | Markus Armbruster | DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), |
1960 | fd8014e1 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
1961 | fd8014e1 | Gerd Hoffmann | }, |
1962 | 12a71a02 | Blue Swirl | }; |
1963 | 12a71a02 | Blue Swirl | |
1964 | 12a71a02 | Blue Swirl | static SysBusDeviceInfo sun4m_fdc_info = {
|
1965 | 12a71a02 | Blue Swirl | .init = sun4m_fdc_init1, |
1966 | 12a71a02 | Blue Swirl | .qdev.name = "SUNW,fdtwo",
|
1967 | 5c02c033 | Blue Swirl | .qdev.size = sizeof(FDCtrlSysBus),
|
1968 | a64405d1 | Jan Kiszka | .qdev.vmsd = &vmstate_sysbus_fdc, |
1969 | 2be37833 | Blue Swirl | .qdev.reset = fdctrl_external_reset_sysbus, |
1970 | fd8014e1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
1971 | f8b6cc00 | Markus Armbruster | DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), |
1972 | fd8014e1 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
1973 | fd8014e1 | Gerd Hoffmann | }, |
1974 | f64ab228 | Blue Swirl | }; |
1975 | f64ab228 | Blue Swirl | |
1976 | f64ab228 | Blue Swirl | static void fdc_register_devices(void) |
1977 | f64ab228 | Blue Swirl | { |
1978 | 8baf73ad | Gerd Hoffmann | isa_qdev_register(&isa_fdc_info); |
1979 | 8baf73ad | Gerd Hoffmann | sysbus_register_withprop(&sysbus_fdc_info); |
1980 | 12a71a02 | Blue Swirl | sysbus_register_withprop(&sun4m_fdc_info); |
1981 | f64ab228 | Blue Swirl | } |
1982 | f64ab228 | Blue Swirl | |
1983 | f64ab228 | Blue Swirl | device_init(fdc_register_devices) |