Revision 0c90c52f
| b/hw/ppc_prep.c | ||
|---|---|---|
| 116 | 116 |
|
| 117 | 117 |
/* PCI intack register */ |
| 118 | 118 |
/* Read-only register (?) */ |
| 119 |
static void _PPC_intack_write (void *opaque,
|
|
| 120 |
target_phys_addr_t addr, uint32_t value)
|
|
| 119 |
static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
|
|
| 120 |
uint64_t value, unsigned size)
|
|
| 121 | 121 |
{
|
| 122 | 122 |
#if 0 |
| 123 |
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
|
| 123 |
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
|
|
| 124 | 124 |
value); |
| 125 | 125 |
#endif |
| 126 | 126 |
} |
| 127 | 127 |
|
| 128 |
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
|
| 128 |
static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr, |
|
| 129 |
unsigned size) |
|
| 129 | 130 |
{
|
| 130 | 131 |
uint32_t retval = 0; |
| 131 | 132 |
|
| ... | ... | |
| 139 | 140 |
return retval; |
| 140 | 141 |
} |
| 141 | 142 |
|
| 142 |
static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
|
| 143 |
{
|
|
| 144 |
return _PPC_intack_read(addr); |
|
| 145 |
} |
|
| 146 |
|
|
| 147 |
static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
|
| 148 |
{
|
|
| 149 |
return _PPC_intack_read(addr); |
|
| 150 |
} |
|
| 151 |
|
|
| 152 |
static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
|
| 153 |
{
|
|
| 154 |
return _PPC_intack_read(addr); |
|
| 155 |
} |
|
| 156 |
|
|
| 157 |
static CPUWriteMemoryFunc * const PPC_intack_write[] = {
|
|
| 158 |
&_PPC_intack_write, |
|
| 159 |
&_PPC_intack_write, |
|
| 160 |
&_PPC_intack_write, |
|
| 161 |
}; |
|
| 162 |
|
|
| 163 |
static CPUReadMemoryFunc * const PPC_intack_read[] = {
|
|
| 164 |
&PPC_intack_readb, |
|
| 165 |
&PPC_intack_readw, |
|
| 166 |
&PPC_intack_readl, |
|
| 143 |
static const MemoryRegionOps PPC_intack_ops = {
|
|
| 144 |
.read = PPC_intack_read, |
|
| 145 |
.write = PPC_intack_write, |
|
| 146 |
.endianness = DEVICE_LITTLE_ENDIAN, |
|
| 167 | 147 |
}; |
| 168 | 148 |
|
| 169 | 149 |
/* PowerPC control and status registers */ |
| ... | ... | |
| 244 | 224 |
return retval; |
| 245 | 225 |
} |
| 246 | 226 |
|
| 247 |
static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
|
|
| 248 |
&PPC_XCSR_writeb, |
|
| 249 |
&PPC_XCSR_writew, |
|
| 250 |
&PPC_XCSR_writel, |
|
| 227 |
static const MemoryRegionOps PPC_XCSR_ops = {
|
|
| 228 |
.old_mmio = {
|
|
| 229 |
.read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
|
|
| 230 |
.write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
|
|
| 231 |
}, |
|
| 232 |
.endianness = DEVICE_LITTLE_ENDIAN, |
|
| 251 | 233 |
}; |
| 252 | 234 |
|
| 253 |
static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
|
|
| 254 |
&PPC_XCSR_readb, |
|
| 255 |
&PPC_XCSR_readw, |
|
| 256 |
&PPC_XCSR_readl, |
|
| 257 |
}; |
|
| 258 | 235 |
#endif |
| 259 | 236 |
|
| 260 | 237 |
/* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
| ... | ... | |
| 503 | 480 |
return ret; |
| 504 | 481 |
} |
| 505 | 482 |
|
| 506 |
static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
|
|
| 507 |
&PPC_prep_io_writeb, |
|
| 508 |
&PPC_prep_io_writew, |
|
| 509 |
&PPC_prep_io_writel, |
|
| 510 |
}; |
|
| 511 |
|
|
| 512 |
static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
|
|
| 513 |
&PPC_prep_io_readb, |
|
| 514 |
&PPC_prep_io_readw, |
|
| 515 |
&PPC_prep_io_readl, |
|
| 483 |
static const MemoryRegionOps PPC_prep_io_ops = {
|
|
| 484 |
.old_mmio = {
|
|
| 485 |
.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
|
|
| 486 |
.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
|
|
| 487 |
}, |
|
| 488 |
.endianness = DEVICE_LITTLE_ENDIAN, |
|
| 516 | 489 |
}; |
| 517 | 490 |
|
| 518 | 491 |
#define NVRAM_SIZE 0x2000 |
| ... | ... | |
| 534 | 507 |
const char *initrd_filename, |
| 535 | 508 |
const char *cpu_model) |
| 536 | 509 |
{
|
| 510 |
MemoryRegion *sysmem = get_system_memory(); |
|
| 537 | 511 |
CPUState *env = NULL; |
| 538 | 512 |
char *filename; |
| 539 | 513 |
nvram_t nvram; |
| 540 | 514 |
M48t59State *m48t59; |
| 541 |
int PPC_io_memory; |
|
| 515 |
MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); |
|
| 516 |
MemoryRegion *intack = g_new(MemoryRegion, 1); |
|
| 517 |
#if 0 |
|
| 518 |
MemoryRegion *xcsr = g_new(MemoryRegion, 1); |
|
| 519 |
#endif |
|
| 542 | 520 |
int linux_boot, i, nb_nics1, bios_size; |
| 543 |
ram_addr_t ram_offset, bios_offset; |
|
| 521 |
MemoryRegion *ram = g_new(MemoryRegion, 1); |
|
| 522 |
MemoryRegion *bios = g_new(MemoryRegion, 1); |
|
| 544 | 523 |
uint32_t kernel_base, initrd_base; |
| 545 | 524 |
long kernel_size, initrd_size; |
| 546 | 525 |
PCIBus *pci_bus; |
| ... | ... | |
| 574 | 553 |
} |
| 575 | 554 |
|
| 576 | 555 |
/* allocate RAM */ |
| 577 |
ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size);
|
|
| 578 |
cpu_register_physical_memory(0, ram_size, ram_offset);
|
|
| 556 |
memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
|
|
| 557 |
memory_region_add_subregion(sysmem, 0, ram);
|
|
| 579 | 558 |
|
| 580 | 559 |
/* allocate and load BIOS */ |
| 581 |
bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE);
|
|
| 560 |
memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE);
|
|
| 582 | 561 |
if (bios_name == NULL) |
| 583 | 562 |
bios_name = BIOS_FILENAME; |
| 584 | 563 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| ... | ... | |
| 591 | 570 |
target_phys_addr_t bios_addr; |
| 592 | 571 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 593 | 572 |
bios_addr = (uint32_t)(-bios_size); |
| 594 |
cpu_register_physical_memory(bios_addr, bios_size,
|
|
| 595 |
bios_offset | IO_MEM_ROM);
|
|
| 573 |
memory_region_set_readonly(bios, true);
|
|
| 574 |
memory_region_add_subregion(sysmem, bios_addr, bios);
|
|
| 596 | 575 |
bios_size = load_image_targphys(filename, bios_addr, bios_size); |
| 597 | 576 |
} |
| 598 | 577 |
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
| ... | ... | |
| 655 | 634 |
isa_bus_irqs(i8259); |
| 656 | 635 |
// pci_bus = i440fx_init(); |
| 657 | 636 |
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */ |
| 658 |
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
|
| 659 |
PPC_prep_io_write, sysctrl, |
|
| 660 |
DEVICE_LITTLE_ENDIAN); |
|
| 661 |
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
|
| 637 |
memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, |
|
| 638 |
"ppc-io", 0x00800000); |
|
| 639 |
memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); |
|
| 662 | 640 |
|
| 663 | 641 |
/* init basic PC hardware */ |
| 664 | 642 |
pci_vga_init(pci_bus); |
| ... | ... | |
| 713 | 691 |
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
| 714 | 692 |
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
| 715 | 693 |
/* PCI intack location */ |
| 716 |
PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
|
| 717 |
PPC_intack_write, NULL, |
|
| 718 |
DEVICE_LITTLE_ENDIAN); |
|
| 719 |
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
|
| 694 |
memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4); |
|
| 695 |
memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack); |
|
| 720 | 696 |
/* PowerPC control and status register group */ |
| 721 | 697 |
#if 0 |
| 722 |
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, |
|
| 723 |
NULL, DEVICE_LITTLE_ENDIAN); |
|
| 724 |
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
|
| 698 |
memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); |
|
| 699 |
memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); |
|
| 725 | 700 |
#endif |
| 726 | 701 |
|
| 727 | 702 |
if (usb_enabled) {
|
Also available in: Unified diff