Revision 0cb892aa

b/target-i386/machine.c
21 21
    }
22 22
};
23 23

  
24
static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
25
{
26
    vmstate_save_state(f, &vmstate_segment, dt);
24
#define VMSTATE_SEGMENT(_field, _state) {                            \
25
    .name       = (stringify(_field)),                               \
26
    .size       = sizeof(SegmentCache),                              \
27
    .vmsd       = &vmstate_segment,                                  \
28
    .flags      = VMS_STRUCT,                                        \
29
    .offset     = offsetof(_state, _field)                           \
30
            + type_check(SegmentCache,typeof_field(_state, _field))  \
27 31
}
28 32

  
29
static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
30
{
31
    vmstate_load_state(f, &vmstate_segment, dt, vmstate_segment.version_id);
32
}
33
#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
34
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
33 35

  
34 36
static const VMStateDescription vmstate_xmm_reg = {
35 37
    .name = "xmm_reg",
......
43 45
    }
44 46
};
45 47

  
46
static void cpu_put_xmm_reg(QEMUFile *f, XMMReg *xmm_reg)
47
{
48
    vmstate_save_state(f, &vmstate_xmm_reg, xmm_reg);
49
}
50

  
51
static void cpu_get_xmm_reg(QEMUFile *f, XMMReg *xmm_reg)
52
{
53
    vmstate_load_state(f, &vmstate_xmm_reg, xmm_reg, vmstate_xmm_reg.version_id);
54
}
48
#define VMSTATE_XMM_REGS(_field, _state, _n)                         \
49
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
55 50

  
56 51
static const VMStateDescription vmstate_mtrr_var = {
57 52
    .name = "mtrr_var",
......
65 60
    }
66 61
};
67 62

  
68
static void cpu_put_mtrr_var(QEMUFile *f, MTRRVar *mtrr_var)
69
{
70
    vmstate_save_state(f, &vmstate_mtrr_var, mtrr_var);
71
}
63
#define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
64
    VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
72 65

  
73
static void cpu_get_mtrr_var(QEMUFile *f, MTRRVar *mtrr_var)
66
static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
74 67
{
75
    vmstate_load_state(f, &vmstate_mtrr_var, mtrr_var, vmstate_mtrr_var.version_id);
68
    fprintf(stderr, "call put_fpreg() with invalid arguments\n");
69
    exit(0);
76 70
}
77 71

  
78 72
#ifdef USE_X86LDOUBLE
......
122 116
    qemu_put_be16s(f, &exp);
123 117
}
124 118

  
119
const VMStateInfo vmstate_fpreg = {
120
    .name = "fpreg",
121
    .get  = get_fpreg,
122
    .put  = put_fpreg,
123
};
124

  
125 125
static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
126 126
{
127 127
    union x86_longdouble *p = opaque;
......
133 133
    return 0;
134 134
}
135 135

  
136
const VMStateInfo vmstate_fpreg_1_mmx = {
137
    .name = "fpreg_1_mmx",
138
    .get  = get_fpreg_1_mmx,
139
    .put  = put_fpreg_error,
140
};
141

  
136 142
static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
137 143
{
138 144
    union x86_longdouble *p = opaque;
......
143 149
    return 0;
144 150
}
145 151

  
152
const VMStateInfo vmstate_fpreg_1_no_mmx = {
153
    .name = "fpreg_1_no_mmx",
154
    .get  = get_fpreg_1_no_mmx,
155
    .put  = put_fpreg_error,
156
};
157

  
158
static bool fpregs_is_0(void *opaque, int version_id)
159
{
160
    CPUState *env = opaque;
161

  
162
    return (env->fpregs_format_vmstate == 0);
163
}
164

  
165
static bool fpregs_is_1_mmx(void *opaque, int version_id)
166
{
167
    CPUState *env = opaque;
168
    int guess_mmx;
169

  
170
    guess_mmx = ((env->fptag_vmstate == 0xff) &&
171
                 (env->fpus_vmstate & 0x3800) == 0);
172
    return (guess_mmx && (env->fpregs_format_vmstate == 1));
173
}
174

  
175
static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
176
{
177
    CPUState *env = opaque;
178
    int guess_mmx;
179

  
180
    guess_mmx = ((env->fptag_vmstate == 0xff) &&
181
                 (env->fpus_vmstate & 0x3800) == 0);
182
    return (!guess_mmx && (env->fpregs_format_vmstate == 1));
183
}
184

  
185
#define VMSTATE_FP_REGS(_field, _state, _n)                               \
186
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
187
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
188
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
189

  
146 190
#else
147 191
static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
148 192
{
......
162 206
    qemu_put_be64s(f, &fp_reg->mmx.MMX_Q(0));
163 207
}
164 208

  
209
const VMStateInfo vmstate_fpreg = {
210
    .name = "fpreg",
211
    .get  = get_fpreg,
212
    .put  = put_fpreg,
213
};
214

  
165 215
static int get_fpreg_0_mmx(QEMUFile *f, void *opaque, size_t size)
166 216
{
167 217
    FPReg *fp_reg = opaque;
......
174 224
    return 0;
175 225
}
176 226

  
227
const VMStateInfo vmstate_fpreg_0_mmx = {
228
    .name = "fpreg_0_mmx",
229
    .get  = get_fpreg_0_mmx,
230
    .put  = put_fpreg_error,
231
};
232

  
177 233
static int get_fpreg_0_no_mmx(QEMUFile *f, void *opaque, size_t size)
178 234
{
179 235
    FPReg *fp_reg = opaque;
......
187 243
    return 0;
188 244
}
189 245

  
246
const VMStateInfo vmstate_fpreg_0_no_mmx = {
247
    .name = "fpreg_0_no_mmx",
248
    .get  = get_fpreg_0_no_mmx,
249
    .put  = put_fpreg_error,
250
};
251

  
252
static bool fpregs_is_1(void *opaque, int version_id)
253
{
254
    CPUState *env = opaque;
255

  
256
    return env->fpregs_format_vmstate == 1;
257
}
258

  
259
static bool fpregs_is_0_mmx(void *opaque, int version_id)
260
{
261
    CPUState *env = opaque;
262
    int guess_mmx;
263

  
264
    guess_mmx = ((env->fptag_vmstate == 0xff) &&
265
                 (env->fpus_vmstate & 0x3800) == 0);
266
    return guess_mmx && env->fpregs_format_vmstate == 0;
267
}
268

  
269
static bool fpregs_is_0_no_mmx(void *opaque, int version_id)
270
{
271
    CPUState *env = opaque;
272
    int guess_mmx;
273

  
274
    guess_mmx = ((env->fptag_vmstate == 0xff) &&
275
                 (env->fpus_vmstate & 0x3800) == 0);
276
    return !guess_mmx && env->fpregs_format_vmstate == 0;
277
}
278

  
279
#define VMSTATE_FP_REGS(_field, _state, _n)                               \
280
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1, vmstate_fpreg, FPReg), \
281
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_mmx, vmstate_fpreg_0_mmx, FPReg), \
282
    VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0_no_mmx, vmstate_fpreg_0_no_mmx, FPReg)
283

  
190 284
#endif /* USE_X86LDOUBLE */
191 285

  
286
static bool version_is_5(void *opaque, int version_id)
287
{
288
    return version_id == 5;
289
}
290

  
291
#ifdef TARGET_X86_64
292
static bool less_than_7(void *opaque, int version_id)
293
{
294
    return version_id < 7;
295
}
296

  
297
static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
298
{
299
    uint64_t *v = pv;
300
    *v = qemu_get_be32(f);
301
    return 0;
302
}
303

  
304
static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
305
{
306
    uint64_t *v = pv;
307
    qemu_put_be32(f, *v);
308
}
309

  
310
const VMStateInfo vmstate_hack_uint64_as_uint32 = {
311
    .name = "uint64_as_uint32",
312
    .get  = get_uint64_as_uint32,
313
    .put  = put_uint64_as_uint32,
314
};
315

  
316
#define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
317
    VMSTATE_SINGLE_TEST(_f, _s, _t, vmstate_hack_uint64_as_uint32, uint64_t)
318
#endif
319

  
192 320
static void cpu_pre_save(void *opaque)
193 321
{
194 322
    CPUState *env = opaque;
......
221 349
    }
222 350
}
223 351

  
224
void cpu_save(QEMUFile *f, void *opaque)
225
{
226
    CPUState *env = opaque;
227
    int i;
228

  
229
    cpu_pre_save(opaque);
230

  
231
    for(i = 0; i < CPU_NB_REGS; i++)
232
        qemu_put_betls(f, &env->regs[i]);
233
    qemu_put_betls(f, &env->eip);
234
    qemu_put_betls(f, &env->eflags);
235
    qemu_put_be32s(f, &env->hflags);
236

  
237
    /* FPU */
238
    qemu_put_be16s(f, &env->fpuc);
239
    qemu_put_be16s(f, &env->fpus_vmstate);
240
    qemu_put_be16s(f, &env->fptag_vmstate);
241

  
242
    qemu_put_be16s(f, &env->fpregs_format_vmstate);
243

  
244
    for(i = 0; i < 8; i++) {
245
        put_fpreg(f, &env->fpregs[i], 0);
246
    }
247

  
248
    for(i = 0; i < 6; i++)
249
        cpu_put_seg(f, &env->segs[i]);
250
    cpu_put_seg(f, &env->ldt);
251
    cpu_put_seg(f, &env->tr);
252
    cpu_put_seg(f, &env->gdt);
253
    cpu_put_seg(f, &env->idt);
254

  
255
    qemu_put_be32s(f, &env->sysenter_cs);
256
    qemu_put_betls(f, &env->sysenter_esp);
257
    qemu_put_betls(f, &env->sysenter_eip);
258

  
259
    qemu_put_betls(f, &env->cr[0]);
260
    qemu_put_betls(f, &env->cr[2]);
261
    qemu_put_betls(f, &env->cr[3]);
262
    qemu_put_betls(f, &env->cr[4]);
263

  
264
    for(i = 0; i < 8; i++)
265
        qemu_put_betls(f, &env->dr[i]);
266

  
267
    /* MMU */
268
    qemu_put_sbe32s(f, &env->a20_mask);
269

  
270
    /* XMM */
271
    qemu_put_be32s(f, &env->mxcsr);
272
    for(i = 0; i < CPU_NB_REGS; i++) {
273
        cpu_put_xmm_reg(f, &env->xmm_regs[i]);
274
    }
275

  
276
#ifdef TARGET_X86_64
277
    qemu_put_be64s(f, &env->efer);
278
    qemu_put_be64s(f, &env->star);
279
    qemu_put_be64s(f, &env->lstar);
280
    qemu_put_be64s(f, &env->cstar);
281
    qemu_put_be64s(f, &env->fmask);
282
    qemu_put_be64s(f, &env->kernelgsbase);
283
#endif
284
    qemu_put_be32s(f, &env->smbase);
285

  
286
    qemu_put_be64s(f, &env->pat);
287
    qemu_put_be32s(f, &env->hflags2);
288
    
289
    qemu_put_be64s(f, &env->vm_hsave);
290
    qemu_put_be64s(f, &env->vm_vmcb);
291
    qemu_put_be64s(f, &env->tsc_offset);
292
    qemu_put_be64s(f, &env->intercept);
293
    qemu_put_be16s(f, &env->intercept_cr_read);
294
    qemu_put_be16s(f, &env->intercept_cr_write);
295
    qemu_put_be16s(f, &env->intercept_dr_read);
296
    qemu_put_be16s(f, &env->intercept_dr_write);
297
    qemu_put_be32s(f, &env->intercept_exceptions);
298
    qemu_put_8s(f, &env->v_tpr);
299

  
300
    /* MTRRs */
301
    for(i = 0; i < 11; i++)
302
        qemu_put_be64s(f, &env->mtrr_fixed[i]);
303
    qemu_put_be64s(f, &env->mtrr_deftype);
304
    for(i = 0; i < 8; i++) {
305
        cpu_put_mtrr_var(f, &env->mtrr_var[i]);
306
    }
307

  
308
    /* KVM-related states */
309

  
310
    qemu_put_sbe32s(f, &env->pending_irq_vmstate);
311
    qemu_put_be32s(f, &env->mp_state);
312
    qemu_put_be64s(f, &env->tsc);
313

  
314
    /* MCE */
315
    qemu_put_be64s(f, &env->mcg_cap);
316
    qemu_put_be64s(f, &env->mcg_status);
317
    qemu_put_be64s(f, &env->mcg_ctl);
318
    for (i = 0; i < MCE_BANKS_DEF * 4; i++) {
319
        qemu_put_be64s(f, &env->mce_banks[i]);
320
    }
321
    qemu_put_be64s(f, &env->tsc_aux);
322
 }
323

  
324 352
static int cpu_pre_load(void *opaque)
325 353
{
326 354
    CPUState *env = opaque;
......
358 386
    return cpu_post_load(env, version_id);
359 387
}
360 388

  
361
int cpu_load(QEMUFile *f, void *opaque, int version_id)
362
{
363
    CPUState *env = opaque;
364
    int i, guess_mmx;
365

  
366
    cpu_pre_load(env);
367

  
368
    if (version_id < 3 || version_id > CPU_SAVE_VERSION)
369
        return -EINVAL;
370
    for(i = 0; i < CPU_NB_REGS; i++)
371
        qemu_get_betls(f, &env->regs[i]);
372
    qemu_get_betls(f, &env->eip);
373
    qemu_get_betls(f, &env->eflags);
374
    qemu_get_be32s(f, &env->hflags);
375

  
376
    qemu_get_be16s(f, &env->fpuc);
377
    qemu_get_be16s(f, &env->fpus_vmstate);
378
    qemu_get_be16s(f, &env->fptag_vmstate);
379
    qemu_get_be16s(f, &env->fpregs_format_vmstate);
380

  
381
    guess_mmx = ((env->fptag_vmstate == 0xff) && (env->fpus_vmstate & 0x3800) == 0);
382

  
383
    for(i = 0; i < 8; i++) {
384
#ifdef USE_X86LDOUBLE
385
        switch(env->fpregs_format_vmstate) {
386
        case 0:
387
            get_fpreg(f, &env->fpregs[i], 0);
388
            break;
389
        case 1:
390
            if (guess_mmx) {
391
                get_fpreg_1_mmx(f, &env->fpregs[i], 0);
392
            } else {
393
                get_fpreg_1_no_mmx(f, &env->fpregs[i], 0);
394
            }
395
            break;
396
        default:
397
            return -EINVAL;
398
        }
389
const VMStateDescription vmstate_cpu = {
390
    .name = "cpu",
391
    .version_id = CPU_SAVE_VERSION,
392
    .minimum_version_id = 3,
393
    .minimum_version_id_old = 3,
394
    .pre_save = cpu_pre_save,
395
    .pre_load = cpu_pre_load,
396
    .post_load = cpu_post_load,
397
    .fields      = (VMStateField []) {
398
        VMSTATE_UINTTL_ARRAY(regs, CPUState, CPU_NB_REGS),
399
        VMSTATE_UINTTL(eip, CPUState),
400
        VMSTATE_UINTTL(eflags, CPUState),
401
        VMSTATE_UINT32(hflags, CPUState),
402
        /* FPU */
403
        VMSTATE_UINT16(fpuc, CPUState),
404
        VMSTATE_UINT16(fpus_vmstate, CPUState),
405
        VMSTATE_UINT16(fptag_vmstate, CPUState),
406
        VMSTATE_UINT16(fpregs_format_vmstate, CPUState),
407
        VMSTATE_FP_REGS(fpregs, CPUState, 8),
408

  
409
        VMSTATE_SEGMENT_ARRAY(segs, CPUState, 6),
410
        VMSTATE_SEGMENT(ldt, CPUState),
411
        VMSTATE_SEGMENT(tr, CPUState),
412
        VMSTATE_SEGMENT(gdt, CPUState),
413
        VMSTATE_SEGMENT(idt, CPUState),
414

  
415
        VMSTATE_UINT32(sysenter_cs, CPUState),
416
#ifdef TARGET_X86_64
417
        /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
418
        VMSTATE_HACK_UINT32(sysenter_esp, CPUState, less_than_7),
419
        VMSTATE_HACK_UINT32(sysenter_eip, CPUState, less_than_7),
420
        VMSTATE_UINTTL_V(sysenter_esp, CPUState, 7),
421
        VMSTATE_UINTTL_V(sysenter_eip, CPUState, 7),
399 422
#else
400
        switch(env->fpregs_format_vmstate) {
401
        case 0:
402
            if (guess_mmx) {
403
                get_fpreg_0_mmx(f, &env->fpregs[i], 0);
404
            } else {
405
                get_fpreg_0_no_mmx(f, &env->fpregs[i], 0);
406
            }
407
            break;
408
        case 1:
409
            get_fpreg(f, &env->fpregs[i], 0);
410
            break;
411
        default:
412
            return -EINVAL;
413
        }
423
        VMSTATE_UINTTL(sysenter_esp, CPUState),
424
        VMSTATE_UINTTL(sysenter_eip, CPUState),
414 425
#endif
415
    }
416

  
417
    for(i = 0; i < 6; i++)
418
        cpu_get_seg(f, &env->segs[i]);
419
    cpu_get_seg(f, &env->ldt);
420
    cpu_get_seg(f, &env->tr);
421
    cpu_get_seg(f, &env->gdt);
422
    cpu_get_seg(f, &env->idt);
423

  
424
    qemu_get_be32s(f, &env->sysenter_cs);
425
    if (version_id >= 7) {
426
        qemu_get_betls(f, &env->sysenter_esp);
427
        qemu_get_betls(f, &env->sysenter_eip);
428
    } else {
429
        env->sysenter_esp = qemu_get_be32(f);
430
        env->sysenter_eip = qemu_get_be32(f);
431
    }
432

  
433
    qemu_get_betls(f, &env->cr[0]);
434
    qemu_get_betls(f, &env->cr[2]);
435
    qemu_get_betls(f, &env->cr[3]);
436
    qemu_get_betls(f, &env->cr[4]);
437 426

  
438
    for(i = 0; i < 8; i++)
439
        qemu_get_betls(f, &env->dr[i]);
440

  
441
    qemu_get_sbe32s(f, &env->a20_mask);
442

  
443
    qemu_get_be32s(f, &env->mxcsr);
444
    for(i = 0; i < CPU_NB_REGS; i++) {
445
        cpu_get_xmm_reg(f, &env->xmm_regs[i]);
446
    }
427
        VMSTATE_UINTTL(cr[0], CPUState),
428
        VMSTATE_UINTTL(cr[2], CPUState),
429
        VMSTATE_UINTTL(cr[3], CPUState),
430
        VMSTATE_UINTTL(cr[4], CPUState),
431
        VMSTATE_UINTTL_ARRAY(dr, CPUState, 8),
432
        /* MMU */
433
        VMSTATE_INT32(a20_mask, CPUState),
434
        /* XMM */
435
        VMSTATE_UINT32(mxcsr, CPUState),
436
        VMSTATE_XMM_REGS(xmm_regs, CPUState, CPU_NB_REGS),
447 437

  
448 438
#ifdef TARGET_X86_64
449
    qemu_get_be64s(f, &env->efer);
450
    qemu_get_be64s(f, &env->star);
451
    qemu_get_be64s(f, &env->lstar);
452
    qemu_get_be64s(f, &env->cstar);
453
    qemu_get_be64s(f, &env->fmask);
454
    qemu_get_be64s(f, &env->kernelgsbase);
439
        VMSTATE_UINT64(efer, CPUState),
440
        VMSTATE_UINT64(star, CPUState),
441
        VMSTATE_UINT64(lstar, CPUState),
442
        VMSTATE_UINT64(cstar, CPUState),
443
        VMSTATE_UINT64(fmask, CPUState),
444
        VMSTATE_UINT64(kernelgsbase, CPUState),
455 445
#endif
456
    if (version_id >= 4) {
457
        qemu_get_be32s(f, &env->smbase);
458
    }
459
    if (version_id >= 5) {
460
        qemu_get_be64s(f, &env->pat);
461
        qemu_get_be32s(f, &env->hflags2);
462
        if (version_id < 6)
463
            qemu_get_be32s(f, &env->halted);
464

  
465
        qemu_get_be64s(f, &env->vm_hsave);
466
        qemu_get_be64s(f, &env->vm_vmcb);
467
        qemu_get_be64s(f, &env->tsc_offset);
468
        qemu_get_be64s(f, &env->intercept);
469
        qemu_get_be16s(f, &env->intercept_cr_read);
470
        qemu_get_be16s(f, &env->intercept_cr_write);
471
        qemu_get_be16s(f, &env->intercept_dr_read);
472
        qemu_get_be16s(f, &env->intercept_dr_write);
473
        qemu_get_be32s(f, &env->intercept_exceptions);
474
        qemu_get_8s(f, &env->v_tpr);
475
    }
476

  
477
    if (version_id >= 8) {
446
        VMSTATE_UINT32_V(smbase, CPUState, 4),
447

  
448
        VMSTATE_UINT64_V(pat, CPUState, 5),
449
        VMSTATE_UINT32_V(hflags2, CPUState, 5),
450

  
451
        VMSTATE_UINT32_TEST(halted, CPUState, version_is_5),
452
        VMSTATE_UINT64_V(vm_hsave, CPUState, 5),
453
        VMSTATE_UINT64_V(vm_vmcb, CPUState, 5),
454
        VMSTATE_UINT64_V(tsc_offset, CPUState, 5),
455
        VMSTATE_UINT64_V(intercept, CPUState, 5),
456
        VMSTATE_UINT16_V(intercept_cr_read, CPUState, 5),
457
        VMSTATE_UINT16_V(intercept_cr_write, CPUState, 5),
458
        VMSTATE_UINT16_V(intercept_dr_read, CPUState, 5),
459
        VMSTATE_UINT16_V(intercept_dr_write, CPUState, 5),
460
        VMSTATE_UINT32_V(intercept_exceptions, CPUState, 5),
461
        VMSTATE_UINT8_V(v_tpr, CPUState, 5),
478 462
        /* MTRRs */
479
        for(i = 0; i < 11; i++)
480
            qemu_get_be64s(f, &env->mtrr_fixed[i]);
481
        qemu_get_be64s(f, &env->mtrr_deftype);
482
        for(i = 0; i < 8; i++) {
483
            cpu_get_mtrr_var(f, &env->mtrr_var[i]);
484
        }
485
    }
486

  
487
    if (version_id >= 9) {
488
        qemu_get_sbe32s(f, &env->pending_irq_vmstate);
489
        qemu_get_be32s(f, &env->mp_state);
490
        qemu_get_be64s(f, &env->tsc);
491
    }
492

  
493
    if (version_id >= 10) {
494
        qemu_get_be64s(f, &env->mcg_cap);
495
        qemu_get_be64s(f, &env->mcg_status);
496
        qemu_get_be64s(f, &env->mcg_ctl);
497
        for (i = 0; i < MCE_BANKS_DEF * 4; i++) {
498
            qemu_get_be64s(f, &env->mce_banks[i]);
499
        }
463
        VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUState, 11, 8),
464
        VMSTATE_UINT64_V(mtrr_deftype, CPUState, 8),
465
        VMSTATE_MTRR_VARS(mtrr_var, CPUState, 8, 8),
466
        /* KVM-related states */
467
        VMSTATE_INT32_V(pending_irq_vmstate, CPUState, 9),
468
        VMSTATE_UINT32_V(mp_state, CPUState, 9),
469
        VMSTATE_UINT64_V(tsc, CPUState, 9),
470
        /* MCE */
471
        VMSTATE_UINT64_V(mcg_cap, CPUState, 10),
472
        VMSTATE_UINT64_V(mcg_status, CPUState, 10),
473
        VMSTATE_UINT64_V(mcg_ctl, CPUState, 10),
474
        VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10),
475
        /* rdtscp */
476
        VMSTATE_UINT64_V(tsc_aux, CPUState, 11),
477
        VMSTATE_END_OF_LIST()
500 478
    }
479
};
501 480

  
502
    if (version_id >= 11) {
503
        qemu_get_be64s(f, &env->tsc_aux);
504
    }
481
void cpu_save(QEMUFile *f, void *opaque)
482
{
483
    vmstate_save_state(f, &vmstate_cpu, opaque);
484
}
505 485

  
506
    tlb_flush(env, 1);
507
    return 0;
486
int cpu_load(QEMUFile *f, void *opaque, int version_id)
487
{
488
    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
508 489
}

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