root / hw / xio3130_downstream.c @ 0cdd3d14
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1 | 48ebf2f9 | Isaku Yamahata | /*
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2 | 48ebf2f9 | Isaku Yamahata | * x3130_downstream.c
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3 | 48ebf2f9 | Isaku Yamahata | * TI X3130 pci express downstream port switch
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4 | 48ebf2f9 | Isaku Yamahata | *
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5 | 48ebf2f9 | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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6 | 48ebf2f9 | Isaku Yamahata | * VA Linux Systems Japan K.K.
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7 | 48ebf2f9 | Isaku Yamahata | *
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8 | 48ebf2f9 | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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9 | 48ebf2f9 | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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10 | 48ebf2f9 | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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11 | 48ebf2f9 | Isaku Yamahata | * (at your option) any later version.
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12 | 48ebf2f9 | Isaku Yamahata | *
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13 | 48ebf2f9 | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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14 | 48ebf2f9 | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 48ebf2f9 | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 48ebf2f9 | Isaku Yamahata | * GNU General Public License for more details.
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17 | 48ebf2f9 | Isaku Yamahata | *
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18 | 48ebf2f9 | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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19 | 48ebf2f9 | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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20 | 48ebf2f9 | Isaku Yamahata | */
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21 | 48ebf2f9 | Isaku Yamahata | |
22 | 48ebf2f9 | Isaku Yamahata | #include "pci_ids.h" |
23 | 48ebf2f9 | Isaku Yamahata | #include "msi.h" |
24 | 48ebf2f9 | Isaku Yamahata | #include "pcie.h" |
25 | 48ebf2f9 | Isaku Yamahata | #include "xio3130_downstream.h" |
26 | 48ebf2f9 | Isaku Yamahata | |
27 | 48ebf2f9 | Isaku Yamahata | #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ |
28 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_REVISION 0x1 |
29 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_OFFSET 0x70 |
30 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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31 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_NR_VECTOR 1 |
32 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_OFFSET 0x80 |
33 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_SVID 0 |
34 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_SSID 0 |
35 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_EXP_OFFSET 0x90 |
36 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_AER_OFFSET 0x100 |
37 | 48ebf2f9 | Isaku Yamahata | |
38 | 48ebf2f9 | Isaku Yamahata | static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, |
39 | 48ebf2f9 | Isaku Yamahata | uint32_t val, int len)
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40 | 48ebf2f9 | Isaku Yamahata | { |
41 | 48ebf2f9 | Isaku Yamahata | pci_bridge_write_config(d, address, val, len); |
42 | 48ebf2f9 | Isaku Yamahata | pcie_cap_flr_write_config(d, address, val, len); |
43 | 6bde6aaa | Michael S. Tsirkin | pcie_cap_slot_write_config(d, address, val, len); |
44 | 48ebf2f9 | Isaku Yamahata | msi_write_config(d, address, val, len); |
45 | 09b926d4 | Isaku Yamahata | pcie_aer_write_config(d, address, val, len); |
46 | 48ebf2f9 | Isaku Yamahata | } |
47 | 48ebf2f9 | Isaku Yamahata | |
48 | 48ebf2f9 | Isaku Yamahata | static void xio3130_downstream_reset(DeviceState *qdev) |
49 | 48ebf2f9 | Isaku Yamahata | { |
50 | 40021f08 | Anthony Liguori | PCIDevice *d = PCI_DEVICE(qdev); |
51 | 48ebf2f9 | Isaku Yamahata | msi_reset(d); |
52 | 48ebf2f9 | Isaku Yamahata | pcie_cap_deverr_reset(d); |
53 | 48ebf2f9 | Isaku Yamahata | pcie_cap_slot_reset(d); |
54 | 48ebf2f9 | Isaku Yamahata | pcie_cap_ari_reset(d); |
55 | 48ebf2f9 | Isaku Yamahata | pci_bridge_reset(qdev); |
56 | 48ebf2f9 | Isaku Yamahata | } |
57 | 48ebf2f9 | Isaku Yamahata | |
58 | 48ebf2f9 | Isaku Yamahata | static int xio3130_downstream_initfn(PCIDevice *d) |
59 | 48ebf2f9 | Isaku Yamahata | { |
60 | 48ebf2f9 | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
61 | 48ebf2f9 | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
62 | 48ebf2f9 | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
63 | 48ebf2f9 | Isaku Yamahata | int rc;
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64 | 09b926d4 | Isaku Yamahata | int tmp;
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65 | 48ebf2f9 | Isaku Yamahata | |
66 | 48ebf2f9 | Isaku Yamahata | rc = pci_bridge_initfn(d); |
67 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
68 | 48ebf2f9 | Isaku Yamahata | return rc;
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69 | 48ebf2f9 | Isaku Yamahata | } |
70 | 48ebf2f9 | Isaku Yamahata | |
71 | 48ebf2f9 | Isaku Yamahata | pcie_port_init_reg(d); |
72 | 48ebf2f9 | Isaku Yamahata | |
73 | 48ebf2f9 | Isaku Yamahata | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, |
74 | 48ebf2f9 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
75 | 48ebf2f9 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
76 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
77 | 09b926d4 | Isaku Yamahata | goto err_bridge;
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78 | 48ebf2f9 | Isaku Yamahata | } |
79 | 48ebf2f9 | Isaku Yamahata | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
80 | 48ebf2f9 | Isaku Yamahata | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
81 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
82 | 09b926d4 | Isaku Yamahata | goto err_bridge;
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83 | 48ebf2f9 | Isaku Yamahata | } |
84 | 48ebf2f9 | Isaku Yamahata | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, |
85 | 48ebf2f9 | Isaku Yamahata | p->port); |
86 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
87 | 09b926d4 | Isaku Yamahata | goto err_msi;
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88 | 48ebf2f9 | Isaku Yamahata | } |
89 | 0ead87c8 | Isaku Yamahata | pcie_cap_flr_init(d); |
90 | 48ebf2f9 | Isaku Yamahata | pcie_cap_deverr_init(d); |
91 | 48ebf2f9 | Isaku Yamahata | pcie_cap_slot_init(d, s->slot); |
92 | 48ebf2f9 | Isaku Yamahata | pcie_chassis_create(s->chassis); |
93 | 48ebf2f9 | Isaku Yamahata | rc = pcie_chassis_add_slot(s); |
94 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
95 | 09b926d4 | Isaku Yamahata | goto err_pcie_cap;
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96 | 48ebf2f9 | Isaku Yamahata | } |
97 | 48ebf2f9 | Isaku Yamahata | pcie_cap_ari_init(d); |
98 | 09b926d4 | Isaku Yamahata | rc = pcie_aer_init(d, XIO3130_AER_OFFSET); |
99 | 09b926d4 | Isaku Yamahata | if (rc < 0) { |
100 | 09b926d4 | Isaku Yamahata | goto err;
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101 | 09b926d4 | Isaku Yamahata | } |
102 | 48ebf2f9 | Isaku Yamahata | |
103 | 48ebf2f9 | Isaku Yamahata | return 0; |
104 | 09b926d4 | Isaku Yamahata | |
105 | 09b926d4 | Isaku Yamahata | err:
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106 | 09b926d4 | Isaku Yamahata | pcie_chassis_del_slot(s); |
107 | 09b926d4 | Isaku Yamahata | err_pcie_cap:
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108 | 09b926d4 | Isaku Yamahata | pcie_cap_exit(d); |
109 | 09b926d4 | Isaku Yamahata | err_msi:
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110 | 09b926d4 | Isaku Yamahata | msi_uninit(d); |
111 | 09b926d4 | Isaku Yamahata | err_bridge:
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112 | 09b926d4 | Isaku Yamahata | tmp = pci_bridge_exitfn(d); |
113 | 09b926d4 | Isaku Yamahata | assert(!tmp); |
114 | 09b926d4 | Isaku Yamahata | return rc;
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115 | 48ebf2f9 | Isaku Yamahata | } |
116 | 48ebf2f9 | Isaku Yamahata | |
117 | 48ebf2f9 | Isaku Yamahata | static int xio3130_downstream_exitfn(PCIDevice *d) |
118 | 48ebf2f9 | Isaku Yamahata | { |
119 | 09b926d4 | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
120 | 09b926d4 | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
121 | 09b926d4 | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
122 | 09b926d4 | Isaku Yamahata | |
123 | 09b926d4 | Isaku Yamahata | pcie_aer_exit(d); |
124 | 09b926d4 | Isaku Yamahata | pcie_chassis_del_slot(s); |
125 | 48ebf2f9 | Isaku Yamahata | pcie_cap_exit(d); |
126 | 09b926d4 | Isaku Yamahata | msi_uninit(d); |
127 | 48ebf2f9 | Isaku Yamahata | return pci_bridge_exitfn(d);
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128 | 48ebf2f9 | Isaku Yamahata | } |
129 | 48ebf2f9 | Isaku Yamahata | |
130 | 48ebf2f9 | Isaku Yamahata | PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction, |
131 | 48ebf2f9 | Isaku Yamahata | const char *bus_name, pci_map_irq_fn map_irq, |
132 | 48ebf2f9 | Isaku Yamahata | uint8_t port, uint8_t chassis, |
133 | 48ebf2f9 | Isaku Yamahata | uint16_t slot) |
134 | 48ebf2f9 | Isaku Yamahata | { |
135 | 48ebf2f9 | Isaku Yamahata | PCIDevice *d; |
136 | 48ebf2f9 | Isaku Yamahata | PCIBridge *br; |
137 | 48ebf2f9 | Isaku Yamahata | DeviceState *qdev; |
138 | 48ebf2f9 | Isaku Yamahata | |
139 | 48ebf2f9 | Isaku Yamahata | d = pci_create_multifunction(bus, devfn, multifunction, |
140 | 48ebf2f9 | Isaku Yamahata | "xio3130-downstream");
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141 | 48ebf2f9 | Isaku Yamahata | if (!d) {
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142 | 48ebf2f9 | Isaku Yamahata | return NULL; |
143 | 48ebf2f9 | Isaku Yamahata | } |
144 | 48ebf2f9 | Isaku Yamahata | br = DO_UPCAST(PCIBridge, dev, d); |
145 | 48ebf2f9 | Isaku Yamahata | |
146 | 48ebf2f9 | Isaku Yamahata | qdev = &br->dev.qdev; |
147 | 48ebf2f9 | Isaku Yamahata | pci_bridge_map_irq(br, bus_name, map_irq); |
148 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint8(qdev, "port", port);
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149 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint8(qdev, "chassis", chassis);
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150 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint16(qdev, "slot", slot);
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151 | 48ebf2f9 | Isaku Yamahata | qdev_init_nofail(qdev); |
152 | 48ebf2f9 | Isaku Yamahata | |
153 | 48ebf2f9 | Isaku Yamahata | return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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154 | 48ebf2f9 | Isaku Yamahata | } |
155 | 48ebf2f9 | Isaku Yamahata | |
156 | 48ebf2f9 | Isaku Yamahata | static const VMStateDescription vmstate_xio3130_downstream = { |
157 | 48ebf2f9 | Isaku Yamahata | .name = "xio3130-express-downstream-port",
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158 | 48ebf2f9 | Isaku Yamahata | .version_id = 1,
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159 | 48ebf2f9 | Isaku Yamahata | .minimum_version_id = 1,
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160 | 48ebf2f9 | Isaku Yamahata | .minimum_version_id_old = 1,
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161 | 6bde6aaa | Michael S. Tsirkin | .post_load = pcie_cap_slot_post_load, |
162 | 48ebf2f9 | Isaku Yamahata | .fields = (VMStateField[]) { |
163 | 48ebf2f9 | Isaku Yamahata | VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
164 | 09b926d4 | Isaku Yamahata | VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
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165 | 09b926d4 | Isaku Yamahata | vmstate_pcie_aer_log, PCIEAERLog), |
166 | 48ebf2f9 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
167 | 48ebf2f9 | Isaku Yamahata | } |
168 | 48ebf2f9 | Isaku Yamahata | }; |
169 | 48ebf2f9 | Isaku Yamahata | |
170 | 40021f08 | Anthony Liguori | static Property xio3130_downstream_properties[] = {
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171 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), |
172 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
173 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
174 | 40021f08 | Anthony Liguori | DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
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175 | 40021f08 | Anthony Liguori | port.br.dev.exp.aer_log.log_max, |
176 | 40021f08 | Anthony Liguori | PCIE_AER_LOG_MAX_DEFAULT), |
177 | 40021f08 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
178 | 40021f08 | Anthony Liguori | }; |
179 | 40021f08 | Anthony Liguori | |
180 | 40021f08 | Anthony Liguori | static void xio3130_downstream_class_init(ObjectClass *klass, void *data) |
181 | 40021f08 | Anthony Liguori | { |
182 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
183 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
184 | 40021f08 | Anthony Liguori | |
185 | 40021f08 | Anthony Liguori | k->is_express = 1;
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186 | 40021f08 | Anthony Liguori | k->is_bridge = 1;
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187 | 40021f08 | Anthony Liguori | k->config_write = xio3130_downstream_write_config; |
188 | 40021f08 | Anthony Liguori | k->init = xio3130_downstream_initfn; |
189 | 40021f08 | Anthony Liguori | k->exit = xio3130_downstream_exitfn; |
190 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_TI; |
191 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_TI_XIO3130D; |
192 | 40021f08 | Anthony Liguori | k->revision = XIO3130_REVISION; |
193 | 39bffca2 | Anthony Liguori | dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
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194 | 39bffca2 | Anthony Liguori | dc->reset = xio3130_downstream_reset; |
195 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_xio3130_downstream; |
196 | 39bffca2 | Anthony Liguori | dc->props = xio3130_downstream_properties; |
197 | 40021f08 | Anthony Liguori | } |
198 | 40021f08 | Anthony Liguori | |
199 | 39bffca2 | Anthony Liguori | static TypeInfo xio3130_downstream_info = {
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200 | 39bffca2 | Anthony Liguori | .name = "xio3130-downstream",
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201 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
202 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIESlot),
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203 | 39bffca2 | Anthony Liguori | .class_init = xio3130_downstream_class_init, |
204 | 48ebf2f9 | Isaku Yamahata | }; |
205 | 48ebf2f9 | Isaku Yamahata | |
206 | 83f7d43a | Andreas Färber | static void xio3130_downstream_register_types(void) |
207 | 48ebf2f9 | Isaku Yamahata | { |
208 | 39bffca2 | Anthony Liguori | type_register_static(&xio3130_downstream_info); |
209 | 48ebf2f9 | Isaku Yamahata | } |
210 | 48ebf2f9 | Isaku Yamahata | |
211 | 83f7d43a | Andreas Färber | type_init(xio3130_downstream_register_types) |
212 | 48ebf2f9 | Isaku Yamahata | |
213 | 48ebf2f9 | Isaku Yamahata | /*
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214 | 48ebf2f9 | Isaku Yamahata | * Local variables:
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215 | 48ebf2f9 | Isaku Yamahata | * c-indent-level: 4
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216 | 48ebf2f9 | Isaku Yamahata | * c-basic-offset: 4
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217 | 48ebf2f9 | Isaku Yamahata | * tab-width: 8
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218 | 48ebf2f9 | Isaku Yamahata | * indent-tab-mode: nil
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219 | 48ebf2f9 | Isaku Yamahata | * End:
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220 | 48ebf2f9 | Isaku Yamahata | */ |